JP7211902B2 - Time measuring device and method - Google Patents

Description

The present invention relates to time measurement technology for measuring the time length of an input target period based on a low-speed clock and a high-speed clock.

Since the ultrasonic flowmeter obtains the flow velocity of the fluid based on the propagation time of the ultrasonic pulses transmitted and received between the transducers, a time measurement technology is required to accurately measure the propagation time.
Conventionally, as one of such time measurement techniques, there has been proposed a method of performing highly accurate measurement by combining a low-speed clock and a high-speed clock (for example, see Patent Document 1).

In the conventional method described above, the measurement start point of the target period is assumed to be synchronized with the reference cycle of the low-speed clock. Asynchronous to the cycle. For this reason, the general period from the start of measurement to the elapsed measurement synchronized with the reference period that arrived after the end of measurement is measured by the number of clocks (pulses) of the low-speed clock. is measured by the number of clocks (pulses) of the high-speed clock, and the time length of the target period is calculated based on the results of counting the summary period and the excess period.

JP 2007-051890 A Japanese Patent Application Laid-Open No. 2008-014801

When a high-frequency clock generation circuit such as a ring oscillator is used, the power consumption required to generate a high-speed clock is considerably higher than that of a low-speed clock. It is possible to suppress the power consumption required for the generation of
On the other hand, the clock generation circuit does not stabilize the cycle at the start of clock generation, and requires a certain period of time until the cycle stabilizes.

FIG. 6 is a timing chart showing period fluctuations of the high-speed clock. In FIG. 6, the high-speed clock CLKH starts to be generated from time t0 in synchronization with the low-speed clock CLKL. An example is shown in which the cycle of the clock CLKH is not stable.

Therefore, when the generation of the high-speed clock is started at the end of measurement of the target period, that is, at the start of the excess period, the high-speed clock used to measure the excess period has a cycle different from the steady cycle after stabilization. Therefore, when the excess period ΔT is measured with a high-speed clock assuming a steady period, an error occurs in the counting result, leading to a problem of deterioration in measurement accuracy of the target period.

The present invention is intended to solve such problems, and an object thereof is to provide a time measurement technique capable of improving the measurement accuracy of the target period.

In order to achieve such an object, the time measuring device according to the present invention includes a low-speed clock generation circuit that generates a low-speed clock with a constant reference period, and a high-speed clock generation circuit that generates a high-speed clock faster than the low-speed clock. and a measurement processing circuit that counts the low-speed clock and the high-speed clock based on the input measurement start time and measurement end time of the target period, and measures the time length of the target period based on the obtained count result. and the measurement processing circuit includes a low-speed clock counter that counts, with the low-speed clock, an approximate period from the measurement start time to the measurement lapse time synchronized with the reference period that has arrived after the measurement end time, a high-speed clock counter that counts an excess period from the measurement end point to the measurement elapsed point with the high-speed clock from the high-speed clock generation circuit that starts generating at the measurement end point; and the high-speed clock per the reference period. a storage circuit for storing a reference clock number indicating the clock number of the target period, based on the count results of the low-speed clock counter and the high-speed clock counter, the reference clock number, and the time length of the reference period; a time calculation circuit that calculates a length of time; and the number of reference clocks relates to the high-speed clock generated within a cycle fluctuation period corresponding to a plurality of the reference cycles after the start of generation of the high-speed clock. It consists of the number of clocks of the high-speed clock per reference period.

Further, in one configuration example of the time measurement device according to the present invention, the time calculation circuit calculates the low-speed clock in the excess period based on the count results of the low-speed clock counter and the high-speed clock counter and the number of reference clocks. calculating the number of clocks, calculating the time length of the excess period based on the obtained low speed count number and the time length of the reference period, and subtracting the time length of the excess period from the time length of the summary period; By doing so, the time length of the target period is calculated.

In one configuration example of the time measurement device according to the present invention, the measurement processing circuit generates the high-speed clock for a period corresponding to the first reference period from the start of clock generation in the high-speed clock generation circuit. and a second reference clock number indicating the number of clocks of the high-speed clock generated in a period corresponding to the next reference period adjacent to the first reference period. and a reference clock calculation circuit for calculating a clock number located between the first reference clock number and the second reference clock number as the reference clock number.

In one configuration example of the time measurement device according to the present invention, the measurement processing circuit generates the high-speed clock for a period corresponding to the first reference period from the start of clock generation in the high-speed clock generation circuit. as the first reference clock number; and a clock of the high-speed clock generated in a period corresponding to the next reference period following the first reference period. and a second reference clock measuring circuit for measuring the number as the second reference clock number.

In one configuration example of the time measuring device according to the present invention, the reference clock calculation circuit performs a product-sum operation on the first reference clock number and the second reference clock number with respective weights, The number of reference clocks is calculated.

In one configuration example of the time measurement device according to the present invention, the reference clock calculation circuit sets the first reference clock number to Ms1, the second reference clock number to Ms2, and weights Ms1 and Ms2. are w1 and w2, the reference clock number Ms is calculated by the following equation.

In one configuration example of the time measuring device according to the present invention, the reference clock calculation circuit sets the first reference clock number to Ms1, the second reference clock number to Ms2, and calculates the difference between Ms1 and Ms2. is the absolute value of |Ms1-Ms2|, and a value greater than 0 and smaller than |Ms1-Ms2| is m, the reference clock number Ms is calculated by the following equation.

Further, a time measurement method according to the present invention is a time measurement method used in a time measurement device that includes a low-speed clock generation circuit, a high-speed clock generation circuit, and a measurement processing circuit and measures the time length of an input target period. a low-speed clock generation step in which the low-speed clock generation circuit generates a low-speed clock with a constant reference period; a high-speed clock generation step in which the high-speed clock generation circuit generates a high-speed clock faster than the low-speed clock; Measurement processing in which a measurement processing circuit counts the low-speed clock and the high-speed clock based on the measurement start time and the measurement end time of the target period, and measures the time length of the target period based on the obtained count result. a low-speed clock count step of counting the low-speed clock during a period from the measurement start time to the measurement lapse time synchronized with the reference period that has arrived after the measurement end time; and a high-speed clock counting step of counting the high-speed clock during a period from the measurement end point to the measurement elapsed point; a storage step of storing a reference clock number indicating the number of the high-speed clocks per reference period; a time calculation step of calculating the time length of the target period based on the count results of the low-speed clock count step and the high-speed clock count step, the number of reference clocks, and the time length of the reference period; The number of clocks is the number of clocks of the high-speed clock per the reference period regarding the high-speed clock generated within a period variation period corresponding to a plurality of the reference periods after the start of generation of the high-speed clock. It is.

According to the present invention, even if the high-speed clock generation circuit starts generating the high-speed clock at the end of the measurement of the target period, i.e., at the start of the excess period, the reference clock takes into account the cycle fluctuation of the high-speed clock at the start of generation. number will be used to measure overtime. As a result, errors in the count result can be reduced compared to when the excess period is measured with the high-speed clock assuming a steady period with a stable high-speed clock, and as a result, it is possible to improve the measurement accuracy of the target period. becomes.

FIG. 1 is a block diagram showing the configuration of the time measuring device. FIG. 2 is a sequence diagram showing the process of calculating the target period. FIG. 3 is a block diagram illustrating a process of calculating a target period according to the first embodiment; FIG. 4 is a timing chart showing the process of calculating the number of reference clocks according to the first embodiment. FIG. 5 is a block diagram showing the process of calculating the target period according to the second embodiment. FIG. 6 is a timing chart showing period fluctuations of the high-speed clock.

Next, embodiments of the present invention will be described with reference to the drawings.
[First embodiment]
First, a time measuring device 10 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the time measuring device.
The time measurement device 10 is mounted in a field device such as an ultrasonic flowmeter, and measures the time length of the input target period Tm based on the low-speed clock CLKL and the high-speed clock CLKH.

As shown in FIG. 1, the time measurement device 10 includes a low-speed clock generation circuit 11A, a high-speed clock generation circuit 11B, and a measurement processing circuit 12 as main circuit units.

The low-speed clock generation circuit 11A is a circuit section that generates a low-speed clock CLKL with a constant reference period Ts.
The high-speed clock generation circuit 11B is a circuit section that generates a high-speed clock CLKH that is faster than the low-speed clock CLKL.
These low-speed clock generation circuit 11A and high-speed clock generation circuit 11B consist of general clock generation circuits. In particular, when high measurement accuracy is required and the period of the high-speed clock CLKH is set to 100 ps or less (10 GHz or more), a high-frequency type such as a ring oscillator in which an odd number of NOT gate circuits are connected in a ring is used. .

The measurement processing circuit 12 counts the low-speed clock CLKL and the high-speed clock CLKH based on the measurement start time T1 and the measurement end time T2 of the target period Tm, which are specified by the input start pulse Pstart and stop pulse Pstop. This is a circuit unit that measures the target period Tm based on the obtained count result, that is, the low-speed count number (pulse number) N and the high-speed count number (pulse number) M.

The measurement processing circuit 12 includes a low-speed clock counter 13A, a high-speed clock counter 13B, a first reference clock measurement circuit 14A, a second reference clock measurement circuit 14B, a reference clock calculation circuit 15, a storage circuit 16, and a time calculation circuit 17 . A case where the measurement processing circuit 12 is composed of a plurality of circuit units will be described below as an example, but the present invention is not limited to this. You may comprise a part or all.

The low-speed clock counter 13A counts the general period T from the measurement start time T1 to the measurement elapsed time T3 that is synchronized with the reference period Ts that has arrived after the measurement end time T2, using the low-speed clock CLKL. is a circuit unit that outputs
The high-speed clock counter 13B is a circuit unit that counts the high-speed clock CLKH for an excess period ΔT from the measurement end time T2 to the measurement elapsed time T3, and outputs a high-speed count number M as a count result.

The first reference clock measurement circuit 14A measures the number of clocks of the high-speed clock CLKH generated in the period Ts1 corresponding to the first reference period Ts from the clock generation start time (t0) in the high-speed clock generation circuit 11B as a first is a circuit unit that measures (counts) as the reference clock number Ms1.
The second reference clock measurement circuit 14B measures (counts) the number of high-speed clocks CLKH in a period Ts2 corresponding to the next reference period Ts subsequent to the first reference period Ts as a second reference clock number Ms2. It is a circuit part that

The reference clock calculation circuit 15 relates to the high-speed clock CLKH generated in the high-speed clock generation circuit 11B within a constant period variation period Tx corresponding to a plurality of reference periods Ts after the start of generation of the high-speed clock CLKH. This is a circuit section that calculates the number of clocks of the high-speed clock CLKH per reference period Ts as the number of reference clocks Ms.

Specifically, the reference clock calculation circuit 15 calculates the number of clocks of the high-speed clock CLKH generated in the period Ts1 corresponding to the first reference period Ts from the measurement end point T2, that is, the clock generation start point of the high-speed clock generation circuit 11B. a first reference clock number Ms1 indicating It has a function of calculating a clock number located between the first reference clock number Ms1 and the second reference clock number Ms2 as the reference clock number Ms by performing statistical processing. Details regarding the calculation process of the reference clock number Ms will be described later.

In the present embodiment, an example will be described in which two periods of the reference period Ts from the clock generation start time t0 of the high-speed clock CLKH, that is, the period Ts1 and the period Ts2 are defined as the period variation period Tx. As a result, even when the time measurement device 10 measures the target period Tm in the ultrasonic flowmeter, the approximate period T from the measurement end point T2 to the measurement elapsed point T3 is shifted by one reference period Ts. The number of possible reference clocks Ms can be calculated.
Note that the period fluctuation period Tx is not limited to the time length of two periods of the reference period Ts. A period corresponding to three or more cycles of the reference period Ts may be set as the period variation period Tx according to the period variation characteristics of time.

The storage circuit 16 is composed of a semiconductor memory and a register as a whole, and is calculated by the reference clock calculation circuit 15, and is the reference clock number Ms indicating the number of clocks of the high-speed clock CLKH per reference period Ts and the period of the low-speed clock CLKL. This is a circuit unit that stores the time length of the reference cycle Ts.

The time calculation circuit 17 calculates a low-speed count number N and a high-speed count number M, which are the count results of the low-speed clock counter 13A and the high-speed clock counter 13B, and the time length of the reference clock number Ms and the reference period Ts of the storage circuit 16. , a circuit unit for calculating the time length of the target period Tm. Details regarding the calculation process of the target period Tm will be described later.

[Operation of the first embodiment]
Next, operation of the time measuring device 10 according to the present embodiment will be described with reference to FIGS. 2, 3, and 4. FIG. FIG. 2 is a sequence diagram showing the process of calculating the target period. FIG. 3 is a block diagram illustrating a process of calculating a target period according to the first embodiment; FIG. 4 is a timing chart showing the process of calculating the number of reference clocks according to the first embodiment.

[Calculation process for the target period]
First, the calculation process of the target period Tm according to the present embodiment will be described.
In a general ultrasonic flowmeter, a start pulse Pstart is generated in synchronization with the reference period Ts of the low-speed clock CLKL, and a certain number of ultrasonic pulses are continuously transmitted from one transducer in response to this start pulse Pstart. be done. This ultrasonic pulse is received by the other transducer, and a stop pulse Pstop is generated when the received waveform exceeds the threshold.

The period from the start pulse Pstart to the stop pulse Pstop corresponds to the propagation time of the ultrasonic pulse, and the fluid flow rate is calculated based on this propagation time.
Therefore, as shown in FIG. 2, the time measuring device 10 measures the period from the input signal start pulse Pstart to the stop pulse Pstop as the target period Tm, and outputs the obtained measured time value. Hereinafter, the time lengths of the target period Tm, the overview period T, the excess period ΔT, and the reference period Ts may also be referred to as Tm, T, ΔT, and Ts, respectively.

The low-speed clock generation circuit 11A is assumed to always generate the low-speed clock CLKL with a constant reference period Ts, and the reference period Ts and the start pulse Pstart indicating the measurement start point T1 of the target period Tm are synchronized. shall be On the other hand, since the time length of the target period Tm changes arbitrarily, the measurement end point T2 of the target period Tm is asynchronous with respect to the reference period Ts. Therefore, the low-speed clock counter 13A measures, with the low-speed clock CLKL, the general period T from the measurement start time T1 to the measurement elapsed time T3 that is synchronized with the reference cycle Ts that comes after the measurement end time T2.

Further, in response to the enable signal EL from the measurement processing circuit 12, the high-speed clock generation circuit 11B starts generating the high-speed clock CLKH from the measurement end time T2, and the high-speed clock counter 13B starts generating the high-speed clock CLKH from the measurement end time T2 to the measurement elapsed time. The excess period ΔT up to T3 is measured with the high-speed clock CLKH.
The time calculation circuit 17 calculates the time length of the target period Tm based on the measurement results of the summary period T and excess period ΔT.

As shown in FIG. 2, the time length of the target period Tm is calculated by Tm=T−ΔT, which is obtained by subtracting the excess period ΔT from the general period T. At this time, the general period T is represented by an integral multiple of the reference period Ts of the low-speed clock CLKL, that is, N times the low-speed count number. On the other hand, since the excess period ΔT is measured by the high-speed clock CLKH, it is represented by an integral multiple of the period of the high-speed clock CLKH, ie, M times the high-speed count. Therefore, when expressing the number of high-speed counts M by the number of reference cycles Ts, if the number of high-speed counts per reference cycle Ts, that is, the number of reference clocks Ms is used, the number of excess low-speed counts ΔN corresponding to the excess period ΔT can be obtained by the following equation: (1).

The low speed count number N is counted by the low speed clock counter 13A, and the high speed count number M is counted by the high speed clock counter 13B. Therefore, if the reference clock number Ms and the time length of the reference period Ts are set in the storage circuit 16, the time length of the target period Tm is obtained by the time calculation circuit 17 by the following equation (2).

[Calculation process of reference clock number]
Next, referring to FIGS. 2, 3 and 4, the process of calculating the number of reference clocks Ms will be described. In the time measurement device 10 according to the present embodiment, the high-speed clock generation circuit 11B is activated in accordance with the excess period ΔT for the purpose of reducing power consumption. This is because power consumption is large when a high-frequency clock generation circuit such as a ring oscillator is used as the high-speed clock generation circuit 11B.

In the case of such a high-speed clock generation circuit 11B, as shown in FIG. 6, the cycle is not stable at the start of clock generation, and a certain period of time is required until the cycle is stabilized. Therefore, when the generation of the high-speed clock CLKH is started at the measurement end point T2 of the target period Tm, the high-speed clock CLKH used for measuring the excess period ΔT has a period different from the stable period after stabilization. For this reason, when the excess period ΔT is measured on the premise of a steady cycle, an error occurs in the count result, leading to a decrease in measurement accuracy of the target period Tm.

For this reason, the time measurement device 10 according to the present embodiment is provided with a first reference clock measurement circuit 14A, a second reference clock measurement circuit 14B, and a reference clock calculation circuit 15. High-speed clock CLKH generated per reference period Ts within a certain period variation period Tx corresponding to a plurality of reference periods Ts after the start of generation of clock CLKH, for example, within two reference periods Ts is calculated in advance as the reference clock number Ms.

At this time, as shown in FIGS. 3 and 4, first, in the first reference clock measurement circuit 14A, the measurement end time T2, that is, the first reference period Ts from the clock generation start time in the high-speed clock generation circuit 11B. A first reference clock number Ms1 indicating the number of high-speed clocks CLKH generated in the period Ts1 is counted. Next, in the second reference clock measurement circuit 14B, a second reference clock number Ms2 indicating the number of high-speed clocks CLKH generated in a period Ts2 corresponding to the next reference period Ts adjacent to the first reference period Ts. to count.

After that, in the reference clock calculation circuit 15, the first reference clock number Ms1 and the second reference clock number Ms2 are multiplied by preset weights w1 and w2, respectively, to obtain the reference clock number Ms. is calculated by the following equation (3). However, the relationship between these weights w1 and w2 is assumed to be w1+w2=1. As a result, a clock number intermediate between the first reference clock number Ms1 and the second reference clock number Ms2 is calculated as the reference clock number Ms.

FIG. 4 shows a calculation example of the number of reference clocks Ms. In this case, the measurement elapsed time T3 is at the time T3a after the measurement end time T2 by 1/2 the reference period Ts, that is, the case A in which the excess period ΔTa is the period from the measurement end time T2 to the time T3a. and the case where the measurement elapsed time T3 is at the time T3b after the measurement end time T2 by 3/2 the reference period Ts, that is, the case B in which the excess period ΔTb is the period from the measurement end time T2 to the time T3b. explain. These cases A and B may switch from case A to case B when measuring the propagation time of the ultrasonic pulse in the ultrasonic flowmeter. Care should be taken to avoid continuation.

As shown in FIG. 4, it is assumed that generation of the high-speed clock CLKH is started from the measurement end point T2, and the first reference clock measurement circuit 14A generates the high-speed clock CLKH during a period Ts1 corresponding to one reference period Ts from the measurement end point T2. Assume that the first reference clock number obtained by counting is Ms1=64. On the other hand, it is assumed that the second reference clock number obtained by counting the high-speed clock CLKH in the second reference clock measuring circuit 14B in the next period Ts2 corresponding to one reference cycle Ts is Ms2=36. .

Further, the count numbers obtained by counting the high-speed clock CLKH by the high-speed clock counter 13B are 40 and 24 in each of the first and second half cycles of the period Ts1, and the numbers obtained by counting the high-speed clock CLKH in each of the first and second half cycles of the period Ts2 are 40 and 24. Assume that the count numbers obtained by counting the high-speed clock CLKH with the high-speed clock counter 13B are 20 and 16, respectively.

Here, when the first reference clock number Ms1=64 is used as the reference clock number Ms, the excess low-speed count number ΔNa obtained by converting the excess period ΔTa of case A with the low-speed clock CLKL is ΔNa=Ma/ Ms1=40/64≈0.625. Also, the excess low speed count number ΔNb obtained by converting the excess period ΔTb of case B with the low speed clock CLKL is ΔNb=Mb/Ms1=84/64≈1.313.
On the other hand, when the second reference clock number Ms2=36 is used as the reference clock number Ms, the excess low speed count number ΔNa in the excess period ΔTa of case A is ΔNa=Ma/Ms2=40/36≈1.111. . Further, the excess low speed count number ΔNb in the excess period ΔTb of case B is ΔNb=Mb/Ms2=84/36≈2.333.

Therefore, regardless of whether the first reference clock number Ms1 or the second reference clock number Ms2 is used, the excessively low speed count numbers ΔNa and ΔNb are discontinuous between cases A and B, resulting in The time length of the target period Tm is also discontinuous.

On the other hand, in this embodiment, for example, when the weights w1 and w2 are 8/28 and 20/28, respectively, the first reference clock number Ms1=64 and the second reference clock number Ms2=36. The number of reference clocks Ms is Ms=64×8/28+36×20/28=44. As a result, the excess low speed count number ΔNa in the excess period ΔTa of case A is ΔNa=Ma/Ms=40/44≈0.909. Further, the excess low speed count number ΔNb in the excess period ΔTb of case B is ΔNb=Mb/Ms=84/44≈1.909.

Therefore, when the reference clock number Ms according to the present embodiment is used, the excessively low speed count numbers ΔNa and ΔNb are continuous between the case A and the case B, and the time length of the target period Tm obtained as a result is also continuous. will do.

[Effects of the first embodiment]
As described above, in the present embodiment, the low-speed clock counter 13A uses the low-speed clock CLKL to measure the general period T from the measurement start time T1 to the measurement elapsed time T3 that is synchronized with the reference cycle Ts that has arrived after the measurement end time T2. The high-speed clock counter 13B counts the excess period ΔT from the measurement end time T2 to the measurement elapsed time T3 with the high-speed clock CLKH, and the time calculation circuit 17 counts the count results of the low-speed clock counter 13A and the high-speed clock counter 13B, That is, based on the low-speed count number N, the high-speed count number M, the reference clock number Ms, and the time length of the reference period Ts, the time length of the target period Tm is calculated, and a plurality of times after starting generation of the high-speed clock CLKH. With respect to the high-speed clock CLKH generated within the period variation period Tx corresponding to the reference period Ts, the clock number of the high-speed clock CLKH per reference period Ts is used as the reference clock number Ms.

Specifically, based on the count results of the low-speed clock counter 13A and the high-speed clock counter 13B, that is, the low-speed count number N, the high-speed count number M, and the reference clock number Ms, the time calculation circuit 17 calculates the low-speed clock in the target period Tm. The count number N is calculated, and the time length of the target period Tm is calculated based on the obtained low speed count number N and the time length of the reference period Ts.

As a result, even if the high-speed clock generation circuit 11B starts generating the high-speed clock CLKH at the measurement end time T2 of the target period Tm, that is, at the start time of the excess period ΔT, the period fluctuation of the high-speed clock CLKH at the start of generation is considered. The calculated reference clock number Ms is used to measure the excess period ΔT. Therefore, compared to the case where the excess period ΔT is measured with the high-speed clock CLKH assuming that the period of the high-speed clock CLKH is stable, the error in the count result can be reduced, and as a result, the measurement accuracy of the target period Tm can be improved. can be increased.

Further, in the present embodiment, the reference clock calculation circuit 15 is provided in the measurement processing circuit 12, and the high-speed clock generated in the period Ts1 corresponding to the first reference period Ts from the clock generation start time t0 in the high-speed clock generation circuit 11B is generated. A first reference clock number Ms1 indicating the clock number of the clock CLKH and a second reference clock number indicating the clock number of the high-speed clock CLKH generated in a period Ts2 corresponding to the next reference period Ts adjacent to the first reference period Ts. A clock number located between the first reference clock number Ms1 and the second reference clock number Ms2 may be calculated as the reference clock number Ms from the reference clock number Ms2.

As a result, regarding the high-speed clock CLKH generated within the period variation period Tx corresponding to a plurality of reference periods Ts after the start of generation of the high-speed clock CLKH, the number of high-speed clocks CLKH per reference period Ts is It can be easily calculated as the number of reference clocks Ms. Moreover, since the reference clock number Ms can be calculated by the time measuring device 10, a separate operation for calculating the reference clock number Ms is not required, and the system configuration required for time measurement can be greatly simplified.

Further, in this embodiment, the measurement processing circuit 12 is provided with a first reference clock measurement circuit 14A and a second reference clock measurement circuit 14B, and the first reference clock measurement circuit 14A is the high-speed clock generation circuit 11B. The clock number of the high-speed clock CLKH generated in the period Ts1 corresponding to the first reference period Ts from the clock generation start time t0 is measured as the first reference clock number Ms1, and the second reference clock measurement circuit 14B , the number of high-speed clocks CLKH generated in a period Ts2 corresponding to the next reference period Ts subsequent to the first reference period Ts may be measured as the second reference clock number Ms2.
As a result, the first reference clock number Ms1 and the second reference clock number Ms2 necessary for calculating the reference clock number Ms in the reference clock calculation circuit 15 can be measured with an extremely simple circuit configuration.

Further, in the present embodiment, the reference clock calculation circuit 15 calculates the reference clock number Ms by multiplying the first reference clock number Ms1 and the second reference clock number Ms2 with the respective weights w1 and w2. It may be calculated.
Specifically, when the reference clock calculation circuit 15 sets the first reference clock number to Ms1, the second reference clock number to Ms2, and the weights of Ms1 and Ms2 to w1 and w2, the reference clock number Ms is calculated as , may be calculated by the above-described formula (3).
This makes it possible to calculate the number of reference clocks Ms with extremely simple arithmetic processing.

[Second embodiment]
Next, a time measuring device 10 according to a second embodiment of the invention will be described.
In the first embodiment, when the reference clock number Ms is calculated in the reference clock calculation circuit 15, the weights of the first reference clock number Ms1 and the second reference clock number Ms2 are set to w1 and w2, and the above equation ( The case where the reference clock number Ms is calculated by the sum-of-products operation shown in 3) has been described as an example.

In the present embodiment, as the calculation process of the reference clock number Ms, the reference clock calculation circuit 15 calculates the reference clock number Ms using the difference between the first reference clock number Ms1 and the second reference clock number Ms2. will be explained. In the time measurement device 10 according to the present embodiment, the configuration other than the reference clock calculation circuit 15 and the calculation process of the target period Tm are the same as those in the first embodiment, and the details will be described here. detailed description is omitted.

[Calculation process for the target period]
A process of calculating the target period Tm according to the present embodiment will be described with reference to FIG. FIG. 5 is a block diagram showing the process of calculating the target period according to the second embodiment.
In this embodiment, in the process of calculating the reference clock number Ms, the reference clock calculation circuit 15 sets the first reference clock number to Ms1, the second reference clock number to Ms2, and the absolute value of the difference between Ms1 and Ms2. is set to |Ms1-Ms2|, and a value larger than 0 and smaller than |Ms1-Ms2| is set to a coefficient m, the number of reference clocks Ms is calculated by the following equation (4).

[Effects of Second Embodiment]
As described above, in the present embodiment, the reference clock calculation circuit 15 assumes that the first reference clock number is Ms1, the second reference clock number is Ms2, and the absolute difference between Ms1 and Ms2 is calculated. is a value |Ms1-Ms2| and a value larger than 0 and smaller than |Ms1-Ms2|

As a result, by simply adjusting the coefficient m within the range of 0<m<|Ms1-Ms2| It can be calculated as the number Ms, and the calculation processing load of the reference clock number Ms can be reduced.

[Expansion of Embodiment]
Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a non-contradictory range.

REFERENCE SIGNS LIST 10 Time measurement device 11A Low-speed clock generation circuit 11B High-speed clock generation circuit 12 Measurement processing circuit 13A Low-speed clock counter 13B High-speed clock counter 14A First reference clock measurement circuit 14B Second reference clock measurement circuit 15 Reference clock calculation circuit 16 Storage circuit 17 Time calculation circuit CLKL Low-speed clock CLKH High-speed clock Pstart Start pulse Pstop Stop pulse N Low-speed count number, M... high-speed count number, Ms1... first reference clock number, Ms2... second reference clock number, Ms... reference clock number, w1, w2... weight, m... coefficient, Ts... reference period, T... overview Period, Tm... Target period, T1... Measurement start time, T2... Measurement end time, T3... Measurement elapsed time, ΔT, ΔTa, ΔTb... Excess period, ΔN, ΔNa, ΔNb... Excess low speed count number, Tx... Cycle fluctuation period , Ts1, Ts2 . . . period.

Claims (8)

a low-speed clock generation circuit that generates a low-speed clock with a constant reference period;
a high-speed clock generation circuit that generates a high-speed clock faster than the low-speed clock;
a measurement processing circuit that counts the low-speed clock and the high-speed clock based on the input measurement start time and measurement end time of the target period, and measures the time length of the target period based on the obtained count result; prepared,
The measurement processing circuit is
a low-speed clock counter that counts, with the low-speed clock, an approximate period from the measurement start point to the measurement lapse point that is synchronized with the reference period that has arrived after the measurement end point;
a high-speed clock counter that counts an excess period from the measurement end point to the measurement elapsed point using the high-speed clock from the high-speed clock generation circuit that starts generating at the measurement end point;
a storage circuit for storing a reference clock number indicating the number of clocks of the high-speed clock per reference period;
a time calculation circuit that calculates the time length of the target period based on the count results of the low-speed clock counter and the high-speed clock counter, the number of reference clocks, and the time length of the reference period;
The number of reference clocks is the number of high-speed clocks per reference period for the high-speed clock generated within a period variation period corresponding to a plurality of reference periods after the start of generation of the high-speed clock. A time measuring device characterized by comprising: In the time measuring device according to claim 1,
The time calculation circuit calculates the number of low-speed clocks in the excess period based on the count results of the low-speed clock counter and the high-speed clock counter and the reference clock number, and calculates the obtained low-speed count number and the reference clock number. The time length of the excess period is calculated based on the time length of the cycle, and the time length of the target period is calculated by subtracting the time length of the excess period from the time length of the summary period. A time measuring device. In the time measuring device according to claim 1 or claim 2,
The measurement processing circuit comprises: a first reference clock number indicating the number of clocks of the high-speed clock generated in a period corresponding to the first reference period from the start of clock generation in the high-speed clock generation circuit; From a second reference clock number indicating the number of clocks of the high-speed clock generated in a period corresponding to the next reference period adjacent to the reference period, the first reference clock number and the second reference clock number are obtained. A time measuring device, further comprising a reference clock calculation circuit for calculating a clock number positioned between , as the reference clock number. In the time measuring device according to claim 3,
The measurement processing circuit is
A first reference clock measurement circuit for measuring, as the first reference clock number, the number of clocks of the high-speed clock generated in a period corresponding to the first reference period from the start of clock generation in the high-speed clock generation circuit. When,
a second reference clock measuring circuit for measuring, as the second reference clock number, the clock number of the high-speed clock generated in a period corresponding to the next reference period following the first reference period; A time measuring device characterized by: In the time measuring device according to claim 3 or claim 4,
The time measurement device, wherein the reference clock calculation circuit calculates the reference clock number by performing a product-sum operation on the first reference clock number and the second reference clock number with respective weights. In the time measuring device according to claim 3 or claim 4,
When the first reference clock number is Ms1, the second reference clock number is Ms2, and the weights of Ms1 and Ms2 are w1 and w2, the reference clock calculation circuit calculates the reference clock number Ms as follows: A time measuring device characterized by calculating with the following formula.

In the time measuring device according to claim 3 or claim 4,
The reference clock calculation circuit defines the first reference clock number as Ms1, the second reference clock number as Ms2, and the absolute value of the difference between Ms1 and Ms2 as |Ms1−Ms2|, which is larger than 0 and |Ms1 A time measuring device, wherein the reference clock number Ms is calculated by the following equation, where m is a value smaller than -Ms2|.

A time measurement method used in a time measurement device that includes a low-speed clock generation circuit, a high-speed clock generation circuit, and a measurement processing circuit and measures the time length of an input target period,
a low-speed clock generation step in which the low-speed clock generation circuit generates a low-speed clock with a constant reference period;
a high-speed clock generation step in which the high-speed clock generation circuit generates a high-speed clock faster than the low-speed clock;
Measurement in which the measurement processing circuit counts the low-speed clock and the high-speed clock based on the measurement start time and the measurement end time of the target period, and measures the time length of the target period based on the obtained count result. a processing step;
The measurement processing step includes
a low-speed clock count step of counting the low-speed clock during a period from the measurement start time to the measurement lapse time synchronized with the reference period that has arrived after the measurement end time;
a high-speed clock count step of counting the high-speed clock during a period from the measurement end point to the measurement elapsed point;
a storage step of storing a reference clock number indicating the clock number of the high-speed clock per the reference period;
a time calculation step of calculating the time length of the target period based on the count results of the low-speed clock count step and the high-speed clock count step, the number of reference clocks, and the time length of the reference period;
The number of reference clocks is the number of high-speed clocks per reference period for the high-speed clock generated within a period variation period corresponding to a plurality of reference periods after the start of generation of the high-speed clock. A time measurement method characterized by comprising:

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