CN112082607B - Time measurement device and method - Google Patents
Time measurement device and method Download PDFInfo
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- CN112082607B CN112082607B CN202010435036.8A CN202010435036A CN112082607B CN 112082607 B CN112082607 B CN 112082607B CN 202010435036 A CN202010435036 A CN 202010435036A CN 112082607 B CN112082607 B CN 112082607B
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
- G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
- G01F1/66—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by measuring frequency, phase shift or propagation time of electromagnetic or other waves, e.g. using ultrasonic flowmeters
- G01F1/667—Arrangements of transducers for ultrasonic flowmeters; Circuits for operating ultrasonic flowmeters
Abstract
The invention provides a time measuring device and a time measuring method, which can improve the measuring precision during the period of an object. A time calculation circuit (17) calculates the time length of a target period (Tm) from the count results of a low-speed clock counter (13A) and a high-speed clock counter (13B), that is, the low-speed count number (N) and the high-speed count number (M), the reference clock number (Ms), and the time length of a reference period (Ts), and uses the clock number of the high-speed Clock (CLKH) in each reference period (Ts) related to the high-speed Clock (CLKH) as the reference clock number (Ms), wherein the high-speed Clock (CLKH) is generated in a period varying period (Tx) corresponding to a plurality of reference periods (Ts) from the start of the generation of the high-speed Clock (CLKH).
Description
Technical Field
The present invention relates to a time measurement technique for measuring a time length during an input object from a low-speed clock and a high-speed clock, and more particularly, to a time measurement apparatus and method.
Background
In an ultrasonic flowmeter, since the flow velocity of a fluid is obtained from the propagation time of an ultrasonic pulse transmitted and received between transducers, a time measurement technique for measuring the propagation time with high accuracy is required.
Conventionally, as one of such time measurement techniques, a method of combining a low-speed clock and a high-speed clock to perform high-precision measurement has been proposed (for example, refer to patent document 1).
In the conventional method, the measurement start time point of the target period is synchronized with the reference period of the low-speed clock, but the time length of the target period is arbitrarily changed, so the measurement end time point of the target period becomes unsynchronized with respect to the reference period. Therefore, the summary period from the measurement start time point to the measurement elapsed time point synchronized with the reference period, which comes after the measurement end time point, is measured by the clock number (pulse number) of the low-speed clock, and the excess period from the measurement end time point to the measurement elapsed time point is measured by the clock number (pulse number) of the high-speed clock, and the time length of the target period is calculated from the result of counting the summary period and the excess period.
[ Prior Art literature ]
[ patent literature ]
Patent document 1 Japanese patent laid-open No. 2007-051890
Patent document 2 japanese patent laid-open publication No. 2008-014801
Disclosure of Invention
[ problem to be solved by the invention ]
In the case of using a high-frequency clock generation circuit such as a ring oscillator, since the power consumption required for generating a high-speed clock is considerably larger than that of a low-speed clock, the power consumption required for generating a high-speed clock can be suppressed when the high-speed clock is generated only for an excessive period.
On the other hand, the clock generation circuit is unstable in period at the start of clock generation, and a fixed period is required before the period is stable.
Fig. 6 is a timing chart showing a period change of the high-speed clock. Fig. 6 shows an example in which the high-speed clock CLKH is generated from the time t0 in synchronization with the low-speed clock CLKL, but the period of the high-speed clock CLKH is unstable at the time t1 at which one reference period has elapsed from the time t0 and further at the time t2 at which two reference periods have elapsed.
Therefore, when the generation of the high-speed clock is started at the measurement end time point of the object period, that is, at the start time point of the excess period, the high-speed clock used in the measurement of the excess period becomes a period different from the steady-state period after the stabilization. Therefore, if the steady-state period is assumed and the period Δt is exceeded by the high-speed clock measurement, there is a problem that an error occurs in the count result, and the measurement accuracy in the target period is lowered.
The present invention is an invention for solving such problems, and an object thereof is to provide a time measurement technique capable of improving measurement accuracy during a target period.
[ means of solving the problems ]
To achieve this object, a time measuring apparatus of the present invention includes: a low-speed clock generation circuit that generates a low-speed clock at a fixed reference period; a high-speed clock generation circuit that generates a high-speed clock at a higher speed than the low-speed clock; and a measurement processing circuit that counts the low-speed clock and the high-speed clock according to a measurement start time point and a measurement end time point of the input object period, and measures a time length of the object period according to the obtained count result; the measurement processing circuit includes: a low-speed clock counter that counts, with the low-speed clock, a summary period from the measurement start time point to a measurement elapsed time point that arrives after the measurement end time point in synchronization with the reference period; a high-speed clock counter that counts an excess period from the measurement end time point to the measurement elapsed time point by using the high-speed clock generated by the high-speed clock generation circuit at the measurement end time point; a memory circuit that stores a reference clock number indicating the number of clocks of the high-speed clock in each of the reference periods; a time calculation circuit that calculates a time length of the object period based on count results of the low-speed clock counter and the high-speed clock counter, the reference clock number, and a time length of the reference period; the reference clock number includes the clock number of the high-speed clock in each of the reference periods related to the high-speed clock generated during a period varying period corresponding to a plurality of the reference periods from the start of the generation of the high-speed clock.
In addition, one configuration of the time measuring device of the present invention is, for example, as follows: the time calculation circuit calculates the number of the low-speed clocks in the excess period based on the count results of the low-speed clock counter and the high-speed clock counter and the reference clock number, calculates the time length of the excess period based on the obtained low-speed count number and the time length of the reference period, and calculates the time length of the object period by subtracting the time length of the excess period from the time length of the summary period.
In addition, one configuration of the time measuring device of the present invention is, for example, as follows: the measurement processing circuit further includes a reference clock calculation circuit that calculates, as the reference clock number, a clock number located intermediate between a first reference clock number indicating the number of clocks of the high-speed clock generated during a period corresponding to a first reference period from a clock generation start time point in the high-speed clock generation circuit and a second reference clock number indicating the number of clocks of the high-speed clock generated during a period corresponding to a next reference period adjacent to the first reference period.
In addition, one configuration of the time measuring device of the present invention is, for example, as follows: the measurement processing circuit further includes a first reference clock measurement circuit that measures, as the first reference clock count, the number of clocks of the high-speed clock generated during a period corresponding to an initial reference period from a clock generation start time point in the high-speed clock generation circuit, and a second reference clock measurement circuit that measures, as the second reference clock count, the number of clocks of the high-speed clock generated during a period corresponding to a next reference period after the initial reference period.
In addition, one configuration of the time measuring device of the present invention is, for example, as follows: the reference clock calculation circuit performs multiply-accumulate operation on the first reference clock number and the second reference clock number by using respective weights, thereby calculating the reference clock number.
In addition, one configuration of the time measuring device of the present invention is, for example, as follows: the reference clock calculation circuit calculates the reference clock number Ms by the following equation, assuming that the first reference clock number is Ms1, the second reference clock number is Ms2, and weights of Ms1 and Ms2 are w1 and w 2.
[ mathematics 1]
Ms＝w1×Ms1+w2×Ms2
Where w1+w2=1
In addition, one configuration of the time measuring device of the present invention is, for example, as follows: the reference clock calculation circuit calculates the reference clock number Ms by the following equation, assuming that the first reference clock number is Ms1, the second reference clock number is Ms2, the absolute value of the difference between Ms1 and Ms2 is |m1-m2|, and the value larger than 0 and smaller than |m1-m2| is m.
[ math figure 2]
Ms＝(Ms1+Ms2-|Ms1-Ms2|)/2+m
Where 0 < m < |Ms1-Ms2|
The time measurement method according to the present invention is a time measurement method used in a time measurement device that includes a low-speed clock generation circuit, a high-speed clock generation circuit, and a measurement processing circuit and measures a time length of an input object period, the time measurement method including: a low-speed clock generation step of generating a low-speed clock at a fixed reference period by the low-speed clock generation circuit; a high-speed clock generation step of generating a high-speed clock at a higher speed than the low-speed clock by the high-speed clock generation circuit; and a measurement processing step of counting the low-speed clock and the high-speed clock according to a measurement start time point and a measurement end time point during the object period, and measuring a time length during the object period according to the obtained count result; the measurement processing step includes: a low-speed clock counting step of counting the low-speed clock during a period from the measurement start time point to a measurement elapsed time point synchronized with the reference period, which comes after the measurement end time point; a high-speed clock counting step of counting the high-speed clock during a period from the measurement end time point to the measurement elapsed time point; a storage step of storing a reference clock number indicating the number of clocks of the high-speed clock in each of the reference periods; a time calculation step of calculating a time length of the object period based on the count results of the low-speed clock count step and the high-speed clock count step, the reference clock count, and the time length of the reference period; the reference clock number includes the clock number of the high-speed clock in each of the reference periods related to the high-speed clock generated during a period varying period corresponding to a plurality of the reference periods from the start of the generation of the high-speed clock.
[ Effect of the invention ]
According to the present invention, when the high-speed clock generation circuit starts the generation of the high-speed clock at the measurement end time point of the target period, that is, at the start time point of the excess period, the reference clock number taking into consideration the period fluctuation of the high-speed clock at the start of the generation can be used for the measurement of the excess period. Therefore, compared with a case where the period exceeding period is measured by the high-speed clock on the premise of a steady-state period in which the period of the high-speed clock is stable, the error of the count result can be reduced, and as a result, the measurement accuracy of the target period can be improved.
Drawings
Fig. 1 is a block diagram showing the configuration of a time measurement device.
Fig. 2 is a sequence diagram showing a calculation process during an object.
Fig. 3 is a block diagram showing a calculation process during an object of the first embodiment.
Fig. 4 is a timing chart showing a process of calculating the reference clock number according to the first embodiment.
Fig. 5 is a block diagram showing a calculation process during an object of the second embodiment.
Fig. 6 is a timing chart showing a period change of the high-speed clock.
[ description of symbols ]
10: time measuring device
11A: low-speed clock generation circuit
11B: high-speed clock generation circuit
12: measurement processing circuit
13A: low-speed clock counter
13B: high-speed clock counter
14A: first reference clock measuring circuit
14B: second reference clock measuring circuit
15: reference clock calculation circuit
16: memory circuit
17: time calculation circuit
CLKL: low-speed clock
CLKH: high-speed clock
EN: enable signal
m: coefficients of
M: high-speed count
Ma, mb: counting number
Ms: reference clock number
Ms1: first reference clock number
Ms2: second reference clock number
N: low speed count
Pstart: start pulse
Pstop: stop pulse
T0, T1, T2, T3a, T3b: time of day
T: summary period
T1: measurement start time point
T2: end of measurement time point
T3: measuring the elapsed time point
Tm: during an object
Ts: reference period
Ts1, ts2: during the period of time
Tx: during period of variation
w1, w2: weighting of
Δn, Δna, Δnb: over low count
Δt, Δta, Δtb: over period of time
Detailed Description
Embodiments of the present invention will be described with reference to the drawings.
First embodiment
First, a time measurement device 10 according to a first embodiment of the present invention will be described with reference to fig. 1. Fig. 1 is a block diagram showing the configuration of a time measurement device.
The time measuring device 10 is, for example, a device mounted on a field device such as an ultrasonic flowmeter, and measures the time length of the input target period Tm based on the low-speed clock CLKL and the high-speed clock CLKH.
As shown in fig. 1, the time measuring apparatus 10 includes a low-speed clock generating circuit 11A, a high-speed clock generating circuit 11B, and a measurement processing circuit 12 as main circuit parts.
The low-speed clock generation circuit 11A is a circuit portion that generates the low-speed clock CLKL at a fixed reference period Ts.
The high-speed clock generation circuit 11B is a circuit portion that generates a high-speed clock CLKH that is higher in speed than the low-speed clock CLKL.
The low-speed clock generation circuit 11A and the high-speed clock generation circuit 11B include a general clock generation circuit. In particular, when the period of the high-speed clock CLKH is set to 100ps or less (10 GHz or more) as required for high measurement accuracy, for example, a high-frequency type ring oscillator in which an odd number of NOT gates (NOT gates) are connected in a ring shape may be used.
The measurement processing circuit 12 is a circuit section as follows: the low-speed clock CLKL and the high-speed clock CLKH are counted based on the measurement start time point T1 and the measurement end time point T2 of the target period Tm determined by the input start pulse Pstart and stop pulse Pstop, and the target period Tm is measured based on the obtained count results, i.e., the low-speed count number (pulse number) N and the high-speed count number (pulse number) M.
The measurement processing circuit 12 includes a low-speed clock counter 13A, a high-speed clock counter 13B, a first reference clock measurement circuit 14A, a second reference clock measurement circuit 14B, a reference clock calculation circuit 15, a storage circuit 16, and a time calculation circuit 17 as main circuit portions. The case where the measurement processing circuit 12 includes a plurality of circuit units will be described below as an example, but the present invention is not limited to this, and a part or all of the circuit units may be configured by cooperation of a central processing unit (Central Processing Unit, CPU) and a program.
The low-speed clock counter 13A is a circuit section as follows: the summary period T from the measurement start time point T1 to the measurement elapsed time point T3, which is synchronized with the reference period Ts and comes after the measurement end time point T2, is counted by the low-speed clock CLKL, and the low-speed count number N is output as a count result.
The high-speed clock counter 13B is a circuit section as follows: the excess period Δt from the measurement end time point T2 to the measurement elapsed time point T3 is counted by the high-speed clock CLKH, and the high-speed count number M is output as a count result.
The first reference clock measurement circuit 14A is a circuit section as follows: the number of clocks of the high-speed clock CLKH generated in the period Ts1 corresponding to the first reference period Ts from the clock generation start time point (t 0) in the high-speed clock generation circuit 11B is measured (counted) as the first reference clock number Ms 1.
The second reference clock measurement circuit 14B is a circuit portion as follows: the number of clocks of the high-speed clock CLKH in the period Ts2 corresponding to the next reference period Ts after the first reference period Ts is measured (counted) as the second reference clock number Ms2.
The reference clock calculation circuit 15 is a circuit section as follows: the high-speed clock CLKH is calculated by using, as the reference clock number Ms, the number of clocks of the high-speed clock CLKH in each reference period Ts, which is generated in the high-speed clock generation circuit 11B during a fixed period fluctuation period Tx corresponding to a plurality of reference periods Ts from the start of generation of the high-speed clock CLKH.
Specifically, the reference clock calculation circuit 15 has the following functions: by performing statistical processing on the first reference clock number Ms1 and the second reference clock number Ms2, the number of clocks located in the middle between the first reference clock number Ms1 and the second reference clock number Ms2 is calculated as the reference clock number Ms, the first reference clock number Ms1 represents the number of clocks of the high-speed clock CLKH generated in the period Ts1 corresponding to the first reference period Ts from the measurement end time point T2, that is, the clock generation start time point in the high-speed clock generation circuit 11B, and the second reference clock number Ms2 represents the number of clocks of the high-speed clock CLKH generated in the period Ts2 corresponding to the next reference period Ts adjacent to the first reference period Ts. Details regarding the calculation process of the reference clock number Ms will be described later.
In the present embodiment, a case will be described in which two reference periods Ts, that is, a period Ts1 and a period Ts2 are set as a period fluctuation period Tx from a clock generation start time point t0 of the high-speed clock CLKH. Thus, the reference clock number Ms that may be generated when the time measuring device 10 measures the target period Tm in the ultrasonic flowmeter can be calculated, in which case the exceeding period Δt from the measurement end time point T2 to the measurement elapsed time point T3 is shifted by only one reference period Ts.
The period fluctuation period Tx is not limited to the time length of the two reference periods Ts, and may be set to a period corresponding to three or more reference periods Ts as the period fluctuation period Tx in accordance with the fluctuation characteristic of the target period Tm to be measured by the time measuring device 10 or the period fluctuation characteristic at the start of generation by the high-speed clock generating circuit 11B.
The memory circuit 16 is a circuit section as follows: as a whole, a semiconductor memory or a register is included, and the reference clock count Ms indicating the number of clocks of the high-speed clock CLKH in each reference period Ts calculated by the reference clock calculation circuit 15 and the time length of the reference period Ts as the period of the low-speed clock CLKL are stored.
The time calculation circuit 17 is a circuit section as follows: the time length of the target period Tm is calculated from the low-speed count number N and the high-speed count number M, which are count results of the low-speed clock counter 13A and the high-speed clock counter 13B, and the time length of the reference clock number Ms and the reference period Ts of the memory circuit 16. Details regarding the calculation process of Tm during the subject will be described later.
Operation of the first embodiment
Next, the operation of the time measuring device 10 according to the present embodiment will be described with reference to fig. 2, 3, and 4. Fig. 2 is a sequence diagram showing a calculation process during an object. Fig. 3 is a block diagram showing a calculation process during an object of the first embodiment. Fig. 4 is a timing chart showing a process of calculating the reference clock number according to the first embodiment.
[ calculation procedure during object ]
First, a process of calculating the target period Tm in the present embodiment will be described.
In a general ultrasonic flowmeter, a start pulse Pstart is generated in synchronization with a reference period Ts of a low-speed clock CLKL, and a fixed number of ultrasonic pulses are continuously transmitted from one transducer in response to the start pulse Pstart. The ultrasonic pulse is received by the other transducer, and a stop pulse Pstop is generated at a point in time when the received waveform exceeds a threshold value.
The period from the start pulse Pstart to the stop pulse Pstop corresponds to the propagation time of the ultrasonic pulse, and the fluid flow rate is calculated from the propagation time.
Therefore, as shown in fig. 2, the time measurement device 10 measures a period from the start pulse Pstart to the stop pulse Pstop as an input signal as a target period Tm, and outputs the obtained measurement time value. Hereinafter, the target period Tm, the summary period T, the exceeding period Δt, and the time length of the reference period Ts are also referred to as Tm, T, Δt, and Ts, respectively.
The low-speed clock generation circuit 11A is configured to generate the low-speed clock CLKL at a constant reference period Ts, and the reference period Ts is synchronized with the start pulse Pstart at the measurement start time point T1 indicating the target period Tm. On the other hand, since the time length of the target period Tm arbitrarily changes, the measurement end time point T2 of the target period Tm becomes asynchronous with respect to the reference period Ts. Therefore, the low-speed clock counter 13A measures the summary period T from the measurement start time point T1 to the measurement elapsed time point T3 synchronized with the reference period Ts, which comes after the measurement end time point T2, using the low-speed clock CLKL.
The high-speed clock generation circuit 11B starts generation of the high-speed clock CLKH from the measurement end time point T2 in response to the enable signal EN from the measurement processing circuit 12, and the high-speed clock counter 13B measures the excess period Δt from the measurement end time point T2 to the measurement elapsed time point T3 using the high-speed clock CLKH.
The time calculation circuit 17 calculates the time length of the target period Tm from the measurement results of the summary period T and the excess period Δt.
As shown in fig. 2, the time length of the target period Tm is calculated by subtracting tm=t—Δt exceeding the period Δt from the summary period T. At this time, the summary period T is represented by an integer multiple of the reference period Ts of the low-speed clock CLKL, that is, N times the low-speed count number. On the other hand, the exceeding period Δt is measured by the high-speed clock CLKH, and is therefore represented by an integer multiple of the period of the high-speed clock CLKH, that is, a high-speed count number M. Therefore, when the reference clock number Ms, which is the high-speed count number per reference period Ts, is used when the high-speed count number M is represented by the number of reference periods Ts, the excess low-speed count number Δn corresponding to the excess period Δt is obtained by the following equation (1).
[ math 3]
The low-speed count N is counted by the low-speed clock counter 13A, and the high-speed count M is counted by the high-speed clock counter 13B. Therefore, when the time length of the reference clock number Ms and the reference period Ts is set in the memory circuit 16, the time length of the target period Tm is obtained by the time calculation circuit 17 according to the following equation (2).
[ mathematics 4]
Tm＝T-ΔT
＝Ts×(N-ΔN)…(2)
[ calculation procedure of reference clock count ]
Next, a process of calculating the reference clock number Ms will be described with reference to fig. 2, 3, and 4. In the time measurement device 10 of the present embodiment, the high-speed clock generation circuit 11B is started up against the exceeding period Δt for the purpose of reducing the power consumption. The reason for this is that: when a high-frequency clock generation circuit such as a ring oscillator is used as the high-speed clock generation circuit 11B, power consumption is large.
In the case of such a high-speed clock generation circuit 11B, as shown in fig. 6, the period is unstable at the start of clock generation, and a fixed period is required before the period is stable. Therefore, when the generation of the high-speed clock CLKH is started at the measurement end time point T2 of the object period Tm, the high-speed clock CLKH used in the measurement exceeding the period Δt becomes a period different from the steady-state period after stabilization. Therefore, when the steady-state period is measured over the period Δt on the assumption, an error occurs in the count result, and the measurement accuracy of the target period Tm decreases.
Therefore, in the time measurement device 10 of the present embodiment, the first reference clock measurement circuit 14A, the second reference clock measurement circuit 14B, and the reference clock calculation circuit 15 are provided, and the number of clocks of the high-speed clock CLKH in each reference period Ts related to the high-speed clock CLKH, which is generated in the high-speed clock generation circuit 11B within a fixed period variation period Tx corresponding to a plurality of reference periods Ts, for example, within two reference periods Ts from the start of generation of the high-speed clock CLKH, is calculated in advance as the reference clock number Ms.
At this time, as shown in fig. 3 and 4, first, the first reference clock measurement circuit 14A counts the first reference clock number Ms1, which represents the number of clocks of the high-speed clock CLKH generated in the period Ts1 corresponding to the first reference period Ts from the measurement end time point T2, that is, the clock generation start time point in the high-speed clock generation circuit 11B. Next, the second reference clock measurement circuit 14B counts a second reference clock number Ms2, the second reference clock number Ms2 representing the number of clocks of the high-speed clock CLKH generated in a period Ts2 corresponding to the next reference period Ts adjacent to the first reference period Ts.
Thereafter, the reference clock calculation circuit 15 calculates the reference clock number Ms by multiplying and accumulating the first reference clock number Ms1 and the second reference clock number Ms2 by the weights w1 and w2 set in advance, respectively, by the following equation (3). The relationship between the weights w1 and w2 is w1+w2=1. Thus, the number of clocks located in the middle between the first reference clock number Ms1 and the second reference clock number Ms2 is calculated as the reference clock number Ms.
[ math 5]
Ms＝w1×Ms1+w2×Ms2
Here w1+w2=1 … (3)
Fig. 4 shows an example of calculation of the reference clock number Ms. Here, an example will be described in which the measurement elapsed time point T3 is located at a time T3a that exceeds only the 1/2 reference period Ts from the measurement end time point T2, that is, an example a in which the exceeding period Δta is a period from the measurement end time point T2 to the time T3a, and an example B in which the measurement elapsed time point T3 is located at a time T3B that exceeds only the 3/2 reference period Ts from the measurement end time point T2, that is, an example in which the exceeding period Δtb is a period from the measurement end time point T2 to the time T3B. In the case of switching from example a to example B after measuring the propagation time of an ultrasonic pulse in the ultrasonic flowmeter, the above examples a and B must be considered so that the measurement results do not become discontinuous at the switching timing of the above examples a and B.
As shown in fig. 4, the generation of the high-speed clock CLKH is started from the measurement end time point T2, and the first reference clock count obtained by counting the high-speed clock CLKH by the first reference clock measurement circuit 14A in the period Ts1 of one reference period Ts from the measurement end time point T2 is Ms1 = 64. On the other hand, in the period Ts2 of the next reference period Ts, the second reference clock count obtained by counting the high-speed clock CLKH by the second reference clock measurement circuit 14B is Ms2 = 36.
The count number obtained by counting the high-speed clock CLKH by the high-speed clock counter 13B in each half period of the first half and the second half of the period Ts1 is 40 and 24, and the count number obtained by counting the high-speed clock CLKH by the high-speed clock counter 13B in each half period of the first half and the second half of the period Ts2 is 20 and 16.
Here, when the first reference clock number Ms 1=64 is used as the reference clock number Ms, the excess low-speed count number Δna obtained by converting the excess period Δta of example a with the low-speed clock CLKL becomes Δna=ma/Ms 1=40/64 ∈0.625. The excess low-speed count number Δnb obtained by converting the excess period Δtb of example B with the low-speed clock CLKL becomes Δnb=mb/m1=84/64·1.313.
On the other hand, when the second reference clock number Ms 2=36 is used as the reference clock number Ms, the count at the low speed exceeding Δna in the exceeding period Δta of example a becomes Δna=ma/Ms 2=40/36 ∈1.111. The count of the excess low speed Δnb in the excess period Δtb in example B is Δnb=mb/Ms 2=84/36+.2.333.
Therefore, when either of the first reference clock number Ms1 and the second reference clock number Ms2 is used, both the count at a low speed Δna and the count at a low speed Δnb are not continuous between the example a and the example B, and as a result, the time length of the obtained target period Tm is also not continuous.
On the other hand, in the present embodiment, for example, when the weights w1 and w2 are 8/28 and 20/28, respectively, the first reference clock number Ms 1=64 and the second reference clock number Ms 2=36, and thus the reference clock number Ms becomes ms=64×8/28+36×20/28=44. Thus, the count of excess low speed Δna in the excess period Δta of example a becomes Δna=ma/ms=40/44+.0.909. The count of the excess low speed Δnb in the excess period Δtb in example B is Δnb=mb/ms=84/44+. 1.909.
Therefore, when the reference clock number Ms of the present embodiment is used, the time length of the obtained target period Tm is also continuous between the example a and the example B when the low-speed count number Δna is exceeded and the low-speed count number Δnb is exceeded.
Effect of the first embodiment
Thus, the present embodiment is as follows: the low-speed clock counter 13A counts the summary period T from the measurement start time point T1 to the measurement elapsed time point T3 synchronized with the reference period Ts, which is the time period after the measurement end time point T2, by the low-speed clock CLKL, and the high-speed clock counter 13B counts the excess period Δt from the measurement end time point T2 to the measurement elapsed time point T3 by the high-speed clock CLKH, and the time calculation circuit 17 calculates the time period Tm of the target period based on the count results of the low-speed clock counter 13A and the high-speed clock counter 13B, that is, the low-speed count number N and the high-speed count number M, the reference clock number Ms, and the time period of the reference period Ts, and uses the clock number of the high-speed clock CLKH in each reference period Ts related to the high-speed clock CLKH, which is generated in the period fluctuation period Tx corresponding to a plurality of reference periods Ts, from the start of generation of the high-speed clock CLKH.
Specifically, the time calculation circuit 17 is as follows: the low-speed count number N in the target period Tm is calculated based on the count results of the low-speed clock counter 13A and the high-speed clock counter 13B, that is, the low-speed count number N and the high-speed count number M, and the reference clock number Ms, and the time length of the target period Tm is calculated based on the obtained time length of the low-speed count number N and the reference period Ts.
Thus, when the high-speed clock generation circuit 11B starts the generation of the high-speed clock CLKH at the measurement end time point T2 of the target period Tm, that is, at the start time point of the exceeding period Δt, the reference clock number Ms in which the period fluctuation of the high-speed clock CLKH at the start of the generation is taken into consideration can be used for the measurement of the exceeding period Δt. Therefore, compared with the case where the period Δt is measured by the high-speed clock CLKH on the premise of a steady-state period in which the period of the high-speed clock CLKH is stable, the error of the count result can be reduced, and as a result, the measurement accuracy of the target period Tm can be improved.
In the present embodiment, the reference clock calculation circuit 15 may be provided in the measurement processing circuit 12, and the reference clock number Ms may be calculated based on a first reference clock number Ms1 and a second reference clock number Ms2, the first reference clock number Ms1 indicating the number of clocks of the high-speed clock CLKH generated in the period Ts1 corresponding to the first reference period Ts from the clock generation start time point t0 in the high-speed clock generation circuit 11B, and the second reference clock number Ms2 indicating the number of clocks of the high-speed clock CLKH generated in the period Ts2 corresponding to the next reference period Ts adjacent to the first reference period Ts.
Thus, the number of clocks of the high-speed clock CLKH in each reference period Ts related to the high-speed clock CLKH generated in the period of the period variation period Tx corresponding to the plurality of reference periods Ts from the start of the generation of the high-speed clock CLKH can be easily calculated as the reference clock number Ms. Further, since the reference clock number Ms can be calculated by the time measuring apparatus 10, an additional operation for calculating the reference clock number Ms is not required, and the system configuration required for time measurement can be greatly simplified.
In the present embodiment, the measurement processing circuit 12 may be provided with a first reference clock measurement circuit 14A and a second reference clock measurement circuit 14B, the first reference clock measurement circuit 14A may measure, as a first reference clock number Ms1, the number of clocks of the high-speed clock CLKH generated in a period Ts1 corresponding to the first reference period Ts from a clock generation start time point t0 in the high-speed clock generation circuit 11B, and the second reference clock measurement circuit 14B may measure, as a second reference clock number Ms2, the number of clocks of the high-speed clock CLKH generated in a period Ts2 corresponding to the next reference period Ts after the first reference period Ts.
With this configuration, the first reference clock number Ms1 and the second reference clock number Ms2 required for calculation of the reference clock number Ms in the reference clock calculation circuit 15 can be measured with an extremely simple circuit configuration.
In the present embodiment, the reference clock calculation circuit 15 may calculate the reference clock number Ms by performing multiply-accumulate operation on the first reference clock number Ms1 and the second reference clock number Ms2 by using the weights w1 and w 2.
Specifically, the reference clock calculation circuit 15 may calculate the reference clock number Ms by the above equation (3) when the first reference clock number is Ms1, the second reference clock number is Ms2, and weights of Ms1 and Ms2 are w1 and w 2.
This allows the reference clock number Ms to be calculated by extremely simple arithmetic processing.
Second embodiment
Next, a time measuring device 10 according to a second embodiment of the present invention will be described.
In the first embodiment, a case will be described in which, when the reference clock count Ms is calculated in the reference clock calculation circuit 15, weights of the first reference clock count Ms1 and the second reference clock count Ms2 are set to w1 and w2, and the reference clock count Ms is calculated by the product accumulation operation shown in the above formula (3).
In the present embodiment, a case will be described in which the reference clock calculation circuit 15 calculates the reference clock number Ms using the difference between the first reference clock number Ms1 and the second reference clock number Ms2 as the calculation process of the reference clock number Ms. In the time measurement device 10 of the present embodiment, the configuration other than the reference clock calculation circuit 15 and the calculation process of the target period Tm are the same as those of the first embodiment, and a detailed description thereof is omitted here.
[ calculation procedure during object ]
The process of calculating the target period Tm according to the present embodiment will be described with reference to fig. 5. Fig. 5 is a block diagram showing a calculation process during an object of the second embodiment.
In the present embodiment, as a process of calculating the reference clock number Ms, the reference clock calculation circuit 15 calculates the reference clock number Ms by the following expression (4) when the first reference clock number Ms1, the second reference clock number Ms2, the absolute value of the difference between Ms1 and Ms2, ms1-Ms2, and the value larger than 0 and smaller than |ms1-Ms2 are set as the coefficient m.
[ math figure 6]
Ms＝(Ms1+Ms2-|Ms1-Ms2|)/2+m
Here 0 < m < |Ms1-Ms2| … (4)
Effect of the second embodiment
Thus, the present embodiment is as follows: the reference clock calculation circuit 15 calculates the reference clock number Ms by the above equation (4) when the first reference clock number Ms1, the second reference clock number Ms2, the absolute value of the difference between Ms1 and Ms2, and the value larger than 0 and smaller than |m1 to m2| are each represented by the coefficient m.
Thus, by adjusting the coefficient m in the range of 0 < m < |m1-m2|, the number of clocks located in the middle between the first reference clock number Ms1 and the second reference clock number Ms2 can be calculated as the reference clock number Ms, and the calculation processing load of the reference clock number Ms can be reduced.
Extension of the embodiment
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the embodiments. Various modifications, which can be understood by a practitioner, can be made in the constitution or detail of the present invention within the scope of the present invention. The embodiments may be arbitrarily combined and implemented within a range not contradictory to each other.
Claims (7)
1. A time measurement device, comprising:
a low-speed clock generation circuit that generates a low-speed clock at a fixed reference period;
a high-speed clock generation circuit that generates a high-speed clock at a higher speed than the low-speed clock; and
a measurement processing circuit that counts the low-speed clock and the high-speed clock according to a measurement start time point and a measurement end time point of an input object period, and measures a time length of the object period according to an obtained count result;
the measurement processing circuit includes:
a low-speed clock counter that counts, with the low-speed clock, a summary period from the measurement start time point to a measurement elapsed time point that arrives after the measurement end time point in synchronization with the reference period;
a high-speed clock counter that counts an excess period from the measurement end time point to the measurement elapsed time point by using the high-speed clock generated by the high-speed clock generation circuit at the measurement end time point;
a memory circuit that stores a reference clock number indicating the number of clocks of the high-speed clock in each of the reference periods; and
a time calculation circuit that calculates a time length of the object period based on count results of the low-speed clock counter and the high-speed clock counter, the reference clock number, and a time length of the reference period;
the reference clock number is the number of clocks of the high-speed clock generated in each reference period during a period corresponding to a period variation of a plurality of the reference periods after the high-speed clock is generated,
the measurement processing circuit further includes a reference clock calculation circuit that calculates, as the reference clock number, a clock number located intermediate between a first reference clock number indicating the number of clocks of the high-speed clock generated during a period corresponding to a first reference period from a clock generation start time point in the high-speed clock generation circuit and a second reference clock number indicating the number of clocks of the high-speed clock generated during a period corresponding to a next reference period adjacent to the first reference period.
2. The apparatus according to claim 1, wherein,
the time calculation circuit calculates the number of the low-speed clocks in the excess period based on the count results of the low-speed clock counter and the high-speed clock counter and the reference clock number, calculates the time length of the excess period based on the obtained low-speed count number and the time length of the reference period, and calculates the time length of the object period by subtracting the time length of the excess period from the time length of the summary period.
3. The apparatus according to claim 1, wherein,
the measurement processing circuit further includes:
a first reference clock measurement circuit that measures, as the first reference clock number, the number of clocks of the high-speed clock generated in a period corresponding to an initial reference period from a clock generation start time point in the high-speed clock generation circuit; and
and a second reference clock measurement circuit configured to measure, as the second reference clock number, the number of clocks of the high-speed clock generated during a period corresponding to a next reference period after the first reference period.
4. The apparatus according to claim 1, wherein,
the reference clock calculation circuit performs multiply-accumulate operation on the first reference clock number and the second reference clock number by using respective weights, thereby calculating the reference clock number.
5. The apparatus according to claim 1, wherein,
the reference clock calculation circuit calculates the reference clock number Ms by the following equation when the first reference clock number is Ms1, the second reference clock number is Ms2, and weights of Ms1 and Ms2 are w1 and w2,
Ms＝w1×Ms1+w2×Ms2
here w1+w2=1.
6. The apparatus according to claim 1, wherein,
the reference clock calculation circuit calculates the reference clock number Ms by the following equation, when the first reference clock number is Ms1, the second reference clock number is Ms2, the absolute value of the difference between Ms1 and Ms2 is |M1-Ms 2|, and the value larger than 0 and smaller than |M1-Ms 2| is m,
Ms＝(Ms1+Ms2-|Ms1-Ms2)/2+m
here 0 < m < |Ms1-Ms2|.
7. A time measurement method used in a time measurement device that includes a low-speed clock generation circuit, a high-speed clock generation circuit, and a measurement processing circuit and measures a time length of an input object period, the time measurement method comprising:
a low-speed clock generation step of generating a low-speed clock at a fixed reference period by the low-speed clock generation circuit;
a high-speed clock generation step of generating a high-speed clock at a higher speed than the low-speed clock by the high-speed clock generation circuit; and
a measurement processing step of counting the low-speed clock and the high-speed clock according to a measurement start time point and a measurement end time point of the object period, and measuring a time length of the object period according to the obtained count result;
the measurement processing step includes:
a low-speed clock counting step of counting the low-speed clock during a period from the measurement start time point to a measurement elapsed time point synchronized with the reference period, which comes after the measurement end time point;
a high-speed clock counting step of counting the high-speed clock during a period from the measurement end time point to the measurement elapsed time point;
a storage step of storing a reference clock number indicating the number of clocks of the high-speed clock in each of the reference periods; and
a time calculation step of calculating a time length of the object period based on the count results of the low-speed clock count step and the high-speed clock count step, the reference clock count, and the time length of the reference period;
the reference clock number is the number of clocks of the high-speed clock generated in each reference period during a period corresponding to a period variation of a plurality of the reference periods after the high-speed clock is generated,
the measurement processing circuit includes a reference clock calculation circuit that calculates, as the reference clock number, a clock number located intermediate between a first reference clock number indicating the number of clocks of the high-speed clock generated during a period corresponding to an initial reference period from a clock generation start time point in the high-speed clock generation circuit and a second reference clock number indicating the number of clocks of the high-speed clock generated during a period corresponding to a next reference period adjacent to the initial reference period.
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