JP4193102B2 - Physical quantity measuring device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a physical quantity measuring device, and more particularly to a physical quantity measuring device in which a pulse counter for counting a sensor vibration frequency that changes in accordance with a physical quantity is improved.
[0002]
[Prior art]
As shown in FIG. 6, the conventional physical quantity measuring device detects a physical quantity P such as differential pressure / pressure, flow rate, temperature, etc. as a distortion, and counts a counter with a pulse train signal Fc corresponding to the magnitude of the physical quantity P. The counter includes a count calculation unit 110 that calculates a physical quantity Pcalc based on the counted value.
[0003]
The count calculation unit 110 includes a sensor / driver circuit 111, a count circuit 112 including a counter and a register, a computer CPU (113) that calculates a frequency F and a physical quantity Pcalc, and a crystal oscillator 114.
[0004]
The sensor / driver circuit 111 includes a vibrator that oscillates at a frequency corresponding to the magnitude of the physical quantity P and an oscillation circuit that detects the physical quantity P as distortion, and outputs it as a pulse train signal Fc having the vibrator frequency. To do.
[0005]
As shown in FIG. 7, the counting circuit 112 includes a control unit 121, an Fc counter 122, an MCLK counter 123, an Fc register 124, and an MCLK register 125. The crystal oscillator 114 (see FIG. 6) within a certain period of time. ) And the Fc signal from the sensor / driver circuit 111 (see FIG. 6) are counted and output as MCLK count value M and Fc count value N.
[0006]
The MCLK counter 123 and the Fc counter 122 are 8- to 32-bit free-run counters that count rising edges of the reference clocks MCLK and Fc signals, respectively.
[0007]
The values of these counters are latched every time at the falling edge of the reference clock MCLK immediately after the rising edge of the count allowable signal GATE and immediately after the rising edge of the Fc signal. Simultaneously with the latch, a read request signal IRQ is generated to issue a count value Read request to the computer CPU (113) (see FIG. 6).
[0008]
The reference clock MCLK is a pulse train of several MHz from the crystal oscillator 114, and the pulse train signal Fc is a pulse train of tens to hundreds of kHz from the sensor / driver circuit 111. The count allowable signal GATE is a signal of several tens to several hundreds msec for counting the reference clock MCLK and the pulse signal Fc for about GATE 1 pulse.
[0009]
The read request signal IRQ is a count value (within a register) Read request signal to the computer CPU (113). DataBus is a data bus for transmitting a count value to the computer CPU (113).
[0010]
The computer CPU (113) receives the MCLK count value M and the Fc count value N, which are the number of pulses of the counting circuit 112, and calculates the vibration frequency of the vibrator according to the physical quantity P by the following equation.
[0011]
Frequency fcalc = N / (M / fmclk) = fmclk × (N / M) (1)
fmclk; natural frequency N of crystal oscillator; Fc count value M; MCLK count value
Although not shown in the figure, the pulse having the frequency fcal is counted from the frequency fcalc thus obtained, and the physical quantity Pcalc is calculated by D / A conversion.
[0013]
Now, the operation of the physical quantity measuring apparatus provided with such a count calculation unit 110 will be described below with reference to FIGS. 6 and 7 and the timing chart shown in FIG.
[0014]
First, the MCLK counter 123 and the Fc counter 122 are free counters that count the rising edges of the reference clock MCLK and the Fc signal, respectively, but the count value is the rising edge of the signal Fc immediately after the rising edge (point A) of the count allowable signal GATE. Latched at the falling edge (point C) of the reference clock MCLK immediately after point B).
[0015]
Then, a read request signal IRQ is generated simultaneously with each latch, and a count value Read request is issued to the computer CPU (113). When the computer CPU (113) completes Read, the read request signal IRQ is turned off.
[0016]
Here, if the respective values latched at a certain rise are Mk + 1 and Nk + 1, the count values of the MCLK counter and the Fc counter counted in 1 GATE (counting time) are Mk + 1−Mk and Nk + 1−Nk, respectively.
Therefore, the above equation (1) can be transformed into the following equation (2).
[0017]
Frequency fcalc
= Fmclk × (Nk + 1−Nk) / (Mk + 1−Mk) (1)
It becomes.
[0018]
Here, {(Mk + 1−Mk) / fmclk} indicates a time for receiving (Nk + 1−Nk) Fc signal pulses, and is the most accurate time in the circuit formed by the reference clock MCLK. Depends on the value of the pulse train signal Fc.
[0019]
Further, if the GATE period is increased, the values of (Mk + 1−Mk) and (Nk + 1−Nk) can be increased. Therefore, fluctuations in the pulse train signal Fc are averaged and decreased, and the weight of the count error of the MCLK counter (1 / (Mk + 1−Mk) also becomes smaller.
[0020]
[Problems to be solved by the invention]
However, in the pulse counter in the physical quantity measuring device described in the prior art, there is a particular fluctuation (fluctuation) of the frequency fcalc.
[0021]
The oscillation (fluctuation) of the frequency fcalc finally appears as a fluctuation of the physical quantity that is the output of the measuring apparatus.
There are the following two causes of the oscillation of the frequency fclac.
(1) Fc signal fluctuation in the pulse train, which is generated by random noise generated in the sensor and the excitation circuit.
(2) There is a limit on the resolution of the counter, which is due to the dependence on the clock (pulse width) of the crystal oscillator.
[0022]
As a countermeasure against these (1) and (2), there is a method in which the period of the count allowable signal GATE is made longer and the MCLK counter value M and the Fc counter value N are counted more. As a result, a time average can be taken for the Fc signal with fluctuation, and the influence of the MCLK count error can be reduced.
[0023]
However, if the cycle of the count allowance signal GATE is made longer, the frequency / physical quantity update cycle (dead time) becomes longer and the response becomes slower. On the other hand, if the cycle of the count allowable signal GATE is shortened, the output of the measuring device fluctuates, leading to deterioration in accuracy.
[0024]
At present, measuring devices are often required to have a high accuracy of 0.1% or less, but the period of the count allowable signal GATE for realizing this is about several hundreds msec. On the other hand, as a response speed of the measuring apparatus, a demand of 100 msec or less is increasing.
[0025]
As a countermeasure for the above (2), there is a method of using a crystal oscillator having a high frequency, but there is a problem that a high-frequency oscillator cannot be used in a two-wire transmitter having a severe restriction on current consumption.
[0026]
Therefore, a low-frequency crystal oscillator (reference clock) is used and a counter that performs stable frequency counting with a short update cycle is configured with a small circuit scale, realizing a high-resolution and high-speed response physical quantity measuring device for the input quantity. Having problems that must be solved.
[0027]
[Means for Solving the Problems]
In order to solve the above problems, a physical quantity measuring apparatus according to the present invention is configured as follows.
(1) In a physical quantity measuring device including a count calculation unit that counts a counter with a pulse train signal Fc corresponding to the magnitude of the physical quantity P and calculates the physical quantity Pcalc based on the counted value.
The count calculation unit
Sensor / driver means for outputting a frequency corresponding to the magnitude of the physical quantity P as a pulse train signal Fc;
Fc counter means for starting counting with the pulse train signal Fc;
A plurality of MCLK counter means for starting counting with the reference clock immediately after each generation of the pulse train signal Fc;
A physical quantity Pcalc obtained by dividing an average value obtained by adding the respective MCLK count values counted by the plurality of MCLK counter means by a natural frequency by the Fc count value counted by the Fc counter means is generated. Physical quantity generation means;
A physical quantity measuring device comprising:
(2) In a physical quantity measuring device including a count calculation unit that counts a counter with a pulse train signal Fc corresponding to the magnitude of the physical quantity P and calculates the physical quantity Pcalc based on the counted value.
The count calculation unit
Sensor / driver means for outputting a frequency corresponding to the magnitude of the physical quantity P as a pulse train signal Fc;
Counter counting permission means for controlling the counting time of the counter;
Fc counter means for starting counting with the pulse train signal Fc;
MCLK counter means for starting counting with a reference clock MCLK immediately after the pulse train signal Fc signal every time the pulse train signal Fc is generated;
.., I generated by the counter counting permission means, every time the MCLK counter value counted by the MCLK counter means is divided by the natural frequency, the Fc counter means counts the value. It was divided by Fc count value to generate a unique physical amount obtained in advance have been set the counting allowable signal GATE1,2, · · ·, when the number of occurrences of i is completed, by averaging the unique physical quantity Generating means for generating a physical quantity Pcalc,
A physical quantity measuring device comprising:
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Next, various embodiments of the physical quantity measuring device according to the present invention will be described with reference to the drawings.
[0029]
As shown in FIG. 1, the physical quantity measuring apparatus according to the first embodiment of the present invention detects a physical quantity P such as differential pressure / pressure, flow rate, temperature, etc. as a strain, and a pulse train corresponding to the magnitude of the physical quantity P. The counter is counted by the signal Fc, and the count calculation unit 10 that calculates the physical quantity Pcalc based on the counted value is provided.
[0030]
The count calculation unit 10 generates a pulse train signal Fc and outputs a frequency corresponding to the magnitude of the physical quantity P, and outputs the pulse train signal Fc from the sensor / driver circuit 11 as a sensor / driver circuit. A counting circuit 12 having a counter and a register for inputting and counting, a crystal oscillator 14 for supplying a reference clock MCLK to the counting circuit 12, and an MCLK counter value M and an Fc counter value N obtained by the counting circuit 12 are input. And a computer CPU (13) for calculating the frequency F and the pressure value Pcalc.
[0031]
As shown in FIG. 2, the counting circuit 12 receives the count value Read signal, the read request signal ACK, the count allowable signal GATE, and the Fc signal from the computer CPU (13) (see FIG. 1), and is controlled by the reference clock MCLK. .., I (24, 25, 26,...), A control unit 21 that performs counting, an Fc counter 22 that counts based on an Fc signal, an MCLK counter 23 that counts based on a reference clock MCLK, an Fc register 24 27) and an AND gate.
[0032]
Among them, the Fc counter 22 and the Fc register 24 constitute an Fc counter means, and the MCLK counter 23 and the plurality of MCLK registers 1, 2,..., I (25, 26, 27) constitute a plurality of MCLK counter means. [0033]
The computer CPU (13) is obtained by dividing the average value obtained by adding the respective MCLK count values counted by the plurality of MCLK counter means by the natural frequency, and dividing by the Fc count value counted by the Fc counter means. Physical quantity generating means for generating the physical quantity Pcalc.
[0034]
Next, the operation of the physical quantity measuring apparatus having such a configuration will be described below with reference to FIGS. 1 and 2 and the flowchart shown in FIG.
[0035]
First, the Fc register 24 and the MCLK register 1 (25) have the falling edge (point C) of the reference clock MCLK immediately after the rising edge (point B) immediately after the rising edge (point A) of the count allowable signal GATE. Then, the values of the MCLK counter 23 and the Fc counter 23 are latched.
[0036]
The MCLK register 2 (26) receives the MCLK counter 23 at the falling edge (point E) of the reference clock MCLK immediately after the rising edge (point D) of the second Fc signal after the rising edge (point A) of the count allowable signal GATE. The value of is latched.
[0037]
The MCLK register i (27) sets the MCLK counter 23 at the falling edge (point G) of the reference clock MCLK immediately after the rising edge (point F) of the i-th Fc signal after the rising edge (point A) of the count allowable signal GATE. Latch the value.
[0038]
Then, after latching the MCLK counter 23 in the MCLK registers 1, 2,..., I (25, 26, 27) until the rising edge (point i) of the Fc signal in this way, the data is read out to the computer CPU (13). A request signal IRQ is transmitted, and the Fc register 24 and MCLK registers 1, 2,..., I (25, 26, 27) on the data bus are transmitted.
[0039]
In the computer CPU (13), a value obtained by dividing the average value obtained by adding the respective MCLK count values of the MCLK registers 1, 2,..., I (25, 26, 27) by the natural frequency by the physical quantity generation means is calculated as Fc. A physical quantity Pcalc obtained by dividing by the Fc count value of the register 24 is generated.
[0040]
In this way, the number of MCLK counters that are counters of the reference clock MCLK is set to one, and a plurality of registers that are latched at different timings are prepared, thereby reducing the circuit scale and wiring of the reference clock MCLK as much as possible. By suppressing it, current consumption can be reduced.
[0041]
Here, the values of the Fc register 24, MCLK register 1 (25),..., MCLK register i (27) latched by the Fc signal at the rising edge (point A) of the first count allowable signal GATE are Nk, M1k, and Mik. To do.
[0042]
When the values of the Fc register 24, MCLK register 1 (25),..., MCLK register i (27) latched by the Fc signal at the rising edge (H point) of the next count allowable signal GATE are Nk + 1, M1k + 1, Mik + 1, vibration The formula for calculating the frequency of the child can be calculated by the following formula (3).
[0043]
fclac = fmclk × (N k + 1- N k) / {{(M 1k + 1- M 1k) + (M 2k + 1- M 2k) +, ..., + (M ik + 1- M ik)} / i} ... Equation (3)
[0044]
Since the frequency of the Fc signal is around several hundreds to several hundreds of kHz, the data is latched in the MCLK registers 1, 2,..., I (25, 26, 27) with a shift of several tens to several hundreds of μs.
[0045]
On the other hand, since the cycle of the count allowable signal GATE is several tens to several hundreds of ms, if the number i of the MCLK registers 1, 2,..., I (25, 26, 27) is about 10, then within one count allowable signal GATE. A series of operations is completed.
[0046]
That is, if a maximum of 10 registers are provided and the average value is the MCLK count value, so-called fluctuations in the Fc signal are averaged and stable frequency counting can be performed.
[0047]
As described above, the fluctuation of the frequency generated in the sensor and the vibration circuit is due to random noise. If the above equation (3) is used to calculate from the data latched at the frequency timing, the equation ( In 2), the same fluctuation reduction effect as when the gate time is multiplied by i can be obtained.
[0048]
The diagram shown in FIG. 4 shows changes in the frequency fluctuation of the vibrator when the number of registers is increased. The reference clock is 2 MHz, the Fc signal is 100 kHz, and the count allowable signal GATE is 40 msec. This is a graph of the state of vibration width when
[0049]
This figure means that when the number of registers increases from one to two, the vibration width decreases rapidly, and when the number of registers increases from three to seven, the vibration width gradually decreases. Even if the number of registers continues to decrease to about 10 and the number of registers ahead increases, the vibration width does not decrease much. Ideally, the number of registers is up to 10 and preferably about 8 to 10.
[0050]
In this way, in the present invention, there is one MCLK counter that is a counter of the reference clock MCLK, and a plurality of registers (MCLK registers 1, 2,..., I (25, 26, 27) that latch at different timings relative thereto. ), The current consumption can be reduced by reducing the circuit scale and suppressing the wiring of the reference clock MCLK as much as possible.
[0051]
Next, a physical quantity measuring apparatus according to a second embodiment of the present invention will be described with reference to the drawings. The overall configuration of the physical quantity measuring device is the same as that shown in FIG. 1, and only the counting circuit is different, so only the counting circuit will be described.
As shown in FIG. 5, the counting circuit that constitutes the physical quantity measuring device of the second embodiment uses the values of the Fc counter and the MCLK counter of the plurality of count allowable signals GATE1, 2,. The control unit 21A, 21B, 21C, Fc counter 1, 2,..., I (22A, 22B, 22C), MCLK counter 1, 2, ..., i (23A, 23B, 23C) , I (24A, 24B, 24C) and MCLK registers 1, 2,..., I (25A, 25B, 25C).
[0053]
In such a configuration, in the case of the count allowance signal GATE1, the count value of the Fc counter 1 (22A) is latched in the Fc register 1 (24A), and the count value of the MCLK counter 1 (23A) is the MCLK register 1 (25A). ) Is latched.
[0054]
Similarly, in the case of the next count allowable signal GATE2, the count value of the Fc counter 2 (22B) is latched in the Fc register 2 (24B), and the count value of the MCLK counter 2 (23B) is stored in the MCLK register 2 (25B). Latched.
[0055]
In the case of the next count permission signal GATEi, the count value of the Fc counter i (22C) is latched in the Fc register i (24C), and the count value of the MCLK counter i (23C) is stored in the MCLK register i (25C). Latched.
[0056]
In this way, the contents of the plurality of registers are averaged by transmitting the read request signal IRQ to the computer CPU after all the count values in the count allowance signals GATE1, 2,..., I are latched in the registers. A physical quantity Pcalc is generated.
[0057]
In this way, if the circuit scale and current consumption are not severely limited, it is possible to prepare a plurality of counter / register pairs, a plurality of count permission signals GATE that allow the counter to be counted, and a minute time offset. The same thing as the first embodiment is obtained.
[0058]
【The invention's effect】
As described above, the physical quantity measuring device according to the present invention has a pulse train signal having fluctuations by latching a counter having a short counting time, that is, a counter counted by the reference clock MCLK, by shifting the value a plurality of times with a minute shift. A time averaged value for Fc can be obtained. This means that a counter that uses a low-frequency reference clock MCLK and performs stable frequency counting in a short update cycle can be configured with a small circuit scale, and a physical quantity measuring device that can perform high-resolution and high-speed response to input physical quantities can be realized. effective.
[Brief description of the drawings]
FIG. 1 is a block diagram of a count calculation unit constituting a physical quantity measuring device according to the present invention.
FIG. 2 is a block diagram of a counting circuit constituting the count calculation unit.
FIG. 3 is a timing chart of the count calculation unit.
FIG. 4 is a graph showing the relationship between the number of counters and the vibration width.
FIG. 5 is a block diagram of a counting circuit constituting the count calculation unit.
FIG. 6 is a block diagram of a count calculation unit that constitutes a physical quantity measuring device in the prior art.
7 is a block diagram of a counting circuit that constitutes the count calculation unit in FIG. 6. FIG.
8 is a timing chart of the count calculation unit in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Count calculation part 11 Sensor / driver circuit 12 Count circuit 12A Count circuit 13 Computer 14 Crystal oscillator 21 Control part 21A Control part 1
21B Control unit 2
21C Control unit i
22 Fc counter 22A Fc counter 1
22B Fc counter 2
22C Fc counter i
23 MCLK counter 23A MCLK counter 1
23B MCLK counter 2
23C MCLK counter i
24 Fc register 24A Fc register 1
24B Fc register 2
24C Fc register i
25 MCLK register 1
25A MCLK register 1
25B MCLK register 2
25C MCLK register i
26 MCLK register 2
27 MCLK register i

Claims (2)

In a physical quantity measuring device including a count calculation unit that counts a counter with a pulse train signal Fc corresponding to the magnitude of the physical quantity P and calculates the physical quantity Pcalc based on the counted value,
The count calculation unit
Sensor / driver means for outputting a frequency corresponding to the magnitude of the physical quantity P as a pulse train signal Fc;
Fc counter means for starting counting with the pulse train signal Fc;
A plurality of MCLK counter means for starting counting with the reference clock immediately after each generation of the pulse train signal Fc;
A physical quantity Pcalc obtained by dividing an average value obtained by adding the respective MCLK count values counted by the plurality of MCLK counter means by a natural frequency by the Fc count value counted by the Fc counter means is generated. A physical quantity measuring device. In a physical quantity measuring device including a count calculation unit that counts a counter with a pulse train signal Fc corresponding to the magnitude of the physical quantity P and calculates the physical quantity Pcalc based on the counted value,
The count calculation unit
Sensor / driver means for outputting a frequency corresponding to the magnitude of the physical quantity P as a pulse train signal Fc;
Counter counting permission means for controlling the counting time of the counter;
Fc counter means for starting counting with the pulse train signal Fc;
MCLK counter means for starting counting with a reference clock MCLK immediately after the pulse train signal Fc signal every time the pulse train signal Fc is generated;
.., I generated by the counter counting permission means, every time the MCLK counter value counted by the MCLK counter means is divided by the natural frequency, the Fc counter means counts the value. It was divided by Fc count value to generate a unique physical amount obtained in advance have been set the counting allowable signal GATE1,2, · · ·, when the number of occurrences of i is completed, by averaging the unique physical quantity Generating means for generating a physical quantity Pcalc,
A physical quantity measuring device comprising:

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