JP7210356B2 - sense amplifier circuit - Google Patents

Description

The present invention relates to sense amplifier circuits.

A semiconductor memory device that stores 1-bit data using a memory cell composed of a pair of transistors (hereinafter also referred to as a pair of cells) is known (for example, Patent Document 1). In a sense amplifier circuit for reading data from memory cells of such a semiconductor memory device, a pair of bit lines are connected to respective drain terminals of transistors forming a pair of cells. The pair of bit lines are each connected to a power supply line via, for example, an on-state PMOS transistor, and charged to the voltage level of the power supply voltage. When the amplifier starts operating, the PMOS transistors are turned off, disconnecting the pair of bit lines from the power supply and discharging through the pair of cells.

Assuming that the positive cell of the pair of cells has an expected value of 1 and the complementary cell has an expected value of 0, the cell with an expected value of 1 flows more current than the cell with an expected value of 0, so the voltage drops. is fast. Therefore, of the transistors connected to each of the pair of output nodes of the sense amplifier circuit, the transistor connected to the bit line on the positive cell side is turned on before the transistor connected to the bit line on the complementary cell side. current begins to flow, and the voltage level at the positive output node rises. The output node on the positive side is connected to the output terminal of the amplifier output via an inverter, and when the voltage level exceeds the threshold of the inverter, the output of the logic value obtained by inverting the voltage of the output node is determined as the amplifier output.

JP 2018-181390 A

However, in the sense amplifier circuit as described above, since the charge voltage of each bit line drops significantly due to the influence of parasitic capacitance during discharge, the drain voltage of each of the transistors forming a pair of cells drops, resulting in a decrease in cell current. , the read margin becomes smaller. In particular, when an operation at a low voltage is required, almost no cell current flows, so there is no margin, and there is a problem that a stable read operation cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a sense amplifier circuit capable of realizing stable expected value determination.

A sense amplifier circuit according to the present invention is a memory cell comprising a first cell storing data and a second cell storing complementary data of the data, and a first bit connected to the first cell. and a second bit line connected to the second cell, wherein in a first period, which is a period before the start of data reading, the first bit line is read. and the second bit line, and during a second period, which is a period after the start of data reading, the supply of the ground potential to the first bit line and the second bit line is stopped. The data value of the data stored in the first cell is determined based on the bit line voltage control unit to be stopped and the voltage of the first bit line and the voltage of the second bit line in the second period. a first transistor of a first conductivity type having one end supplied with a power supply voltage in the second period and having the other end connected to the first bit line; , the second transistor of the first conductivity type having one end supplied with the power supply voltage in the second period and the other end connected to the second bit line; and the control end of the second transistor. , a first output node having a voltage corresponding to a current flowing in a current path including a connecting portion between the first transistor and the first bit line; a control end of the first transistor; a second output node having a voltage corresponding to a current flowing through a current path including a connection portion between the transistor and the second bit line, the voltage of the first output node and the second output; The data value of the data stored in the first cell is determined based on the node voltage .

According to the sense amplifier circuit of the present invention, stable expected value determination can be realized.

3 is a circuit diagram showing the configuration of the sense amplifier circuit of the embodiment; FIG. 4 is a time chart showing read operation by the sense amplifier circuit of the embodiment; 3 is a circuit diagram showing the configuration of a sense amplifier circuit of a comparative example; FIG. 4 is a time chart showing a read operation by a sense amplifier circuit of a comparative example;

Preferred embodiments of the present invention are described in detail below. In the following description of the embodiments and the attached drawings, substantially the same or equivalent parts are denoted by the same reference numerals.

FIG. 1 is a circuit diagram showing the configuration of the sense amplifier circuit 100 of this embodiment. The sense amplifier circuit 100 includes a determination section 11, bit line voltage control sections 12A and 12B, and latch sections 13A and 13B. The sense amplifier circuit 100 also has a terminal (BL terminal) connected to the bit line BL and a terminal (BLC terminal) connected to the bit line BLC. The bit line BL is connected to the drain terminal of a first transistor (not shown) forming a positive cell for storing 1-bit data. The bit line BLC is connected to the drain terminal of a second transistor (not shown) forming a complementary cell storing complementary data of the 1-bit data.

The determination unit 11 is a determination unit that determines the value of data read from a memory cell composed of a first transistor and a second transistor. The determination unit 11 includes transistors PM0, PM1, PM2, PM3 and PM4 which are P-channel MOSFETs, and transistors NM1, NM2, MM3 and NM4 which are N-channel MOSFETs.

The transistor PM0 has a source connected to a power supply line (power supply voltage VDD) of the VDD power supply, and a drain connected to the sources of the transistors PM1 and PM2. An amplifier enable signal SAEB is supplied to the gate of the transistor PM0.

The amplifier enable signal SAEB is a signal whose signal level changes between logic level 0 and logic level 1. FIG. In the following description, the signal level of logic level 0 is called "L" level, and the signal level of logic level 1 is called "H" level.

The transistor PM0 is turned on when the amplifier enable signal SAEB is at "L" level, and connects between the sources of the transistors PM1 and PM2 and the power supply line of the VDD power supply. The transistor PM0 is turned off when the amplifier enable signal SAEB is at "H" level, and disconnects the sources of the transistors PM1 and PM2 from the power supply line of the VDD power supply.

The sources of transistors PM1 and PM2 are connected together and to the drain of transistor PM0. The drain of transistor PM1 is connected to bit line BL. The drain of transistor PM2 is connected to bit line BLC. A gate of the transistor PM2 is connected to an output node S, which is a node serving as a first output terminal of the determination section 11 . A gate of the transistor PM1 is connected to an output node SN, which is a node serving as a second output terminal of the determination section 11 .

The source of the transistor PM3 is connected to the drain of the transistor PM1 and also to the bit line BL. The source of the transistor PM4 is connected to the drain of the transistor PM2 and also to the bit line BLC. A drain of the transistor PM3 is connected to the output node S. The drain of transistor PM4 is connected to output node SN.

Gates of transistors PM3 and PM4 are connected to each other and receive an amplifier enable signal SAEB. The transistors PM3 and PM4 are turned on when the amplifier enable signal SAEB is at "L" level, and turned off when the amplifier enable signal SAEB is at "H" level.

A drain of the transistor NM1 is connected to the output node S. The drain of transistor NM2 is connected to output node SN. A power supply voltage VDD is supplied to each gate of the transistors NM1 and NM2.

The sources of each of transistors NM3 and NM4 are grounded. The drain of transistor NM3 is connected to the source of transistor NM1. The drain of transistor NM4 is connected to the source of transistor NM2. The gate of the transistor NM3 is connected to the gate of the transistor NM1 and receives the power supply voltage VDD. The gate of the transistor NM4 is connected to the gate of the transistor NM2 and receives the power supply voltage VDD.

The bit line voltage control units 12A and 12B switch the supply and stop of the supply of the ground potential VSS to the bit lines BL and BLC (that is, connection and disconnection with the ground line) to control the bit lines BL and the bit lines. It controls the voltage of the line BLC.

The bit line voltage controller 12A is composed of a transistor NM5, which is an N-channel MOSFET. The transistor NM5 has a source grounded and a drain connected to the bit line BL. A discharge signal PRENB is supplied to the gate of the transistor NM5. The bit line voltage controller 12B is composed of a transistor NM6, which is an N-channel MOSFET. The transistor NM6 has a source grounded and a drain connected to the bit line BLC. A discharge signal PRENB is supplied to the gate of the transistor NM6.

The transistor NM5 is turned on when the signal level of the discharge signal PRENB is "H" level, and fixes the bit line BL to the ground potential VSS. Further, the transistor NM5 is turned off when the signal level of the discharge signal PRENB is "L", and disconnects the bit line BL from the ground potential VSS. Similarly, the transistor NM6 is turned on when the signal level of the discharge signal PRENB is "H" level, and fixes the bit line BLC to the ground potential VSS. Further, the transistor NM6 is turned off when the signal level of the discharge signal PRENB is "L", and disconnects the bit line BLC from the ground potential VSS.

The latch section 13A is a latch circuit section that holds a signal having a voltage level corresponding to the voltage of the output node S and outputs it as an output data signal RD_LATB. The latch section 13A is composed of, for example, inverters INV0 and INV1. The input end of the inverter INV1 is connected to the output node S. The input end of the inverter INV0 is connected to the output end of the inverter INV1. The output terminal of the inverter INV0 is connected to an output terminal for outputting the output data signal RD_LATB. When the voltage of the output node S exceeds the threshold value of the inverter INV1, data with a signal level reflecting the voltage of the output node S is output as the output data signal RD_LATB.

The latch unit 13B is a latch circuit unit that holds a signal having a voltage level corresponding to the voltage of the output node SN and outputs it as an output data signal RD_LAT. The latch section 13B is composed of inverters INV2 and INV3, for example. The input terminal of the inverter INV2 is connected to the output node SN. The input end of the inverter INV3 is connected to the output end of the inverter INV2. The output terminal of the inverter INV3 is connected to an output terminal for outputting the output data signal RD_LAT. When the voltage of the output node SN exceeds the threshold value of the inverter INV2, data with a signal level reflecting the voltage of the output node SN is output as the output data signal RD_LAT.

Next, the data read operation of the sense amplifier circuit 100 of this embodiment will be described with reference to the time chart of FIG. Here, the expected value of the positive cell (ie, the first transistor) connected to the bit line BL is 1, and the expected value of the complementary cell (ie, the second transistor) connected to the bit line BLC is 0. A case will be described.

The read start signal READ and the standby signal READY are supplied to a control circuit (not shown) provided outside the sense amplifier circuit 100, for example. While the read start signal READ is at "L" level and the standby signal READY is at "H" level, the sense amplifier circuit 100 is set in the standby state.

During this standby period (period up to time T1 in FIG. 2), the amplifier enable signal SAEB and the discharge signal PRENB are controlled to be at "H" level. The transistors NM5 and NM6 are kept on by receiving the "H" level discharge signal PRENB at their gates. The bit lines BL and BLC are grounded and fixed at the ground potential VSS.

When the read start signal READ becomes "H" level, the standby signal READY becomes "L" level, then the amplifier enable signal SAEB becomes "L" level (time T2 in FIG. 2), and the discharge signal PRENB becomes "L" level (time T2). It changes sequentially to time T3) in FIG.

When the amplifier enable signal SAEB becomes "L" level, the determination section 11 of the sense amplifier circuit 100 starts operating. The transistor PM0 is turned on by receiving the "L" level amplifier enable signal SAEB at its gate, and the sources of the transistors PM1 and PM2 are connected to the power supply line of the VDD power supply.

Further, the transistor PM3 is turned on by receiving the "L" level amplifier enable signal SAEB at its gate. This connects the bit line BL to the transistors NM1 and NM3 via the transistor PM3. Similarly, the transistor PM4 is turned on by receiving the "L" level amplifier enable signal SAEB at its gate. This connects the bit line BLC to the transistors NM2 and NM4 via the transistor PM4.

On the other hand, the transistors NM5 and NM6 are turned off by receiving the "L" level discharge signal PRENB at their gates. This disconnects the bit line BL and the bit line BLC from the ground potential VSS.

The voltages of the bit lines BL and BLC start to rise due to the current flowing from the VDD power supply line through the transistors PM0 and PM1 (time T4 in FIG. 2).

Since the bit line BL is grounded through the first transistor forming the positive cell with the expected value 1, the current Ip hardly flows through the current path formed by the transistors PM3, NM1 and NM3. Therefore, the voltage of output node S does not rise much and is maintained at a voltage level near ground potential VSS.

On the other hand, since the bit line BLC is grounded via the second transistor forming the complementary cell with the expected value 0, it is in an open state. Therefore, a current Im flows through the current path formed by the transistors PM4, NM2 and NM4. As a result, the voltage of output node SN rises.

Due to the rise in the voltage of the output node SN, the transistor PM1 whose gate is connected to the output node SN is turned off, and no current flows to the bit line BL side. Therefore, the voltage difference between the bit line BL and the bit line BLC and the voltage difference between the output node S and the output node SN increase over time.

When the voltage of the output node SN exceeds the threshold value of the inverter INV2 of the latch section 13B, the output data signal RD_LAT is inverted and reinverted, and the output logical value is determined (after time T5 in FIG. 2). As a result, the sense amplifier circuit 100 outputs an "H" level output data signal RD_LAT and an "L" level output data signal RD_LATB.

As described above, in the sense amplifier circuit 100 of this embodiment, the bit lines BL and BLC are previously fixed to the ground potential VSS, and the positive cell and the complementary cell (that is, the first transistor and the second transistor) are connected during discharging. Using the fact that the cell on the expected value 1 side is grounded, the current flowing through the current path of the determination unit 11 is controlled to determine the data. According to such a configuration, the voltage of the bit line does not drop and the voltage rises to the power supply voltage VDD level, so the decrease in cell current is suppressed, and stable expected value determination can be performed even at a low voltage.

In FIG. 3, unlike the sense amplifier circuit 100 of this embodiment, the bit lines BL and BLC are previously charged to the power supply voltage VDD, and data is obtained by utilizing the difference in voltage change based on the magnitude of the current from the cell during discharge. 3 is a circuit diagram showing the configuration of a sense amplifier circuit 200 of a comparative example for determining whether .

In the sense amplifier circuit 200, the bit line voltage control section 22A is composed of the transistor PM5, which is a P-channel MOSFET, and precharges the bit line BL to the power supply voltage VDD during standby. The bit line voltage controller 22B is also composed of a transistor PM6, which is a P-channel MOSFET, and precharges the bit line BLC to the power supply voltage VDD during standby.

A gate of the transistor PM1 is connected to the bit line BL. A gate of the transistor PM2 is connected to the bit line BLC. The drain of the transistor PM1 is connected to the source of the transistor PM3 and also to the drain of the transistor NM7, which is an N-channel MOSFET. The drain of the transistor PM2 is connected to the source of the transistor PM4 and to the drain of the transistor NM8, which is an N-channel MOSFET.

Each of the transistors NM7 and NM8 has a source grounded and a gate supplied with the amplifier enable signal SAEB. While the signal level of the amplifier enable signal SAEB is at "H" level, the transistors NM7 and NM8 are turned on. As a result, the drains of the transistors PM1 and PM2 are fixed to the ground potential VSS. When the signal level of the amplifier enable signal SAEB becomes "L" level, the transistors NM7 and NM8 are turned off. This disconnects the drains of the transistors PM1 and PM2 from the ground potential VSS.

One of the source and drain of the transistor NM0 is connected to the drain of the transistor PM1 and the source of the transistor PM3, and the other is connected to the drain of the transistor PM2 and the source of the transistor PM4. The gate of transistor NM0 is commonly connected to the gates of transistors PM3 and PM4, and receives amplifier enable signal SAEB.

The transistor NM1 has a source grounded and a drain connected to the drain of the transistor PM3 and the output node S. A gate of the transistor NM1 is connected to the output node SN. The transistor NM2 has a source grounded and a drain connected to the drain of the transistor PM4 and the output node SN. A gate of the transistor NM2 is connected to the output node S.

The transistor NM3 has a source grounded and a drain connected to the output node S. A control signal LATRES is supplied to the gate of the transistor NM3. The transistor NM4 has a source grounded and a drain connected to the output node SN. A control signal LATRES is supplied to the gate of the transistor NM4.

The inverter INV1 has an input terminal connected to the output node S, and outputs a signal having a voltage level obtained by inverting the voltage of the output node S as the output data signal RD_LATB. The inverter INV2 has an input end connected to the output node SN, and outputs a signal having a voltage level obtained by inverting the voltage of the output node SN as the output data signal RD_LAT.

The transistor PM7 has a source connected to the power supply line of the VDD power supply and a gate connected to the output terminal of the inverter INV1. The transistor PM8 has a source connected to the power supply line of the VDD power supply and a gate connected to the output terminal of the inverter INV2.

The transistor PM9 has a source connected to the drain of the transistor PM7 and a drain connected to the output node S. A control signal LATRES is supplied to the gate of the transistor PM9. The transistor PM10 has a source connected to the drain of the transistor PM8 and a drain connected to the output node SN. A control signal LATRES is supplied to the gate of the transistor PM10.

FIG. 4 is a time chart showing a data read operation by the sense amplifier circuit 200 of the comparative example. Here, when the expected value of the positive cell (ie, the first transistor) connected to the bit line BL is 1, and the expected value of the negative cell (ie, the second transistor) connected to the bit line BLC is 0 is assumed.

When the sense amplifier circuit 200 is on standby, the signal level of the discharge signal PRENB is "L" level, and the bit lines BL and BLC are charged to the power supply voltage VDD through the transistors PM5 and PM6.

When the read start signal READ becomes "H" level and the amplifier enable signal SAEB becomes "L" level and the amplifier circuit starts to operate, the bit lines BL and BLC are connected to the transistors forming the positive cell and the negative cell, respectively. Further, when the discharge signal PRENB becomes "H" level, the transistors PM5 and PM6 are turned off, and the bit lines BL and BLC are disconnected from the power supply line of the VDD power supply. As a result, the bit lines BL and BLC are discharged through the transistors forming the positive cell and the negative cell, respectively, and the voltage drops.

The current from the positive cells, which are cells with an expected value of 1, is greater than the current from the negative cells, which are cells with an expected value of 0. Therefore, the bit line BL has a faster discharge speed and a faster voltage drop than the bit line BLC. Therefore, the transistor PM1 whose gate is connected to the bit line BL is turned on before the transistor PM2 whose gate is connected to the bit line BLC, and the current Ip begins to flow, and the voltage level of the output node S rises. continue. When the voltage of the output node S exceeds the threshold of the inverter INV1, a signal having a voltage level inverted from the voltage of the output node S is output as the output data signal RD_LATB.

However, in the sense amplifier circuit 200 of the comparative example, as indicated by the arrows in FIG. 2, the voltages of the bit lines BL and BLC drop greatly due to the parasitic capacitance. As a result, the drain voltage of the transistor forming each cell is lowered, the cell current is reduced, and the read margin is reduced. Therefore, when data is read using the sense amplifier circuit 200 of the comparative example, a stable read operation cannot be performed.

On the other hand, in the sense amplifier circuit 100 of this embodiment, the bit lines BL and BLC are previously fixed to the ground potential VSS during standby as described above. Therefore, the drop in the voltages of the bit lines BL and BLC during discharging does not occur as in the comparative example. Therefore, a decrease in cell current is suppressed, and the voltage of the output node SN rises to the level of the power supply voltage VDD, so that a wide read margin can be secured.

As described above, according to the sense amplifier circuit 100 of this embodiment, stable expected value determination is possible.

It should be noted that the present invention is not limited to those shown in the above embodiments. For example, in the above embodiment, the transistor PM0 is turned on and off by receiving the amplifier enable signal SAEB at its gate. However, the configuration of the portion corresponding to the transistor PM0 is not limited to this, and is composed of switching elements capable of switching connection and disconnection between the power supply line of the VDD power supply and the sources of the transistors PM1 and PM2. It is good if there is.

Further, in the above-described embodiment, an example has been described in which the latch section 13A and the latch section 13B are each composed of inverters connected in series. However, the configuration of the latch section is not limited to this, and may be configured to output binarized signals of the voltages of the output nodes S and SN as the data signals RD_LAT and RD_LATB.

100 sense amplifier circuit 11 determination units 12A and 12B bit line voltage control units 13A and 13B latch units PM0 to PM4 P-channel transistors NM1 to NM6 N-channel transistors INV0 to INV3 inverter

Claims (6)

A memory cell comprising a first cell storing data and a second cell storing complementary data of the data is connected to a first bit line connected to the first cell and the second cell. a sense amplifier circuit for reading data through a second bit line,
A ground potential is supplied to the first bit line and the second bit line in a first period, which is a period before the start of the data read, and in a second period, which is the period after the start of the data read, a bit line voltage control unit that stops supplying the ground potential to the first bit line and the second bit line;
a determination unit that determines a data value of data stored in the first cell based on the voltage of the first bit line and the voltage of the second bit line in the second period;
has
The determination unit
a first conductivity type first transistor having one end supplied with a power supply voltage in the second period and having the other end connected to the first bit line;
a second transistor of the first conductivity type having one end supplied with the power supply voltage in the second period and having the other end connected to the second bit line;
a first output node connected to a control terminal of the second transistor and having a voltage corresponding to a current flowing through a current path including a connection portion between the first transistor and the first bit line;
a second output node connected to the control terminal of the first transistor and having a voltage corresponding to a current flowing through a current path including a connection portion between the second transistor and the second bit line;
has
A sense amplifier circuit that determines a data value of data stored in the first cell based on the voltage of the first output node and the voltage of the second output node . a third transistor of the first conductivity type having one end connected to a connection portion between the other end of the first transistor and the first bit line and the other end connected to the first output node;
a fourth transistor of the first conductivity type having one end connected to a connection portion between the other end of the second transistor and the second bit line and the other end connected to the second output node;
2. The sense amplifier circuit of claim 1 , further comprising: Each of the third transistor and the fourth transistor receives at its control end an enable signal having a signal level of logic level 1 during the first period and a signal level of logic level 0 during the second period. 3. The sense amplifier circuit according to claim 2 , wherein: a switch element that receives the supply of the enable signal and switches connection and disconnection between one end of each of the first transistor and the second transistor and the supply line of the power supply voltage according to the signal level of the enable signal; 4. The sense amplifier circuit of claim 3 , comprising: a fifth transistor of a second conductivity type opposite to the first conductivity type, one end of which is grounded and the other end of which is connected to the first bit line; is grounded and the other end is connected to the second bit line;
Each of the fifth transistor and the sixth transistor has a control end supplied with a discharge signal having a signal level of logic level 1 during the first period and a signal level of logic level 0 during the second period. ,
5. The sense amplifier circuit according to claim 1 , wherein: a first latch section including a first inverter having an input terminal connected to the first output node, and holding and outputting binary signal level data corresponding to the voltage of the first output node; ,
a second latch section including a second inverter whose input terminal is connected to the second output node, and which holds and outputs binary signal level data corresponding to the voltage of the second output node; ,
6. The sense amplifier circuit according to any one of claims 1 to 5 , comprising:

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