JP7206882B2 - Phase difference adjustment circuit - Google Patents

Phase difference adjustment circuit Download PDF

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JP7206882B2
JP7206882B2 JP2018235523A JP2018235523A JP7206882B2 JP 7206882 B2 JP7206882 B2 JP 7206882B2 JP 2018235523 A JP2018235523 A JP 2018235523A JP 2018235523 A JP2018235523 A JP 2018235523A JP 7206882 B2 JP7206882 B2 JP 7206882B2
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phase difference
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JP2020098966A (en
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知之 荒井
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Denso Corp
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Denso Corp
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本発明は、複数の送信チャネルを有して位相変調信号を送信するものにおいて、送信チャネル間の位相差を調整する回路に関する。 The present invention relates to a circuit that adjusts the phase difference between transmission channels in a system that has a plurality of transmission channels and transmits phase-modulated signals.

複数の送信チャネルにより例えばＢＰＳＫ（Binary Phase Shift Keying）変調信号を送信する装置において、複数のチャネル間における位相誤差の実効値は、１０°未満であることが求められる。 In a device that transmits, for example, BPSK (Binary Phase Shift Keying) modulated signals through a plurality of transmission channels, the effective value of phase error between the plurality of channels is required to be less than 10°.

特表平１０－５０３６３４号公報Japanese Patent Publication No. 10-503634

上記の要求に従って位相差を補正するには、別途測定器を用いる必要があった。
本発明は上記事情に鑑みてなされたものであり、その目的は、測定器を用いることなく複数のチャネル間と各チャネルとにおける位相誤差を補正できる位相差調整回路を提供することにある。 In order to correct the phase difference according to the above requirements, it was necessary to use a separate measuring instrument.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase difference adjusting circuit capable of correcting phase errors between a plurality of channels and between each channel without using a measuring instrument.

請求項１記載の位相差調整回路によれば、位相変調信号を送信する複数の送信チャネルの１つを、位相補正を行う際に基準チャネルとして用いる。位相差検出回路は、基準チャネルの出力端子とその他の送信チャネルの出力端子との間に接続され、両者の送信信号の相対位相差が所定値である状態を検出する。そして、調整回路は、各チャネルについて補正用ベクトルを設定し、位相差検出回路の出力を参照することで、基準チャネルの補正用ベクトルとその他の送信チャネルの補正用ベクトルとの相対位相差が、前記所定値となるように調整する。具体的には、最初に基準チャネルについてチャネル内位相精度補正を行い、次に基準チャネルとその他の送信チャネルとの間でチャネル間相対位相補正を行う。 According to the phase difference adjustment circuit of claim 1, one of a plurality of transmission channels for transmitting phase-modulated signals is used as a reference channel when performing phase correction. A phase difference detection circuit is connected between the output terminal of the reference channel and the output terminal of the other transmission channel, and detects a state in which the relative phase difference between the transmission signals of the two is a predetermined value. Then, the adjustment circuit sets a correction vector for each channel and refers to the output of the phase difference detection circuit, so that the relative phase difference between the correction vector for the reference channel and the correction vector for the other transmission channels is Adjustment is made so as to obtain the predetermined value. Specifically, intra-channel phase accuracy correction is first performed on the reference channel, and then inter-channel relative phase correction is performed between the reference channel and the other transmission channels.

このように構成すれば、位相差調整回路は、簡単に構成できる所定値の位相差を検出する位相差検出回路を用いて、複数の送信チャネル間の相対位相差を調整できるので、別途測定器を用いて調整を行う必要がなくなる。 With this configuration, the phase difference adjustment circuit can adjust the relative phase difference between a plurality of transmission channels using a phase difference detection circuit that detects a phase difference of a predetermined value that can be easily configured. It is no longer necessary to make adjustments using

請求項２記載の位相差調整回路によれば、所定値が１８０°に設定される位相差検出回路を用い、調整回路は記基準チャネルの補正用ベクトルとその他の送信チャネルの補正用ベクトルとの相対位相差を１８０°に設定，及び調整する。すなわち、所定値を１８０°に設定した位相差検出回路は一層簡単に構成できるので、位相差調整回路自体を簡単に構成できる。 According to the phase difference adjusting circuit of claim 2, a phase difference detecting circuit in which the predetermined value is set to 180° is used, and the adjusting circuit detects the difference between the correction vector of the reference channel and the correction vector of the other transmission channels. Set and adjust the relative phase difference to 180°. That is, since the phase difference detection circuit in which the predetermined value is set to 180° can be configured more simply, the phase difference adjustment circuit itself can be configured easily.

第１実施形態であり、送信装置の構成を示す機能ブロック図1 is a functional block diagram showing the configuration of a transmission device according to the first embodiment; FIG. 送信チャネルＴＸ１，ＴＸ２に夫々設定する補正用ベクトルを示す図FIG. 4 shows correction vectors set for transmission channels TX1 and TX2, respectively; チャネル内直交位相精度補正処理を示すフローチャートFlowchart showing intra-channel quadrature phase accuracy correction processing チャネル間相対位相補正処理を示すフローチャートFlowchart showing inter-channel relative phase correction processing 第２実施形態であり、送信チャネルＴＸ１，ＴＸ２に夫々設定する補正用ベクトルを示す図FIG. 11 is a diagram showing correction vectors set in the transmission channels TX1 and TX2, respectively, according to the second embodiment; チャネル間相対位相補正処理を示すフローチャートFlowchart showing inter-channel relative phase correction processing

（第１実施形態）
図１に示すように、本実施形態の送信装置１は、位相変調信号であるＢＰＳＫ信号を送信するもので、２つの送信チャネルＴＸ１，ＴＸ２を備えている。ＰＬＬ回路２は、外部の図示しない発振子より入力される基準周波数信号Ｘｔａｌを所定の逓倍率で逓倍して、送信チャネルＴＸ１，ＴＸ２及び第１位相調整部３に供給する。第１位相調整部３には、基準周波数信号Ｘｔａｌも入力されている。例えば、基準周波数信号Ｘｔａｌの周波数は５０ＭＨｚ程度であり、ＰＬＬ回路２が出力する信号の周波数は４０ＧＨｚ程度である。 (First embodiment)
As shown in FIG. 1, a transmission device 1 of this embodiment transmits a BPSK signal, which is a phase-modulated signal, and has two transmission channels TX1 and TX2. The PLL circuit 2 multiplies a reference frequency signal Xtal input from an external oscillator (not shown) by a predetermined multiplication rate, and supplies it to the transmission channels TX1 and TX2 and the first phase adjuster 3 . A reference frequency signal Xtal is also input to the first phase adjuster 3 . For example, the frequency of the reference frequency signal Xtal is about 50 MHz, and the frequency of the signal output from the PLL circuit 2 is about 40 GHz.

送信チャネルＴＸ１は、入力バッファ４（１），移相器５（１），２逓倍回路６（１），出力バッファ７（１），結合器又はカプラ８（１）及び電力検出器９（１）を備えている。送信チャネルＴＸ２は、送信チャネルＴＸ１と対称に構成されており、入力バッファ４（２）～電力検出器９（２）を備えている。移相器５（１）及び５（２）は、第１位相調整部３に内蔵されているロジック部１２から中央ロジック部１０を介して制御される。 The transmit channel TX1 comprises an input buffer 4(1), a phase shifter 5(1), a doubler 6(1), an output buffer 7(1), a combiner or coupler 8(1) and a power detector 9(1). ). The transmission channel TX2 is configured symmetrically with the transmission channel TX1, and includes an input buffer 4(2) to a power detector 9(2). The phase shifters 5 ( 1 ) and 5 ( 2 ) are controlled via the central logic section 10 from the logic section 12 incorporated in the first phase adjustment section 3 .

ＰＬＬ回路２の出力信号は、第１位相調整部３のＩＱミキサ１１に入力され、基準周波数信号Ｘｔａｌは、第１位相調整部３のロジック部１２に入力されている。ロジック部１２は、ＩＱミキサ１１に入力する位相ＩＱ（ΔＢＢ）を生成する。ＩＱミキサ１１は、入力された位相分ＩＱを含むＩＱ信号を２逓倍回路１３に出力する。２逓倍回路１３は、入力されるＩＱ信号の周波数を２逓倍した信号Ｓ２をミキサ１４に入力する。 The output signal of the PLL circuit 2 is input to the IQ mixer 11 of the first phase adjustment section 3 and the reference frequency signal Xtal is input to the logic section 12 of the first phase adjustment section 3 . The logic unit 12 generates a phase IQ (Δ BB ) to be input to the IQ mixer 11 . The IQ mixer 11 outputs to the 2-multiplying circuit 13 an IQ signal containing IQ for the input phase. The doubling circuit 13 inputs to the mixer 14 a signal S2 obtained by doubling the frequency of the input IQ signal.

ミキサ１４には、カプラ８（２）及びスイッチ１５を介して、送信チャネルＴＸ２の出力信号が信号Ｓ１として入力される。スイッチ１５は、送信装置１が通常の送信を行う際にはオフにされている。ミキサ１４は、信号Ｓ１及びＳ２を乗算した信号Ｓ３をＡ／Ｄコンバータ１６に入力する。Ａ／Ｄコンバータ１６は、信号Ｓ３をＡ／Ｄ変換したデータをロジック部１２に入力する。ロジック部１２は、中央ロジック部１０に対して制御信号を入力する。ロジック部１０及び１２は調整回路に相当する。 The output signal of the transmission channel TX2 is input to the mixer 14 via the coupler 8(2) and the switch 15 as the signal S1. The switch 15 is turned off when the transmitting device 1 performs normal transmission. The mixer 14 inputs to the A/D converter 16 a signal S3 obtained by multiplying the signals S1 and S2. The A/D converter 16 inputs data obtained by A/D converting the signal S3 to the logic section 12 . The logic section 12 inputs a control signal to the central logic section 10 . The logic units 10 and 12 correspond to adjustment circuits.

本実施形態では、送信チャネルＴＸ２を補正用の基準チャネルとして用いる。ここで、各信号Ｓ１～Ｓ３は、以下の式で表される。
Ｓ１＝Ａ・ｓｉｎ｛ωｔ＋φｒ（Ｔ）＋φｒ（ＰＳｒ）｝
Ｓ２＝Ｂ・ｓｉｎ（ωｔ＋２ΔＢＢ＋Δ）
Ｓ３＝ＡＢ／２・ｃｏｓ｛φｒ（Ｔ）＋φｒ（ＰＳｒ）－２ΔＢＢ－Δ｝
Ａ，Ｂ：信号Ｓ１，Ｓ２の振幅係数
φｒ（Ｔ）：基準チャネルの位相の温度Ｔによる変動分
φｒ（ＰＳｒ）：移相器５（２）により付与される位相分
ΔＢＢ：ロジック部１２によりＩＱミキサ１１に設定される位相分
Δ：基準チャネルＴＸ２と第１位相調整部３との位相差 In this embodiment, the transmission channel TX2 is used as a reference channel for correction. Here, each of the signals S1 to S3 is represented by the following equations.
S1=A·sin {ωt+φr(T)+φr(PSr)}
S2=B·sin(ωt+ 2ΔBB +Δ)
S3=AB/2·cos{φr(T)+φr(PSr) −2ΔBB −Δ}
A, B: Amplitude coefficients of signals S1 and S2 φr(T): Fluctuation of reference channel phase due to temperature T φr(PSr): Phase given by phase shifter 5(2) ΔBB : Logic unit 12 Δ: the phase difference between the reference channel TX2 and the first phase adjuster 3

また、送信チャネルＴＸ１，ＴＸ２の間には、カプラ８（１），８（２）を介して第２位相調整部１７が接続されている。第２位相調整部１７は、位相検出回路１８を備えている。この位相検出回路１８は、送信チャネルＴＸ１，ＴＸ２それぞれの出力信号の相対位相差が１８０°となった状態のみを検出するように構成されている。位相検出回路１８の検出信号は、ロジック部１２に入力される。 A second phase adjuster 17 is connected between the transmission channels TX1 and TX2 via couplers 8(1) and 8(2). The second phase adjustment section 17 has a phase detection circuit 18 . The phase detection circuit 18 is configured to detect only the state where the relative phase difference between the output signals of the transmission channels TX1 and TX2 is 180°. A detection signal from the phase detection circuit 18 is input to the logic section 12 .

次に、本実施形態の作用について説明する。送信チャネル間ＴＸ１，ＴＸ２の相対位相を調整するに当たり、図２に示すように、各送信チャネルのそれぞれに、補正用のベクトル（１），（２）を設定する。送信チャネルＴＸ１については、単位円上において補正用ベクトル（１），（２）を何れも「１」に設定する。送信チャネルＴＸ２については、補正用ベクトル（１）を１０ａ１／２０ｅｊφ１に設定し、補正用ベクトル（２）を１０ａ２／２０ｅｊ（φ２＋１８０）に設定する。ａ１，ａ２は振幅ばらつき［ｄＢ］であり、φ１，φ２は位相ばらつき［ｄｅｇ］である。そして、最初にチャネル内直交位相精度の補正を行い、次に、チャネル間相対位相補正を行う。 Next, the operation of this embodiment will be described. In adjusting the relative phases of the transmission channels TX1 and TX2, correction vectors (1) and (2) are set for each transmission channel, respectively, as shown in FIG. For the transmission channel TX1, the correction vectors (1) and (2) are both set to "1" on the unit circle. For transmission channel TX2, correction vector (1) is set to 10 a1/20 e jφ1 and correction vector (2) is set to 10 a2/20 e j(φ2+180) . a1 and a2 are amplitude variations [dB], and φ1 and φ2 are phase variations [deg]. First, the intra-channel quadrature phase accuracy is corrected, and then the inter-channel relative phase correction is performed.

＜チャネル内直交位相精度補正＞
図３に示すように、先ず、位相調整部３及び１７，送信チャネルＴＸ１及びＴＸ２，ＰＬＬ回路２及び中央ロジック部１０を起動する（Ｓ１）。次に、中央ロジック部１０は、送信チャネルＴＸ２の移相器５（２）を制御して、補正用ベクトル（１）を設定するための位相を付与する（Ｓ２）。 <Intra-channel quadrature phase accuracy correction>
As shown in FIG. 3, first, the phase adjusters 3 and 17, the transmission channels TX1 and TX2, the PLL circuit 2 and the central logic section 10 are activated (S1). Next, the central logic unit 10 controls the phase shifter 5(2) of the transmission channel TX2 to give a phase for setting the correction vector (1) (S2).

次に、ロジック部１２は、ＩＱミキサ１１に任意の位相ΔＢＢ０を設定し（Ｓ３）、スイッチ１５をオンする（Ｓ４）。この時、ミキサ１４より出力される信号Ｓ３のＤＣ値をＡ／Ｄコンバータ１６によりＡ／Ｄ変換したデータをＳ３０とし、ロジック部１２に記憶させる（Ｓ５）。 Next, the logic unit 12 sets an arbitrary phase ΔBB0 to the IQ mixer 11 (S3) and turns on the switch 15 (S4). At this time, data obtained by A/D converting the DC value of the signal S3 output from the mixer 14 by the A/D converter 16 is set as S30 and stored in the logic section 12 (S5).

次に、中央ロジック部１０は、送信チャネルＴＸ２の移相器５（２）を制御して、補正用ベクトル（２）を設定するための位相を付与する（Ｓ６）。ロジック部１２は、前記位相ΔＢＢ０に対し、位相を９０°増加させた位相ΔＢＢ９０をＩＱミキサ１１に設定する（Ｓ７）。この時、ミキサ１４より出力される信号Ｓ３のＤＣ値をＡ／Ｄコンバータ１６によりＡ／Ｄ変換したデータをＳ３１８０とし、ロジック部１２に記憶させる（Ｓ８）。 Next, the central logic unit 10 controls the phase shifter 5(2) of the transmission channel TX2 to give a phase for setting the correction vector (2) (S6). The logic unit 12 sets the phase ΔBB90 , which is obtained by increasing the phase ΔBB0 by 90°, in the IQ mixer 11 (S7). At this time, data obtained by A/D converting the DC value of the signal S3 output from the mixer 14 by the A/D converter 16 is set as S3 180 and stored in the logic section 12 (S8).

それから、中央ロジック部１０は、データＳ３０とデータＳ３１８０とが等しくなるように（Ｓ９）移相器５（２）の位相を増加させる（Ｓ１２）。データＳ３０とデータＳ３１８０とが等しくなると（Ｓ９；ＹＥＳ）、ロジック部１２は、その時点で移相器５（２）に設定していた位相を記憶する（Ｓ１０）。その後、スイッチ１５をオフにする（Ｓ１１）。 Then, central logic unit 10 increases the phase of phase shifter 5(2) (S12) so that data S3 0 and data S3 180 are equal (S9). When the data S30 and the data S3180 are equal (S9; YES), the logic section 12 stores the phase set in the phase shifter 5(2) at that time (S10). After that, the switch 15 is turned off (S11).

＜チャネル間相対位相補正＞
図４に示すように、先ずステップＳ１と同様の処理行うと（Ｓ２１）、中央ロジック部１０は、移相器５（２）に補正用ベクトル（２）を設定するための位相を付与し（Ｓ２２）、移相器５（１）に補正用ベクトル（１）を設定するための位相を付与する（Ｓ２３）。そして、位相検出回路１８の出力を参照して、送信チャネルＴＸ１，ＴＸ２の出力信号間の位相差が１８０°になったか否かを判断する（Ｓ２４）。 <Inter-channel relative phase correction>
As shown in FIG. 4, when the same processing as step S1 is first performed (S21), the central logic unit 10 gives the phase for setting the correction vector (2) to the phase shifter 5 (2) ( S22), the phase for setting the correction vector (1) is given to the phase shifter 5(1) (S23). Then, referring to the output of the phase detection circuit 18, it is determined whether or not the phase difference between the output signals of the transmission channels TX1 and TX2 has reached 180° (S24).

位相差が１８０°でなければ（Ｓ２４；ＮＯ）、ロジック部１２は、中央ロジック部１０を介して移相器５（１）の位相を増加させる（Ｓ１６）。位相差が１８０°になると（Ｓ２４；ＹＥＳ）、ロジック部１２はその時点で移相器５（１）に設定していた位相を記憶する（Ｓ２５）。
尚、通常の通信を行っている際に温度の影響によって生じるドリフト分については、随時又は一定期間毎に図３及び図４に示す処理を実行することで補正すれば良い。 If the phase difference is not 180° (S24; NO), the logic section 12 increases the phase of the phase shifter 5(1) via the central logic section 10 (S16). When the phase difference reaches 180° (S24; YES), the logic section 12 stores the phase set in the phase shifter 5(1) at that time (S25).
It should be noted that the amount of drift caused by the influence of temperature during normal communication may be corrected by executing the processing shown in FIGS.

以上のように本実施形態によれば、送信チャネルＴＸ１，ＴＸ２のうち、送信チャネルＴＸ２を、位相補正を行う際に基準チャネルとして用いる。位相差検出回路１８は、基準チャネルＴＸ２の出力端子と送信チャネルＸ１の出力端子との間に接続され、両者の送信信号の相対位相差が所定値，１８０°である状態を検出する。そして、ロジック部１０及び１２は、各チャネルについて補正用ベクトルを設定し、位相差検出回路１８の出力を参照することで、基準チャネルの補正用ベクトルとその他の送信チャネルの補正用ベクトルとの相対位相差が、１８０°となるように調整する。 As described above, according to the present embodiment, of the transmission channels TX1 and TX2, the transmission channel TX2 is used as the reference channel when performing phase correction. A phase difference detection circuit 18 is connected between the output terminal of the reference channel TX2 and the output terminal of the transmission channel X1, and detects a state where the relative phase difference between the transmission signals of both is a predetermined value of 180°. Then, the logic units 10 and 12 set a correction vector for each channel and refer to the output of the phase difference detection circuit 18 to determine the relative values of the correction vector of the reference channel and the correction vectors of the other transmission channels. The phase difference is adjusted to 180°.

このように構成すれば、簡単に構成できる１８０°の位相差を検出する位相差検出回路１８を用いて、複数の送信チャネル間の相対位相差を調整できるので、別途測定器を用いて調整を行う必要がなくなる。 With this configuration, it is possible to adjust the relative phase difference between a plurality of transmission channels by using the phase difference detection circuit 18 for detecting the 180° phase difference, which can be easily configured, so that a separate measuring device is used for adjustment. you don't have to do it.

（第２実施形態）
以下、第１実施形態と同一部分については同一符号を付して説明を省略し、異なる部分について説明する。第２実施形態では、位相差検出回路１８に替えて、９０°の位相差を検出する位相差検出回路を用いる場合を示す。図５に示すように、基準チャネルである送信チャネルＴＸ２には、位相差９０°毎に４つのベクトルを（１）～（４）を設定する。補正用ベクトル（１）を１０ａ１／２０ｅｊφ１に設定すると、ベクトル（２）～（４）は以下のように表される。
補正用ベクトル（２）：１０ａ２／２０ｅｊ（φ２＋９０）
補正用ベクトル（３）：１０ａ３／２０ｅｊ（φ３＋１８０）
補正用ベクトル（４）：１０ａ４／２０ｅｊ（φ４＋２７０） (Second embodiment)
Hereinafter, the same parts as those of the first embodiment are denoted by the same reference numerals, and descriptions thereof are omitted, and different parts are described. In the second embodiment, instead of the phase difference detection circuit 18, a phase difference detection circuit that detects a phase difference of 90° is used. As shown in FIG. 5, four vectors (1) to (4) are set for each 90° phase difference in the transmission channel TX2, which is the reference channel. If correction vector (1) is set to 10 a1/20 e jφ1 , vectors (2) to (4) are expressed as follows.
Correction vector (2): 10 a2/20 e j (φ2+90)
Correction vector (3): 10 a3/20 e j (φ3+180)
Correction vector (4): 10 a4/20 e j (φ4+270)

そして、図６に示すフローチャートでは、ステップＳ２２に替わるステップＳ２７において、中央ロジック部１０は、移相器５（２）に補正用ベクトル（１）を設定するための位相を付与する。また、ステップＳ２４に替わるステップＳ２８では、位相検出回路の出力を参照して、送信チャネルＴＸ１，ＴＸ２の出力信号間の位相差が９０°になったか否かを判断する。
以上のように第２実施形態によれば、９０°の位相差を検出する位相差検出回路を用いた場合でも、第１実施形態と同様の効果が得られる。 In the flowchart shown in FIG. 6, in step S27 instead of step S22, the central logic unit 10 gives the phase for setting the correction vector (1) to the phase shifter 5(2). In step S28 replacing step S24, the output of the phase detection circuit is referenced to determine whether or not the phase difference between the output signals of the transmission channels TX1 and TX2 has reached 90°.
As described above, according to the second embodiment, even when a phase difference detection circuit that detects a phase difference of 90° is used, the same effect as in the first embodiment can be obtained.

（その他の実施形態）
送信チャネル数は、「３」以上でも良い。
送信信号はＢＰＳＫ信号に限ることなく、ＱＰＳＫ信号でも良い。
周波数の具体的数値等は、個別の設計に応じて適宜変更すれば良い。
２逓倍回路に替えて、３以上の逓倍を行う回路を用いても良い。 (Other embodiments)
The number of transmission channels may be "3" or more.
The transmission signal is not limited to a BPSK signal, and may be a QPSK signal.
Specific numerical values of the frequency may be appropriately changed according to individual designs.
A circuit that multiplies by 3 or more may be used instead of the 2-multiply circuit.

本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

図面中、１は送信装置、３は第１位相調整部、５は移相器、１０は中央ロジック部、１２はロジック部、１８は位相差検出回路を示す。 In the drawing, 1 is a transmitter, 3 is a first phase adjuster, 5 is a phase shifter, 10 is a central logic section, 12 is a logic section, and 18 is a phase difference detection circuit.

Claims (2)

位相変調信号を送信する複数の送信チャネル（ＴＸ１，ＴＸ２）の１つ（ＴＸ２）を、位相補正を行う際に基準チャネルとして用い、
前記基準チャネルの出力端子と、その他の送信チャネルの出力端子との間に接続され、両者の送信信号の相対位相差が所定値である状態を検出する位相差検出回路（１８）と、
各チャネルについて補正用ベクトルを設定し、前記位相差検出回路の出力を参照することで、前記基準チャネルの補正用ベクトルと前記その他の送信チャネルの補正用ベクトルとの相対位相差が、前記所定値となるように調整する調整回路（３，１０）とを備え、
前記調整回路は、最初に前記基準チャネルについてチャネル内位相精度補正を行い、次に前記基準チャネルと前記その他の送信チャネルとの間でチャネル間相対位相補正を行う位相差調整回路。 Using one (TX2) of a plurality of transmission channels (TX1, TX2) for transmitting phase-modulated signals as a reference channel when performing phase correction,
a phase difference detection circuit (18) connected between the output terminal of the reference channel and the output terminal of the other transmission channel and detecting a state in which the relative phase difference between the two transmission signals is a predetermined value;
By setting a correction vector for each channel and referring to the output of the phase difference detection circuit, the relative phase difference between the correction vector of the reference channel and the correction vector of the other transmission channel is the predetermined value. and an adjustment circuit (3, 1 0 ) that adjusts so that
The adjustment circuit first performs intra-channel phase accuracy correction for the reference channel, and then performs inter-channel relative phase correction between the reference channel and the other transmission channels . 前記位相差検出回路は、前記所定値が１８０°に設定されており、
前記調整回路は、前記基準チャネルの補正用ベクトルと前記その他の送信チャネルの補正用ベクトルとの相対位相差を１８０°に設定，及び調整する請求項１記載の位相差調整回路。 The predetermined value of the phase difference detection circuit is set to 180°,
2. The phase difference adjustment circuit according to claim 1, wherein said adjustment circuit sets and adjusts the relative phase difference between the correction vector of said reference channel and the correction vector of said other transmission channel to 180 degrees.
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