玖、發明說明： 【發明所屬之技術領域】 本發明提供一種校正相位差之方法及裝置，尤指一種校正同相與正交相訊 號之同相/正交相不匹配的方法及裝置。 【先前技術】 明參閱圖一’圖一為習知直接降頻（direct down_conversion)架構接收 器ίο的示意圖。直接降頻接收器ίο包含有一天線n、一低雜訊放大器(L〇w Noise Amplifier，LNA)12、混頻器 14、24、低通濾波器(LPF)16、26、類比 / 數位轉換器（ADC) 18、28、以及一數位訊號處理器(Digitai signal Pr〇cess〇r， DSP)19。天線11接收一無線通信訊號，而低雜訊放大器12係用於放大天 線11所接收的無線通信訊號。混頻器14將該無線通信訊號與一第一載波 (亦即圖一所示之cos(Wct))混頻產生一類比訊號心，另一混頻器24將該 無線通仏吼號與一苐二載波（亦即圖一所示之sin(Wct+3))混頻產生一類 比訊號8&2。低通濾波器16、26用於分別濾除類比訊號心1、832的高頻成 分。此外，類比/數位轉換器18、28係將類比訊號sal、Sc分別轉換為一相 對應的數位訊號Sdl、Sd2。最後，數位訊號處理器19係用於對數位訊號 Sdi、Sd2進行後續訊號處理。 如業界所習知，上述第一載波與第二載波之間需對應一 9〇度的相位 差，以使此頻後的類比訊號Sal、Sc成為兩正交訊號，分別為同相訊號 (In-phase signal)及正交相訊號(Qua(jrature-phse signal)。然而，在實際的電路 中，因為溫度、製程以及供應電壓的飄移等因素，而會使第一載波與第二 載波之間的理想相位差（亦即90度）產生一相位偏移$，此現象稱為同相/ 正父相不匹配（IQmismatch)。如圖一所示，第一載波C0s(Wct)及第二載波 sm(wet+5)之間具有相位偏移5。同相/正交相不匹配會影響訊號解調變而 增加通訊系統的位元錯誤率(biteiT〇rrate)。因此，必須校正上述相位偏移 δ，以便進一步修正類比訊號Sal、Sa2以增加通訊系統的位元率作itrate)。 麵86 習知之用於直接降頻接收機之同相/正交相不匹配之校正方式有二··一 疋在同相/正交相訊號分別經過類比/數位轉換器18、28轉換為相對應之同 相/正交相數位訊號後，在數位端(digital d〇main)量測兩訊號之相位偏移。之 後’依據該相位差訊號輸出一調整訊號，在類比端（anal〇gd〇main)對同 相/正交相類比訊號作同相/正交相不匹配之相位補償。另一種習知方法亦是 在數位端量測同相/正交相數位訊號之相位偏移。與前述作法不同之處在 於’、在f得相位偏移之後，直接在數位端進行同相/正交相數位訊號補償。 上，兩種作法皆是在數位端偵測同相/正交相數位訊號Sdi、心2之相位偏移， 其實施方式為利用數位訊號處理器19中之數位電路對同相/正交相數位訊 號sdl、Sd2來執行離散傅立葉轉換(Discrete F〇urier Transf〇mi，DFT)以求得相 位，移ά。之後’利用習知的Gram_Schmidt正交化過程，在類比端作相位 補償。或是利用數位電路執行最小均方(Least_Mean_Square，LMS)演算法， 在數位端進行相位補償（詳細實施方式請參照”AdaptiveIQ mismatch cancellation for quadrature IF receiver", Isis Mikhael, Wasiy. B. Mikhael, httpy/bmce*engnucf：edii/%7Eprp/paper6)。然而，利用離散傅立葉轉換計算相 位偏移5的操作不僅需要複雜的邏輯電路進行繁複的邏輯計算，更會增加 額外耗功率。而數位電路需要外界提供外加的校正信號才能執行最小 均方演异法進行補償，同樣也增加電路的複雜度及功率損耗。 【發明内容】 丄因此本發明提供一種用於直接降頻架構之接收機之同相/正交相不匹配 才又正裝置及方法，不需要外加校正信號源即可實施最小均方運算演算 法，並於類比域（analogd〇main)對同相/正交相類比訊號進行同 相/正交相相位補償，以解決上述問題。 依據本發明之申請專利範圍，其係揭露一種同相/正交相不匹配(JQ m1Sm滅)校正裝置及其方法，用以一直接降頻(directd〇*c_rs㈣架構 =通訊系統中，該襄置包含有··一第一混頻器，用以依據一同相載波訊號 此頻-射頻訊遽以產生一同相類比訊號；一第二混頻器，用以依據一正交 藤敗86.: 相載波訊號混頻歸頻《以產生與—正交相減；—校正單元 以依據-同相/正交相不匹配補償訊號來對該同相类員比訊號及該正交相 訊號進行麵’峨正該附咖ttfi歧該正交減比滅之咖正交 不匹配；以及-運算單元，與該校正單元輪，用以依據該同相類比訊號 與該正交相類比訊號執行-最小均方運算以產生該同相/正妹不匹配補4 訊號。 本發明收發機與方法係利用最小均方運算以產生相位補償值以及增益 ，償值，由於本發敝發赫方法係彻—獨立錄位城處理器之運算 單兀，於收發機之類比域（亦即於同相訊號與正交向訊號輸入至數位訊號 處理器之前）即完成校正，所以不僅可降低系統複雜度，更大幅降低數位 訊號處理器的運算負擔。 【實施方式】 凊參閱圖二，圖二為本發明之實施例所提出之直接降頻（direct d_-conversion)架構之收發機（transceiver) 40的示意圖。直接降頻架構 收發機40包含有-天線4卜-低雜訊放大器42、複數個混頻$ 44、54以 及複數個低通濾波器46、56，其功能及實施方式係與習知之直接降頻架構 收發機實質上相同，於此不再贅述。需注意的是，混頻器44係利用第一載 波Q對射頻訊號直接降頻（direct_c〇nvert)以產生一同相類比訊號^。此外， 混頻器54#、利用第二載波〇^對射頻訊號直接降頻以產生正交相類比訊號 Qt。在本實施例中，直接降頻架構收發機40更包括一校正單元34用來校 正同相類比訊號It及正交相類比訊號Qt之增益不匹配與相位不匹配，以及 運算單元36用來計算同相類比訊號it及正交相類比訊號q之增益不匹配 及相位不匹配的程度，並依據計算的結果控制校正單元34執行增益補償及 相位補償。校正單元34及運算單元36之詳細實施方式將於下文中詳述。 此外’收發機40更包括類比/數位轉換裝置48及58，分別用以將同相類比 訊號與正交相類比訊號轉換為相對應之同相數位訊號與正交相數位訊號。 此外數位渓號處理器49可依據同相數位訊號與正交相數位訊號來進行後 J246286 續的數位信號處理。 —^青參閱圖三，圖三為圖二所示之校正單元34與運算單元36㈤功能方塊 不心圖。在本貫施例中，校正單疋34包含有一可程式增益補償單元a以 及一可程式相位麵單元72，而運算單元％則設置有取樣單元料、％、 延遲單元66、合成單元76以及最小均方運算單元78。 可程式增益補償單元62具有一初始增益補償值^，用以藉由調整端 點A之同相類比訊號]^之增益來進行增益補償，輸出同相類比補償訊號^ $端點C ’可程式相位補償單元72具有—初始她補償值心，用以藉由調 二端點B之正交相類比訊號Qt之相位來進行相位補償，輪出正交相類比補 化訊號Qt，於端點D。需注意的是，只要調整同相/正交相類比訊號之一者， 即可對兩訊號之相位及振幅不匹配的情況進行相位及增益補償，且本實施 例亦可藉由碰正交相類比峨的增益及__峨之她分別進行增 盈及相位補償。然後，取樣單元64、74分別對同相類比補償訊號Y與正交 相類比補償訊號Qt，進行取樣以產生兩取樣訊號E、G，如業界所習知，取 樣=元64、74所採用的取樣鮮至少需為被取樣訊號（亦即同相類比補償 aUt與正父相類比樹員訊遗Q/)之頻率的兩倍以上在本實施例中，該 取樣鮮紐取樣城之鱗_倍，但树砸砂此祕。接著，延 遲單元66依據-取樣週期來延遲取樣訊號E，在本實施例中，延遲單元的 使用取樣訊躺1/4職挺遲取樣婦uE以產生—延遲訊號f。織，合 成電路76便合成延遲訊號F與取樣訊號G而得到一合成訊號γ，輸入至最 小=運算單元78中。本實施例中，合成單元％係為加法器。最小均方 運异早το 78纽據合纽號γ及誤差容轴界值d產生—誤差訊號£。如 業界所習知’當執行最小均方運算時，誤差容許轉值d係表示合成訊號γ 於調整時所容許的誤差量，本實施例中，誤差容許臨界值定為零，換 句翻，、㈣最小均方運算單元78可達_整類比_瓣』，與類比正交 相訊號Qt，具有相同振幅以及互為正交的目的。此外，本實施例係應用延遲 訊號二與取樣訊號E來產生最小均方運算所需的輸入參數χ广&，其原理 於後洋述。所以’最小均方運异單元78便依據延遲訊號F，取樣訊號Ε與 誤差訊號£來赶-增細做^來 生-相位補舰02來更新可料她補 早心2以及產 與運算單元36的辅助，最後類比同相訊號L，與類比正=由^單元34 有相同振幅且互為正交。 〃、乂相成號Qt便可具 上述運算單元36的運作可用下列方程式來加以辅助說明 圖二所示之天、線41所接收之射頻訊號Vrp可表示為： = 2 * sin(wLOt + wmt + eQ) 混波器44及54所接收之第一及第二載波可表示為··发明 Description of the invention: [Technical field to which the invention belongs] The present invention provides a method and device for correcting phase difference, especially a method and device for correcting inphase / quadrature phase mismatch of in-phase and quadrature-phase signals. [Prior art] Please refer to FIG. 1 ′. FIG. 1 is a schematic diagram of a conventional direct down-conversion receiver. The direct down-conversion receiver includes an antenna n, a low noise amplifier (LNA) 12, a mixer 14, 24, a low-pass filter (LPF) 16, 26, and an analog / digital converter. (ADC) 18, 28, and a digital signal processor (DSP) 19. The antenna 11 receives a wireless communication signal, and the low noise amplifier 12 is used to amplify the wireless communication signal received by the antenna 11. The mixer 14 mixes the wireless communication signal with a first carrier (that is, cos (Wct) shown in FIG. 1) to generate an analog signal heart, and another mixer 24 mixes the wireless communication signal with a The second carrier (ie, sin (Wct + 3) shown in Figure 1) is mixed to generate an analog signal 8 & 2. The low-pass filters 16, 26 are used to filter the high-frequency components of the analog signal cores 1,832, respectively. In addition, the analog / digital converters 18 and 28 convert the analog signals sal and Sc into corresponding digital signals Sdl and Sd2, respectively. Finally, the digital signal processor 19 is used to perform subsequent signal processing on the digital signals Sdi, Sd2. As is known in the industry, the first carrier and the second carrier need to correspond to a phase difference of 90 degrees, so that the analog signals Sal and Sc after this frequency become two orthogonal signals, which are in-phase signals (In- phase signal) and quadrature phase signal (Qua (jrature-phse signal). However, in actual circuits, due to factors such as temperature, process and supply voltage drift, the The ideal phase difference (that is, 90 degrees) generates a phase offset $. This phenomenon is called in-phase / positive-parent phase mismatch (IQmismatch). As shown in FIG. 1, the first carrier C0s (Wct) and the second carrier sm ( Wet +5) has a phase offset of 5. The mismatch between the in-phase and quadrature phases will affect the signal demodulation and increase the bit error rate of the communication system (biteiT0rrate). Therefore, the phase offset δ must be corrected, In order to further modify the analog signals Sal and Sa2 to increase the bit rate of the communication system as itrate). There are two known correction methods for the in-phase / quadrature-phase mismatch of direct down-conversion receivers: 1. The in-phase / quadrature-phase signals are converted to the corresponding in-phase by analog / digital converters 18 and 28 respectively. After quadrature phase digital signals, measure the phase offset of the two signals at the digital end (digital domain). After that, an adjustment signal is output according to the phase difference signal, and the in-phase / quadrature-phase analog signal is compensated for in-phase / quadrature phase mismatch at the analog end (anal0gd〇main). Another conventional method is to measure the phase offset of in-phase / quadrature-phase digital signals at the digital end. The difference from the previous method is that after the phase shift of f, the in-phase / quadrature-phase digital signal compensation is performed directly at the digital end. In the above two methods, the phase shift of the in-phase / quadrature-phase digital signal Sdi and core 2 is detected at the digital end. The implementation method is to use the digital circuit in the digital signal processor 19 to in-phase / quadrature-phase digital signal. sdl, Sd2 to perform Discrete Fourier Transform (DFT) to obtain phase and shift. After that, phase compensation is performed on the analog side using the conventional Gram_Schmidt orthogonalization process. Or use a digital circuit to perform a Least_Mean_Square (LMS) algorithm and perform phase compensation at the digital end (for detailed implementation, please refer to "AdaptiveIQ mismatch cancellation for quadrature IF receiver ", Isis Mikhael, Wasiy. B. Mikhael, httpy / bmce * engnucf: edii /% 7Eprp / paper6). However, the operation of calculating phase offset 5 using discrete Fourier transform not only requires complicated logic circuits to perform complicated logic calculations, but also increases additional power consumption. Digital circuits require external supply The added correction signal can perform the minimum mean square differentiation method to compensate, and it also increases the complexity and power loss of the circuit. [Summary of the Invention] 丄 The present invention provides an in-phase / quadrature for a receiver with a direct frequency reduction architecture. The device and method are normalized only when the phases do not match. The minimum mean square operation algorithm can be implemented without additional correction signal source, and the in-phase / quadrature-phase analog signal is in-phase / quadrature-phase in the analog domain (analog domain). Compensation to solve the above problems. According to the scope of patent application of the present invention, it discloses a kind of Phase / quadrature phase mismatch (JQ m1Sm off) correction device and method thereof for a direct frequency reduction (directd0 * c_rs㈣ architecture = communication system, which includes a first mixer, which is used for Based on the same-phase carrier signal, this frequency-radio frequency signal is used to generate the same analog signal; a second mixer is used to generate a positive and negative signal according to a quadrature phase. Cross-subtraction;-the correction unit uses the-in-phase / quadrature-phase mismatch compensation signal to face the in-phase class comparison signal and the quadrature-phase signal. A quadrature mismatch; and-an arithmetic unit and a round of the correction unit for performing a -minimum mean square operation on the in-phase analog signal and the quadrature-phase analog signal to generate the in-phase / positive mismatch complement 4 signal. The transceiver and method of the present invention use the minimum mean square operation to generate a phase compensation value and a gain and compensation value. Since the method of the present invention is a thorough-independent recording unit processor, it is used in the analog domain of the transceiver. (That is, in-phase signal and quadrature signal input The calibration is completed before the digital signal processor, so it can not only reduce the system complexity, but also greatly reduce the computing load of the digital signal processor. [Embodiment] 凊 Refer to FIG. 2. FIG. 2 is a direct solution of the embodiment of the present invention. Schematic diagram of a direct d_-conversion transceiver 40. The direct-down architecture transceiver 40 includes an antenna 4 and a low noise amplifier 42, a plurality of mixers $ 44, 54 and a plurality of The functions and implementation modes of the low-pass filters 46 and 56 are substantially the same as those of the conventional direct frequency-reduction architecture transceiver, and details are not described herein again. It should be noted that the mixer 44 uses the first carrier Q to directly down-convert the RF signal (direct_convert) to generate the same analog signal ^. In addition, the mixer 54 # directly reduces the frequency of the radio frequency signal by using the second carrier signal ^ to generate a quadrature phase analog signal Qt. In this embodiment, the direct frequency down conversion transceiver 40 further includes a correction unit 34 for correcting the gain mismatch and phase mismatch of the in-phase analog signal It and the quadrature-phase analog signal Qt, and the operation unit 36 is used to calculate the in-phase The degree of gain mismatch and phase mismatch of the analog signal it and the quadrature-phase analog signal q, and the correction unit 34 is controlled to perform gain compensation and phase compensation according to the calculation result. The detailed implementation of the correction unit 34 and the operation unit 36 will be described in detail below. In addition, the 'transceiver 40 further includes analog / digital conversion devices 48 and 58 for converting in-phase analog signals and quadrature-phase analog signals to corresponding in-phase digital signals and quadrature-phase digital signals, respectively. In addition, the digital signal processor 49 can perform the subsequent digital signal processing based on the in-phase digital signal and the quadrature-phase digital signal. — ^ Refer to Figure 3. Figure 3 is a schematic diagram of the functional blocks of the correction unit 34 and the arithmetic unit 36 shown in Figure 2. In the present embodiment, the correction unit 34 includes a programmable gain compensation unit a and a programmable phase surface unit 72, and the arithmetic unit% is provided with a sampling unit material, a%, a delay unit 66, a synthesis unit 76, and a minimum unit. Mean square operation unit 78. The programmable gain compensation unit 62 has an initial gain compensation value ^ for performing gain compensation by adjusting the gain of the in-phase analog signal of terminal A] ^, and outputs the in-phase analog compensation signal ^ $ end point C 'programmable phase compensation The unit 72 has an initial compensation value center for performing phase compensation by adjusting the phase of the quadrature phase analog signal Qt at the endpoint B, and turns out the quadrature phase analog supplement signal Qt at the endpoint D. It should be noted that as long as one of the in-phase / quadrature-phase analog signals is adjusted, the phase and gain compensation can be performed in the case where the phase and amplitude of the two signals do not match, and this embodiment can also be performed by touching the quadrature-phase analog. Gao's gain and __E's gain and phase compensation, respectively. Then, the sampling units 64 and 74 respectively sample the in-phase analog compensation signal Y and the quadrature-phase analog compensation signal Qt to generate two sampling signals E and G. As is known in the industry, sampling = sampling used by the elements 64 and 74. It must be at least twice the frequency of the sampled signal (that is, the in-phase analog compensation aUt and the positive father analog tree member signal Q /). In this embodiment, the sampling scale of the sampling city is _ times as large, but The tree smashed this secret. Then, the delay unit 66 delays the sampling signal E according to the -sampling period. In this embodiment, the delay unit uses the sampling signal to lag the sampling signal uE to generate a -delay signal f. Then, the synthesizing circuit 76 synthesizes the delayed signal F and the sampling signal G to obtain a synthesized signal γ, which is input to the minimum = operation unit 78. In this embodiment, the synthesis unit% is an adder. The minimum mean square is different as early as το 78, according to the joint number γ and the error tolerance axis boundary value d-the error signal £. As is known in the industry, 'when performing the minimum mean square operation, the error allowable turn value d represents the amount of error that the composite signal γ allows when adjusting. In this embodiment, the error allowable threshold is set to zero, in other words, The minimum mean square operation unit 78 can reach _whole analogy_lobe '', and the orthogonal quadrature signal Qt has the same amplitude and the purpose of being orthogonal to each other. In addition, this embodiment uses the delayed signal two and the sampled signal E to generate the input parameter χ wide & required for the minimum mean square operation, the principle of which will be described later. Therefore, the 'minimum mean square operation difference unit 78 is based on the delay signal F, the sampling signal E and the error signal £ to rush-to refine it ^ the next life-phase compensation ship 02 to update the expected Shexin 2 and production and operation unit Auxiliary 36, the last analog in-phase signal L, has the same amplitude as the analog positive = unit 34 and is orthogonal to each other. The operation of the above-mentioned arithmetic unit 36 can be provided by the Q and Q phase numbers. The following equation can be used to supplement the explanation. The radio frequency signal Vrp received by the sky and line 41 shown in Figure 2 can be expressed as: = 2 * sin (wLOt + wmt + eQ) The first and second carriers received by mixers 44 and 54 can be expressed as ...
Cj = sin(wLOt) cq =(l + ^1)*cos(^0/ + 01) 方程式(1) 方程式(2)Cj = sin (wLOt) cq = (l + ^ 1) * cos (^ 0 / + 01) Equation (1) Equation (2)
It =cos(^ + /90)It = cos (^ + / 90)
Qt = -(1 + s^siniwj + ^0-(5^ 純方程式(L)、（2)所表示之同相類比訊號11與正交相類比訊號Qt係由 射頻峨Vrf依據載波訊號Q、〇^分卿降頻處理所產生的。此外，頻率 WL〇^m係為已知數值’ e】代表載波訊號Ci、Cq間的增益不匹酉己，以衫 1代表載波訊號Cl、Cq間的相位不匹配。 方程式(3)Qt =-(1 + s ^ siniwj + ^ 0- (5 ^ The in-phase analog signal 11 and the quadrature-phase analog signal represented by the pure equations (L), (2) Qt are based on the carrier signal Q, 〇Vrf. ^ Frequency reduction is generated. In addition, the frequency WL0 ^ m is a known value. 'E] represents that the gain between the carrier signals Ci and Cq is not equal. Let 1 represent the carrier signal between Cl and Cq. Phase mismatch Equation (3)
It?= fV * cos(wJ + θ0)It? = FV * cos (wJ + θ0)
Qt ’ (1 + 〇 sinK/ + 0。- 4 + 0) 方程式(4) 同相類比補償訊號V與正交相類比補償訊號Qt，係由同相類比訊號It 及正交相類比訊號Qt進行相位補償及增細、所得。上式方程式⑶係所表示 瞧86 w’M式(4)則表示於校 補仏兀件72所提供的相位補償值為0。 E”cosK^。⑷，其中㈣*丁〇 方程式(5) F(k) = W * c〇sK (k ^i)T〇+e〇]s=w, ύη(^ + ^〇)方程式⑹ 以輸時間t中爾職Tg來取樣咖比補償訊號V ^取樣週期％係為27r/Wm的四分之…m (k) (1 + ^Osin^^T； +θ0-δι+φ)，其中 t=k*T〇 方程式(7) y(t) = G(k) η- F(k) =, W *sin(wmkT0 + θ0) - (1 + 8x)sm^JT0 -^θ0-δι+φ) 方程式(8) 八⑺=_ -少(’卜 -W * sin(W/wAT。+ 0。）— (1 + ^)sin(M^r。+ % 一 $ + 0)，其中 ^) = 0 方程式(9) 方程式(7)係表示於時間t中以取樣週期Tg來取樣正交類比補償相訊號 Qt’以輸出取樣訊號G(k)。方程式(8)係表示係表示取樣訊號G(k)與延遲訊號 F(k)經由合成產生一合成訊號y(t)。對於方程式⑼而言，上述之d(t)係為一 各δ午誤差界值’用來设定以敢小均方運算校正相位與增益不匹配時可容 許的誤差量。 x2(k)=轉): δφ =^(^mkT0 +θ0-δί+φ)^ψ^ cos(wmkT0 + 0〇) = E(k)，其中 4遠小於1 方程式(10) x1(k) = aA(k) = 1 aw ：-sin(wmkT0 + θ0) = -F(k) 方程式(11) 1^46286Qt '(1 + 〇sinK / + 0.-4 + 0) Equation (4) In-phase analog compensation signal V and quadrature-phase analog compensation signal Qt are phase-compensated by the in-phase analog signal It and the quadrature-phase analog signal Qt. And refinement, income. The equation (3) shown in the above equation (see equation 86) is shown in equation (4). The phase compensation value provided by the correction compensation element 72 is zero. E ”cosK ^ .⑷, where ㈣ * 丁 〇 equation (5) F (k) = W * c〇sK (k ^ i) T〇 + e〇] s = w, ύη (^ + ^ 〇) equation ⑹ Sampling the coffee compensation signal V ^ with sampling time Tg at the time t ^ The sampling cycle% is a quarter of 27r / Wm ... m (k) (1 + ^ Osin ^^ T; + θ0-δι + φ), Where t = k * T〇 equation (7) y (t) = G (k) η- F (k) =, W * sin (wmkT0 + θ0)-(1 + 8x) sm ^ JT0-^ θ0-δι + φ) Equation (8) Eight ⑺ = _-少 ('卜 -W * sin (W / wAT. + 0.) — (1 + ^) sin (M ^ r. +% one $ + 0), where ^) = 0 Equation (9) Equation (7) indicates that the orthogonal analog compensation phase signal Qt 'is sampled at the sampling period Tg in time t to output the sampling signal G (k). Equation (8) indicates that it means sampling The signal G (k) and the delayed signal F (k) are combined to produce a composite signal y (t). For Equation ⑼, the above d (t) is a δ-day error bounds' used to set How dare the small mean square operation correct the allowable amount of error when the phase and gain do not match. X2 (k) = turn): δφ = ^ (^ mkT0 + θ0-δί + φ) ^ ψ ^ cos (wmkT0 + 0〇) = E (k), where 4 is far less than 1 Equation (10) x1 (k) = aA (k) = 1 aw -sin (wmkT0 + θ0) = -F (k) Equation (11) ^ 46286 1
方程式(10)與方程式(11)分別表示習知最小均方運算所需的輪入參數 X!(k)與X2(k)，因此，明顯可知一輸入參數x^k)即為延遲訊號F(k)的反相 訊號’以及另一輸入參數X2(k)即為取樣訊號E(k)，所以圖三所示之最小均 方運算單元78便可經由|馬接於取樣單元64與延遲單元66的輪出端來達到 接收所要之輸入參數X/k)與X2(k)的目的，請注意，輪入參數\(k)係為延 遲訊號F(k)的反相訊號，因此延遲訊號F(k)必須先經由反向處理（例如一 反向器）後才用來作為輸入參數X^k)。 W(k + 1) = Ψ(^ + 2μ^ sign[^y(k)] * sign[-F(k)] 0(A: +1) = 0(^:) + 2μ * sign[-y{k)] * sign[E(k)] 方程式(12) 方程式(13) 如業界所習知，方程式⑽與方程式⑽係為習知最小均方運算的迴路 方程式’所以，便可經由最小均方運算來消除直接降頻式收發機仞之增益 不匹配與相位不匹配。 曰皿 a需注意的是，本發賴提出之方法亦可於與遠端通赠、統進行通訊之 I ’以收發機之發送端紐職域至接收端來對自身進行她及增益補 償的方式來實施。 本發明所提出之用於直接降頻架構收發機之同相/正交相不匹配校正單 凡與方法係依據利用同相/正交相類比訊號來量測兩訊號之同相/正交相不 ，配的情形。並以最小均方運算以產生相位補償值以及增益補償值，於類 比端對同相/正交相類比訊號進行相位及增益補償。 蜀 ^數位喊處職之運料元提絲小財崎制她_^ 信號’且於類比端進行校正。所以不僅可降低系統複雜度，更 大巾田降低數位訊號處理器的運算負擔。 等佳實補，凡依轉所做之均 等夂化飾，^應屬本發明專利之涵蓋範圍。 12 谓286 【圖式簡單說明】 圖式之簡單說明 圖一為習知之直接降頻架構接收器的示意圖。 圖二為本發明之實侧所提it!之直接降_構之收發機的示意圖 圖三為圖二所示之校正單元與運算單元的示意圖。 圖式之符號說明 12、42 低雜訊放大器 16 x 26 ^ 46 ^ 56 低通濾波器 19、49 數位訊號處理器 36 運算單元 64 ^ 74 取樣單元 72 芝鱼式相位補償單元 78 最小均方運算單元 11、41Equation (10) and equation (11) respectively represent the turn-in parameters X! (K) and X2 (k) required for the conventional minimum mean square operation, so it is obvious that an input parameter x ^ k) is the delayed signal F (k) 's inverted signal' and another input parameter X2 (k) is the sampling signal E (k), so the minimum mean square operation unit 78 shown in Figure 3 can be connected to the sampling unit 64 and the delay via The round end of unit 66 is used to achieve the purpose of receiving the required input parameters X / k) and X2 (k). Please note that the round-in parameter \ (k) is the reverse signal of the delay signal F (k), so the delay The signal F (k) must be used as an input parameter X ^ k after being processed in reverse (for example, an inverter). W (k + 1) = Ψ (^ + 2μ ^ sign [^ y (k)] * sign [-F (k)] 0 (A: +1) = 0 (^ :) + 2μ * sign [-y (k)] * sign [E (k)] Equation (12) Equation (13) As is well known in the industry, Equation ⑽ and Equation ⑽ are the loop equations of the conventional minimum mean square operation. Therefore, the minimum mean The square operation is used to eliminate the gain mismatch and phase mismatch of the direct downconversion transceiver. It should be noted that the method proposed by the present invention can also be used to communicate with the remote end and communicate with the remote I 'from the transceiver's sending end to the receiving end to perform her and gain compensation. To implement. The in-phase / quadrature-phase mismatch correction method used in the direct down-conversion transceiver of the present invention is based on measuring the in-phase / quadrature-phase disparity of two signals based on the use of in-phase / quadrature-phase analog signals. Situation. The minimum mean square operation is used to generate a phase compensation value and a gain compensation value. Phase and gain compensation is performed on the in-phase / quadrature-phase analog signal at the analog end. Shu ^ Digitally called Yun Shiyuan, the source of material, Ti Si Xiaocaisaki made her _ ^ signal 'and corrected it on the analog side. Therefore, it can not only reduce the system complexity, but also reduce the computational burden of the digital signal processor. Waiting for the best real supplements, and all the equalizing decoration according to Zhuan Zhuan, should belong to the scope of the invention patent. 12 As 286 [Simplified description of the diagram] Brief description of the diagram Figure 1 is a schematic diagram of a conventional direct frequency-reduction architecture receiver. FIG. 2 is a schematic diagram of a direct descending transceiver of the it! Mentioned in the real side of the present invention. FIG. 3 is a schematic diagram of a correction unit and an arithmetic unit shown in FIG. Explanation of Symbols in Drawings 12, 42 Low Noise Amplifier 16 x 26 ^ 46 ^ 56 Low Pass Filter 19, 49 Digital Signal Processor 36 Operation Unit 64 ^ 74 Sampling Unit 72 Shiba-type Phase Compensation Unit 78 Minimum Mean Square Operation Units 11, 41
— 瘦生/數位雙多器 單元 全或單元— Slim / Digital Dual Multiplexer Unit All or Unit
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