JP7192338B2 - Method for sorting silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a method for sorting silicon carbide semiconductor devices.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are multiple types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors are limited to use at a switching frequency of about several kHz, and IGBTs are limited to use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or an IGBT, making it difficult to increase the current, but it is capable of high-speed switching operation up to several MHz.

However, there is a strong demand in the market for power semiconductor devices that combine large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. . From the viewpoint of power semiconductor devices, semiconductor materials that can replace silicon are being investigated, and silicon carbide (SiC) is a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. is attracting attention.

The background to this is that silicon carbide is a chemically very stable material, has a wide bandgap of 3 eV, can be used extremely stably as a semiconductor even at high temperatures, and has a maximum electric field strength that is one order of magnitude greater than that of silicon. be done. Since silicon carbide has a high possibility of exceeding the material limit of silicon, its use in power semiconductor applications, especially MOSFETs, is greatly expected to grow in the future. In particular, its on-resistance is expected to be small, and a vertical SiC-MOSFET having even lower on-resistance while maintaining high withstand voltage characteristics can be expected. The withstand voltage is the limit voltage at which the element does not malfunction or break down.

(Structure of Silicon Carbide Semiconductor Device)
The structure of a conventional silicon carbide semiconductor device will be described using an n-channel vertical MOSFET as an example. FIG. 6 is a cross-sectional view showing an example of the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 6, n-type silicon carbide epitaxial layer 2 is deposited on the front surface of n ⁺ -type silicon carbide substrate 1, and p ⁺ -type base region 3 is selected as the surface layer of n-type silicon carbide epitaxial layer 2. is provided. A p-type base layer 4 is deposited on the front surface of the n-type silicon carbide epitaxial layer 2 , and the p-type base layer 4 is provided with an n ⁺ -type source region 5 , a p ⁺ -type contact region 6 and an n-type well region 7 . It is provided selectively.

A gate electrode 9 is provided on the surfaces of the p-type base layer 4 and the n ⁺ -type source region 5 with a gate insulating film 8 interposed therebetween. A source electrode 10 is provided on the surface of the n ⁺ -type source region 5 and the p ⁺ -type contact region 6 . A drain electrode 11 is provided as a back surface electrode on the back surface of the n ⁺ -type silicon carbide substrate 1 .

(Silicon carbide semiconductor element on silicon carbide semiconductor wafer)
FIG. 7 is a top view showing an example of a silicon carbide semiconductor element on a silicon carbide semiconductor wafer. A silicon carbide semiconductor device is manufactured by cutting (dicing) a plurality of silicon carbide semiconductor elements 100 formed on a silicon carbide semiconductor wafer 110 into chips. Cutting from silicon carbide semiconductor wafer 110 is performed by cutting, for example, the dotted line portion in FIG.

Here, there is a technique for controlling the occurrence of cracks in a semiconductor substrate. For example, the semiconductor layer includes an element region and an outer peripheral region surrounding the outer periphery of the element region. is known (see Patent Document 1, for example). Further, when scribing in the direction perpendicular to the crystal axis of the silicon carbide substrate, the left and right edge angles with respect to the ridge line of the edge are made different, and the edge angle at the high position seen from the crystal axis is large, and the other is small. A technique of scribing using a wheel is known (see Patent Document 2, for example).

JP 2016-18952 A JP 2017-22422 A

Here, on the back side of a silicon carbide semiconductor device using a silicon carbide substrate, defects such as distortion and peeling of the back electrode often occur. Distortion is cracks (scratches) or chips that occur in the substrate.

(Individualized Silicon Carbide Semiconductor Device)
FIG. 8 is a top view showing an example of a silicon carbide semiconductor device separated into pieces. In the silicon carbide semiconductor device, an edge termination region 210 that surrounds the active region 211 and retains a breakdown voltage is provided at the outer periphery of the active region 211 through which the main current flows. is provided. The active region is the region through which current flows when in the ON state. The singulation of silicon carbide semiconductor devices is performed by cutting silicon carbide semiconductor wafer 110 in invalid region 201 . The singulation cut surface 200 is a cut surface by singulation. A gate pad region 212 is provided in the active region 211 . A distortion 220 shown in FIG. 8 is an example of distortion on the front side of the invalid area 201 .

(Strain of Silicon Carbide Semiconductor Device)
FIG. 9 is a side view showing an example of strain in a silicon carbide semiconductor device. The strain of the silicon carbide semiconductor element includes strain 220 on the front surface side, strain 221 on the back surface side, and strain 222 on the cut surface side. Among them, the distortion 221 on the rear surface side is caused by, for example, foreign matter adhering to the rear surface of the n ⁺ -type silicon carbide substrate 1 before the drain electrode 11 is provided on the rear surface of the n ⁺ -type silicon carbide substrate 1 shown in FIG. or due to the presence of cracks (flaws) or chipping on the back surface of n ⁺ -type silicon carbide substrate 1 .

In addition to the distortion 221 , a defect such as a portion where the drain electrode 11 is separated from the back surface of the n ⁺ -type silicon carbide substrate 1 is also generated on the back surface side of the silicon carbide semiconductor element. Such peeling of the drain electrode 11 from the back surface of the n ⁺ -type silicon carbide substrate 1 is performed by, for example, carbon (C) on the back surface of the n ⁺ -type silicon carbide substrate 1, thereby forming the drain electrode on the back surface of the n ⁺ -type silicon carbide substrate 1 . 11 are not in close contact with each other.

Carbon on the back surface of n ⁺ -type silicon carbide substrate 1 is generated by, for example, carbon existing in n ⁺ -type silicon carbide substrate 1 appearing on the back surface of n ⁺ -type silicon carbide substrate 1 by heat treatment. Carbon on the back surface of n ⁺ -type silicon carbide substrate 1 is also generated when, for example, carbon generated when gate insulating film 8 is formed flows into the back surface of n ⁺ -type silicon carbide substrate 1 .

However, these defects on the back side include minute defects that cannot be identified by an automatic visual inspection device or by visual inspection. Such minute defects on the back surface side rarely have a large effect on the characteristics of the silicon carbide semiconductor device when the silicon carbide semiconductor device is started to be used, and are difficult to detect even in general electrical tests and characteristic tests. . When a silicon carbide semiconductor device having defects on the back side is used for a long period of time and stress such as thermal stress of an implant pin is applied to the defects on the back side, the defects on the back side grow, resulting in failure of the silicon carbide semiconductor device. Electrical characteristics deteriorate.

In order to solve the above-described problems of the prior art, the present invention selects silicon carbide semiconductor devices that have no defects on the back surface side, and can screen silicon carbide semiconductor devices that are less likely to deteriorate in reliability even after long-term use. It is an object of the present invention to provide a method for sorting silicon semiconductor devices.

In order to solve the above-described problems and achieve the object of the present invention, a method for sorting silicon carbide semiconductor devices according to the present invention has the following features. A method for selecting a silicon carbide semiconductor device including a MOSFET, wherein the MOSFET includes a first electrode and a gate electrode provided on a front surface side of a silicon carbide substrate and a first electrode and a gate electrode provided on a back surface side of the silicon carbide substrate. a second electrode; In the first step, the temperature of the MOSFET is set to a predetermined temperature. In a second step, the forward voltage of the MOSFET is measured at the predetermined temperature. After the second step, in a third step, a continuous pulse is applied to the gate electrode for a predetermined time while a positive voltage higher than the ON voltage of the MOSFET is applied to the second electrode . After the third step, in a fourth step, the forward voltage of the MOSFET measured in the second step is measured again at the predetermined temperature. In the fifth step, the rate of change of the forward voltage measured in the fourth step with respect to the forward voltage measured in the second step is calculated. In the sixth step, it is determined whether or not the rate of change calculated in the fifth step is lower than a predetermined value. In each of the second step and the fourth step, the above-described Measure the forward voltage of the MOSFET.

Further, a method for sorting silicon carbide semiconductor devices according to the present invention has the following features. A method for selecting a silicon carbide semiconductor device including a MOSFET, wherein the MOSFET includes a first electrode and a gate electrode provided on a front surface side of a silicon carbide substrate and a first electrode and a gate electrode provided on a back surface side of the silicon carbide substrate. a second electrode; In the first step, the temperature of the MOSFET is set to a predetermined temperature. In the second step, the threshold voltage of the MOSFET is measured as the characteristic value of the MOSFET at the predetermined temperature. After the second step, in a third step, a continuous pulse is applied to the gate electrode for a predetermined time while a positive voltage higher than the ON voltage of the MOSFET is applied to the second electrode . After the third step, in the fourth step, the threshold voltage of the MOSFET is measured again as the characteristic value of the MOSFET measured in the second step at the predetermined temperature. In the fifth step, the rate of change of the characteristic value measured in the fourth step with respect to the characteristic value measured in the second step is calculated. In the sixth step, it is determined whether or not the rate of change calculated in the fifth step is lower than a predetermined value. In each of the second step and the fourth step, the threshold voltage of the MOSFET is measured by applying a voltage to the gate electrode while applying a positive voltage to the second electrode.

In addition, the method for sorting silicon carbide semiconductor devices according to the present invention has the following features in the invention described above. The characteristic value further includes the forward voltage of the MOSFET . In each of the second step and the fourth step, the above-described The forward voltage of the MOSFET is also measured. In the fifth step, for each of the plurality of characteristic values, a rate of change of the characteristic value measured in the fourth step with respect to the characteristic value measured in the second step is calculated. In the sixth step, it is determined whether or not at least one of the rate of change calculated for each of the plurality of characteristic values in the fifth step is lower than the predetermined value.

Further, in the method for selecting a silicon carbide semiconductor device according to the present invention, in the invention described above, the characteristic value further includes a forward voltage of a built-in diode of the MOSFET. In each of the second step and the fourth step, a voltage of 1 V or higher with a current density of 0.1 A/cm ² or higher is applied to the first electrode to flow a current from the first electrode to the second electrode. and measuring the forward voltage of the built-in diode of the MOSFET, and in the fifth step, for each of the plurality of characteristic values, the characteristic value measured in the second step is compared to the characteristic value measured in the second step by the fourth step. calculating the rate of change of the measured characteristic value, and in the sixth step, determining whether at least one of the rate of change calculated for each of the plurality of characteristic values in the fifth step is lower than the predetermined value; It has the feature of judging

In addition, the method for sorting silicon carbide semiconductor devices according to the present invention has the following features in the invention described above. The MOSFET includes a first electrode provided on the front surface side of the silicon carbide substrate, a second electrode provided on the back surface side of the silicon carbide substrate, and a front surface of the silicon carbide substrate. a first semiconductor layer of a first conductivity type provided; a second semiconductor layer of a second conductivity type provided on a side of the first semiconductor layer opposite to the silicon carbide substrate; and the second semiconductor layer. and a first conductivity type first semiconductor region having a higher impurity concentration than the silicon carbide substrate, and a gate insulating film in contact with the second semiconductor layer. The gate electrode is provided on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer. The first electrode is provided on surfaces of the first semiconductor region and the second semiconductor layer.

In addition, the method for sorting silicon carbide semiconductor devices according to the present invention has the following features in the invention described above. The MOSFET further includes a trench penetrating through the second semiconductor layer and reaching the first semiconductor layer. The gate electrode is provided inside the trench via the gate insulating film.

Further, the method for sorting silicon carbide semiconductor devices according to the present invention is characterized in that, in the invention described above, the predetermined temperature is a temperature of 300° C. or lower.

Further, the method for sorting silicon carbide semiconductor devices according to the present invention is characterized in that, in the invention described above, the predetermined value is 1%.

Further, the method for selecting silicon carbide semiconductor devices according to the present invention is characterized in that, in the invention described above, the frequency of the continuous pulses is 100 kHz or more and 500 kHz or less.

According to the invention described above, it is possible to determine the magnitude of the overheat resistance of the silicon carbide semiconductor device by applying continuous pulses to the gate electrode of the silicon carbide semiconductor device for a predetermined period of time.

According to the method for selecting silicon carbide semiconductor devices according to the present invention, it is possible to select silicon carbide semiconductor devices having no defect on the back surface side, and to screen silicon carbide semiconductor devices whose reliability is unlikely to deteriorate even after long-term use. It has the effect of being able to

FIG. 1 is a flowchart showing a method for sorting silicon carbide semiconductor devices according to an embodiment. FIG. 2 is a graph showing an example of the relationship between the frequency of continuous pulses and the change rate of the threshold voltage of a MOSFET. FIG. 3 is a graph showing an example of the relationship between the frequency of continuous pulses and the forward voltage of a MOSFET. FIG. 4 is a graph showing an example of the relationship between the frequency of continuous pulses and the forward voltage of the built-in diode. FIG. 5 is a cross-sectional view showing another example of the structure of the silicon carbide semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view showing an example of the structure of a conventional silicon carbide semiconductor device. FIG. 7 is a top view showing an example of a silicon carbide semiconductor element on a silicon carbide semiconductor wafer. FIG. 8 is a top view showing an example of a silicon carbide semiconductor device separated into pieces. FIG. 9 is a side view showing an example of strain in a silicon carbide semiconductor device.

Preferred embodiments of a method for sorting silicon carbide semiconductor devices according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.

(Embodiment)
(Silicon Carbide Semiconductor Device Sorting Method According to Embodiment)
FIG. 1 is a flowchart showing a method for sorting silicon carbide semiconductor devices according to an embodiment. A method for sorting silicon carbide semiconductor devices according to an embodiment is a method for sorting out silicon carbide semiconductor devices having no defect on the back surface side. Defects on the back side of the silicon carbide semiconductor device are defects such as distortion and peeling of the back electrode, as described above.

A vertical MOSFET (hereinafter simply referred to as MOSFET) will be described below as an example of a silicon carbide semiconductor device to be sorted. The silicon carbide semiconductor devices to be sorted may be in the state of a wafer before cutting, the state of chips cut from the wafer, or the state of a product assembled into a module.

In the method for selecting silicon carbide semiconductor devices according to the embodiment, first, the temperature of the target MOSFET is set to a predetermined temperature (step S1: first step). For example, the temperature of the MOSFET is adjusted to a temperature in the range of room temperature (for example, 20°C) to 300°C. The higher the temperature of the MOSFET, the more likely the defects on the rear surface side of the MOSFET are enlarged.

Adjustment of the temperature of the MOSFET in step S1 can be performed, for example, by energizing the MOSFET. For example, the temperature of the MOSFET can be adjusted by applying a forward current of constant current density until the MOSFET reaches the above temperature range. Here, the forward current is the current that flows from the drain electrode to the source electrode of the MOSFET.

Next, the threshold voltage of the target MOSFET, the forward voltage of the MOSFET, and the forward voltage of the built-in diode are measured while maintaining the MOSFET temperature (predetermined temperature) adjusted in step S1 (step S2: 2 steps). Each characteristic value of these MOSFETs changes according to the excessive thermal resistance when a large current flows in a short time through a MOSFET with a defect on the back side. Transient thermal resistance is the reciprocal of thermal conductivity during power loss on a pulse.

The threshold voltage of a MOSFET is the gate voltage (voltage applied to the gate electrode) at which current begins to flow between the drain and source of the MOSFET. For example, the threshold voltage of a MOSFET is measured by gradually increasing the gate voltage while applying a positive voltage to the drain electrode with respect to the source electrode and identifying the gate voltage when forward current begins to flow. can do.

The forward voltage of a MOSFET is the voltage between the source and the drain when a forward current of a predetermined current value flows through the MOSFET. For example, the forward voltage of a MOSFET is the source-drain voltage when a positive voltage is applied to the drain electrode with the potential of the source electrode set to 0 V, and a current of a predetermined current value flows from the drain electrode to the source electrode. can be measured by determining the voltage between Alternatively, specifying the voltage between the source and the drain when the potential of the drain electrode is set to 0 V and a negative voltage is applied to the source electrode to flow a current of a predetermined current value from the source electrode to the drain electrode. may be measured by The predetermined current value is, for example, a current value selected from a range of 0.1 A or more and 100 A or less, and is 25 A as an example. The forward voltages of these MOSFETs are measured while a voltage equal to or higher than the threshold voltage of the MOSFETs is applied to the gate electrode.

The forward voltage of the built-in diode is the voltage between the source and drain when a current of a predetermined current value flows through the diode formed between the source and drain of the MOSFET. For example, the forward voltage of the built-in diode is the source- It can be measured by identifying the voltage across the drain. The predetermined current value is, for example, a current value selected from a range of 0.1 A or more and 100 A or less, and is 25 A as an example. At this time, it is preferable to apply a voltage of 1 V or more to the drain electrode at a current density of 0.1 A/cm ² or more, for example. Alternatively, the forward voltage of the built-in diode is obtained by applying a positive voltage to the source electrode with the potential of the drain electrode set to 0 V, and flowing a current of a predetermined current value from the source electrode to the drain electrode. can be measured by determining the voltage between

Next, a continuous pulse is applied to the gate electrode of the target MOSFET for a predetermined time (step S3: third step). A continuous pulse is a periodic pulse of voltage. For example, in step S3, the voltage applied to the gate electrode of the MOSFET is periodically turned on and off. The frequency of the continuous pulse can be, for example, 100 kHz or more and 500 kHz or less. The duty ratio of continuous pulses can be set to, for example, 10% or more. When applying continuous pulses to the gate electrode of the target MOSFET, a voltage higher than the ON voltage is applied between the source electrode and the drain electrode. A voltage higher than the ON voltage is, for example, a voltage of 5 V or more. At this time, the current flowing between the source electrode and the drain electrode can be, for example, 25 A (0.57 mm ² in active area).

The voltage of the continuous pulse is preferably as high as possible. This is because MOSFET defects do not grow when the voltage of the continuous pulse is low. For example, the continuous pulse is preferably a pulse with a current density of 0.1 A/cm ² or higher and a voltage of 10 V or higher.

The continuous pulse current can be set to 1 A or more and 3 A or less if the silicon carbide semiconductor devices to be sorted are in the wafer state described above. Further, if the silicon carbide semiconductor device to be sorted is in the above-described chip state, the continuous pulse current can be set to 20 A or more and 60 A or less. Further, the current of the continuous pulses can be set to 100 A or more and 300 A or less if the silicon carbide semiconductor device to be sorted is in the product state described above.

The predetermined time during which the continuous pulse is applied is such that the defect in the MOSFET with the defect on the back side will grow sufficiently and the MOSFET with no defect on the back side will not be destroyed. As an example, if the frequency of the continuous pulse is 100 kHz, the predetermined time can be 30 seconds or more and 300 seconds or less.

Next, the threshold voltage of the target MOSFET, the forward voltage of the MOSFET, and the forward voltage of the built-in diode are measured again (step S4: 4th step). These measuring methods are the same as those in step S2.

Next, based on the measurement results in steps S2 and S4, the rate of change of each of the threshold voltage of the MOSFET, the forward voltage of the MOSFET, and the forward voltage of the built-in diode is calculated (step S5: fifth step). . Assuming that the threshold voltage of the MOSFET measured in step S2 is Vth1 and the threshold voltage of the MOSFET measured in step S4 is Vth2, the rate of change in the threshold voltage of the MOSFET is calculated by, for example, Vth2/Vth1. be able to. Also, the change rate of the threshold voltage of the MOSFET may be calculated by (Vth2-Vth1)/T. T is the predetermined time for applying the pulse voltage to the gate electrode in step S3.

Similarly, if the forward voltage of the MOSFET measured in step S2 is Von1 and the forward voltage of the MOSFET measured in step S4 is Von2, the rate of change in the forward voltage of the MOSFET can be calculated by, for example, Von2/Von1. can be done. Also, the change rate of the forward voltage of the MOSFET may be calculated by (Von2-Von1)/T. If the forward voltage of the built-in diode measured in step S2 is Von3, and the forward voltage of the built-in diode measured in step S4 is Von4, the rate of change of the forward voltage of the built-in diode is given by, for example, Von4/Von3. can be calculated. Also, the change rate of the forward voltage of the built-in diode may be calculated by (Von4-Von3)/T.

Next, it is determined whether or not at least one of the rate of change calculated in step S5 is 1% (0.01) or more (step S6: sixth step). If all of the calculated rates of change are less than 1% (step S6: No), it can be determined that there is no defect on the rear surface side of the target MOSFET. In this case, the target MOSFET is sorted out as a qualified product (step S7), and the sorting of the target MOSFET ends.

In step S6, when at least one of the calculated change rates is 1% or more (step S6: Yes), it can be determined that a defect exists on the rear surface side of the target MOSFET. In this case, the target MOSFET is sorted out as a ineligible product (step S8), and the sorting of the target MOSFET ends.

The selection method shown in FIG. It can be determined by a change in direction voltage. Therefore, it is possible to select MOSFETs that have no defect on the back surface side, and screen MOSFETs whose reliability is unlikely to deteriorate even after long-term use.

For example, if at least one of the rate of change of the threshold voltage of the MOSFET, the forward voltage of the MOSFET, and the forward voltage of the built-in diode is 1% (predetermined value) or more, a MOSFET with a defect grows and the electrical characteristics deteriorate. On the other hand, a MOSFET with a rate of change of less than 1% for each of the MOSFET threshold voltage, MOSFET forward voltage, and built-in diode forward voltage has no defects on the back side, so it can be used for a long period of time. It can withstand long-term use with almost no deterioration in characteristics.

In the sorting method shown in FIG. 1, the sorting method for calculating each change rate of the threshold voltage of the MOSFET, the forward voltage of the MOSFET, and the forward voltage of the built-in diode has been described, but the sorting method is not limited to such a sorting method. . For example, the rate of change of some of the characteristic values of the threshold voltage of the MOSFET, the forward voltage of the MOSFET, and the forward voltage of the built-in diode may be calculated.

However, the rates of change of the forward voltage of the MOSFET and the forward voltage of the built-in diode change more with the growth of defects on the back side of the MOSFET than the rate of change of the threshold voltage of the MOSFET. Therefore, from the viewpoint of the sensitivity of detecting the growth of defects on the back side of the MOSFET, it is more preferable to calculate the rate of change of at least one of the forward voltage of the MOSFET and the forward voltage of the built-in diode.

(Silicon carbide semiconductor device according to embodiment)
Next, a silicon carbide semiconductor device according to an embodiment will be described. The structure of the silicon carbide semiconductor device according to the embodiment is the same as the structure of the conventional silicon carbide semiconductor device (see FIG. 6), so illustration is omitted. In the silicon carbide semiconductor device according to the embodiment, an n ^- type silicon carbide epitaxial layer (first conductivity type first semiconductor layer) 2 is deposited.

The n ⁺ -type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer doped with, for example, nitrogen at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 1 . Hereinafter, n ⁺ -type silicon carbide substrate 1 alone, or n ⁺ -type silicon carbide substrate 1 and n-type silicon carbide epitaxial layer 2 are collectively referred to as a silicon carbide semiconductor substrate.

In the silicon ^carbide semiconductor device according to the embodiment, a drain electrode ( A second electrode 11 is provided. Also, the drain electrode 11 is provided with a drain electrode terminal 12 for connection with an external device.

A MOS (metal-oxide film-semiconductor insulating gate) gate structure (element structure) is formed on the front surface side of the silicon carbide semiconductor substrate. Specifically, the p ⁺ -type base region 3 is selected for the surface layer of the n-type silicon carbide epitaxial layer 2 on the side opposite to the n ⁺ -type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate). is provided The p ⁺ -type base region 3 is formed by doping a p-type impurity such as aluminum (Al).

A p-type base layer (second conductivity type second semiconductor layer) 4 is deposited on the side of n-type silicon carbide epitaxial layer 2 opposite to n ⁺ -type silicon carbide substrate 1 . An n ⁺ -type source region (first conductivity type first semiconductor region) 5 , a p ⁺ -type contact region 6 and an n-type well region 7 are selectively provided in the p-type base layer 4 . P-type base layer 4 is a p-type silicon carbide epitaxial layer. The impurity concentration of p-type base layer 4 is lower than that of p ⁺ -type base region 3 . The p-type base layer 4 is formed by doping a p-type impurity such as aluminum.

The n ⁺ -type source region 5 and the p ⁺ -type contact region 6 are in contact with each other. The n ⁺ -type source region 5 is arranged around the p ⁺ -type contact region 6 . N-type well region 7 is provided at a position in contact with a portion of n-type silicon carbide epitaxial layer 2 where p ⁺ -type base region 3 is not formed, and is provided so as to penetrate p-type base layer 4 in the depth direction. It is N-type well region 7 constitutes a drift region together with n-type silicon carbide epitaxial layer 2 . Gate insulating film 8 is provided so as to be in contact with p-type base layer 4 .

A gate electrode 9 is provided on the surfaces of the p-type base layer 4 and the n ⁺ -type source region 5 with a gate insulating film 8 interposed therebetween. A source electrode (first electrode) 10 is provided on the surface of the n ⁺ -type source region 5 and the p ⁺ -type contact region 6 . Gate electrode 9 may be provided on the surface of n-type well region 7 via gate insulating film 8 .

An interlayer insulating film (not shown) is provided over the entire front surface side of the silicon carbide semiconductor substrate so as to cover gate electrode 9 . The source electrode 10 is in contact with the n ⁺ -type source region 5 and the p ⁺ -type contact region 6 through a contact hole opened in the interlayer insulating film. Source electrode 10 is electrically insulated from gate electrode 9 by an interlayer insulating film. Also, the source electrode 10 is provided with a source electrode terminal 13 for connection with an external device. The built-in diode described above includes, for example, a source electrode 10, a p ⁺ -type contact region 6, a p ⁺ -type base region 3, an n-type silicon carbide epitaxial layer 2, an n ⁺ -type silicon carbide substrate 1, and a drain electrode 11. and

(Relationship between frequency of continuous pulses and change rate of threshold voltage of MOSFET)
FIG. 2 is a graph showing an example of the relationship between the frequency of continuous pulses and the change rate of the threshold voltage of a MOSFET. The horizontal axis of FIG. 2 is the frequency (kHz) of the continuous pulse applied to the gate electrode of the MOSFET in step S3 shown in FIG. 1, for example. The vertical axis in FIG. 2 is the change rate (%) of the threshold voltage of the MOSFET calculated in step S5 shown in FIG. 1, for example.

Qualified product characteristics 21 are the characteristics of the rate of change of the threshold voltage of a MOSFET (qualified product) with no defects on the back side thereof with respect to the frequency of continuous pulses applied to the gate electrode. As shown in qualifying product characteristics 21, in a MOSFET with no defect on the back side, even if a continuous pulse of any frequency from 0 kHz to 1000 kHz is applied to the gate electrode, the change rate of the threshold voltage of the MOSFET is almost 0%.

The ineligible product characteristic 22 is the characteristic of the rate of change of the threshold voltage of the MOSFET with a defect on the back side (non-eligible product) with respect to the frequency of continuous pulses applied to the gate electrode. As shown in ineligible product characteristics 22, in a MOSFET with a defect on the back side, even if a continuous pulse of any frequency from 0 kHz to 1000 kHz is applied to the gate electrode, the change rate of the threshold voltage of the MOSFET 1% or more.

Therefore, in step S6 shown in FIG. 1, it is determined whether the MOSFET is a qualified product or an unqualified product by determining whether or not the change rate of the threshold voltage of the MOSFET is 1% or more. can do.

In addition, as shown in the ineligible product characteristic 22, in a MOSFET with a defect on the back side, the rate of change in the threshold voltage of the MOSFET increases as the frequency of the continuous pulse applied to the gate electrode increases. This is because the higher the frequency of the continuous pulse applied to the gate electrode, the greater the excessive thermal resistance in the MOSFET with defects on the back side.

(Relationship between frequency of continuous pulse and forward voltage of MOSFET)
FIG. 3 is a graph showing an example of the relationship between the frequency of continuous pulses and the forward voltage of a MOSFET. The horizontal axis of FIG. 3 represents the frequency (kHz) of continuous pulses applied to the gate electrode of the MOSFET in step S3 shown in FIG. 1, for example. The vertical axis in FIG. 3 is the change rate (%) of the forward voltage of the MOSFET calculated in step S5 shown in FIG. 1, for example.

Qualified product characteristics 31 are the characteristics of the rate of change in the forward voltage of the MOSFET with respect to the frequency of continuous pulses applied to the gate electrode in a MOSFET (qualified product) with no defects on the back side. As shown in qualifying product characteristics 31, in a MOSFET with no defect on the back side, the change rate of the forward voltage of the MOSFET is almost 0 even if a continuous pulse of any frequency from 0 kHz to 1000 kHz is applied to the gate electrode. %become.

The ineligible product characteristic 32 is the characteristic of the change rate of the forward voltage of the MOSFET with a defect on the back side (non-eligible product) with respect to the frequency of continuous pulses applied to the gate electrode. As shown in ineligible product characteristics 32, in a MOSFET with a defect on the back side, the rate of change in the forward voltage of the MOSFET is 1 even if a continuous pulse of any frequency from 0 kHz to 1000 kHz is applied to the gate electrode. % or more.

Therefore, in step S6 shown in FIG. 1, it is determined whether the MOSFET is an acceptable product or an unacceptable product by determining whether or not the rate of change in the forward voltage of the MOSFET is 1% or more. be able to.

Further, as shown in the ineligible product characteristic 32, in a MOSFET with a defect on the back side, the rate of change in the forward voltage of the MOSFET increases as the frequency of the continuous pulse applied to the gate electrode increases. This is because the higher the frequency of the continuous pulse applied to the gate electrode, the greater the excessive thermal resistance in the MOSFET with defects on the back side.

(Relationship between frequency of continuous pulse and forward voltage of built-in diode)
FIG. 4 is a graph showing an example of the relationship between the frequency of continuous pulses and the forward voltage of the built-in diode. The horizontal axis of FIG. 4 represents the frequency (kHz) of the continuous pulse applied to the gate electrode of the MOSFET in step S3 shown in FIG. 1, for example. The vertical axis of FIG. 4 is the change rate (%) of the forward voltage of the built-in diode calculated in step S5 shown in FIG. 1, for example.

A qualifying product characteristic 41 is a characteristic of the rate of change of the forward voltage of the built-in diode with respect to the frequency of continuous pulses applied to the gate electrode in a MOSFET (qualifying product) with no defect on the back side. As shown in qualifying product characteristic 41, in a MOSFET with no defect on the back side, even if a continuous pulse of any frequency from 0 kHz to 1000 kHz is applied to the gate electrode, the change rate of the forward voltage of the built-in diode is almost 0%.

The ineligible product characteristic 42 is the characteristic of the change rate of the forward voltage of the built-in diode with respect to the frequency of continuous pulses applied to the gate electrode in a MOSFET with a defect on the back side (ineligible product). As shown in the ineligible product characteristic 42, in a MOSFET with a defect on the back side, even if a continuous pulse of any frequency from 0 kHz to 1000 kHz is applied to the gate electrode, the change rate of the forward voltage of the built-in diode is 1% or more.

Therefore, in step S6 shown in FIG. 1, it is determined whether the MOSFET is a qualified product or a non-qualified product by determining whether or not the forward voltage change rate of at least the built-in diode is 1% or more. can do.

Further, as shown in the ineligible product characteristic 42, in a MOSFET with a defect on the back side, the higher the frequency of the continuous pulse applied to the gate electrode, the higher the change rate of the forward voltage of the built-in diode. This is because the higher the frequency of the continuous pulse applied to the gate electrode, the greater the excessive thermal resistance in the MOSFET with defects on the back side.

(Another example of structure of silicon carbide semiconductor device according to embodiment)
FIG. 5 is a cross-sectional view showing another example of the structure of the silicon carbide semiconductor device according to the embodiment. As shown in FIG. 5, the silicon carbide semiconductor device according to the embodiment may be a MOSFET having a trench structure. Compared to a planar structure in which channels are formed parallel to the substrate surface (see, eg, FIG. 6), a trench structure in which the channels are formed perpendicular to the substrate surface can increase the cell density per unit area. Therefore, the current density per unit area can be increased, which is advantageous in terms of cost.

In FIG. 5, a trench structure including a trench 18 is formed on the first main surface side (p-type base layer 4 side) of the silicon carbide semiconductor substrate. Specifically, trench 18 penetrates p-type base layer 4 from the surface of p-type base layer 4 opposite to n ⁺ -type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate). reaches the inside of n-type silicon carbide epitaxial layer 2 .

A gate insulating film 8 is formed on the bottom and sidewalls of trench 18 along the inner wall of trench 18 , and gate electrode 9 is formed inside gate insulating film 8 in trench 18 . Gate insulating film 8 insulates gate electrode 9 from n-type silicon carbide epitaxial layer 2 and p-type base layer 4 . A portion of the gate electrode 9 may protrude from above the trench 18 (the side where the source electrode terminal 13 is provided) toward the source electrode terminal 13 .

A p ⁺ -type base region 3 is selectively provided in a surface layer of n-type silicon carbide epitaxial layer 2 on the side opposite to n ⁺ -type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate). there is The lower end (drain-side end) of p ⁺ -type base region 3 is positioned closer to the drain than the bottom of trench 18 .

Further, inside n-type silicon carbide epitaxial layer 2, second p ⁺ -type region 3a is selectively provided. Second p ⁺ -type region 3 a is provided so as to contact the bottom of trench 18 . Second p ⁺ -type region 3a extends from the interface between n ⁺ -type silicon carbide substrate 1 and n-type silicon carbide epitaxial layer 2 from a position closer to the drain than the interface between p-type base layer 4 and n-type silicon carbide epitaxial layer 2. provided at a depth that does not reach

Other structures of the MOSFET shown in FIG. 5 are the same as those of the MOSFET shown in FIG. Even in a MOSFET having a trench structure, if the defect on the back surface side expands, the electrical characteristics in general deteriorate, so the screening method of the present invention is effective.

Although the case where the selection method according to the embodiment is applied to a MOSFET has been described, the selection method according to the embodiment can also be applied to IGBTs and SBDs (Schottky Barrier Diodes) using SiC. In the case of SBDs, for example, by applying a positive voltage pulse signal to the anode electrode, it is possible to select SBDs based on the forward voltage change rate.

For example, IGBTs using SiC can be selected in the same manner as MOSFETs by setting the frequency of the continuous pulse to about 10 kHz or more and 50 kHz or less. For SBDs using SiC, for example, by applying a continuous pulse of positive voltage to the anode electrode and calculating the change rate of the forward voltage of the SBD, it is possible to select the same as the MOSFET.

As described above, according to the silicon carbide semiconductor device sorting method according to the embodiment, the silicon carbide semiconductor device is adjusted to a predetermined temperature, and the overheat resistance is reduced by applying continuous pulses to the gate electrode for a predetermined time. It is possible to calculate the rate of change of the characteristic value that changes accordingly. This characteristic value is at least one of the forward voltage of the silicon carbide semiconductor device, the forward voltage of the built-in diode of the silicon carbide semiconductor device, and the threshold voltage of the silicon carbide semiconductor device.

Then, by determining whether or not the calculated rate of change is lower than 1%, the magnitude of the overheat resistance of the silicon carbide semiconductor device caused by applying continuous pulses to the gate electrode of the silicon carbide semiconductor device for a predetermined period of time is determined. can do. Thereby, it is possible to select silicon carbide semiconductor devices that do not have defects on the back surface side, and to screen silicon carbide semiconductor devices that are less likely to deteriorate in reliability even after long-term use.

Further, the time required for the above selection is the time until the change rate of the above characteristic value exceeds 1% by applying continuous pulses to the gate electrode of the silicon carbide semiconductor device having a defect on the back surface side. Therefore, silicon carbide semiconductor devices can be screened in a short time.

The present invention can be modified in various ways without departing from the scope of the present invention, and in the above-described embodiments, for example, the dimensions and impurity concentration of each part can be set variously according to the required specifications. In addition, in the above-described embodiments, the case of using silicon carbide as a wide bandgap semiconductor is described as an example, but the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN) and diamond. It is possible. In addition, although the first conductivity type is n-type and the second conductivity type is p-type in the embodiments, the present invention can be similarly applied even if the first conductivity type is p-type and the second conductivity type is n-type. .

The method for selecting silicon carbide semiconductor devices according to the present invention is useful, for example, for silicon carbide semiconductor devices used in inverter circuits in which diodes are connected in anti-parallel to silicon carbide semiconductor devices.

1 n ⁺ type silicon carbide substrate 2 n type silicon carbide epitaxial layer 3 p ⁺ type base region 3a second p ⁺ type region 4 p type base layer 5 n ⁺ type source region 6 p ⁺ type contact region 7 n type well region 8 gate Insulating film 9 Gate electrode 10 Source electrode 11 Drain electrode 12 Drain electrode terminal 13 Source electrode terminal 18 Trench 21, 31, 41 Acceptable product characteristics 22, 32, 42 Unacceptable product characteristics

Claims (9)

A method for selecting a silicon carbide semiconductor device comprising a MOSFET , comprising:
The MOSFET includes a first electrode and a gate electrode provided on a front surface side of a silicon carbide substrate;
a second electrode provided on the back surface side of the silicon carbide substrate,
a first step of setting the temperature of the MOSFET to a predetermined temperature;
a second step of measuring the forward voltage of the MOSFET at the predetermined temperature;
After the second step, a third step of applying a continuous pulse to the gate electrode for a predetermined time while a positive voltage higher than the ON voltage of the MOSFET is applied to the second electrode ;
After the third step, a fourth step of measuring again the forward voltage of the MOSFET measured in the second step at the predetermined temperature;
a fifth step of calculating the rate of change of the forward voltage measured in the fourth step with respect to the forward voltage measured in the second step;
a sixth step of determining whether the rate of change calculated in the fifth step is lower than a predetermined value;
including
In each of the second step and the fourth step, the above-described A method for selecting a silicon carbide semiconductor device, comprising measuring a forward voltage of a MOSFET . A method for selecting a silicon carbide semiconductor device comprising a MOSFET , comprising:
The MOSFET includes a first electrode and a gate electrode provided on a front surface side of a silicon carbide substrate;
a second electrode provided on the back surface side of the silicon carbide substrate,
a first step of setting the temperature of the MOSFET to a predetermined temperature;
a second step of measuring a threshold voltage of the MOSFET as a characteristic value of the MOSFET at the predetermined temperature;
After the second step, a third step of applying a continuous pulse to the gate electrode for a predetermined time while a positive voltage higher than the ON voltage of the MOSFET is applied to the second electrode ;
After the third step, a fourth step of measuring again the threshold voltage of the MOSFET as the characteristic value of the MOSFET measured in the second step at the predetermined temperature;
a fifth step of calculating a rate of change of the characteristic value measured in the fourth step with respect to the characteristic value measured in the second step;
a sixth step of determining whether the rate of change calculated in the fifth step is lower than a predetermined value;
including
In each of the second step and the fourth step, the threshold voltage of the MOSFET is measured by applying a voltage to the gate electrode while applying a positive voltage to the second electrode. A method for selecting a silicon carbide semiconductor device. The characteristic value further includes a forward voltage of the MOSFET ,
In each of the second step and the fourth step, the above-described Also measure the forward voltage of the MOSFET,
In the fifth step, for each of the plurality of characteristic values, the rate of change of the characteristic value measured in the fourth step with respect to the characteristic value measured in the second step is calculated;
In the sixth step, determining whether at least one of the rate of change calculated for each of the plurality of characteristic values in the fifth step is lower than the predetermined value;
3. The method for sorting silicon carbide semiconductor devices according to claim 2, wherein: The characteristic value further includes a forward voltage of a built-in diode of the MOSFET,
In each of the second step and the fourth step, the current density is 0.1 A/cm ² measuring the forward voltage of the built-in diode of the MOSFET by applying a voltage of 1 V or more to the first electrode to flow a current from the first electrode to the second electrode;
In the fifth step, for each of the plurality of characteristic values, the rate of change of the characteristic value measured in the fourth step with respect to the characteristic value measured in the second step is calculated;
In the sixth step, determining whether at least one of the rate of change calculated for each of the plurality of characteristic values in the fifth step is lower than the predetermined value;
4. The method for sorting silicon carbide semiconductor devices according to claim 2 or 3, characterized in that: The MOSFET is
a first conductivity type first semiconductor layer provided on the front surface of the silicon carbide substrate;
a second conductivity type second semiconductor layer provided on a side of the first semiconductor layer opposite to the silicon carbide substrate;
a first conductivity type first semiconductor region selectively provided inside the second semiconductor layer and having an impurity concentration higher than that of the silicon carbide substrate;
a gate insulating film in contact with the second semiconductor layer;
further comprising
the gate electrode is provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
The first electrode is provided on the surface of the first semiconductor region and the second semiconductor layer,
The method for sorting silicon carbide semiconductor devices according to any one of claims 1 to 4, characterized in that: The MOSFET further comprises a trench penetrating the second semiconductor layer and reaching the first semiconductor layer,
The gate electrode is provided inside the trench via the gate insulating film,
6. The method for sorting silicon carbide semiconductor devices according to claim 5, wherein: 7. The method for sorting silicon carbide semiconductor devices according to claim 1, wherein said predetermined temperature is a temperature of 300.degree. C. or less. 8. The method for sorting silicon carbide semiconductor devices according to claim 1, wherein said predetermined value is 1%. 9. The method for selecting silicon carbide semiconductor devices according to claim 1, wherein the frequency of said continuous pulse is 100 kHz or more and 500 kHz or less.

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