JP7013683B2 - Method for selecting silicon carbide semiconductor devices - Google Patents

Description

The present invention relates to a method for selecting a silicon carbide semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device that controls a high voltage or a large current. There are multiple types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors: Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which can be used according to the application. Has been done.

For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can increase the current, but they cannot be switched at high speed. Specifically, the bipolar transistor is limited to use at a switching frequency of about several kHz, and the IGBT is limited to use at a switching frequency of about several tens of kHz. On the other hand, the power MOSFET has a lower current density than the bipolar transistor and the IGBT, and it is difficult to increase the current, but high-speed switching operation up to about several MHz is possible.

However, there is a strong demand in the market for power semiconductor devices that have both high current and high speed, and efforts are being made to improve IGBTs and power MOSFETs, and development is now progressing to near the material limit. .. Silicon carbide (SiC) is being studied as a semiconductor material that can replace silicon from the viewpoint of power semiconductor devices, and can manufacture (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. Is attracting attention.

In the background, SiC is a chemically stable material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. This is also because the maximum electric field strength is one order of magnitude higher than that of silicon. Since SiC has a high possibility of exceeding the material limit of silicon, future growth is expected in power semiconductor applications, especially MOSFETs. In particular, it is expected that the on-resistance is small, but a vertical SiC- MOSFET having a lower on-resistance while maintaining high withstand voltage characteristics can be expected.

The structure of a conventional silicon carbide semiconductor device will be described by taking a vertical MOSFET as an example. FIG. 5 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 5, an n-type silicon carbide epitaxial layer 2 is deposited on the front surface of the n ⁺ type silicon carbide substrate 1, and a p ⁺ type base region 3 and a p-type are deposited on the surface of the n-type silicon carbide epitaxial layer 2. The base layer 4 is selectively provided. Further, an n ⁺ type source region 5, a p ⁺ type contact region 6, and an n-type well region 7 are selectively provided on the surface of the p-type base layer 4.

A gate electrode 9 is provided on the surface of the p-type base layer 4 and the n ⁺ -type source region 5 via a gate insulating film 8. Further, a source electrode 10 is provided on the surface of the n-type silicon carbide epitaxial layer 2, the p ⁺ type contact region 6 and the n ⁺ type source region 5. Further, a drain electrode 11 is provided on the back surface of the n ⁺ type silicon carbide substrate 1.

A vertical MOSFET having such a structure incorporates a parasitic pn diode formed by a p ⁺ type base region 3 and an n-type silicon carbide epitaxial layer 2 as a body diode between a source and a drain. This parasitic pn diode can be operated by applying a high potential to the source electrode 10, and a current flows in the direction indicated by the arrow A in FIG. As described above, unlike the IGBT, the MOSFET has a built-in parasitic pn diode, so that the freewheeling diode (FWD: Free Wheeling Diode) used for the inverter can be omitted, which contributes to cost reduction and miniaturization. Hereinafter, the parasitic pn diode of the MOSFET is referred to as a built-in diode.

However, in the silicon carbide semiconductor device, the crystal of the n ⁺ type silicon carbide substrate 1 may be defective. In this case, when a current flows through the built-in diode, holes are injected from the p ⁺ type contact region 6, and electron and hole recombination occur in the n-type silicon carbide epitaxial layer 2 or the n ⁺ type silicon carbide substrate 1. The rebinding energy (3eV) corresponding to the bandgap generated at this time causes the basal plane dislocation, which is a kind of crystal defect existing in the n ⁺ type silicon carbide substrate 1, to move, and the stacking defect sandwiched between the two basal plane dislocations. Extends.

When the stacking defect expands, the stacking defect does not easily carry current, so that the on-resistance of the MOSFET and the forward voltage of the built-in diode increase. If such an operation continues, the stacking defects are cumulatively expanded, so that the loss generated in the inverter circuit increases with time and the amount of heat generated also increases, which causes a device failure. In order to prevent this problem, a SiC-SBD (Schottky Barrier Diode) can be connected in antiparallel to the MOSFET so that current does not flow to the built-in diode of the MOSFET.

FIG. 6 is a diagram showing an example of an inverter circuit using a conventional silicon carbide MOSFET. The inverter circuit includes a plurality of MOSFETs (four MOSFETs 21, 22, 23, 24 in FIG. 6) and is a circuit for driving a load 25 such as a motor. In FIG. 6, the diodes 26, 27, 28, and 29 indicate the built-in diodes of the MOSFETs 21, 22, 23, and 24, respectively. Further, the diodes 30, 31, 32, and 33 indicate SiC-SBDs connected in antiparallel to MOSFETs 21, 22, 23, and 24, respectively. FIG. 6 shows only two sets of two phases of the inverter circuit, that is, two sets of MOSFETs connected in series.

In the inverter circuit shown in FIG. 6, by turning on the MOSFETs 21 and 24 by the signal from the input circuit 34, a current can be passed through the load 25 in the direction of the arrow B. After that, by turning off the MOSFETs 21 and 24 and turning on the MOSFETs 22 and 23 by the signal from the input circuit 34, a current can be passed through the load 25 in the direction of the arrow C. By changing the direction of the current in this way, for example, the arm connected to the motor of the load 25 can be moved left and right.

Here, when the MOSFETs 21 and 24 are off, a reflux current flows through the MOSFETs 21 and 24 in the direction opposite to the arrow B. The return current flows through the SiC-SBDs 30 and 33 having a low threshold voltage Vf, and does not flow through the built-in diodes 26 and 29. Similarly, the MOSFETs 22 and 23 do not flow to the built-in diodes 27 and 28. In this way, when the MOSFET is off, no return current flows through the built-in diode, so that the stacking defect of the MOSFET does not expand.

As an energization inspection device for silicon carbide semiconductor devices, the temperature of the bipolar semiconductor device is set to 150 ° C. or higher and 230 ° C. or lower, and a forward current with a current density of 120 A / cm ² or higher and 400 A / cm ² or lower is continuously applied. A technique for determining whether or not the degree of change in forward resistance is less than a threshold when the forward resistance becomes saturated is known (see, for example, Patent Document 1). Further, as an inspection method of a silicon carbide semiconductor device, a pulse current is passed through a diode to obtain the on-resistance of the diode before and after the pulse current is passed, and a defect of the semiconductor device is found based on the change before and after the pulse current of the on-resistance is passed. The determination technique is known (see, for example, Patent Document 2).

International Publication No. 2014/148294 Japanese Patent Application Laid-Open No. 2015-655250

However, even when the SiC-SBD is connected in antiparallel to the MOSFET as shown in FIG. 6, a current may flow through the built-in diode of the MOSFET at the moment when the MOSFET is switched from on to off, resulting in a stacking defect of the MOSFET. May expand. FIG. 7 is a graph showing the temporal change of the current flowing through the diode of the inverter circuit. In FIG. 7, the horizontal axis represents time and the vertical axis represents current. In FIG. 7, I1 shows the current flowing through the built-in diode, I2 shows the current flowing through the SiC-SBD, and I3 shows the total current flowing through the built-in diode and the SiC-SBD.

FIG. 7 shows the temporal change of the current when the MOSFET is turned from on to off at time T. As shown in FIG. 7, when the MOSFET is turned off, the current I2 flowing through the SiC-SBD gradually increases and settles at a constant value. The current I1 flowing through the built-in diode increases immediately after the MOSFET is turned off, then gradually decreases, and settles at 0.

In this way, the current I1 flowing through the built-in diode is not always 0, but flows only for a short period of the transient state in which the MOSFET is turned from on to off. Hereinafter, this current is referred to as a transient current. FIG. 8 is a graph showing on / off of the silicon carbide MOSFET in the inverter circuit. In FIG. 8, the horizontal axis represents time and the vertical axis represents voltage. As shown in FIG. 8, the time t1 in which the transient current flows through the built-in diode is shorter than the time t2 in which the transient current does not flow. Specifically, the time t1 in which the transient current flows is about several ns after the MOSFET is turned off. However, since MOSFETs are switched at high speed, for example, switching at several MHz, the total time during which a transient current flows during long-term use is a non-negligible amount. Depending on the amount of defects in the crystals of the silicon carbide substrate of the MOSFET, the stacking defects will expand due to the transient current, and the reliability of the MOSFET will decrease.

In order to solve the problems caused by the above-mentioned prior art, the present invention provides a silicon carbide semiconductor device whose reliability does not deteriorate even when used for a long time in an inverter circuit in which a diode is connected in antiparallel to the silicon carbide semiconductor device. It is an object of the present invention to provide a method for selecting a silicon carbide semiconductor device that can be screened.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for selecting a silicon carbide semiconductor device according to the present invention has the following features. A method for selecting a silicon carbide semiconductor device having a MOS FET , first, a first step of setting the temperature of the silicon carbide semiconductor device to 50 ° C. or higher and 145 ° C. or lower is performed. Next, a second step is performed in which a forward current having a current density of 118 A / cm ² or less is passed through the built-in diode of the MOSFET . Before and after the second step, a third step of measuring the forward voltage of the MOSFET is performed. Next, a fourth step of calculating the rate of change of the forward voltage of the MOSFET from the measured forward voltage is performed. Next, a fifth step of selecting the silicon carbide semiconductor device having the calculated rate of change of less than 3% is performed. Further, the method for selecting a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the silicon carbide semiconductor device further includes a diode connected in antiparallel to the MOSFET.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for selecting a silicon carbide semiconductor device according to the present invention has the following features. A method for selecting a silicon carbide semiconductor device used in an inverter circuit including a silicon carbide semiconductor device having a MOS gate structure and a diode connected in antiparallel to the silicon carbide semiconductor device. First, the silicon carbide semiconductor device is selected. The first step of setting the temperature of the semiconductor device to 50 ° C. or higher and 145 ° C. or lower is performed. Next, the current density of the built-in diode of the silicon carbide semiconductor device is 118 A / cm. ² The second step of passing the following forward current is performed. Before and after the second step, a third step of measuring the forward voltage of the built-in diode of the silicon carbide semiconductor device is performed. Next, a fourth step of calculating the rate of change of the forward voltage of the built-in diode of the silicon carbide semiconductor device from the measured forward voltage is performed. Next, a fifth step of selecting the silicon carbide semiconductor device having the calculated rate of change of less than 3% is performed.

Further, the method for selecting a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the temperature of the silicon carbide semiconductor device is set to 60 ° C. or higher and 90 ° C. or lower in the first step.

Further, in the method for selecting a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, in the fifth step, the calculated rate of change is saturated and the calculated rate of change is lower than 3%. It is characterized by selecting semiconductor devices.

Further, the method for selecting a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the diode is a silicon carbide Schottky barrier diode.

Further, as for the method for selecting a silicon carbide semiconductor device according to the present invention, in the above-described invention, the silicon carbide semiconductor device is provided with a first conductive type first semiconductor layer on the front surface of the silicon carbide substrate. A second conductive type second semiconductor layer is provided on the side of the first semiconductor layer opposite to the silicon carbide substrate side. A first conductive type first semiconductor region having a higher impurity concentration than the silicon carbide substrate is selectively provided inside the second semiconductor layer. A gate insulating film that comes into contact with the second semiconductor layer is provided. A gate electrode is provided on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer. The first electrode is provided on the surface of the first semiconductor region and the second semiconductor layer. A second electrode is provided on the back surface of the silicon carbide substrate.

Further, in the method for selecting a silicon carbide semiconductor device according to the present invention, in the above-described invention, the silicon carbide semiconductor device further includes a trench that penetrates the second semiconductor layer and reaches the first semiconductor layer. The gate electrode is characterized in that it is provided inside the trench via the gate insulating film.

According to the above-mentioned invention, the silicon carbide semiconductor device is set to 50 ° C. or higher and 145 ° C. or lower, a forward current having a current density of 118 A / cm ² or less is passed, and the rate of change of the forward voltage is lower than 3%. We are selecting semiconductor devices. As a result, even if the inverter circuit in which the diode is connected in antiparallel to the silicon carbide semiconductor device is used for a long time, the stacking defect of the substrate is less likely to grow and the characteristics of the silicon carbide semiconductor device are not deteriorated. Therefore, it is possible to screen a silicon carbide semiconductor device that does not reduce reliability.

Further, the time required for sorting is a short time until the rate of change of the forward voltage exceeds 3% or the rate of change of the forward voltage is saturated. Therefore, the silicon carbide semiconductor device can be screened in a short time.

According to the method for selecting a silicon carbide semiconductor device according to the present invention, a silicon carbide semiconductor device whose reliability does not deteriorate even when used for a long time in an inverter circuit in which a diode is connected in antiparallel to the silicon carbide semiconductor device can be obtained. It has the effect of being able to be screened.

It is a flowchart which shows the selection method of the silicon carbide semiconductor device which concerns on embodiment. It is a graph which shows the relationship between the current density in the built-in diode of a MOSFET and the rate of change of a forward voltage. It is a graph which shows the example of the selection method of the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the other structure of the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the structure of the conventional silicon carbide semiconductor device. It is a figure which shows an example of the inverter circuit using the conventional silicon carbide MOSFET. It is a graph which shows the time change of the current flowing through the diode of an inverter circuit. It is a graph which shows the on / off of a silicon carbide MOSFET in an inverter circuit.

Hereinafter, preferred embodiments of the method for selecting a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electron or hole is a large number of carriers in the layer or region marked with n or p, respectively. Further, + and-attached to n and p mean that the concentration of impurities is higher and the concentration of impurities is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment)
FIG. 1 is a flowchart showing a method of selecting a silicon carbide semiconductor device according to an embodiment. Hereinafter, MOSFETs will be described as an example of the silicon carbide semiconductor device, but the same applies to other silicon carbide semiconductor devices having a MOS gate structure. In the method for selecting a silicon carbide semiconductor device, first, the temperature of the MOSFET is set (step S1).

In the embodiment, the temperature of the MOSFET is set to 50 ° C. or higher and 145 ° C. or lower. More preferably, the temperature of the MOSFET is set to 60 ° C. or higher and 90 ° C. or lower. If the temperature is lower than 50 ° C., even if a current flows through the built-in diode, the defect does not grow and the MOSFET with a defect in the substrate cannot be screened. Further, if the temperature is higher than 145 ° C., other types of defects different from the defects that grow due to the current flowing through the built-in diode grow, and the MOSFET targeted by the present invention cannot be screened.

Further, the temperature of the MOSFET can be set by energizing the built-in diode of the MOSFET. For example, a forward current with a constant current density is applied by energizing the MOSFET until it reaches the above temperature range. Here, the forward current is the current flowing from the source electrode to the drain electrode.

Next, a forward current is applied to the built-in diode of the MOSFET (step S2). Specifically, the gate electrode and the source electrode of the MOSFET are short-circuited, a positive voltage is applied to the source electrode, and the potential of the drain electrode is set to 0. Further, in the embodiment, a forward current having a current density of 118 A / cm ² or less is passed. The current flowing here may be direct current or pulse current.

Here, FIG. 2 is a graph showing the relationship between the current density and the rate of change of the forward voltage in the built-in diode of the MOSFET. In FIG. 2, the horizontal axis is the current density flowing through the built-in diode, and the unit is A / cm ² . The vertical axis is the rate of change of the forward voltage, and the unit is%. As shown in FIG. 2, the rate of change of the forward voltage increases as the current density increases. The increase in the rate of change of the forward voltage means that the stacking defects of the substrate grow and the on-resistance increases. As described above, it is better to increase the current density in order to detect the defect of the MOSFET. Therefore, in the embodiment, the current density is set to 118 A / cm ² or less.

Next, the forward voltage in the initial state is measured (step S3). In order to judge the growth of stacking defects on the substrate by the change in the forward voltage, the forward voltage in the initial state is measured. Specifically, the voltage between the source electrode and the drain electrode is measured. Let V0 be the voltage measured here. Next, it waits for a predetermined time (step S4). If there is a defect in the substrate, wait for the stacking defect to grow. Here, the predetermined time may be about 1 minute.

Next, the forward voltage is measured (step S5). The voltage measured here is V1. Next, the rate of change of the forward voltage is calculated (step S6). The rate of change of the forward voltage is the rate of change from the forward voltage in the initial state. For example, the rate of change of the forward voltage can be calculated by (V1-V0) / V0 × 100 [%].

Next, it is determined whether or not the rate of change of the forward voltage is ≧ 0.03 (3% or more) (step S7). Here, when it is determined that the rate of change of the forward voltage is not ≥ 0.03 (step S7: No), it is determined whether or not the rate of change of the forward voltage has not changed (step S8). Here, the change in the rate of change of the forward voltage means that the stacking defect of the substrate grows and the on-resistance increases. Since the stacking defect may grow further and the rate of change of the forward voltage ≥ 0.03, the measurement of the forward voltage is continued. Therefore, when the rate of change of the forward voltage is not unchanged (step S8: No), the process returns to step S4, the forward voltage is measured again, and the forward voltage change rate is determined. When the step S8 is performed first, the rate of change of the forward voltage is calculated only once, and it cannot be determined whether or not the rate of change of the forward voltage has changed. Return to S4.

Next, when the rate of change of the forward voltage does not change (step S8: Yes), the change of the forward voltage is saturated, and the rate of change of the forward voltage <0.03 (less than 3%) is in order. Since the directional voltage does not increase, the MOSFET is selected as a qualified product (step S9). On the other hand, when it is determined that the rate of change of the forward voltage ≥ 0.03 (step S7: Yes), the MOSFET is selected as an unqualified product (step S10). As described above, in the embodiment, the MOSFET can be sorted in a short time until the rate of change of the forward voltage exceeds 3% or the rate of change of the forward voltage is saturated. Further, here, the saturation of the rate of change of the forward voltage is judged from the fact that the rate of change of the forward voltage does not change once, but it is judged from the fact that the rate of change of the forward voltage does not change multiple times. May be good.

Here, when a MOSFET having a forward voltage change rate of 3% or more is used in an inverter circuit in which SiC-SBD is connected in antiparallel to the MOSFET and operated for a long period of time, stacking defects on the substrate grow and the MOSFET grows. The characteristics of the are deteriorated. Therefore, this MOSFET is judged to be ineligible. On the other hand, even if a MOSFET in which the rate of change of the forward voltage is less than 3% and the rate of change of the forward voltage does not change any more is used for the inverter circuit and operated for a long period of time, the growth of stacking defects on the substrate is small. It can withstand long-term use without deteriorating the characteristics of the MOSFET.

In this flowchart, a current is passed through the built-in diode of the MOSFET to measure the forward voltage of the built-in diode, but a current may be passed through the MOSFET to measure the forward voltage of the MOSFET. Specifically, in a state where a positive voltage is applied to the drain electrode 11 with respect to the source electrode 10, a voltage equal to or higher than the gate threshold is applied to the gate electrode 9 to pass a current through the MOSFET, and the source electrode 10 and the drain electrode are used. Measure the forward voltage between 11 and 11.

As a result, a series of processes according to this flowchart is completed. By executing this flowchart, it is possible to screen a MOSFET whose reliability does not deteriorate even if it is used for a long time in an inverter circuit in which a diode is connected to the MOSFET in antiparallel.

Next, the silicon carbide semiconductor device according to the embodiment will be described. Since the structure of the silicon carbide semiconductor device according to the embodiment is the same as the structure of the conventional silicon carbide semiconductor device (see FIG. 5), the illustration is omitted.

The silicon carbide semiconductor device according to the embodiment is an n-type silicon carbide epitaxial layer (first conductive type first semiconductor layer) on the main surface (front surface) of the n ⁺ type silicon carbide substrate (silicon carbide substrate) 1. ) 2 is deposited.

The n ⁺ type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer in which, for example, nitrogen is doped with an impurity concentration lower than that of the n ⁺ type silicon carbide substrate 1. Hereinafter, the n ⁺ type silicon carbide substrate 1 alone, or the n ⁺ type silicon carbide substrate 1 and the n-type silicon carbide epitaxial layer 2 are combined to form a silicon carbide semiconductor substrate.

The silicon carbide semiconductor device according to the embodiment has a drain on the surface (the back surface of the silicon carbide semiconductor substrate) opposite to the n-type silicon carbide epitaxial layer 2 side of the n ⁺ type silicon carbide substrate 1 which is a drain region. An electrode (second electrode) 11 is provided. Further, a drain electrode pad (not shown) for connecting to an external device is provided.

A MOS (insulated gate made of metal-oxide film-semiconductor) gate structure (element structure) is formed on the front surface side of the silicon carbide semiconductor substrate. Specifically, the p ⁺ type base region 3 is on the surface layer of the n-type silicon carbide epitaxial layer 2 on the side opposite to the n ⁺ type silicon carbide substrate 1 side (the front surface side of the silicon carbide semiconductor substrate). Is selectively provided. The p ⁺ type base region 3 is doped with, for example, aluminum (Al).

A p-type silicon carbide epitaxial layer (hereinafter referred to as p-type base layer) 4 is formed on the surface of the n-type silicon carbide epitaxial layer 2 sandwiched between the p ⁺ type base region 3 and the adjacent p ⁺ type base regions 3. Are selectively deposited. The impurity concentration of the p-type base layer (second conductive type second semiconductor layer) 4 is lower than the impurity concentration of the p ⁺ type base region 3. The p-type base layer 4 is doped with, for example, aluminum.

An n ⁺ type source region (first conductive type first semiconductor region) 5 and a p ⁺ type contact region 6 are provided on the surface of the p-type base layer 4 on the p ⁺ type base region 3. Further, the n ⁺ type source region 5 and the p ⁺ type contact region 6 are in contact with each other. The n ⁺ type source region 5 is arranged on the outer periphery of the p ⁺ type contact region 6.

Further, in the portion of the p-type base layer 4 on the n-type silicon carbide epitaxial layer 2, an n-type well region 7 that penetrates the p-type base layer 4 in the depth direction and reaches the n-type silicon carbide epitaxial layer 2 is provided. Has been done. The n-type well region 7 constitutes a drift region together with the n-type silicon carbide epitaxial layer 2. A gate electrode 9 is provided on the surface of the portion of the p-type base layer 4 sandwiched between the n ⁺ type source region 5 and the n-type well region 7 via the gate insulating film 8. The gate electrode 9 may be provided on the surface of the n-type well region 7 via the gate insulating film 8.

The interlayer insulating film (not shown) is provided on the entire surface of the silicon carbide semiconductor substrate on the front surface side so as to cover the gate electrode 9. The source electrode (first electrode) 10 is in contact with the n ⁺ type source region 5 and the p ⁺ type contact region 6 via a contact hole opened in the interlayer insulating film. The source electrode 10 is electrically insulated from the gate electrode 9 by an interlayer insulating film. An electrode pad (not shown) is provided on the source electrode 10.

FIG. 3 is a graph showing an example of a method for selecting a silicon carbide semiconductor device according to an embodiment. In FIG. 3, the horizontal axis indicates the current application time, the vertical axis indicates the rate of change of the forward voltage, and the unit is%. Here, Example 1 of FIG. 3 is an example of an unqualified product, and Example 2 is an example of a qualified product.

First, the case of Example 1 will be described. The temperature of the MOSFET is set to 50 ° C. or higher and 145 ° C. or lower, and a forward current having a current density of 118 A / cm ² or lower is applied to the built-in diode of the MOSFET. Next, the initial value of the forward voltage is measured at time t0. Next, after waiting for a predetermined time, the forward voltage is measured at time t1 and the rate of change of the forward voltage is calculated. The rate of change of the forward voltage calculated at time t1 is 3% or less, which is the first calculation of the forward voltage. Therefore, after waiting for a predetermined time, the forward voltage is measured at time t2 and the change of the forward voltage is performed. Calculate the rate. The rate of change of the forward voltage calculated at time t2 is 3% or less, and the rate of change has changed compared to the rate of change at time t1. Therefore, after waiting for a predetermined time, the forward voltage is applied at time t3. Measure and calculate the rate of change of forward voltage. Here, since the rate of change of the forward voltage calculated at time t3 exceeds 3%, the MOSFET is selected as an unqualified product.

Next, the case of Example 2 will be described. As in the case of Example 1, a forward current is applied to the built-in diode of the MOSFET, and the initial value of the forward voltage is measured at time t0. Next, after waiting for a predetermined time, the forward voltage is measured at time t1 and the rate of change of the forward voltage is calculated. The rate of change of the forward voltage calculated at time t1 is 3% or less, which is the first calculation of the forward voltage. Therefore, after waiting for a predetermined time, the forward voltage is measured at time t2 and the change of the forward voltage is performed. Calculate the rate. The rate of change of the forward voltage calculated at time t2 is 3% or less, and the rate of change has changed compared to the rate of change at time t1. Therefore, after waiting for a predetermined time, the forward voltage is applied at time t3. Measure and calculate the rate of change of forward voltage. The time t3 and t4 are the same as the case of time t2. On the other hand, at time t5, the calculated rate of change in the forward voltage is 3% or less, and the rate of change at time t4 and the rate of change at time t5 are equal and do not change. Therefore, the measurement is completed and the MOSFET is selected as a qualified product.

FIG. 4 is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a vertical MOSFET provided with a trench structure. In a vertical MOSFET, a trench structure in which channels are formed perpendicular to the substrate surface can increase the cell density per unit area rather than a planar structure in which channels are formed parallel to the substrate surface. The current density per area can be increased, which is advantageous in terms of cost.

In FIG. 4, a trench structure is formed on the first main surface side (p-type base layer 4 side) of the silicon carbide semiconductor substrate. Specifically, the trench 18 penetrates the p-type base layer 4 from the surface opposite to the n ⁺ type silicon carbide substrate 1 side of the p-type base layer 4 (the first main surface side of the silicon carbide semiconductor substrate). Then, it reaches the n-type silicon carbide epitaxial layer 2. A gate insulating film 8 is formed on the bottom and side walls of the trench 18 along the inner wall of the trench 18, and a gate electrode 9 is formed inside the gate insulating film 8 in the trench 18. The gate electrode 9 is insulated from the n-type silicon carbide epitaxial layer 2 and the p-type base layer 4 by the gate insulating film 8. A part of the gate electrode 9 may protrude from above the trench 18 (the side where the source electrode pad is provided) toward the source electrode pad side.

A p ⁺ type base region 3 is selectively provided on the surface of the n-type silicon carbide epitaxial layer 2 on the side opposite to the n ⁺ type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). ing. The p ⁺ type base region 3 reaches a position deeper on the drain side than the bottom of the trench 18. The lower end portion (drain side end portion) of the p ⁺ type base region 3 is located on the drain side with respect to the bottom portion of the trench 18.

Further, a second p ⁺ type region 3a is selectively provided inside the n-type silicon carbide epitaxial layer 2. The second p ⁺ type region 3a is provided so as to be in contact with the bottom of the trench 18. The second p ⁺ type region 3a includes the n ⁺ type silicon carbide substrate 1 and the n-type silicon carbide epitaxial layer 2 from a position deeper on the drain side than the interface between the p-type base layer 4 and the n-type silicon carbide epitaxial layer 2. It is provided at a depth that does not reach the interface.

Since the other structure of the MOSFET shown in FIG. 4 is the same as the structure of the MOSFET shown in FIG. 5, the description thereof will be omitted. Since the vertical MOSFET provided with the trench structure also has a built-in diode composed of the p-type base layer 4 and the n-type silicon carbide epitaxial layer 2, the sorting method of the present invention is effective.

As described above, according to the method for selecting a silicon carbide semiconductor device according to the embodiment, the temperature of the silicon carbide semiconductor device is set to 50 ° C. or higher and 145 ° C. or lower, and the current density is 118 A / cm ² or lower in this order. Silicon carbide semiconductor devices that pass a directional current and have a rate of change in forward voltage of less than 3% are selected. As a result, even if the inverter circuit in which the diode is connected in antiparallel to the silicon carbide semiconductor device is used for a long time, the stacking defect of the substrate is less likely to grow and the characteristics of the silicon carbide semiconductor device are not deteriorated. Therefore, it is possible to screen a silicon carbide semiconductor device that does not deteriorate in reliability.

Further, the time required for sorting is a short time until the rate of change of the forward voltage exceeds 3% or the rate of change of the forward voltage is saturated. Therefore, in the embodiment, the silicon carbide semiconductor device can be screened in a short time.

In the embodiment, SiC-SBD or Si-SBD may be used as the diode in the silicon carbide semiconductor device. SiC-SBD is preferable because of the heat resistance of the inverter device. It is also possible to use a PN diode instead of the SBD.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set variously according to the required specifications and the like. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide bandgap semiconductor is described as an example, but it can also be applied to a widebandgap semiconductor such as gallium nitride (GaN) other than silicon carbide. Is. Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds.

As described above, the method for selecting a silicon carbide semiconductor device according to the present invention is useful for a silicon carbide semiconductor device used in an inverter circuit in which a diode is connected in antiparallel to the silicon carbide semiconductor device.

1 n ⁺ type silicon carbide substrate 2 n type silicon carbide epitaxial layer 3 p ⁺ type base region 3a 2nd p ⁺ type region 4 p type base layer 5 n ⁺ type source region 6 p ⁺ type contact region 7 n type well region 8 gate Insulating film 9 Gate electrode 10 Source electrode 11 Drain electrode 18 Trench 21, 22, 23, 24 MOSFET
25 Loads 26, 27, 28, 29 Built-in diodes 30, 31, 32, 33 SiC-SBD
34 Input circuit

Claims (8)

It is a method for selecting a silicon carbide semiconductor device having a MOS FET .
The first step of setting the temperature of the silicon carbide semiconductor device to 50 ° C. or higher and 145 ° C. or lower, and
The second step of passing a forward current having a current density of 118 A / cm ² or less through the built-in diode of the MOSFET ,
Before and after the second step, the third step of measuring the forward voltage of the MOSFET and the third step,
The fourth step of calculating the rate of change of the forward voltage of the MOSFET from the measured forward voltage, and
The fifth step of selecting the silicon carbide semiconductor device having the calculated rate of change of less than 3%, and
A method for selecting a silicon carbide semiconductor device, which comprises. The method for selecting a silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device further includes a diode connected in antiparallel to the MOSFET. A method for selecting a silicon carbide semiconductor device used in an inverter circuit including a silicon carbide semiconductor device having a MOS gate structure and a diode connected in antiparallel to the silicon carbide semiconductor device.
The first step of setting the temperature of the silicon carbide semiconductor device to 50 ° C. or higher and 145 ° C. or lower, and
The current density of the built-in diode of the silicon carbide semiconductor device is 118 A / cm. ² The second step of passing the following forward current and
Before and after the second step, the third step of measuring the forward voltage of the built-in diode of the silicon carbide semiconductor device and the third step.
The fourth step of calculating the rate of change of the forward voltage of the built-in diode of the silicon carbide semiconductor device from the measured forward voltage, and
The fifth step of selecting the silicon carbide semiconductor device having the calculated rate of change of less than 3%, and
A method for selecting a silicon carbide semiconductor device, which comprises. The method for selecting a silicon carbide semiconductor device according to claim 1 or 3, wherein in the first step, the temperature of the silicon carbide semiconductor device is set to 60 ° C. or higher and 90 ° C. or lower. One of claims 1 to 4, wherein in the fifth step, the silicon carbide semiconductor device is selected, wherein the calculated change rate is saturated and the calculated change rate is lower than 3%. The method for selecting a silicon carbide semiconductor device according to the above. The method for selecting a silicon carbide semiconductor device according to any one of claims 2 to 5, wherein the diode is a silicon carbide Schottky barrier diode. The silicon carbide semiconductor device is
The first conductive type first semiconductor layer provided on the front surface of the silicon carbide substrate and
A second conductive type second semiconductor layer provided on the opposite side of the first semiconductor layer with respect to the silicon carbide substrate side,
A first conductive type first semiconductor region having a higher impurity concentration than the silicon carbide substrate, which is selectively provided inside the second semiconductor layer,
The gate insulating film in contact with the second semiconductor layer and
A gate electrode provided on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor layer, and
The first semiconductor region, the first electrode provided on the surface of the second semiconductor layer, and
The second electrode provided on the back surface of the silicon carbide substrate and
The method for selecting a silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the silicon carbide semiconductor device is provided. The silicon carbide semiconductor device is
Further provided with a trench that penetrates the second semiconductor layer and reaches the first semiconductor layer.
The method for selecting a silicon carbide semiconductor device according to claim 7, wherein the gate electrode is provided inside the trench via the gate insulating film.

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