JP7191026B2 - 動的凍結Ｐｏｌａｒ符号 - Google Patents

動的凍結Ｐｏｌａｒ符号 Download PDF

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JP7191026B2
JP7191026B2 JP2019536511A JP2019536511A JP7191026B2 JP 7191026 B2 JP7191026 B2 JP 7191026B2 JP 2019536511 A JP2019536511 A JP 2019536511A JP 2019536511 A JP2019536511 A JP 2019536511A JP 7191026 B2 JP7191026 B2 JP 7191026B2
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channel
channel indices
encoding
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JP2020506575A (ja
JP2020506575A5 (enExample
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ジエン・リ
チャンロン・シュ
チャオ・ウェイ
ジレイ・ホウ
ジン・ジアン
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
    • H03M13/353—Adaptation to the channel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2942—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes wherein a block of parity bits is computed only from combined information bits or only from parity bits, e.g. a second block of parity bits is computed from a first block of parity bits obtained by systematic encoding of a block of information bits, or a block of parity bits is obtained by an XOR combination of sub-blocks of information bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60—General implementation details not specific to a particular type of compression
    • H03M7/6011—Encoder aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Error Detection And Correction (AREA)
JP2019536511A 2017-01-16 2018-01-16 動的凍結Ｐｏｌａｒ符号 Active JP7191026B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CNPCT/CN2017/071255 2017-01-16
PCT/CN2017/071255 WO2018129734A1 (en) 2017-01-16 2017-01-16 Dynamic frozen polar codes
PCT/CN2018/072761 WO2018130221A1 (en) 2017-01-16 2018-01-16 Dynamic frozen polar codes

Publications (3)

Publication Number Publication Date
JP2020506575A JP2020506575A (ja) 2020-02-27
JP2020506575A5 JP2020506575A5 (enExample) 2021-02-04
JP7191026B2 true JP7191026B2 (ja) 2022-12-16

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US (1) US11171672B2 (enExample)
EP (1) EP3568920B1 (enExample)
JP (1) JP7191026B2 (enExample)
KR (2) KR20190102209A (enExample)
CN (1) CN110192347B (enExample)
CA (1) CA3045933C (enExample)
WO (2) WO2018129734A1 (enExample)

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US11411593B2 (en) 2020-04-29 2022-08-09 Eagle Technology, Llc Radio frequency (RF) system including programmable processing circuit performing butterfly computations and related methods
US11502715B2 (en) * 2020-04-29 2022-11-15 Eagle Technology, Llc Radio frequency (RF) system including programmable processing circuit performing block coding computations and related methods
US11374704B2 (en) 2020-05-07 2022-06-28 Cisco Technology, Inc. Mapping bit positions using predicted error values
US11588588B2 (en) * 2020-08-10 2023-02-21 Mediatek Inc. Additional bit freezing for polar coding
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WO2022093988A1 (en) 2020-10-30 2022-05-05 XCOM Labs, Inc. Clustering and/or rate selection in multiple-input multiple-output communication systems
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Also Published As

Publication number Publication date
EP3568920A4 (en) 2020-09-09
CN110192347A (zh) 2019-08-30
JP2020506575A (ja) 2020-02-27
CN110192347B (zh) 2023-09-29
KR102871015B1 (ko) 2025-10-14
WO2018129734A1 (en) 2018-07-19
BR112019014205A2 (pt) 2020-03-17
US11171672B2 (en) 2021-11-09
WO2018130221A1 (en) 2018-07-19
KR20220165818A (ko) 2022-12-15
US20190372605A1 (en) 2019-12-05
CA3045933A1 (en) 2018-07-19
KR20190102209A (ko) 2019-09-03
CA3045933C (en) 2024-05-14
EP3568920B1 (en) 2024-12-11
EP3568920A1 (en) 2019-11-20

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