JP7184845B2 - Low CTE boro-aluminosilicate glass for glass carrier wafer - Google Patents

Description

FIELD OF THE INVENTION The present invention relates to low brittle, low CTE boro-aluminosilicate glasses for use as glass carrier wafers. The invention also relates to a glass carrier wafer made of said low CTE boro-aluminosilicate glass and its use as a glass carrier wafer for processing silicon substrates. The invention further relates to a method of providing a low CTE boro-aluminosilicate glass.

BACKGROUND OF THE INVENTION Solid state electronic devices such as semiconductor chips and dies are typically fabricated from semiconductor materials such as silicon, germanium or gallium/arsenide. Circuitry is formed on one surface of such devices, for example, with input/output pads formed around the perimeter.

Many small electronic consumer products include, for example, notebooks, smart phones, digital cameras, modems, global positioning systems and electronic watches. Rapidly increasing consumer demand for smaller product sizes and low-profile products builds smaller, thinner, higher-power semiconductor devices that can be manufactured more efficiently and with higher yields. It is the impetus for the search for a method. Therefore, it is necessary to develop inexpensive, ultra-thin and compact devices so that many small electronic devices can be widely used in the future.

For example, as a technique for hermetically packaging integrated circuits as part of a wafer, wafer Wafer-level-packaging (WLP) is widely applied. The resulting package is substantially the same size as the die. WLP enables wafer fabrication, packaging, testing and burn-in to be integrated at the wafer level, with the goal of streamlining the fabrication process that takes place from inception to shipment to the customer with a single silicon device. . It is readily recognized that the WLP can be a major component of the final fabrication cost and resulting device dimensions.

Reusable glass carrier wafers are widely applied in the semiconductor industry, for example as carrier wafers for thinning and backgrinding of silicon substrates. Such glasses are used to prevent cracking and warping of semiconductor substrate materials, such as silicon materials, for example, due to thermal expansion imbalance between the glass carrier wafer and the silicon substrate during processing. It is desirable to have a CTE that is sufficiently close to the coefficient of thermal expansion (CTE). See, for example, US Pat. No. 5,599,753 (US 5,599,753 A, Jenaer Glaswerk GmbH) and US Pat. No. 5,610,108 (US 5,610,108 A, Schott Glaswerke). The glasses described have a coefficient of thermal expansion (CTE) of 4-6 ppm/K and are therefore unsuitable as glass carrier wafers for silicon substrates due to the CTE mismatch. Other borosilicate glasses, such as proposed in US Pat. No. 5,547,904 (US 5,547,904 A, Schott AG), contain Li ₂ O, which means that the silicon substrate It is not preferred in the semiconductor industry as it can be contaminated with lithium ions.

In contrast to such glass carrier wafer applications, glasses for WLP applications and other applications that require glass cutting are also required to exhibit good dicing performance. Alkali-free aluminosilicate glass, which has a low CTE similar to silicon, is otherwise suitable as a glass carrier wafer, but often has poor cutting and dicing performance. Accordingly, there is a need in the art to provide a glass that is not only suitable for semiconductor carrier wafer applications, but also exhibits high dicing performance, e.g., high dicing yield, and high cutting performance.

Description of the Invention It is therefore an object of the present invention to provide a glass which overcomes the drawbacks of the prior art. In particular, it is an object of the present invention to provide a glass with a low CTE, in particular a CTE close to that of silicon, and a glass wafer made of this glass with good dicing or cutting performance. Another object of the present invention is to provide a glass and a glass carrier wafer made of this glass suitable for use in the semiconductor industry, in particular for WLP and MEMS applications. Another object of the present invention is to provide a glass, or a glass wafer made thereof, for use in the semiconductor industry that enables cost-effective semiconductor device manufacturing. Another object of the present invention is to provide glasses and glass wafers with high dicing yields, especially for use in WLP and MEMS applications.

This object is solved by a low CTE glass, a glass carrier wafer, a use and a method according to the independent claims. Preferred embodiments of each aspect are described in the dependent claims. A "low CTE glass" according to this specification generally refers to a glass having a CTE of 4.0 ppm/K or less.

The present invention is based on the insight that lowering the hardness and increasing the fracture toughness of the glass composition is an important factor in the dicing quality and dicing performance of glass wafers (as assessed by edge chipping properties). there is The present invention provides a desired glass composition by simultaneously adjusting the ratio of "network modifier" to "network former" and the ratio of "boron oxide" to "aluminum oxide" in a given boroaluminosilicate glass composition. It is based on the amazing insight that traits can be obtained.

を有する低脆性の低ＣＴＥボロアルミノシリケートガラスであって、特にウェハーレベルパッケージング（ＷＬＰ）用途での使用に向けた低ＣＴＥボロアルミノシリケートガラスにおいて、
多面体１つあたりの非架橋酸素の平均数（ＮＢＯ）は、－０．２以上であり、比Ｂ_２Ｏ_３／Ａｌ_２Ｏ_３は、０．５以上であり、ここで、前記ＮＢＯは、ＮＢＯ＝２×Ｏ_ｍｏｌ／（Ｓｉ_ｍｏｌ＋Ａｌ_ｍｏｌ＋Ｂ_ｍｏｌ）－４と定義される低ＣＴＥボロアルミノシリケートガラスに関する。 The present invention therefore provides the following composition in mol %:

1. A low CTE boro-aluminosilicate glass, particularly for use in wafer level packaging (WLP) applications, having:
The average number of non-bridging oxygens per polyhedron (NBO) is greater than or equal to −0.2 and the ratio B ₂ O ₃ /Al ₂ O ₃ is greater than or equal to 0.5, wherein said NBO is It relates to a low CTE boro-aluminosilicate glass defined as NBO=2×O _mol /(Si _mol +Al _mol +B _mol )−4.

An increase in the average number of NBO and/or the B ₂ O ₃ /Al ₂ O ₃ ratio above a certain value gives only a limited further improvement in brittleness and thus the resulting dicing It is believed that a significant improvement in performance is no longer obtained. In addition, too high an NBO number and/or a _B2O3 / _{Al2O3 ratio} can increase the CTE _mismatch , making the glass unsuitable for bonding with silicon, for example in WLP applications. For most of the required applications, the average number NBO is preferably less than or equal to -0.1 and the B ₂ O ₃ /Al ₂ O ₃ ratio is preferably less than or equal to 10, in terms of dicing performance. It has been found that a glass composition is obtained that exhibits advantageous properties while at the same time being sufficiently CTE matched to silicon to permit bonding with silicon during processing. However, depending on the particular application, e.g. when the _CTE does not need to be matched to silicon, values of NBO and _B2O3 / _Al2O3 above these upper limits may not _be advantageous glass compositions. It should be understood as being able to provide things.

When considering the structure of glass, the concept of NBO (Non-Bridging Oxygen) is widely used. NBO can be considered a parameter that describes the network structure of a glass resulting from a specific chemical composition. Surprisingly, the network structure exhibited by the NBO of the low CTE glasses described herein can beneficially affect the brittleness index, expressed as _HV /K _IC , and thus the dicing performance of the glass. There was found.

The network structure of glasses can be characterized by the four parameters X, Y, Z and R defined below:
X = average number of non-bridging oxygens per polyhedron, i.e. NBO;
Y = average number of bridging oxygens per polyhedron;
Z=average total number of oxygens per polyhedron; and R=ratio of total number of oxygens to total number of network formers.

R can be derived from the molar composition of the low CTE glass. These four parameters X, Y, Z and R can be calculated according to the following formulas:
R = O _mol / (Si _mol + Al _mol + B _mol ) (1)
Y=2Z-2R (2)
X=2R-Z (3)
For silicate:
Z=4 (4).

From equations (1), (3) and (4),
X=2×O _mol /(Si _mol +Al _mol +B _mol )−4 (5)
can be concluded.

However, considering only the influence of NBO, if the NBO value is relatively high, the hardness of the glass may decrease and the fracture toughness may increase. Therefore, it is found that simultaneously adjusting the ratio B ₂ O ₃ /Al ₂ O ₃ to a relatively high value can increase the scratch resistance of the glass through the influence of boron on the modification of the glass network. One of the insights. It has been found that by adjusting both NBO and B ₂ O ₃ /Al ₂ O ₃ simultaneously according to the limits given by the present invention, good dicing performance of the glass can be achieved.

In one preferred embodiment, the average number of non-bridging oxygens per polyhedron is greater than or equal to −0.18, preferably greater than or equal to −0.16, and/or the ratio B ₂ O ₃ /Al ₂ O ₃ is 0.8 or more, preferably 1.0 or more.

を有する。 Preferably, the glass is an alkali-free glass and has the following composition in mol %:

have

By "alkali-free" herein is meant that the alkali content is less than 0.01 mol %.

を有する。 In another preferred embodiment, the glass may be an alkali-containing glass having the following composition in mol %:

have

In one preferred embodiment, the low CTE boro-aluminosilicate glass according to the present invention has a brittleness index H _V /K _IC of 12 μm ^−1/2 or less, preferably 10 μm ^−1/2 or less, more preferably 8 μm ^{−1/2 or} less. have Here, _HV refers to Vickers hardness, and _KIC refers to fracture toughness of glass. The fracture toughness K _IC in this case represents the critical stress intensity factor at which a slight crack in the glass begins to grow.

The Vickers hardness _HV (MPa) is obtained by applying a force of 0.2 kgf to the surface of the glass wafer using a pyramidal indenter and calculating _HV from _HV = 1.8 × P/a ² . , where P is the test load on the indenter (MPa) and a represents the half diagonal length of the indentation (μm). Then, the fracture toughness (unit: MPa·m ^1/2 ) was calculated by the following formula: K _IC =0.16×(c/a) ^−3/2 (H _V ·a ^1/2 ), where where a is the half length (μm) of the diagonal of the indentation and c is the half length (μm) of the crack produced by the indentation. Correspondingly, the brittleness can be determined by dividing the hardness by the fracture toughness.

When using the low CTE glass according to the present invention in the semiconductor industry, it is preferred that the low CTE glass is substantially free of _Li2O in order to prevent contamination of silicon substrates by lithium ions. "Substantially free" as used herein means that the content is less than 0.01 mol %.

In another preferred embodiment, the low CTE boro-aluminosilicate glass has a coefficient of thermal expansion (CTE) between 2.0 ppm/K and 4.0 ppm/K. Preferably, the CTE of the glass is in the range of 2.6ppm/K to 3.8ppm/K. Overall, the CTE of the glass prevents warping and cracking that can occur due to CTE mismatch between the low CTE boro-aluminosilicate glass carrier wafer and the silicon substrate bonded to the glass carrier wafer. For this reason, it is preferable to be close to the CTE of the silicon substrate.

In one preferred embodiment, the low CTE boro-aluminosilicate glass has a transition temperature T _g of above 550°C, preferably above 650°C, more preferably above 700°C.

In another aspect of the invention, the low CTE boro-aluminosilicate glass of the invention is provided as a glass wafer. The glass wafer preferably has a thickness in the range 0.05 mm to 1.2 mm, preferably in the range 0.1 mm to 0.7 mm. More generally, the glass wafer preferably has a thickness of 1.2 mm or less, 0.7 mm or less, 0.5 mm or less, 0.35 mm or less, 0.1 mm or less or 0.05 mm or less. Preferably selected thicknesses are 100 μm, 200 μm, 250 μm, 400 μm, 500 μm, 550 μm, 700 μm or 1000 μm. The surface dimensions of the glass wafer are preferably about 15 cm, about 20 cm or about 30 cm, or preferably about 6 inches, about 8 inches or about 12 inches, depending on specific needs. The shape of this glass wafer may be rectangular, circular, or elliptical. Other shapes and dimensions may be used if required for a particular application.

In one preferred embodiment, the glass carrier wafer has a maximum edge chipping size of 30 μm or less, preferably 20 μm or less, more preferably 10 μm or less after dicing. For many applications, a maximum edge chipping size of 30 μm may be sufficient. However, it is generally desirable to further increase the effective area available without chipping after dicing, and thus further reduce the maximum edge chipping size.

Dicing is preferably accomplished by cutting with a resin blade, diamond particle blade or composite blade. The blade in this case preferably has, for example, a diameter of 56 mm, a thickness of 0.15 mm, a feed rate of 5 mm/s and a rotational speed of 20 krpm. However, it should be understood that glasses according to the present invention will also exhibit advantageous properties with other blade and/or process parameter selections. It is understood that the above values for maximum edge chipping size are values that can be obtained with optimized dicing parameters that can be routinely determined by those skilled in the art.

The invention further relates to a bonded article comprising such a glass carrier wafer and a silicon substrate bonded to the glass carrier wafer, in particular by means of an adhesive. If the application requires release, the adhesive can be UV sensitive, for example, and can be deactivated by exposure to UV radiation. This can be advantageous if the glass carrier wafer is used in a method for treating silicon substrates, for example during thinning and/or backgrinding of silicon substrates. It has been found that adjusting the NBO of a given glass composition can also be advantageous in terms of transmission and solarization resistance of such glass carrier wafers (see, eg, PCT/CN2015/071159).

However, the low CTE boro-aluminosilicate glass and the glass carrier wafer made of said low-CTE boro-aluminosilicate glass according to the present invention are preferably used in wafer level packaging (WLP) applications and/or especially in microelectromechanical systems (MEMS). It is preferably used as a glass carrier wafer for processing silicon substrates. WLP refers to, for example, the packaging of integrated circuits as part of a wafer, as opposed to the conventional method of cutting the wafer into individual circuits (dies) and then packaging them. MEMS refers to miniature integrated devices or systems that include electrical and mechanical elements. The size of these elements may range from sub-micrometer to millimeter level, and in a particular system anywhere from one to a few, possibly thousands or millions It can be a number. WLP processes are particularly advantageous in the fabrication of MEMS.

In a preferred use of a glass carrier wafer, processing a silicon substrate bonded to the glass carrier wafer includes dicing the silicon substrate from the glass carrier wafer surface while it remains adhered to the glass carrier wafer. In this case, the first cut can be made from the glass wafer surface through the glass wafer to the adhesive layer, for example, without cutting the silicon substrate. A second cut can then be made in the groove of the first cut, preferably with a thinner cutting blade, thereby leaving the silicon substrate still adhered to the cut glass carrier wafer. Separate into dies. Preferably, a dicing film, especially a dicing tape, is applied to the silicon substrate before dicing, for example before making the second cut. This dicing film is generally left intact during the second cut.

Note that multiple cutting blades may be utilized that may also accomplish the above dicing in a single cutting step. For example, the above-described dicing method with two cutting steps is still preferred in the art because there are some problems with controlling dicing yield and blade life. By using separate cutting blades for different materials, for example, process parameters and blade conditions can be better controlled and adapted to the respective material to be cut.

The low CTE boro-aluminosilicate glass is, in another aspect of the invention, a method of providing a low-brittle, low-CTE boro-aluminosilicate glass containing _at least _SiO2 , _Al2O3 and _B2O3 , comprising _: In particular, a method of providing a low CTE boro-aluminosilicate glass as described herein, wherein the method achieves a low brittleness index H _V /K _IC , in particular a brittleness index H _V /K _IC of less than 12 μm ^−1/2 adjusting the NBO number _of a given low CTE boro-aluminosilicate glass _composition and altering said composition by adjusting the ratio of _B2O3 / _Al2O3 , wherein , the NBO number indicates that a method defined as NBO=2×O _mol /(Si _mol +Al _mol +B _mol )−4 is provided. Preferably, the method includes adjusting the NBO number to be above a lower limit, which is preferably -0.2. More preferably, the method comprises adjusting _{the B2O3} / _Al2O3 ratio above a lower limit, in _particular such that _{the B2O3 / Al2O3 ratio} is above a lower limit of 0.5. including adjusting to

The objects, features and advantages of the present invention are explained in more detail by the examples and embodiments described below with reference to the accompanying drawings. Exemplary figures used to describe the invention are shown schematically below.

An exemplary dicing process in a wafer level packaging (WLP) application is shown in cross-section in FIG. FIG. 2 shows a schematic diagram of a cut edge of a glass wafer showing edge chipping after cutting. FIG. 3 shows a graph of NBO versus brittleness for several exemplary glass compositions. FIG. 4 shows a graph of NBO versus maximum edge chipping size for several exemplary glass compositions. FIG. 5 shows a graph of the ratio B ₂ O ₃ /Al ₂ O ₃ versus brittleness for several exemplary glass compositions. FIG _. 6 shows a graph of _the ratio _B2O3 / _Al2O3 versus maximum edge chipping size for several exemplary glass compositions. FIG. 7 shows a magnified view of a cut edge of a glass sample according to the invention having an NBO of −0.162. FIG. 8 shows a magnified view of a cut edge of a glass sample according to the invention having an NBO of −0.140. FIG. 9 shows a magnified view of a cut edge of a glass sample according to the invention having an NBO of −0.129.

Dimensions and aspect ratios in these figures are not to scale and are partially exaggerated for better visualization. Corresponding elements in these figures are generally referenced by the same reference numerals.

Detailed Description of Drawings and Examples Figure 1 shows an exemplary dicing process in a wafer level packaging (WLP) application. Silicon substrate 2 is bonded to glass wafer 1 via adhesive layer 3 . The glass wafer 1 has a thickness t. In a first cutting step, the glass wafer 1 is cut with a first blade 4 having a first width _w1 . The cut in this case extends into the adhesive layer 3 but not into the silicon substrate 2 . This cutting is accomplished by rotating blades 4 .

After the cut with the first blade 4 is established, a second cut with the second blade 5 is made. This second blade 5 has a second width w ₂ which is smaller than the width w ₁ of the first blade 4 . This second cut is made inside the kerf created by the first cutting step. Due to the smaller width w ₂ of this second cutting blade 5 , this second cutting step can be performed without affecting the glass wafer 1 . This second cut extends through the silicon substrate 2 and preferably to the dicing tape 6 . This dicing tape 6 prevents the now completely separated dies from falling apart. This dicing tape 6 is applied before the second cutting step, before the first cutting step, or after the first cutting step.

After cutting, the glass wafer 1 has a new cutting edge 10 as illustrated in FIG. This cut edge 10 typically exhibits some degree of edge chipping 11 as a result of the first cutting process. Such edge chipping 11 can lead, for example, to propagating cracks, which eventually lead to breakage of the glass wafer 1 during cutting and further processing. Furthermore, edge chipping 11 reduces the area A that can be effectively utilized after dicing. Therefore, by reducing edge chipping 11, the dicing yield can be increased. Overall, a characteristic maximum edge chipping size C can be specified, which depends, for example, on the cutting blade used and other cutting parameters, such as the feed rate and rotation speed of the blade. However, for a given set of cutting parameters, the maximum edge chipping size C can be reduced by using a specific glass material for the glass wafer 1 .

The glass wafer 1 made of glass according to the invention therefore has a lower tendency to edge chipping and thus allows a higher dicing yield as can be seen from the examples below.

Examples Table 1 below shows eleven exemplary glass compositions according to the present invention. Examples 12-14 provide exemplary comparative glasses not within the scope of the present invention. Examples 1-5 and 7-11 show compositions of alkali-free glasses, and Example 6 describes an alkali-containing glass.

表１：本発明による例１～１１および比較例１２～１４の組成物

Table 1: Compositions of Examples 1-11 according to the invention and Comparative Examples 12-14

Table 2 below lists selected relevant parameters of the glass compositions of Examples 1-11 and Comparative Examples 12-14 according to Table 1.

表２：本発明によるガラス例１～１１および比較例１２～１４の構造パラメーター、特性および性能

Table 2: Structural parameters, properties and performance of glasses according to the invention Examples 1-11 and Comparative Examples 12-14

These Examples 1-11 according to the invention span a range of NBO numbers from -0.2 (rounded) to -0.12. The B ₂ O ₃ /Al ₂ O ₃ ratio in this case ranges from 0.6 (rounded) to about 1.6. The glass transition temperatures range from 560°C (rounded) to 715°C. As can be seen from Table 2, the Vickers hardness H _V of all glass samples 1-11 ranged from 5255 MPa (rolled) to 5725 MPa, and the fracture toughness K _IC was 0.45 MPa m ^1/2 to 0.88 MPa·m ^1/2 . The resulting brittleness is defined as H _V /K _IC , which ranges from 6.5 μm ^−1/2 to 11.9 μm ^−1/2 .

Comparative Examples 12-14 have NBO numbers less than -0.2 and ratios B ₂ O ₃ /Al ₂ O ₃ less than 0.5.

Table 2 also shows the chipping performance obtained when cutting glass samples in the far right column. The term "chipping size" herein refers to the maximum chipping size C, as illustrated in FIG. The samples were cut with a soft 600 mesh dicing blade with a diameter of 56 mm and a width w _{1 of} 0.15 mm at a feed rate of 5 mm/s and a rotation speed of 20 krpm. Chipping performance was found to be less dependent on these dicing parameters, and comparable results were observed for dicing parameter ranges typically applied in the art, eg, for WLP applications.

The thickness t of the glass samples was 0.5 mm for all glass compositions of Examples 1-14. It is clear that for any NBO number of -0.2 or greater, the maximum edge chipping size obtained is 30 μm or less, whereas the maximum edge chipping size of Comparative Examples 12-14 is greater than 30 μm. I can see it.

FIG. 3 shows the values of brittleness H _V /K _IC versus NBO number, while FIG. 4 shows the corresponding values for chipping size. 5 and 6 show corresponding graphs for the B ₂ O ₃ /Al ₂ O ₃ ratio. Both plots clearly show a decreasing trend in _brittleness and chipping size with the relevant parameters NBO and _B2O3 / _Al2O3 , with an _NBO of -0.2. and a ratio B ₂ O ₃ /Al ₂ O ₃ of 0.5, the brittleness index H _V /K _IC transitions from values above 12 μm ^−1/2 (dashed line) to values below it and the maximum chipping size transitions from values above 30 μm (dashed line) to values below.

7-9 show enlarged views of the cutting blades of selected samples of Examples 7, 9 and 10 according to Table 1. FIG. FIG. 7 shows a sample of glass according to Example 7 with an NBO of −0.162. As can be seen from this figure, the maximum edge chipping size is 14.42 μm, which is rounded to 14 μm in Table 2. Similarly, FIG. 8 shows a sample of glass according to Example 9 of Table 1. It has an NBO of −0.140 and a maximum edge chipping size obtained of 12.25 μm. A sample of the glass according to Example 10 is shown in FIG. It has an NBO of −0.129 and a maximum edge chipping size of 9.48 μm. The corresponding maximum edge chipping size values in Table 2 are each rounded to the nearest integer.

Claims (17)

Composition in mol % of:

and a Li _O -free, low-brittle, low-CTE boro-aluminosilicate glass carrier wafer comprising:
The average number of non-bridging oxygens per polyhedron (NBO) is greater than or equal to −0.2 and the ratio B ₂ O ₃ /Al ₂ O ₃ is greater than or equal to 0.5, wherein said NBO is A glass carrier wafer made of said low CTE boro-aluminosilicate glass, defined as NBO=2×O _mol /(Si _mol +Al _mol +B _mol )−4. The glass is an alkali-containing glass and has the following composition in mol %:

The glass carrier wafer of claim 1, having 3. Glass carrier wafer according to claim 1 or 2, wherein _SiO2 is max. 82.5 mol%. Said average number of non-bridging oxygens per polyhedron (NBO) is greater than or equal to -0.18, preferably greater than or equal to -0.16, and/or said ratio B ₂ O ₃ /Al ₂ O ₃ is , is greater than or equal to 0.8, preferably greater than or equal to 1.0. The method of claims 1 to 4, wherein the average number of non-bridging oxygens (NBO) per polyhedron is -0.1 or less, and the ratio B ₂ O ₃ /Al ₂ O ₃ is 10 or less. A glass carrier wafer according to any one of the preceding claims. The brittleness index H _V /K _IC is 12 μm ^−1/2 or less, preferably 10 μm ^−1/2 or less, more preferably 8 μm ^−1/2 or less, where H _V is the Vickers hardness. and K _IC refers to the fracture toughness of the boro-aluminosilicate glass. 7. Any one of claims 1 to 6, wherein the coefficient of thermal expansion (CTE) is in the range of 2.0 ppm/K to 4.0 ppm/K, preferably in the range of 2.6 ppm/K to 3.8 ppm/K. The glass carrier wafer according to 1. A glass carrier wafer according to any of the preceding claims, wherein said glass has a transition temperature T _g above 550°C, preferably above 650°C, more preferably above 700°C. A glass carrier wafer according to any one of claims 1 to 8, wherein the glass carrier wafer made of low CTE boro-aluminosilicate glass is for wafer level packaging (WLP) applications. A glass carrier wafer according to any preceding claim, having a thickness of 1.2 mm or less, preferably 0.7 mm or less, preferably 0.5 mm or less, more preferably 0.35 mm or less. The glass carrier wafer according to any of the preceding claims, wherein the maximum edge chipping size after dicing of said glass carrier wafer is 30 µm or less, preferably 20 µm or less, more preferably 10 µm or less. Bonded article comprising a glass carrier wafer according to any one of claims 1 to 11 and a silicon substrate bonded to said glass carrier wafer , in particular by means of an adhesive layer. Use of the glass carrier wafer according to any of claims 1-11 as a carrier wafer for processing silicon substrates in Wafer Level Packaging (WLP) applications. 14. Use according to claim 13 , wherein the silicon substrate is adhered to the glass carrier wafer , in particular by means of an adhesive layer. 15. Use according to claim 13 or 14 , wherein the processing of the silicon substrate comprises dicing from the glass carrier wafer side while the silicon substrate is still adhered to the glass carrier wafer . Use according to any one of claims 13 to 15 , wherein a dicing film, in particular a dicing tape, is applied to the silicon substrate before dicing the silicon substrate. A method of providing a glass carrier wafer according to any one of claims 1 to 11, wherein the method comprises using a given low CTE boron to achieve a brittleness index H _V /K _IC of less than 12 ^µm adjusting the NBO number of the composition of _the aluminosilicate glass and changing said composition by adjusting the ratio of _B2O3 / _Al2O3 , wherein said NBO number is NBO=2 _* A method defined as O _mol /(Si _mol +Al _mol +B _mol )−4.

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