JP2020128339A - Low-cte boroaluminosilicate glass for glass carrier wafers - Google Patents

Abstract

To provide a glass with a low CTE, in particular a CTE close to the CTE of silicon, and a glass wafer made of the glass with good dicing or cutting performance.SOLUTION: A low CTE boroaluminosilicate glass having low brittleness in particular for use in wafer-level-packaging (WLP) applications is disclosed. The glass has a composition in mol% of: SiOof 60-85, AlOof 1-17, BOof 8-20, NaO of 0-5, KO of 0-5, MgO of 0-10, CaO of 0-10, SrO of 0-10, and BaO of 0-10. The average number of non-bridging oxygen per polyhedron (NBO) is equal to or larger than -0.2, and the ratio BO/AlOis equal to or larger than 0.5, where the NBO is defined as NBO=2×O/(Si+Al+B)-4.SELECTED DRAWING: Figure 3

Description

FIELD OF THE INVENTION The present invention relates to low brittle, low CTE boroaluminosilicate glasses for use as glass carrier wafers. The invention also relates to a glass carrier wafer made of said low CTE boroaluminosilicate glass and its use as a glass carrier wafer for processing silicon substrates. The invention further relates to a method of providing a low CTE boroaluminosilicate glass.

BACKGROUND OF THE INVENTION Solid state electronic devices such as semiconductor chips and dies are typically made from semiconductor materials such as silicon, germanium or gallium/arsenide. Circuitry is formed on one surface of such a device, with input/output pads formed, for example, around the perimeter.

Many small electronic consumer products include, for example, notebooks, smartphones, digital cameras, modems, global positioning systems and electronic watches. The rapid increase in consumer demand for smaller product sizes and low profile products will build smaller, thinner and higher power semiconductor devices that can be manufactured more efficiently and with higher yields. It has been the impetus for exploring methods. Therefore, it is necessary to develop an inexpensive, ultra-thin, compact device in order to spread a large number of small electronic devices in the future.

For example, as opposed to the conventional method of packaging individual circuits (dies) by slicing the wafer and then packaging them, for example, as a technique of hermetically packaging an integrated circuit in a state of a part of the wafer, the wafer is BACKGROUND Level-packaging (WLP) is widely applied. The resulting package is substantially the same size as the die. WLP enables wafer-level integration of wafer fabrication, packaging, test and burn-in at the wafer level with the goal of streamlining the fabrication process from start to finish with one silicon device. .. It will be readily appreciated that WLP may be a major component of final fabrication cost and resulting device size.

For example, a reusable glass carrier wafer is widely applied in the semiconductor industry as a carrier wafer for thinning processing and back grinding processing of a silicon substrate. Such a glass is used, for example, for the purpose of preventing cracks or warpage caused by the imbalance of the thermal expansion property between the glass carrier wafer and the silicon substrate during processing, for example, a semiconductor substrate material such as a silicon material. It is desirable to have a CTE that is close enough to the coefficient of thermal expansion (CTE). See, for example, US Pat. No. 5,599,753 (US 5,599,753 A, Jenaer Glaswerk GmbH) and US Pat. No. 5,610,108 A (Schott Glaswerke). The glasses described have a coefficient of thermal expansion (CTE) of 4-6 ppm/K and are therefore not suitable as glass carrier wafers for silicon substrates due to CTE mismatch. For example, another borosilicate glass proposed in US Pat. No. 5,547,904 (US Pat. No. 5,547,904 A, Schott AG) contains Li ₂ O, which is a silicon substrate. It is not preferred in the semiconductor industry because it can be contaminated by lithium ions.

Unlike such applications for glass carrier wafers, glass for WLP applications and other applications requiring cutting of glass is also required to exhibit good dicing performance. Alkali-free aluminosilicate glass having a low CTE similar to that of silicon is suitable as a glass carrier wafer in other respects, but is often insufficient in terms of cutting performance and dicing performance. Therefore, there is a need in the art to provide a glass that is not only suitable for semiconductor carrier wafer applications, but also exhibits high dicing performance and high cutting performance, for example, which ensures a high dicing yield.

Description of the invention It is therefore an object of the present invention to provide a glass which overcomes the drawbacks of the prior art. In particular, an object of the present invention is to provide a glass having a low CTE, particularly a CTE close to that of silicon, and a glass wafer made of the glass having good dicing performance or cutting performance. Another object of the invention is to provide a glass suitable for use in the semiconductor industry, especially for WLP and MEMS applications, and glass carrier wafers made of said glass. Another object of the present invention is to provide a glass or glass wafer made of said glass for use in the semiconductor industry, which enables cost-effective production of semiconductor devices. Another object of the invention is to provide glass and glass wafers with high dicing yield, especially for use in WLP and MEMS applications.

This object is solved by a low CTE glass, glass carrier wafer, use and method according to the independent claims. Preferred embodiments of each aspect are set out in the dependent claims. "Low CTE glass" according to the present specification generally means a glass having a CTE of 4.0 ppm/K or less.

The present invention is based on the insight that lowering hardness and increasing fracture toughness of glass compositions is an important factor in dicing quality and dicing performance of glass wafers (as assessed by edge chipping properties). There is. The present invention provides a desired boroaluminosilicate glass composition by simultaneously adjusting the ratio of "network modifier" to "network former" and the ratio of "boron oxide" to "aluminum oxide". It is based on the amazing insight that you can get the traits.

を有する低脆性の低ＣＴＥボロアルミノシリケートガラスであって、特にウェハーレベルパッケージング（ＷＬＰ）用途での使用に向けた低ＣＴＥボロアルミノシリケートガラスにおいて、
多面体１つあたりの非架橋酸素の平均数（ＮＢＯ）は、−０．２以上であり、比Ｂ_２Ｏ_３／Ａｌ_２Ｏ_３は、０．５以上であり、ここで、前記ＮＢＯは、ＮＢＯ＝２×Ｏ_ｍｏｌ／（Ｓｉ_ｍｏｌ＋Ａｌ_ｍｏｌ＋Ｂ_ｍｏｌ）−４と定義される低ＣＴＥボロアルミノシリケートガラスに関する。 Therefore, the present invention provides the following composition in mol %:

A low CTE boroaluminosilicate glass having low brittleness, which is particularly suitable for use in wafer level packaging (WLP) applications.
The average number of non-bridging oxygen (NBO) per polyhedron is −0.2 or more, and the ratio B ₂ O ₃ /Al ₂ O ₃ is 0.5 or more, wherein the NBO is It relates to a low CTE boroaluminosilicate glass defined as NBO=2×O _mol /(Si _mol +Al _mol +B _mol )-4.

If the average number of NBO and/or the ratio of B ₂ O ₃ /Al ₂ O ₃ shows an increase above a certain value, only a limited further improvement in brittleness is obtained, and thus the resulting dicing It is believed that no significant improvement in performance will be obtained anymore. Furthermore, if the NBO number and/or the B ₂ O ₃ /Al ₂ O ₃ ratio is too high, the CTE mismatch increases, which may result in a glass that is not suitable for bonding with silicon in WLP applications, for example. For most needed applications, the average number NBO is preferably -0.1 or less, and if _{B 2 O 3 / Al 2 O} 3 ratio is preferably 10 or less, with respect to the dicing performance It has been found that a glass composition is obtained which exhibits advantageous properties while at the same time having a CTE that is well matched to silicon so that it can be bonded to silicon during processing. However, depending on the particular application, for example, if the CTE does not have to be matched with silicon, NBO and B ₂ O ₃ /Al ₂ O ₃ values above these upper limits may be advantageous glass compositions. It should be understood that it can provide things.

When considering the structure of glass, the concept of NBO (Non-Bridging Oxygen, non-bridging oxygen) is widely used. NBO can be regarded as a parameter that represents the network structure of glass due to a particular chemical composition. Surprisingly, the network structure exhibited by the NBO of the low CTE glasses described herein can beneficially affect the brittleness index, expressed as H _V /K _IC , and thus the dicing performance of the glass. There was found.

The glass network can be characterized by the four parameters X, Y, Z and R defined below:
X = average number of non-bridging oxygens per polyhedron, ie NBO;
Y = average number of bridging oxygen atoms per polyhedron;
Z = average number of total oxygen per polyhedron; and R = ratio of total number of oxygen to total number of network formers.

R can be derived from the molar composition of the low CTE glass. These four parameters X, Y, Z and R can be calculated according to the following formula:
R=O _mol /(Si _mol +Al _mol +B _mol ) (1)
Y=2Z-2R (2)
X=2R-Z (3)
For silicates:
Z=4 (4).

From equations (1), (3) and (4),
X=2* _Omol /( _Simol + _Almol + _Bmol )-4 (5)
Can be concluded.

However, only by considering the influence of NBO, the hardness of the glass may be low and the fracture toughness may be high when the NBO value is relatively high. Therefore, at the same time, by adjusting the ratio B ₂ O ₃ /Al ₂ O ₃ to a relatively high value, it is possible to enhance the scratch resistance of the glass by the effect of boron on the modification of the glass network. This is one of the insights. It has been found that good dicing performance of the glass can be achieved by adjusting both NBO and B ₂ O ₃ /Al ₂ O ₃ at the same time according to the limits given by the invention.

In one preferred embodiment, the average number of non-bridging oxygen per one polyhedron is at -0.18 or more, preferably -0.16 or more, and / or the ratio _{B 2 O 3 / Al 2 O} 3 Is 0.8 or more, preferably 1.0 or more.

を有する。 Preferably, the glass is a non-alkali glass and has the following mol% composition:

Have.

By "alkali-free" according to the present specification is meant that the alkali content is less than 0.01 mol %.

を有する。 In another preferred embodiment, the glass may be an alkali-containing glass and has the following mol% composition:

Have.

In a preferred embodiment, the low CTE boroaluminosilicate glass according to the present invention has a brittleness index H _V /K _{IC of} 12 μm ^−1/2 or less, preferably 10 μm ^−1/2 or less, more preferably 8 μm ^−1/2 or less. Have. Here, H _V refers to Vickers hardness, and K _IC refers to fracture toughness of glass. The fracture toughness K _{IC in} this case represents a critical stress intensity factor at which slight cracks in glass begin to grow.

Vickers hardness _H V (MPa) is obtained by the surface of the glass wafer using a pyramid indenter applies a force of 0.2 _kgf, by ^{H V = 1.8 × P / a} 2 calculates the _{H V} , Where P is the test load (MPa) on the indenter, and a represents the half length (μm) of the diagonal line of the indentation. Then, the fracture toughness (unit: MPa·m ^1/2 ) was calculated by the following formula: K _IC =0.16×(c/a) ^−3/2 (H _V ·a ^1/2 ) Where a is the half length (μm) of the diagonal of the indentation and c is the half length (μm) of the crack created by the indentation. Correspondingly, brittleness can be determined by dividing this hardness by this fracture toughness.

When the low CTE glass according to the present invention is used in the semiconductor industry, it is preferable that the low CTE glass contains substantially no Li ₂ O in order to prevent contamination of the silicon substrate with lithium ions. By "substantially free" according to the present specification is meant that the content is less than 0.01 mol %.

In another preferred embodiment, the low CTE boroaluminosilicate glass has a coefficient of thermal expansion (CTE) of 2.0 ppm/K or more and 4.0 ppm/K or less. Preferably, the CTE of the glass is in the range of 2.6 ppm/K to 3.8 ppm/K. Overall, the CTE of the glass prevents warpage and cracks that can occur due to CTE mismatch between the glass carrier wafer made of the low CTE boroaluminosilicate glass and the silicon substrate bonded to the glass carrier wafer. Therefore, it is preferable that it is close to the CTE of the silicon substrate.

In a preferred embodiment, the low CTE boroaluminosilicate glass has a transition temperature _Tg of greater than 550°C, preferably greater than 650°C, more preferably greater than 700°C.

In another aspect of the present invention, the low CTE boroaluminosilicate glass of the present invention is provided as a glass wafer. The glass wafer preferably has a thickness in the range of 0.05 mm to 1.2 mm, preferably 0.1 mm to 0.7 mm. More generally, the glass wafer preferably has a thickness of 1.2 mm or less, 0.7 mm or less, 0.5 mm or less, 0.35 mm or less, 0.1 mm or less or 0.05 mm or less. The preferred thickness selected is 100 μm, 200 μm, 250 μm, 400 μm, 500 μm, 550 μm, 700 μm or 1000 μm. The surface dimensions of the glass wafer are preferably about 15 cm, about 20 cm or about 30 cm, or, depending on the particular requirements, preferably about 6 inches, about 8 inches or about 12 inches. The shape of the glass wafer may be rectangular, circular, or elliptical. Other shapes and dimensions may be applied if required for a particular application.

In a preferred embodiment, the glass carrier wafer has a maximum edge chipping size after dicing of 30 μm or less, preferably 20 μm or less, more preferably 10 μm or less. For many applications, a maximum edge chipping size of 30 μm may be sufficient. However, it is generally preferred to further increase the available area that can be utilized without chipping after dicing, and thus further reduce the maximum edge chipping size.

Dicing is preferably accomplished by cutting with a resin blade, diamond particle blade or composite blade. The blade in this case preferably has, for example, a diameter of 56 mm, a thickness of 0.15 mm, a feed rate of 5 mm/s and a rotation rate of 20 krpm. However, it should be understood that the glass according to the present invention exhibits advantageous properties when other blades and/or process parameters are selected. It is understood that the above values for maximum edge chipping size are those that can be obtained by optimized dicing parameters that can be routinely determined by one of ordinary skill in the art.

The invention further relates to a bonded article comprising such a glass carrier wafer and a silicon substrate bonded to the glass carrier wafer, in particular with an adhesive. If the application requires peeling, the adhesive can be, for example, UV sensitive and can be deactivated by irradiation with UV radiation. This can be advantageous if the glass carrier wafer is used in a method of treating a silicon substrate, for example during thinning and/or back grinding of a silicon substrate. It has been found that adjusting the NBO of a given glass composition can also be advantageous in terms of transmission and solarization resistance of such glass carrier wafers (see eg PCT/CN2015/071159).

However, the low CTE boroaluminosilicate glass according to the invention and the glass carrier wafers made of said low CTE boroaluminosilicate glass are preferably used in wafer level packaging (WLP) applications and/or especially in microelectromechanical systems (MEMS). It is preferably used as a glass carrier wafer for processing silicon substrates. WLP refers to a technique of packaging, for example, an integrated circuit in a state of a part of a wafer, as opposed to a conventional method of cutting a wafer into individual circuits (dies) and then packaging them. The MEMS refers to a small integrated device or a small integrated system including an electric element and a mechanical element. The size of these elements can range from the sub-micrometer to the millimeter level, either from 1 to a few, and in some cases up to thousands or millions in a particular system. It can be a number. The WLP process is particularly advantageous in the manufacture of MEMS.

In a preferred use of the glass carrier wafer, treating the silicon substrate bonded to the glass carrier wafer comprises dicing the silicon substrate from the surface of the glass carrier wafer while still adhered to the glass wafer. In this case, the first cutting can be performed from the glass wafer surface through the glass wafer, for example to the adhesive layer, without cutting the silicon substrate. A second cut can then be made in the groove of the first cut, preferably using a thinner cutting blade, so that the silicon substrate remains adhered to the cut glass carrier wafer. Separate into dies. Preferably, a dicing film, especially a dicing tape, is attached to the silicon substrate before dicing, for example, before performing the second cutting. This dicing film is generally left untouched during the second cutting.

It should be noted that multiple cutting blades may be utilized that can also achieve the above dicing in a single cutting step. The above-mentioned dicing method with two cutting steps is still preferred in the art because of some problems with, for example, controlling dicing yield and blade life. By using separate cutting blades for different materials, for example, process parameters and blade conditions can be better controlled and they can be adapted to each material to be cut.

The present low CTE boroaluminosilicate glass is, in another aspect of the present invention, a method for providing a low brittleness low CTE boroaluminosilicate glass containing at least SiO ₂ , Al ₂ O ₃ and B ₂ O _3. In particular, in a method for providing a low CTE boroaluminosilicate glass as described herein, the method achieves a low brittleness index H _V /K _IC , in particular a brittleness index H _V /K _IC of less than 12 μm ^−1/2. In order to modify the composition of a given low CTE boroaluminosilicate glass by adjusting the NBO number and adjusting the B ₂ O ₃ /Al ₂ O ₃ ratio, wherein , The number of NBO is NBO=2×O _mol /(Si _mol +Al _mol +B _mol )-4, which means that a method is provided. Preferably, the method comprises adjusting the NBO number above a lower limit, which is preferably -0.2. More preferably, the _method, so that the _{B 2 O 3 / Al 2 O} 3 ratio comprises adjusting to exceed the lower limit, in particular _{B 2 O 3 / Al 2 O} 3 ratio is higher than the lower limit of 0.5 Including adjusting.

The objects, features and advantages of the present invention will be described in more detail with reference to the accompanying drawings by the examples and embodiments described below. Exemplary diagrams used to describe the present invention are shown schematically below.

FIG. 1 illustrates in cross-section an exemplary dicing process in wafer level packaging (WLP) applications. FIG. 2 shows a schematic view of a cutting edge of a glass wafer showing edge chipping after cutting. FIG. 3 shows a graph of NBO versus brittleness for some exemplary glass compositions. FIG. 4 shows a graph of NBO vs. maximum edge chipping size for some exemplary glass compositions. FIG. 5 shows a graph of the ratio B ₂ O ₃ /Al ₂ O ₃ versus brittleness for some exemplary glass compositions. FIG. 6 shows a graph of the ratio B ₂ O ₃ /Al ₂ O ₃ vs. maximum edge chipping size for some exemplary glass compositions. FIG. 7 shows an enlarged view of the cutting edge of a glass sample according to the invention with an NBO of -0.162. FIG. 8 shows an enlarged view of the cutting edge of a glass sample according to the invention with an NBO of -0.140. FIG. 9 shows an enlarged view of the cutting edge of a glass sample according to the invention with an NBO of -0.129.

The dimensions and aspect ratios in these figures are not to scale and are partially oversized for better visualization. Corresponding elements in these figures are generally referred to by the same reference numbers.

DETAILED DESCRIPTION OF THE FIGURES AND EXAMPLES FIG. 1 illustrates an exemplary dicing process in wafer level packaging (WLP) applications. The silicon substrate 2 is bonded to the glass wafer 1 via the adhesive layer 3. The glass wafer 1 has a thickness t. In the first cutting step, the glass wafer 1 is cut with the first blade 4 having the first width w ₁ . The cut in this case extends to the adhesive layer 3 but not to the silicon substrate 2. This cutting is achieved by the rotating blade 4.

After the cutting by the first blade 4 is established, the second cutting by the second blade 5 is performed. This second blade 5 has a second width w ₂ which is smaller than the width w ₁ of the first blade 4. This second cutting is performed inside the cutting groove generated in the first cutting step. Since the width w ₂ of the second cutting blade 5 is smaller, this second cutting step can be performed without affecting the glass wafer 1. This second cut extends through the silicon substrate 2 and preferably to the dicing tape 6. The dicing tape 6 now prevents the completely separated dies from falling apart. The dicing tape 6 is attached before the second cutting step, before the first cutting step, or after the first cutting step.

After cutting, the glass wafer 1 has a new cutting edge 10 as illustrated in FIG. This cutting edge 10 usually exhibits some edge chipping 11 as a result of the first cutting process. Such edge chippings 11 can cause, for example, propagation cracks, which eventually lead to breakage of the glass wafer 1 during cutting and further processing. Further, the edge chipping 11 reduces the area A that can be effectively used after dicing. Therefore, the dicing yield can be increased by reducing the edge chipping 11. In general, a characteristic maximum edge chipping size C can be specified, which depends, for example, on the cutting blade used and other cutting parameters, such as the blade feed rate and rotational speed. However, for a given set of cutting parameters, the maximum edge chipping size C can be reduced by using a particular glass material for the glass wafer 1.

Therefore, the glass wafer 1 made of glass according to the present invention reduces the tendency of edge chipping and thus enables a high dicing yield as will be seen from the examples below.

Examples Table 1 below shows 11 exemplary glass compositions according to the present invention. Examples 12-14 show exemplary comparative glasses that are not within the scope of the invention. Examples 1 to 5 and 7 to 11 show the composition of alkali-free glass, and Example 6 describes alkali-containing glass.

表１：本発明による例１〜１１および比較例１２〜１４の組成物

Table 1: Compositions of Examples 1-11 according to the invention and Comparative Examples 12-14

Table 2 below lists selected relevant parameters for the glass compositions of Examples 1-11 and Comparative Examples 12-14 according to Table 1.

表２：本発明によるガラス例１〜１１および比較例１２〜１４の構造パラメーター、特性および性能

Table 2: Structural parameters, properties and performances of Glass Examples 1-11 according to the invention and Comparative Examples 12-14.

These examples 1 to 11 according to the invention cover a range of (rounded) NBO numbers from -0.2 to -0.12. The B ₂ O ₃ /Al ₂ O ₃ ratio in this case is in the range (rounded) from 0.6 to about 1.6. The glass transition temperature is in the range (rounded) 560°C to 715°C. As can be seen from Table 2, the Vickers hardness _{H V} of all the glass samples 1 to 11 is in the range of up to 5725MPa from 5255MPa to (rounded), fracture toughness _{K IC} is 0.45 MPa ^{· m 1/2} To 0.88 MPa·m ^1/2 . Resulting brittleness is defined as _H V _{/ K IC,} which is in the range from 6.5 [mu] m ^-1/2 to 11.9 ^-1/2.

Comparative Examples 12 to 14 has a specific _{B 2 O 3 / Al 2 O} 3 of NBO number and less than 0.5 less than -0.2.

Table 2 also shows the chipping performance obtained when the glass sample was cut in the rightmost column. As shown in FIG. 2, the “chipping size” here refers to the maximum chipping size C. The sample was cut with a soft 600 mesh dicing blade having a diameter of 56 mm and a width w _{1 of} 0.15 mm at a feed rate of 5 mm/s and a rotation rate of 20 krpm. The chipping performance was found to be less dependent on these dicing parameters, with comparable results observed in the art for the range of dicing parameters normally applied in, for example, WLP applications.

The glass sample thickness t was 0.5 mm for all glass compositions of Examples 1-14. It is apparent that the maximum edge chipping size obtained is 30 μm or less for any NBO number of −0.2 or more, whereas the maximum edge chipping size of Comparative Examples 12 to 14 exceeds 30 μm. You can see it.

FIG. 3 shows the brittle H _V /K _IC values with respect to the NBO number, while FIG. 4 shows the corresponding values for the chipping size. 5 and 6 show the corresponding graphs for the ratio B ₂ O ₃ /Al ₂ O ₃ . From any of the plot is shown clearly that tends to decrease brittleness and chipping size according to NBO and _{B 2 O 3 / Al 2 O} 3 is associated parameters, NBO -0.2 Value and a ratio B ₂ O ₃ /Al ₂ O ₃ of 0.5, the brittleness index H _V /K _IC shifts from a value above 12 μm ^−1/2 (broken line) to a value below this, and the maximum chipping size Shifts from a value above 30 μm (broken line) to a value below this.

7-9 show enlarged views of the cutting blades of the selected samples of Examples 7, 9 and 10 according to Table 1. FIG. 7 shows a sample of glass according to Example 7 with NBO of −0.162. As can be seen from this figure, the maximum edge chipping size is 14.42 μm, which is rounded to 14 μm in Table 2. Similarly, FIG. 8 shows a glass sample according to Example 9 of Table 1. It has an NBO of -0.140 and a maximum edge chipping size of 12.25 μm. FIG. 9 shows a sample of glass according to Example 10. It has an NBO of -0.129 and a maximum edge chipping size of 9.48 μm. The corresponding maximum edge chipping size values in Table 2 are rounded to the nearest integer.

Claims (18)

Composition in the following mol%:

A low CTE boroaluminosilicate glass having low brittleness, which is particularly suitable for use in wafer level packaging (WLP) applications.
The average number of non-bridging oxygen (NBO) per polyhedron is −0.2 or more, and the ratio B ₂ O ₃ /Al ₂ O ₃ is 0.5 or more, wherein the NBO is Low CTE boroaluminosilicate glass defined as NBO=2×O _mol /(Si _mol +Al _mol +B _mol )-4. Alkali-free glass with the following mol% composition:

The low CTE boroaluminosilicate glass according to claim 1, which comprises: Alkali-containing glass, with the following mol% composition:

The low CTE boroaluminosilicate glass according to claim 1, which comprises: The average number of non-bridging oxygen (NBO) per polyhedron is −0.18 or more, preferably −0.16 or more, and/or the ratio B ₂ O ₃ /Al ₂ O ₃ is The low CTE boroaluminosilicate glass according to any one of claims 1 to 3, which is 0.8 or higher, preferably 1.0 or higher. The average number of non-bridging oxygen per the polyhedron one (NBO) is -0.1 or less, and the ratio _{B 2 O 3 / Al 2 O} 3 is 10 or less, from the claims 1 to 4 The low CTE boroaluminosilicate glass according to any one of 1. The brittleness index H _V /K _IC is 12 μm ^−1/2 or less, preferably 10 μm ^−1/2 or less, more preferably 8 μm ^−1/2 or less, where H _V is Vickers hardness. The low CTE boroaluminosilicate glass according to any one of claims 1 to 5, wherein K _IC refers to the fracture toughness of the boroaluminosilicate glass. The low CTE boroaluminosilicate glass according to any one of claims 1 to 6, which is substantially free of Li ₂ O. The coefficient of thermal expansion (CTE) is in the range of 2.0 ppm/K to 4.0 ppm/K, preferably in the range of 2.6 ppm/K to 3.8 ppm/K. The low CTE boroaluminosilicate glass according to any one of claims 1. 550 ° C., preferably above 650 ° C. greater, more preferably a 700 ° C. greater than the transition temperature _{T g,} the low CTE boro aluminosilicate glass of any one of claims 1 to 8. A glass carrier wafer made of a low CTE boroaluminosilicate glass according to any one of claims 1 to 9. The glass carrier wafer according to claim 10, having a thickness of 1.2 mm or less, preferably 0.7 mm or less, preferably 0.5 mm or less, and more preferably 0.35 mm or less. The glass carrier wafer according to claim 10 or 11, wherein the maximum edge chipping size after dicing of the glass carrier wafer is 30 µm or less, preferably 20 µm or less, and more preferably 10 µm or less. A bonded article comprising a glass carrier wafer according to any one of claims 10 to 12 and a silicon substrate bonded to the glass carrier wafer, in particular by means of an adhesive layer. As a carrier wafer of a glass carrier wafer according to any one of claims 10 to 13, preferably for wafer level packaging (WLP) applications, in particular for processing silicon substrates of microelectromechanical systems (MEMS). Use of. Use according to claim 14, wherein the silicon substrate is adhered to the glass carrier wafer, in particular by means of an adhesive layer. The use according to claim 14 or 15, wherein the processing of the silicon substrate includes dicing from the surface of the glass carrier wafer while the silicon substrate is adhered to the glass wafer. Use according to any one of claims 14 to 16, wherein a dicing film, in particular a dicing tape, is applied to the silicon substrate before dicing the silicon substrate. A method for providing a low brittleness low CTE boro aluminosilicate glass containing at least _SiO 2, _Al 2 _{O 3} and _B 2 _{O 3,} especially low CTE rag according to any one of claims 1 to 9 a method of providing a aluminosilicate glass, the method is less brittle index _H V _{/ K IC,} in order to achieve a particularly brittle index _H V _{/ K IC} of less than 12 [mu] m ^-1/2, given the low CTE Boroarumino Modifying the composition by adjusting the NBO number of the composition of the silicate glass and by adjusting the ratio of B ₂ O ₃ /Al ₂ O ₃ , wherein the NBO number is NBO=2×O. _The method defined as _mol /( _Simol + _Almol + _Bmol )-4.

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