JP7178379B2 - Bus interface device - Google Patents

Description

The present invention relates to a bus interface device that generates a bus interface. Among them, the present invention particularly relates to a technology that is effective when applied to an integrated circuit device or the like equipped with a function that realizes safety and high reliability. The present invention can also be applied to a control technology such as a plan using a bus interface device.

2. Description of the Related Art Conventionally, integrated circuit devices have been used in electronic equipment in order to realize the functions of the electronic equipment. This integrated circuit device is often realized by mounting a plurality of functional blocks such as a central processing unit (CPU), memory, timer, and communication on a single semiconductor chip.

A functional block mounted on a semiconductor chip is called an intellectual property (IP). This IP may be designed in-house or designed by another company. can shorten the man-hours and reduce the development cost. In recent years, the miniaturization of the semiconductor design process has progressed, and the number of functions that can be mounted on one integrated circuit device has increased. There are also cases of using IP that is provided in a form that anyone can freely use as open source. Such a design method is called IP-based design.

In IP-based design, each functional block is designed based on individual specifications. Functional verification and performance verification are required. Also, if the IPs do not have a common interface for connection, design man-hours are required to connect the IPs. Furthermore, in the early implementation of IP-based design for systems that require high reliability, such as social infrastructure systems, there may be cases where IPs that do not have high-reliability functions must be used. In that case, the issue is how to guarantee high-reliability functions.

Japanese Patent Application Laid-Open No. 2007-193842 (Patent Document 1) is a background art of this technical field. This patent document 1 describes a technique for reducing design man-hours and further improving design efficiency in IP-based LSI design. Specifically, the IP database includes system level IPs used in system level design, and in the system level IPs, each IP is divided into a processing algorithm description part, an input data structure definition part, and an output data structure definition part. The conversion circuit generation means refers to the IP database and generates a data conversion circuit between the communication channel and the IP when providing the communication channel between the IPs that perform data communication in the architecture or functional design. (see abstract).

JP 2007-193842 A

In Patent Document 1, in IP-based LSI design, an IP database having system-level IP including an input data structure definition part and an output data structure definition part is provided, and conversion circuit generation means refers to the IP database to establish a communication channel. describes a technique for improving design efficiency in IP-based LSI design by generating a data conversion circuit between and IP.

However, in the IP-based LSI design technology in Patent Document 1, the system level IP registered in the IP database has all the bus interface definitions represented by the input definition and the output definition, and the channel input side conversion circuit generation The means and channel output side conversion circuit generation means receive information and automatically generate a bus conversion circuit on the premise that there is a bus interface definition for each IP.

Therefore, it can be applied when using an IP whose bus interface definition is known, such as an IP created in the past by one's own company. However, it is considered difficult to apply to LSI design when using an IP for which there is no presupposed bus interface definition. This problem is not described in Patent Document 1. Note that the IP for which there is no presupposed bus interface definition includes IP directly introduced from other companies, IP obtained indirectly by being included in LSI products, etc., and IP obtained from the Internet as open source.

In order to solve the above problems, for example, the configurations described in the claims are adopted.

The present application includes a plurality of means for solving the above problems. To give one example, in a bus interface device that generates a bus interface that indicates the input definition and output definition of an electronic device that uses an IP, which is a design asset, specifying a bus interface from each of a first IP including a bus interface definition and a second IP not including a bus interface definition; a bus interface extraction unit that compares the correspondence of the second bus interfaces in the IP and extracts the second bus interface and the corresponding first bus interface whose output signal needs to be converted in order to satisfy a predetermined criterion; a bus interface conversion generation unit for generating a bus conversion circuit description for converting an output signal of the second bus interface using the extracted first bus interface and the second bus interface; a high-reliability interface for generating a high-reliability interface circuit description that is a bus interface that satisfies the predetermined criteria by inputting the output signal to be converted using the first bus interface and the second bus interface that have been converted; A bus interface device having a generator.

The present invention also includes an integrated circuit device generated using the bus conversion circuit description and the high-reliability interface circuit description generated by the bus interface device. Furthermore, the present invention also includes various control systems equipped with this integrated circuit device.

According to the present invention, it becomes possible to use an IP that does not include a bus interface definition with higher reliability. Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

1 is an example of a configuration diagram of a bus interface device according to a first embodiment; FIG. Fig. 3 is an example of an IP database of IPs with bus interface definitions; It is an example of an IP database of IPs without bus interface definitions. FIG. 4 is an example of a configuration diagram of a bus interface device to which bus interface extraction template information and high-reliability interface template information are added; It is an example of a bus interface extraction template. 4 is an example of a flow chart showing the operation of a bus interface extraction unit; 4 is an example of a flow chart showing the operation of a bus interface conversion generation unit; It is an example of a high-reliability interface generation template. 4 is an example of a flowchart showing the operation of a highly reliable interface generation unit; FIG. 10 is an example of a configuration diagram of a system using a bus interface device according to a second embodiment; FIG. It is an example of an integrated circuit device designed by the bus interface device according to the third embodiment. It is an example of an integrated circuit device designed by the bus interface device according to the fourth embodiment. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram illustrating an example of a case where a bus interface device according to each embodiment of the present invention is applied to a railway signal control system; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram illustrating an example of applying a bus interface device according to each embodiment of the present invention to a plant control system;

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in the specification and drawings, elements having substantially the same function or configuration are denoted by the same reference numerals, and the description may be omitted if the description is redundant.

First, the bus interface device according to the first embodiment will be described with reference to the drawings. FIG. 1 is an example of a configuration diagram for explaining the bus interface device according to the first embodiment. The bus interface device is implemented by a so-called computer. That is, various functions to be described later are executed by an arithmetic device such as a CPU according to a program.

The bus interface device according to the first embodiment has a bus interface extractor 3 , a bus interface conversion generator 4 and a highly reliable interface generator 5 .

An IP with bus interface definition (1) and an IP without bus interface definition (2) are input to the bus interface extraction unit 3, and the bus interface extraction unit 3 generates and outputs a bus interface 6. FIG.

The bus interface 6 is input to the bus interface conversion generator 4, and the bus interface conversion generator 4 generates and outputs a bus conversion circuit description 7. FIG. Also, the bus interface 6 is input to a highly reliable interface generator 5, which generates and outputs a highly reliable interface circuit description 8. FIG.

FIG. 2 is an example of a diagram illustrating an IP database having a plurality of IPs with bus interface definitions.

All of the IPs contained in the IP database 19 have bus interface definitions, and three types of IPs with bus interface definitions are shown here. An example of an IP with a bus interface definition is an IP whose specification and design have been implemented in-house. It is known from the definition that the IP with bus interface definition (11) has a highly reliable interface (parity) 31. FIG. Similarly, it is known from the definition that the IP with bus interface definition (12) contained in the IP database 19 has a highly reliable interface (ECC) 32. FIG. Further, it is known from the definition that the IP (13) with a bus interface definition included in the IP database 19 has a highly reliable interface (redundant verification) 33. FIG. In other words, a highly reliable interface satisfies predetermined functional conditions. The method of establishing this standard includes in-house standards such as safety.

FIG. 3 is an example of a diagram illustrating an IP database having a plurality of IPs without bus interface definition.

All of the IPs contained in the IP database 29 do not have a bus interface definition, and three types of IPs without a bus interface are shown here. Examples of IPs without bus interface definitions include IPs directly introduced from other companies, IPs indirectly obtained by being included in LSI products, etc., and IPs obtained from the Internet as open sources. It is unknown what kind of bus interface all of the IPs (21), (22), and (23) without bus interface definition have, and what kind of high-reliability interface they have.

FIG. 4 is an example of a configuration diagram for extracting a bus interface and generating a high-reliability interface for the bus interface device of the present invention.

FIG. 4 is different from the bus interface device described in FIG. different. Furthermore, the part where the bus interface extraction template 9 and the high reliability interface generation template 10 are added is different.

Any IP with bus interface definition (15) contained in the IP database 19 and any IP without bus interface definition (25) contained in the IP database 29 are input to the bus interface extractor 3. FIG. Furthermore, a bus interface extraction template 9 is input to the bus interface extraction unit 3 .

The bus interface 6 is input to the highly reliable interface generator 5 , and the highly reliable interface generation template 10 is input to the highly reliable interface generator 5 .

FIG. 5 shows an example of the contents of a bus interface extraction template to be input to the bus interface extractor 3 in the bus interface device of the present invention, which is described using the grammatical format of a general-purpose data definition language. there is

The bus interface extraction template 41 is an example representing the specifications of the bus interface.

The contents of the 1st to 22nd lines of the bus interface extraction template 41 are the bus interface, and "BusInterface" described in the 2nd line represents the bus interface. The name of this BusInterface is the value "busif_a" of the variable name "name" described on the third line.

The contents of the 4th to 20th lines of the bus interface extraction template 41 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, in the fifth to ninth lines, the value of the variable name "type" is "address", the value of the variable name "name" is "addr", and the value of the variable name "bit" is 32. A bit indicates that the signal name is the address signal line of adr.

Also, in the 10th to 14th lines, the value of the variable name "type" is "data", the value of the variable name "name" is "dat", and the value of the variable name "bit" is 32. A bit indicates a data signal line with a signal name of dat.

Furthermore, from the 15th line to the 19th line, the value of the variable name "type" is "command", the value of the variable name "name" is "rd", and the value of the variable name "bit" is 1. 1 bit indicates that it is a command signal line whose signal name is rd.

Bus interface extraction template 42 is an example representing another specification of a bus interface.

The bus interface extraction template 42 differs from the bus interface extraction template 41 in that the bus specifications of the highly reliable interface are inserted in the 20th to 24th lines.

On the 20th to 24th lines representing one of the bus signals included in the variable name "bus_list" described on the 4th line, the value of the variable name "type" is "parity" and the value of the variable name "name" is is "par" and the value of the variable name "bit" is 1, indicating that it is a 1-bit parity signal line whose signal name is par.

Although FIG. 5 shows an example of the bus interface extraction template 9 in the grammatical format of a general-purpose data definition language, bus requirements can be expressed in various formats that can be described.

Next, the bus interface extractor 3 according to the first embodiment will be explained. FIG. 6 is a flow chart for explaining the function (operation) of the bus interface extractor 3 according to the first embodiment.

At step S01, the operation of the bus interface extractor 3 is started.

At step S02, the bus interface extraction unit 3 receives an input of IP (15) with bus interface definition.

At step S03, the bus interface extracting unit 3 receives an input of the IP without bus interface definition (25).

At step S04, the bus interface extraction unit 3 receives the input of the bus interface extraction template 9. FIG.

At step S05, the bus interface extraction unit 3 determines whether or not the input of each input bus interface extraction template (for example, all the bus interface extraction templates) has been received. If each bus interface extraction template has not been input, the process proceeds to step S04. Further, when each bus interface extraction template is input, the process proceeds to step S06.

At step S06, the bus interface extraction unit 3 detects the bus signal line of the IP (15) having the bus interface definition based on the input bus interface extraction template.

At step S07, the bus interface extraction unit 3 detects the bus signal line of the IP (25) without bus interface definition based on the input bus interface extraction template. Here, the bus interface extraction unit 3 determines whether the IP without bus interface definition (25) satisfies a predetermined criterion, that is, whether it is a highly reliable bus interface. As a result, if the predetermined condition is satisfied, the IP without bus interface definition (25) may be used and the subsequent processing may be omitted. Note that this determination may be made in step S02.

At step S08, the bus interface extractor 3 performs pattern matching between the bus interface and the bus interface extraction template. It is determined which bus interface the IP (15) with bus interface definition and the IP (25) without bus interface definition are.

At step S09, the bus interface extraction unit 3 determines whether or not the bus interface matches any bus of the bus interface extraction template as a result of the pattern matching at step S08. Transition. If they do not match, the process proceeds to step S11.

In step S10, the bus interface extractor 3 generates and outputs the bus interface 6 to be converted from the bus interface extractor 3. FIG. After outputting, the operation of the bus interface extractor 3 ends in step S13.

In step S11, the bus interface extracting unit 3 outputs a warning if there is no match as a result of the bus interface pattern matching. This processing is executed via output means such as a display device (not shown in FIG. 1).

At step S12, the bus interface extraction unit 3 determines whether or not to newly include the non-existing template in the bus interface extraction template due to the output of the warning. Based on this determination, the operation of the bus interface extractor 3 is terminated at step S13. Through these series of steps, the bus interface extractor 3 described in this embodiment operates.

Next, the bus interface conversion generator 4 according to the first embodiment will be explained. FIG. 7 is a flowchart for explaining the bus interface conversion generator 4 according to the first embodiment.

At step S21, the operation of the bus interface conversion generator 4 is started.

At step S<b>22 , the bus interface conversion generator 4 receives input from the bus interface 6 .

In step S23, the bus interface conversion generation unit 4 converts the bus interface 6. FIG. That is, each signal line for an address signal, a data signal, a command signal, etc. forming the bus interface of the conversion source is converted into a signal line for the address signal, data signal, command signal, etc. forming the bus interface of the conversion destination.

At step S24, it is determined whether or not the signal lines of each bus interface (for example, all bus interfaces) converted at S23 have been converted. If each bus interface has not been converted, the process proceeds to step S23. After each bus interface has been converted, the process proceeds to step S25.

At step S25, the bus interface conversion generation unit 4 generates and outputs the bus conversion circuit description 7. FIG. Here, when the bus conversion circuit description 7 is output, the operation of the bus interface conversion generation unit 4 ends in step S26. Through these series of steps, the bus interface conversion generator 4 described in this embodiment operates.

FIG. 8 shows an example of contents of a highly reliable interface generation template to be input to the highly reliable interface generator 5 in the bus interface device of this embodiment. As with the bus interface extraction template shown in FIG. 5, it is described using the grammatical format of a general-purpose data definition language.

The high-reliability interface generation template 46 is an example representing specifications required to generate a high-reliability interface. The content of the first to fifteenth lines of the highly reliable interface generation template 46 is the highly reliable interface, and "ReliableBus" described in the second line represents the highly reliable interface. The type of this ReliableBus is the value "parity" of the variable name "type" described on the third line.

The contents of the 4th to 8th lines of the high-reliability interface generation template 46 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, from the 5th to 7th lines, the value of the variable name "name" is "par", the value of the variable name "type" is either "odd" or "even", and the variable name "bit" is A value of 1 indicates that it is a 1-bit parity signal line whose signal name is par.

The content of the ninth to thirteenth lines indicates the type of high-reliability circuit included in the variable name "rel_logic" described in the ninth line. That is, in the 10th to 12th lines, the value of the variable name "bit" is one of 16, 32, 64, or 128, the value of the variable name "type" is "xor", and the variable name "area " is any one of 120, 240, 510, and 980, indicating that it is a parity circuit whose exclusive OR circuit area is determined according to the number of bits.

The high-reliability interface generation template 47 is another example of specifications required to generate a high-reliability interface. The contents of the first to fourteenth lines of the highly reliable interface generation template 47 are the highly reliable interface, and "ReliableBus" described in the second line represents the highly reliable interface. The type of this ReliableBus is the value "ecc" of the variable name "type" described on the third line. The contents of the 4th to 7th lines of the high-reliability interface generation template 47 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, the 5th and 6th lines indicate that the value of the variable name "name" is "ecc" and the value of the variable name "bit" is one of 7, 8, or 9. Indicates that the name is an error correcting code (ECC) of ecc.

Also, the content from the 8th line to the 12th line indicates the type of high-reliability circuit included in the variable name "rel_logic" described in the 8th line. That is, from the 9th to the 11th lines, the value of the variable name "bit" is either 32, 64, or 128, the value of the variable name "type" is "hamming", and the value of the variable name "area" is A value of 1800, 3400, or 6100 represents an error correction code circuit in which the circuit area for Hamming coding is determined according to the number of bits.

The trusted interface generation template 48 is yet another example of specifications required to generate a trusted interface. The content of the 1st to 14th lines of the high-reliability interface generation template 48 is a high-reliability interface. Also, "ReliableBus" described in the second line indicates that it is a highly reliable interface. The type of this ReliableBus is the value "duplex" of the variable name "type" described on the third line.

The contents of the 4th to 7th lines of the high-reliability interface generation template 48 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, the 5th and 6th lines are a multi-bit wide signal where the value of the variable name "name" is "dup" and the value of the variable name "bit" is one of 16, 32, and 64. Indicates that the name is a double matching circuit with dup.

Also, the content from the 8th line to the 12th line indicates the type of high-reliability circuit included in the variable name "rel_logic" described in the 8th line. That is, from the 9th to the 11th lines, the value of the variable name "bit" is either 16, 32, or 64, the value of the variable name "type" is "compare", and the value of the variable name "area" is The value is one of 4200, 8400, and 12900, and indicates that the circuit area of the signal line to be matched is determined according to the number of bits.

Examples of the configuration of each circuit that implements such parity, error correction code, and double matching are described in, for example, the following documents.
Takashi Minamiya, "Fault Tolerant Computer", Ohmsha, February 1991, 1st edition, p. 31-43, 127-133.
In addition, although FIG. 8 shows an example of the high-reliability interface generation template 10 described in the grammatical format of a general-purpose data definition language, bus requirements can be expressed in various formats that can be described.

Next, the high-reliability interface generator 5 according to the first embodiment will be explained. FIG. 9 is a flowchart for explaining the highly reliable interface generator 5 according to the first embodiment.

At step S31, the operation of the highly reliable interface generator 5 is started. At step S<b>32 , the highly reliable interface generator 5 receives input from the bus interface 6 .

At step S<b>33 , the high-reliability interface generation unit 5 receives input of the high-reliability interface generation template 10 .

In step S34, the high-reliability interface generation unit 5 determines whether or not each input high-reliability interface generation template (for example, all high-reliability interface generation templates) has been input to the high-reliability interface generation unit 5. I do. As a result, if each high-reliability interface generation template has not been input, the process proceeds to step S33. After each high-reliability interface generation template is input, the process proceeds to step S34.

In step S35, the highly reliable interface generation unit 5 performs pattern matching between the highly reliable bus interface and the highly reliable interface generation template 10 among the bus interfaces input in step S32. Here, the highly reliable bus interface is the IP 15 with bus interface definition.

At step S36, the highly reliable interface generator 5 determines whether or not the highly reliable bus interface matches any bus of the highly reliable interface generation template as a result of the pattern matching at step S35. Then, if they match, the process proceeds to step S37. If they do not match, the process proceeds to step S38.

In step S37, the highly reliable interface generator 5 generates and outputs the highly reliable interface circuit description 8. FIG. Here, when the highly reliable interface circuit description 8 is output, the operation of the highly reliable interface generation unit 5 ends in step S40. The high-reliability interface circuit description 8 is generated by applying a consistent high-reliability bus interface to the high-reliability interface generation template.

In step S38, the high-reliability interface generator 5 outputs a warning if the pattern matching results in a mismatch. This processing is executed via output means not shown in FIG.

At step S39, the high-reliability interface generation unit 5 determines whether or not to newly include a nonexistent template in the high-reliability interface generation template due to the output of the warning. When this determination is made, the operation of the highly reliable interface generating section 5 ends in step S40. Through these series of steps, the highly reliable interface generator 5 described in this embodiment operates.

According to this embodiment, when designing by connecting a plurality of IPs having different bus interfaces, the means for extracting the bus interfaces enables the use of IPs with bus interface definitions and IPs without bus interface definitions. become easier. Furthermore, by means of generating a high-reliability interface, an IP whose bus interface does not have a high-reliability function can be connected by adding a high-reliability function. As a result, it is possible to easily develop a system that requires high reliability even when using an IP that does not have a bus interface definition. In other words, IP directly introduced from other companies, IP obtained indirectly by being included in LSI products, etc., and IP obtained from the Internet as open source can be easily realized in the development of systems that require high reliability. can be done.

According to the first embodiment described above, a bus interface can be extracted from an IP that does not include a bus interface definition. For this reason, even when designing an IP using an IP whose bus interface does not have a high-reliability function, an environment will be created in which an integrated circuit device or system with a highly-reliable interface can be easily implemented by means of a mechanism for making the interface highly reliable. can provide. For example, it is possible to use an IP directly introduced from another company, an IP indirectly obtained by being included in an LSI product, or an IP obtained from the Internet as an open source.

Next, a bus interface device according to a second embodiment will be described with reference to the drawings. FIG. 10 is a block diagram for explaining the bus interface device according to the second embodiment.

Compared with the configuration diagram of the bus interface device described in FIG. ) is added.

Here, it is assumed that the IP (51) without bus interface definition is one of the IPs (25) without bus interface definition selected from the IP database 29 and has no high-reliability interface. It is also assumed that the IP (54) with bus interface definition is one of the IPs (15) with bus interface definition selected from the IP database 19 and has a highly reliable interface.

The bus conversion circuit 52 is obtained by circuit-implementing the bus conversion circuit description 7 by logic synthesis means, and the highly reliable interface circuit 53 is obtained by circuit-implementing the highly reliable interface circuit description 8 by logic synthesis means.

In the integrated circuit device 50 of FIG. 10, the bus conversion circuit 52 and the highly reliable interface circuit 53 are generated by the bus interface device of this embodiment. This connects the IP (51) without a high-reliability interface and the IP (54) with a high-reliability interface.

According to this embodiment, generation of a bus conversion circuit by the bus interface conversion means and generation of a highly reliable interface circuit by the highly reliable interface generation means are realized. This makes it possible to easily implement an integrated circuit device for a system that requires high reliability even when using an IP with a bus interface definition and an IP without a bus interface definition.

Next, Example 3 will be described with reference to the drawings. FIG. 11 is a block diagram illustrating an integrated circuit device 61 designed using the bus interface device according to the third embodiment.

The integrated circuit device 61 described in this embodiment has IPs (51), (55), bus conversion circuits 52, 56, highly reliable interface circuits 53, 57, comparator circuits 63, 64, and IP (54). ing. The integrated circuit device 61 is configured to compare and collate the results output from the two IP (51) and (55) buses.

At this time, the bus interface device of the present invention is configured to generate circuit descriptions of the bus conversion circuits 52 and 56 and the highly reliable interface circuits 53 and 57, and further generate circuit descriptions of the comparator circuits 63 and 64. do.

The comparison/collation circuit 64 collates the values output from the buses of IP(51) and IP(55) through the bus conversion circuits 52 and 56, and transmits the result to IP(54).

The comparison/collation circuit 63 compares the values output from the high-reliability interface circuits 53 and 57 with respect to the high-reliability interface signals for which IP(51) and IP(55) have no function, and transmits the result to IP(54). do.

The IP (54) receives the bus interface signal 74 output from the comparison/collation circuit 64 and the high-reliability interface signal 75 output from the comparison/collation circuit 63, and connects to the bus 71. FIG.

If the values of the bus conversion circuits 52 and 56 do not match according to the comparison collation circuit 64 , the value is output to the comparison result 77 . For example, when the comparison result 77 is a 1-bit signal, 0 is output when the values match, and 1 is output when the values do not match.

Similarly, if the values of the high-reliability interface circuits 53 and 57 do not match according to the comparison collation circuit 63 , the value is output to the comparison result 76 . For example, when the comparison result 76 is a 1-bit signal, 0 is output when the values match, and 1 is output when the values do not match.

In this embodiment, a highly reliable system is designed in which the same IP is duplicated and implemented and outputs are compared to detect a failure or the like in one of them. At this time, the bus interface device makes it possible to easily realize an integrated circuit device having highly reliable functions, even if it is necessary to add an interface signal line and a circuit for comparison due to duplication.

Next, Example 4 will be described with reference to the drawings. FIG. 12 is a block diagram illustrating an integrated circuit device 62 designed using the bus interface device according to the fourth embodiment.

Compared with the block diagram of the integrated circuit device 61 designed using the bus interface device shown in FIG. , a high-reliability interface circuit 60 is added. Another difference is that the comparison and collation circuits 63 and 64 are replaced with majority circuits 65 and 66, respectively.

At this time, the bus interface device of the present invention generates circuit descriptions of the bus conversion circuits 52, 56, 59 and the highly reliable interface circuits 53, 57, 60, and further generates circuit descriptions of the majority circuits 65, 66. configured to Here, three bus conversion circuits 52, 56, 59 and three high-reliability interface circuits 53, 57, 60 are used, but more than that will suffice.

Majority circuit 66 determines the majority of values output from buses IP(51), IP(55) and IP(58) through bus conversion circuits 52, 56, 59 and transmits the result to IP(54). .

The majority circuit 65 determines the majority of the values output from the highly reliable interface circuits 53, 57, and 60 for the highly reliable interface signals for which IP(51), IP(55), and IP(58) have no function, Send the result to IP (54).

The IP (54) receives the bus interface signal 78 output from the majority circuit 66 and the high-reliability interface signal 79 output from the majority circuit 65, and connects to the bus 71. FIG.

If any one of the values of the bus conversion circuits 52, 56, 59 is found to be mismatched by the majority circuit 66, the values other than the mismatched value are sent to the IP (54).

Similarly, if any of the values of the high-reliability interface circuits 53, 57, and 60 are found to be mismatched by the majority circuit 65, the values other than the mismatched values are sent to IP (54).
In this embodiment, the same IP is implemented in triplicate, and a majority decision is made on the output to design a highly reliable and highly available system that continues to operate even if a failure occurs in one of them. It will be. At this time, the bus interface device makes it possible to easily realize an integrated circuit device having highly reliable and highly available functions, even if it is necessary to add an interface signal line and a circuit based on majority decision due to the triple structure. can.

A fifth embodiment showing a railway signal control system related to the bus interface device of each of the embodiments described above will be described. FIG. 13 is a configuration diagram for explaining the railway signal control system 100 according to the fifth embodiment.

As one of the parts constituting the railway signal controller 101, an integrated circuit device 62 designed using the bus interface device of each embodiment is mounted.

The railway signal control system 100 described in this embodiment obtains positional information while the train 105 is running from sensors attached to the rail portions. These pieces of information are transmitted as train position information 111 to the train position calculation unit 103 via communication means such as wired or wireless communication. The train position data 112 calculated by the train position calculation unit 103 is sent to three IPs (no bus interface definition) mounted on the integrated circuit device 62 of the railway signal controller 101, and addition of a highly reliable interface and majority decision. is processed.

On the other hand, the traffic signal 104 is a device that notifies a running train to stop in an emergency such as a failure or an accident in the railway signal control system 100, and must operate reliably in an emergency to safely stop the train. Therefore, high safety is required.
Therefore, the signal control signal 113 to be transmitted to the signal control unit 102 that controls the traffic signal 104 is output from the integrated circuit device 62 of the railway signal controller 101 with a highly reliable interface added by a highly reliable interface circuit.
A signal control signal 113 is transmitted to the signal control unit 102, and in an emergency, a stop instruction signal 114 is transmitted from the signal control unit 102 to the signal device 104 to notify the stop, thereby safely stopping the train.

According to this embodiment, when designing a system for a railroad that requires an extremely high level of safety, the bus interface device of the present invention can be used to replace a communication interface without a high-reliability function with a communication interface with a high-reliability function. Easy to convert to interface. Therefore, it is possible to reduce the man-hours required for designing a system with high safety and availability, and to realize the system in a short period of time.

Next, a sixth embodiment showing a plant control system related to the bus interface device of each embodiment will be described. FIG. 14 is a configuration diagram for explaining a case where the bus interface device of each embodiment is applied to the plant control system 200. As shown in FIG.

An integrated circuit device 50 designed using the bus interface device of the present invention is mounted as one of the components constituting the controller 204 .

In the plant control system 200 according to the present embodiment, a controller 204 to which a sensor 301 (an example of a weighing device) and a valve 302 (an example of an operation device) are connected is connected via a control network 203 to an HMI (human machine interface). : Human Machine Interface) 202 and the computer 201 . HMI (202) and computer 201 are also connected to plant management server 208 via information network 209 . The plant management server 208 monitors the state of the plant and issues instructions in the event of an abnormality or emergency.

Also, the controller 204 that constitutes the plant control system 200 of this embodiment receives field data from the sensor 301 , performs calculations in the controller 204 , and then outputs a control command to the valve 302 .

Therefore, the monitor signal transmitted from the computer 201 to the controller 204 via the control network 203 is added with a highly reliable interface by a highly reliable interface circuit from the integrated circuit device 50 of the controller 204 . Then, it outputs a control command to the valve 302 . For example, in an emergency when a failure or abnormality occurs, a valve stop signal is sent to the valve 302 to keep the plant in a safe state.

According to this embodiment, when designing a system such as a plant composed of a controller and a computer, a communication interface without a high reliability function can be changed to a communication interface with a high reliability function by using the bus interface device of each embodiment. Easy to convert. Therefore, it is possible to reduce the number of man-hours required for designing a highly safe system, and to realize the system in a short period of time.

The control system described in these embodiments can be used in various systems such as an elevator control system, a railway control system, an automobile control system, a construction machine control system, and a power generation control system.

Moreover, the present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments are detailed and specific descriptions of bus interface devices in order to facilitate understanding of the present invention, and are not necessarily limited to those having all the components described. Also, it is possible to replace part of the constituent elements of one embodiment with part of the constituent elements of another embodiment. It is also possible to add the constituent elements of another embodiment to the constituent elements of one embodiment. Moreover, it is also possible to add, delete, or replace a part of other constituent elements with respect to a part of the constituent elements of each embodiment.

1, 11, 12, 13, 15...IPs with bus interface definition
2, 21, 22, 23, 25...IP without bus interface definition
3 Bus interface extraction unit 4 Bus interface conversion generation unit 5 Highly reliable interface generation unit 6 Bus interface 7 Bus conversion circuit description 8 Highly reliable interface circuit description 9, 41, 42 Bus interface extraction template 10, 46 , 47, 48... Highly reliable interface generation template 19, 29... IP database 31, 32, 33... Highly reliable interface 50, 61, 62... Integrated circuit device 51, 54, 55, 58... IP
52, 56, 59... Bus conversion circuit 53, 57, 60... Highly reliable interface circuit 63, 64... Comparison matching circuit 65, 66... Majority decision circuit 100... Railway signal control system 101... Railway signal controller 102... Signal controller 103 ... Train position calculation unit 200 ... Plant control system 201 ... Computer 202 ... HMI (Human Machine Interface)
203... Control network 204... Controller 208... Plant management server 209... Information network 301... Sensor 302... Valve

Claims (10)

In a bus interface device that generates a bus interface indicating an input definition and an output definition of an electronic device using an IP that is a design asset,
specifying a bus interface from each of a first IP including a bus interface definition and a second IP not including a bus interface definition; a bus interface extraction unit that compares the correspondence of the second bus interfaces in the IP and extracts the second bus interface and the corresponding first bus interface whose output signal needs to be converted in order to satisfy a predetermined criterion; ,
a bus interface conversion generation unit for generating a bus conversion circuit description for converting an output signal of the second bus interface using the extracted first bus interface and the second bus interface;
using the extracted first bus interface and the second bus interface, inputting the output signal to be converted, and generating a highly reliable interface circuit description that is a bus interface satisfying the predetermined criteria; A bus interface device comprising an interface generator. 2. The bus interface device according to claim 1, wherein
The bus interface conversion generation unit uses a bus interface extraction template for extracting the bus interface to specify the corresponding relationship between the signal lines of the first bus interface and the second bus interface. bus interface device. 3. The bus interface device according to claim 1, wherein
The high-reliability interface generator generates the first bus interface corresponding to the extracted second bus interface as the high-reliability interface circuit by applying a high-reliability interface generation template indicating specifications of a high-reliability interface circuit description. A bus interface device characterized by generating a description. 4. The bus interface device according to claim 3,
A bus interface device, wherein the high-reliability interface generator performs pattern matching between the first bus interface and the high-reliability interface generation template. 5. The bus interface device according to any one of claims 1 to 4,
The bus interface device according to claim 1, wherein the bus interface extraction unit determines whether the specified second bus interface requires conversion of the output signal, and executes the extraction if necessary. 6. A bus conversion circuit according to a bus conversion circuit description generated by said bus interface conversion generation unit of a bus interface device according to claim 1, and said highly reliable bus conversion circuit generated by said bus interface conversion generation unit. An integrated circuit device comprising a highly reliable interface circuit according to an interface circuit description. 7. The integrated circuit device of claim 6,
a plurality of the bus conversion circuits according to the bus conversion circuit description;
a plurality of said highly reliable interface circuits according to said highly reliable interface circuit description;
a first comparison/collation circuit that compares the outputs of the plurality of bus conversion circuits;
1. An integrated circuit device comprising a second comparison circuit for comparing outputs of said plurality of highly reliable interface circuits. The integrated circuit device according to claim 7, wherein
each of the plurality of bus conversion circuits and the plurality of high-reliability interface circuits is composed of three or more,
a first majority circuit for majority matching the outputs of the plurality of bus conversion circuits;
An integrated circuit device comprising: an integrated circuit device having a second majority circuit for majority matching of the outputs of the plurality of high-reliability interface circuits. 9. A railway signal control system comprising the integrated circuit device according to claim 7 or 8 as a railway signal controller. A plant control system comprising the integrated circuit device according to claim 7 or 8 as a controller.

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