WO2021157113A1

WO2021157113A1 - Bus interface device

Info

Publication number: WO2021157113A1
Application number: PCT/JP2020/033167
Authority: WO
Inventors: 輝昭酒田; 松本　典剛
Original assignee: 株式会社日立製作所
Priority date: 2020-02-05
Filing date: 2020-09-02
Publication date: 2021-08-12
Also published as: JP2021124934A; JP7178379B2

Abstract

When IP-based LSI design involves using an IP that that does not have a bus interface definition, such as an IP directly introduced from another company, an IP indirectly obtained by being included in an LSI product, etc., or an IP obtained from the Internet as an open source, it is difficult to apply the LSI design. In order to solve the problem described above, the present invention provides a bus interface device having a first IP 1 including a bus interface definition, a second IP 2 not including a bus interface definition, a bus interface extraction unit 3 that extracts a bus interface from the first IP 1 and the second IP 2, a bus interface conversion generation unit 4 that converts and generates a bus interface from the bus interface information extracted by the bus interface extraction unit, and a high-reliability interface generation unit 5 that generates a high-reliability interface for the bus interface.

Description

Bus interface device

The present invention relates to a bus interface device that generates a bus interface. Among them, the technology is particularly effective when applied to integrated circuit devices and the like equipped with functions for realizing safety and high reliability. The present invention can also be applied to a control technique such as a plan using a bus interface device.

Conventionally, integrated circuit devices have been used in electronic devices in order to realize the functions of electronic devices. This integrated circuit device is often realized by mounting a plurality of functional blocks such as a central processing unit (CPU), memory, timer, and communication on one semiconductor chip.

Functional blocks mounted on semiconductor chips are called design assets (Intellectual Property, IP). This IP may be designed in-house or designed by another company, but if it is in a reusable format, it will be designed and verified when creating another semiconductor chip. Man-hours can be shortened and development costs can be reduced. In recent years, the semiconductor design process has become finer and the number of functions that can be mounted on one integrated circuit device has increased. Therefore, it is rare that all the functions are converted into IP and implemented in-house. There are also cases where IP is used as open source, which is provided in a form that anyone can freely use. Such a design method is called IP-based design.

In the IP-based design, each functional block is designed based on individual specifications, but the combination of IPs does not mean that the integrated circuit device meets the specifications and performance required by the entire system, but the IPs are combined. Functional verification and performance verification above are required. Further, when IPs do not have a common interface for connection, design man-hours for connecting IPs are also required. Furthermore, when implementing a system that requires high reliability such as a social infrastructure system at an early stage with an IP-based design, there may be cases where even an IP that does not have a high reliability function must be used. It is conceivable, and guaranteeing a highly reliable function in that case becomes an issue.

As a background technology in this technical field, there is Japanese Patent Application Laid-Open No. 2007-193842 (Patent Document 1). This Patent Document 1 describes a technique for reducing design man-hours and further improving design efficiency in IP-based LSI design. Specifically, the IP database includes a system-level IP used in system-level design, and in the system-level IP, each IP is divided into a processing algorithm description unit, an input data structure definition unit, and an output data structure definition unit. As described, the conversion circuit generating means generates a data conversion circuit between the communication channel and the IP by referring to the IP database when the communication channel is provided between the IPs that perform data communication in the architecture or functional design. It is stated (see summary).

JP-A-2007-193842

Patent Document 1 has an IP database having a system-level IP including an input data structure definition unit and an output data structure definition unit in an IP-based LSI design, and a conversion circuit generating means refers to the IP database and communicate channels. Describes a technique for improving design efficiency in IP-based LSI design by generating a data conversion circuit between and IP.

However, in the IP-based LSI design technology in Patent Document 1, all bus interface definitions represented by input definitions and output definitions exist in the system level IP registered in the IP database, and a channel input side conversion circuit is generated. Means and channel output side conversion circuit generation means receives information and automatically generates a bus conversion circuit on the premise that the bus interface definition of each IP exists.

Therefore, it can be applied when using an IP whose bus interface definition is known, such as an IP created in-house in the past. However, it will be difficult to apply it to LSI design when using an IP that does not have a prerequisite bus interface definition. This problem is not described in Patent Document 1. The IPs for which the prerequisite bus interface definition does not exist include IPs directly introduced from other companies, IPs indirectly obtained in the form of being included in LSI products, and IPs obtained from the Internet as an open source.

In order to solve the above problem, for example, the configuration described in the claims is adopted.

The present application includes a plurality of means for solving the above problems. For example, in a bus interface device that generates a bus interface showing an input definition and an output definition of an electronic device using IP, which is a design asset. The bus interface is specified from each of the first IP including the definition of the bus interface and the second IP not including the definition of the bus interface, and the first bus interface and the second bus interface in the specified first IP are specified. A bus interface extraction unit that compares the correspondence between the second bus interfaces in IP and extracts the second bus interface that needs to be converted into an output signal and the corresponding first bus interface in order to satisfy a predetermined criterion. , A bus interface conversion generator that generates a bus conversion circuit description for converting the output signal of the second bus interface using the extracted first bus interface and the second bus interface, and extraction. A highly reliable interface that inputs the converted output signal using the first bus interface and the second bus interface, and generates a highly reliable interface circuit description which is a bus interface satisfying the predetermined criteria. It is a bus interface device having a generator.

Further, the present invention includes an integrated circuit device generated by using the bus conversion circuit description and the highly reliable interface circuit description generated by the bus interface device. Further, various control systems including this integrated circuit device are also included in the present invention.

According to the present invention, it is possible to use an IP that does not include the definition of a bus interface with higher reliability. Issues, configurations and effects other than those mentioned above will be clarified by the description of the following examples.

It is an example of the block diagram of the bus interface apparatus which concerns on Example 1. FIG. This is an example of an IP database of IP having a bus interface definition. This is an example of an IP database of IP without a bus interface definition. This is an example of a configuration diagram of a bus interface device to which bus interface extraction template information and highly reliable interface template information are added. This is an example of a bus interface extraction template. This is an example of a flowchart showing the operation of the bus interface extraction unit. This is an example of a flowchart showing the operation of the bus interface conversion generator. This is an example of a highly reliable interface generation template. This is an example of a flowchart showing the operation of the highly reliable interface generator. This is an example of a configuration diagram of a system using the bus interface device according to the second embodiment. This is an example of an integrated circuit device designed by the bus interface device according to the third embodiment. This is an example of an integrated circuit device designed by the bus interface device according to the fourth embodiment. It is explanatory drawing explaining an example of the case where the bus interface device which concerns on each Example of this invention is applied to a railroad signal control system. It is explanatory drawing explaining an example when the bus interface apparatus which concerns on each Example of this invention is applied to a plant control system.

Hereinafter, examples of the present invention will be described with reference to the drawings. In the specification and drawings, elements having substantially the same function or configuration are designated by the same reference numerals, and if the description is duplicated, the description may be omitted.

First, the bus interface device according to the first embodiment will be described with reference to the drawings. FIG. 1 is an example of a configuration diagram for explaining the bus interface device according to the first embodiment. The bus interface device is realized by a so-called computer. That is, various functions described later are executed by an arithmetic unit such as a CPU according to a program.

The bus interface device according to the first embodiment has a bus interface extraction unit 3, a bus interface conversion generation unit 4, and a highly reliable interface generation unit 5.

The IP with bus interface definition (1) and the IP without bus interface definition (2) are input to the bus interface extraction unit 3, and the bus interface extraction unit 3 generates and outputs the bus interface 6.

The bus interface 6 is input to the bus interface conversion generation unit 4, and the bus interface conversion generation unit 4 generates and outputs the bus conversion circuit description 7. Further, the bus interface 6 is input to the high-reliability interface generation unit 5, and the high-reliability interface generation unit 5 generates and outputs the high-reliability interface circuit description 8.

FIG. 2 is an example of a diagram illustrating an IP database having a plurality of IPs with a bus interface definition.

All the IPs included in the IP database 19 have a bus interface definition, and here, three types of IPs with a bus interface definition are shown. As an example of an IP with a bus interface definition, an IP that has been implemented from specifications to design in-house is applicable.
It is known from the definition that the IP (11) with a bus interface definition has a highly reliable interface (parity) 31. Similarly, it is known from the definition that the IP (12) with a bus interface definition included in the IP database 19 has a highly reliable interface (ECC) 32. Further, it is known from the definition that the IP (13) with a bus interface definition included in the IP database 19 has a highly reliable interface (duplication collation) 33. That is, a highly reliable interface satisfies a predetermined condition in terms of its function. How to set this standard includes internal standards such as safety.

FIG. 3 is an example of a diagram illustrating an IP database having a plurality of IPs without a bus interface definition.

All the IPs included in the IP database 29 have no bus interface definition, and here, three types of IPs without a bus interface are shown. Examples of IPs without a bus interface definition include IPs directly introduced from other companies, IPs indirectly obtained by being included in LSI products, and IPs obtained from the Internet as an open source. It is unclear what kind of bus interface each of the IPs (21), (22), and (23) without a bus interface definition has, and what kind of highly reliable interface they have.

FIG. 4 is an example of a configuration diagram in the case of extracting the bus interface and generating the highly reliable interface for the bus interface device of the present invention.

FIG. 4 shows that the IP (1) with the bus interface definition is changed to the IP database 19 and the IP (2) without the bus interface definition is changed to the IP database 29 as compared with the bus interface device described with reference to FIG. It's different. Further, the parts to which the bus interface extraction template 9 and the highly reliable interface generation template 10 are added are different.

Any IP with bus interface definition included in the IP database 19 (15) and any IP without bus interface definition included in the IP database 29 (25) are input to the bus interface extraction unit 3. Further, the bus interface extraction template 9 is input to the bus interface extraction unit 3.

The bus interface 6 is input to the high-reliability interface generation unit 5, and the high-reliability interface generation template 10 is further input to the high-reliability interface generation unit 5.

FIG. 5 shows an example of the contents of the bus interface extraction template input to the bus interface extraction unit 3 in the bus interface device of the present invention, and is described using a grammatical format of a general-purpose data definition language. There is.

The bus interface extraction template 41 is an example showing the specifications of the bus interface.

The contents of the first to 22nd lines of the bus interface extraction template 41 are bus interfaces, and the "Bus Interface" described in the second line is a bus interface. The name of this Bus Interface is the value "busif_a" of the variable name "name" described in the third line.

The contents of the 4th to 20th lines of the bus interface extraction template 41 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, in the 5th to 9th lines, the value of the variable name "type" is "address", the value of the variable name "name" is "addr", and the value of the variable name "bit" is 32, 32. A bit indicates that the signal name is the address signal line of adr.

In the 10th to 14th lines, the value of the variable name "type" is "data", the value of the variable name "name" is "dat", and the value of the variable name "bit" is 32, 32. A bit indicates that the signal name is a dat data signal line.

Furthermore, in the 15th to 19th lines, the value of the variable name "type" is "command", the value of the variable name "name" is "rd", and the value of the variable name "bit" is 1. 1 bit indicates that the signal name is the command signal line of rd.

The bus interface extraction template 42 is an example showing another specification of the bus interface.

The bus interface extraction template 42 is different from the bus interface extraction template 41 in that the bus specifications of the highly reliable interface are inserted in the 20th to 24th lines.

In the 20th to 24th lines representing one of the bus signals included in the variable name "bus_list" described in the 4th line, the value of the variable name "type" is "parity" and the value of the variable name "name". Is "par" and the value of the variable name "bit" is 1, indicating that the signal name is a parity signal line of par with 1 bit.

Although FIG. 5 shows an example in which the bus interface extraction template 9 is described in the grammatical format of a general-purpose data definition language, the bus requirements can be expressed in various formats that can be described.

Next, the bus interface extraction unit 3 according to the first embodiment will be described. FIG. 6 is a flowchart illustrating the function (operation) of the bus interface extraction unit 3 according to the first embodiment.

In step S01, the operation of the bus interface extraction unit 3 starts.

In step S02, the bus interface extraction unit 3 accepts the input of the IP (15) with the bus interface definition.

In step S03, the bus interface extraction unit 3 accepts the input of the IP (25) without the bus interface definition.

In step S04, the bus interface extraction unit 3 accepts the input of the bus interface extraction template 9.

In step S05, the bus interface extraction unit 3 determines whether or not the input of each input bus interface extraction template (for example, all bus interface extraction templates) has been accepted. If each bus interface extraction template is not input, the process proceeds to step S04. Further, when each bus interface extraction template is input, the process proceeds to step S06.

In step S06, the bus interface extraction unit 3 detects the bus signal line of the IP (15) with the bus interface definition based on the input bus interface extraction template.

In step S07, the bus interface extraction unit 3 detects the bus signal line of the IP (25) without the bus interface definition based on the input bus interface extraction template. Here, the bus interface extraction unit 3 determines whether the IP (25) without a bus interface definition satisfies a predetermined criterion, that is, is a highly reliable bus interface. As a result, when the predetermined condition is satisfied, the IP (25) without the bus interface definition is diverted, and the subsequent processing does not have to be performed. This determination may be made in step S02.

In step S08, the bus interface extraction unit 3 performs pattern matching between the bus interface and the bus interface extraction template. It is determined which bus interface each bus of the IP (15) with the bus interface definition and the IP (25) without the bus interface definition has.

In step S09, the bus interface extraction unit 3 determines whether or not the bus interface matches any of the buses in the bus interface extraction template as a result of pattern matching in step 08, and if they match, proceeds to step S10. Transition. If they do not match, the process proceeds to step S11.

In step S10, the bus interface extraction unit 3 generates and outputs the bus interface 6 to be converted from the bus interface extraction unit 3. Then, when the output is output, the operation of the bus interface extraction unit 3 ends in step S13.

In step S11, the bus interface extraction unit 3 outputs a warning when the results of bus interface pattern matching do not match. This process is executed via an output means such as a display device (not shown in FIG. 1 or the like).

In step S12, the bus interface extraction unit 3 determines whether or not to newly include the nonexistent template in the bus interface extraction template because the warning is output. Based on this determination, the operation of the bus interface extraction unit 3 ends in step S13. Through these series of steps, the bus interface extraction unit 3 described in this embodiment operates.

Next, the bus interface conversion generation unit 4 according to the first embodiment will be described. FIG. 7 is a flowchart illustrating the bus interface conversion generation unit 4 according to the first embodiment.

In step S21, the operation of the bus interface conversion generation unit 4 starts.

In step S22, the bus interface conversion generation unit 4 receives the input of the bus interface 6.

In step S23, the bus interface conversion generation unit 4 is a step of converting the bus interface 6. That is, each signal line such as an address signal, a data signal, and a command signal constituting the conversion source bus interface is converted into a signal line such as an address signal, a data signal, and a command signal constituting the conversion destination bus interface.

In step S24, it is determined whether or not the signal lines of each bus interface (for example, all bus interfaces) converted in S23 have been converted. If each bus interface has not been converted, the process proceeds to step S23. When each bus interface is converted, the process proceeds to step S25.

In step S25, the bus interface conversion generation unit 4 generates and outputs the bus conversion circuit description 7. Here, when the bus conversion circuit description 7 is output, the operation of the bus interface conversion generation unit 4 ends in step S26. Through these series of steps, the bus interface conversion generation unit 4 described in this embodiment operates.

FIG. 8 shows an example of the contents of the highly reliable interface generation template input to the highly reliable interface generation unit 5 in the bus interface device of this embodiment. Then, as in the bus interface extraction template shown in FIG. 5, the description is made using the grammatical format of a general-purpose data definition language.

The highly reliable interface generation template 46 is an example representing the specifications required to generate a highly reliable interface. The contents of the first to fifteenth lines of the high-reliability interface generation template 46 are high-reliable interfaces, and "Reliable Bus" described in the second line indicates that the high-reliable interface. The type of this Reliable Bus is the value "parity" of the variable name "type" described in the third line.

The contents of the 4th to 8th lines of the highly reliable interface generation template 46 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, in the 5th to 7th lines, the value of the variable name "name" is "par", the value of the variable name "type" is either "odd" or "even", and the variable name is "bit". Indicates that the value is 1 and the signal name is par parity signal line with 1 bit.

The contents of the 9th to 13th lines indicate the types of highly reliable circuits included in the variable name "rel_logic" described in the 9th line. That is, in the 10th to 12th lines, the value of the variable name "bit" is one of 16, 32, 64, and 128, the value of the variable name "type" is "xor", and the variable name "area". Indicates that the "parity circuit" has a value of 120, 240, 510, or 980, and the circuit area of the exclusive OR is determined according to the number of bits.

The highly reliable interface generation template 47 is another example representing the specifications required to generate a highly reliable interface. The contents of the first to 14th lines of the high-reliability interface generation template 47 indicate that the high-reliability interface is used, and "Reliable Bus" described in the second line is the high-reliability interface. The type of this Reliable Bus is the value "ecc" of the variable name "type" described in the third line. The contents of the 4th to 7th lines of the highly reliable interface generation template 47 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, in the 5th to 6th lines, the value of the variable name "name" is "ecc" and the value of the variable name "bit" is any of 7, 8 and 9, and the signal has a multi-bit width. Indicates that the name is an error correction code (ECC) of ecc.

The contents of the 8th to 12th lines indicate the types of highly reliable circuits included in the variable name "rel_logic" described in the 8th line. That is, in the 9th to 11th lines, the value of the variable name "bit" is one of 32, 64, and 128, the value of the variable name "type" is "hamming", and the value of the variable name "area". Indicates that the Hamming code circuit has a value of 1800, 3400, or 6100, and the Hamming code circuit area is determined according to the number of bits.

The highly reliable interface generation template 48 is yet another example showing the specifications required to generate a highly reliable interface. The contents of the first to 14th lines of the highly reliable interface generation template 48 are highly reliable interfaces. In addition, "Reliable Bus" described in the second line indicates that it is a highly reliable interface. The type of this Reliable Bus is the value "duplex" of the variable name "type" described in the third line.

The contents of the 4th to 7th lines of the highly reliable interface generation template 48 represent the types of bus signals included in the variable name "bus_list" described in the 4th line. That is, in the 5th to 6th lines, the value of the variable name "name" is "dup" and the value of the variable name "bit" is one of 16, 32, and 64, which is a signal with a multi-bit width. Indicates that the name is a duplication collation circuit of dup.

The contents of the 8th to 12th lines indicate the types of highly reliable circuits included in the variable name "rel_logic" described in the 8th line. That is, in the 9th to 11th lines, the value of the variable name "bit" is one of 16, 32, and 64, the value of the variable name "type" is "compare", and the value of the variable name "area". It indicates that the value is one of 4200, 8400, and 12900, and the circuit area of the signal line to be collated is determined according to the number of bits.

A configuration example of each circuit that realizes such parity, error correction code, and double collation is described in, for example, the following documents.
Takashi Minamiya, "Fault Tolerant Computer", Ohmsha, February 1991, 1st Edition, p. 31-43, 127-133.
Further, although FIG. 8 shows an example in which the example of the highly reliable interface generation template 10 is described in the grammatical format of a general-purpose data definition language, the bus requirements can be expressed in various formats that can be described.

Next, the highly reliable interface generation unit 5 according to the first embodiment will be described. FIG. 9 is a flowchart illustrating the highly reliable interface generation unit 5 according to the first embodiment.

In step S31, the operation of the highly reliable interface generation unit 5 starts. In step S32, the highly reliable interface generation unit 5 receives the input of the bus interface 6.

In step S33, the high-reliability interface generation unit 5 accepts the input of the high-reliability interface generation template 10.

In step S34, the high-reliability interface generation unit 5 determines whether or not each of the input high-reliability interface generation templates (for example, all high-reliability interface generation templates) has been input to the high-reliability interface generation unit 5. I do. As a result, if each highly reliable interface generation template is not input, the process proceeds to step S33. When each highly reliable interface generation template is input, the process proceeds to step S34.

In step S35, the highly reliable interface generation unit 5 performs pattern matching between the highly reliable bus interface and the highly reliable interface generation template 10 among the bus interfaces input in step S32. Here, the highly reliable bus interface is IP15 with a bus interface definition.

In step S36, the high-reliability interface generation unit 5 determines, as a result of the pattern matching in step 35, whether or not the highly reliable bus interface matches any bus of the high-reliability interface generation template. Then, if they match, the process proceeds to step S37. If they do not match, the process proceeds to step S38.

In step S37, the high-reliability interface generation unit 5 generates and outputs the high-reliability interface circuit description 8. Here, when the high-reliability interface circuit description 8 is output, the operation of the high-reliability interface generation unit 5 ends in step S40. The generation of the highly reliable interface circuit description 8 is executed by applying the matched and highly reliable bus interface to the highly reliable interface generation template.

In step S38, the highly reliable interface generation unit 5 outputs a warning when the results of pattern matching do not match. This process is executed via an output means (not shown in FIG. 1 or the like).

In step S39, the high-reliability interface generation unit 5 determines whether or not to newly include the non-existent template in the high-reliability interface generation template because the warning is output. When this determination is made, the operation of the highly reliable interface generation unit 5 ends in step S40. Through these series of steps, the highly reliable interface generation unit 5 described in this embodiment operates.

According to this embodiment, when designing by connecting a plurality of IPs having different bus interfaces, it is possible to use an IP having a bus interface definition and an IP without a bus interface definition by means for extracting the bus interface. It will be easier. Further, by means of generating a highly reliable interface, it is possible to add a highly reliable function to an IP that does not have a highly reliable function in the bus interface and connect it. As a result, it is possible to easily develop a system that requires high reliability even when using an IP that does not have a bus interface definition. In other words, it is possible to easily develop a system that requires high reliability even with IP directly introduced from other companies, IP indirectly obtained by being included in LSI products, etc., and IP obtained from the Internet as open source. Can be done.

According to the above-mentioned first embodiment, the bus interface can be extracted from the IP that does not include the definition of the bus interface. Therefore, by using a mechanism to improve the reliability of the interface, an environment in which an integrated circuit device or system having a highly reliable interface can be easily mounted even when designing an IP using an IP that does not have a highly reliable function in the bus interface can be created. Can be provided. For example, it is possible to use an IP directly introduced from another company, an IP indirectly obtained in a form included in an LSI product, or an IP obtained from the Internet as open source.

Next, the bus interface device according to the second embodiment will be described with reference to the drawings. FIG. 10 is a block diagram illustrating a bus interface device according to a second embodiment.

The bus interface device described in this embodiment has an IP (51), a bus conversion circuit 52, a highly reliable interface circuit 53, and an IP (54) as compared with the configuration diagram of the bus interface device described in FIG. 4 of the first embodiment. The difference is that the integrated circuit device 50 provided with) is added.

Here, it is assumed that the IP (51) without a bus interface definition is one of the IPs without a bus interface definition (25) selected from the IP database 29, and there is no highly reliable interface. Further, the IP (54) having the bus interface definition is one of the IPs (15) having the bus interface definition selected from the IP database 19, and has a highly reliable interface.

The bus conversion circuit 52 is a circuit implementation of the bus conversion circuit description 7 by a logic synthesis means, and the high reliability interface circuit 53 is a circuit implementation of the high reliability interface circuit description 8 by a logic synthesis means.

In the integrated circuit device 50 of FIG. 10, the bus conversion circuit 52 and the highly reliable interface circuit 53 are generated by the bus interface device of this embodiment. As a result, the IP (51) having no highly reliable interface and the IP (54) having a highly reliable interface are connected.

According to this embodiment, the generation of the bus conversion circuit by the bus interface conversion means and the generation of the high reliability interface circuit by the high reliability interface generation means are realized. This makes it possible to easily realize an integrated circuit device for a system that requires high reliability even when an IP having a bus interface definition and an IP without a bus interface definition are used.

Next, Example 3 will be described with reference to the drawings. FIG. 11 is a block diagram illustrating an integrated circuit device 61 designed using the bus interface device according to the third embodiment.

The integrated circuit device 61 described in this embodiment has IP (51), (55),

bus conversion circuits

52, 56, highly

reliable interface circuits

53, 57,

comparison matching circuits

63, 64, and IP (54). ing. The integrated circuit device 61 is configured to compare and collate the results output from the two IP (51) and (55) buses.

At this time, the bus interface device of the present invention is configured to generate the circuit descriptions of the

bus conversion circuits

52 and 56 and the highly

reliable interface circuits

53 and 57, and further generate the circuit descriptions of the comparison and

collation circuits

63 and 64. do.

The comparison collation circuit 64 collates the values output from the IP (51) and IP (55) buses through the

bus conversion circuits

52 and 56, and transmits the result to the IP (54).

The comparison collation circuit 63 collates the values output from the high-

reliability interface circuits

53 and 57 with respect to the high-reliability interface signal having no function in the IP (51) and the IP (55), and transmits the result to the IP (54). do.

The IP (54) receives the bus interface signal 74 output from the comparison matching circuit 64 and the highly reliable interface signal 75 output from the comparison matching circuit 63 as inputs, and connects to the bus 71.

If the values of the

bus conversion circuits

52 and 56 do not match by the comparison and collation circuit 64, the values are output to the comparison result 77. For example, when the comparison result 77 is a 1-bit signal, 0 is output when the values match, and 1 is output when the values do not match.

Similarly, if the values of the highly

reliable interface circuits

53 and 57 do not match by the comparison and collation circuit 63, the values are output to the comparison result 76. For example, when the comparison result 76 is a 1-bit signal, 0 is output when the values match, and 1 is output when the values do not match.

In this embodiment, the same IP is duplicated and mounted, and the outputs are compared to design a highly reliable system that detects when a failure occurs in one of them. At this time, the bus interface device can easily realize an integrated circuit device having a highly reliable function even when it is necessary to add a circuit by comparison with the signal line of the interface due to duplication.

Next, Example 4 will be described with reference to the drawings. FIG. 12 is a block diagram illustrating an integrated circuit device 62 designed using the bus interface device according to the fourth embodiment.

The integrated circuit device 62 described in this embodiment has an IP (58) and a bus conversion circuit 59 as compared with a block diagram of the integrated circuit device 61 designed by using the bus interface device shown in FIG. 11 of the third embodiment. , High reliability interface circuit 60 is added. Further, the difference is that the comparison and

collation circuits

63 and 64 are replaced with the

majority decision circuits

65 and 66, respectively.

At this time, the bus interface device of the present invention generates the circuit descriptions of the

bus conversion circuits

52, 56, 59 and the highly

reliable interface circuits

53, 57, 60, and further generates the circuit descriptions of the

majority decision circuits

65, 66. Configure to. Here, three

bus conversion circuits

52, 56, 59 and high-

reliability interface circuits

53, 57, 60 are configured, respectively, but any more may be used.

The majority decision circuit 66 determines the majority vote of the values output from the IP (51), IP (55), and IP (58) buses through the

bus conversion circuits

52, 56, and 59, and transmits the result to the IP (54). ..

The majority decision circuit 65 determines the majority vote of the values output from the high

reliability interface circuits

53, 57, 60 for the high reliability interface signals that the IP (51), IP (55), and IP (58) have no function. The result is transmitted to IP (54).

The IP (54) inputs the bus interface signal 78 output from the majority decision circuit 66 and the highly reliable interface signal 79 output from the majority decision circuit 65, and connects to the bus 71.

If any of the values of the

bus conversion circuits

52, 56, and 59 does not match by the majority decision circuit 66, the values other than the mismatched values are transmitted to the IP (54).

Similarly, when any of the values of the high-

reliability interface circuits

53, 57, and 60 is inconsistent by the majority decision circuit 65, the values other than the inconsistent values are transmitted to the IP (54).
In this embodiment, the same IP is tripled and mounted to determine the majority of the output, thereby designing a highly reliable and highly available system that continues to operate even if a failure occurs in any part of the system. It will be. At this time, the bus interface device can easily realize an integrated circuit device having highly reliable and highly available functions even when it is necessary to add an interface signal line and a circuit by majority voting due to triplet. can.

The fifth embodiment showing the railway signal control system related to the bus interface device of each of the above-described embodiments will be described. FIG. 13 is a configuration diagram illustrating the railway signal control system 100 according to the fifth embodiment.

An integrated circuit device 62 designed using the bus interface device of each embodiment is mounted on one of the components constituting the railway signal control controller 101.

The railway signal control system 100 described in this embodiment obtains the moving position information of the train 105 by a sensor attached to the rail portion. These pieces of information are transmitted as train position information 111 to the train position calculation unit 103 via a communication means such as wired or wireless. The train position data 112 calculated by the train position calculation unit 103 is sent to three IPs (without bus interface definition) mounted on the integrated circuit device 62 of the railway signal control controller 101, and a highly reliable interface is added and a majority decision is made. Is processed.

On the other hand, the signal 104 is a device in the railway signal control system 100 that notifies a running train of a stop in an emergency such as a failure or an accident, and it is necessary to operate reliably in an emergency to stop the train safely. Therefore, high safety is required.
Therefore, the signal control signal 113 to be transmitted to the signal control unit 102 that controls the signal 104 is output from the integrated circuit device 62 of the railway signal control controller 101 with a high reliability interface by the high reliability interface circuit added.
The signal control signal 113 is transmitted to the signal control unit 102, and in an emergency, the signal control unit 102 transmits a stop instruction signal 114 to the traffic light 104 to notify the stop, thereby safely stopping the train.

According to this embodiment, when designing a system for railways that requires extremely high safety, the bus interface device of the present invention provides a communication interface without a highly reliable function and a communication having a highly reliable function. It is easy to convert to an interface. Therefore, the man-hours for designing a highly safe and highly available system can be reduced, and the system can be realized in a short period of time.

Next, a sixth embodiment showing a plant control system related to the bus interface device of each embodiment will be described. FIG. 14 is a configuration diagram illustrating a case where the bus interface device of each embodiment is applied to the plant control system 200.

An integrated circuit device 50 designed using the bus interface device of the present invention is mounted on one of the components constituting the controller 204.

In the plant control system 200 described in this embodiment, a controller 204 to which a sensor 301 (an example of a measuring device) and a valve 302 (an example of an operating device) is connected is connected to an HMI (human machine interface) via a control network 203. : Human Machine Interface) 202 and computer 201. Further, the HMI (202) and the computer 201 are connected to the plant management server 208 via the information network 209. Then, the plant management server 208 monitors the state of the plant and issues a command in the event of an abnormality or an emergency.

Further, the controller 204 constituting the plant control system 200 of this embodiment receives field data from the sensor 301, performs an operation on the controller 204, and then outputs a control command to the valve 302.

Therefore, the monitoring signal transmitted from the computer 201 to the controller 204 via the control network 203 is provided with a highly reliable interface by the highly reliable interface circuit from the integrated circuit device 50 of the controller 204. Then, a control command is output to the valve 302. For example, in the event of an emergency when a failure or abnormality occurs, a valve stop signal is transmitted to the valve 302 to keep the plant in a safe state.

According to this embodiment, when designing a system such as a plant composed of a controller or a computer, the bus interface device of each embodiment changes a communication interface having no highly reliable function into a communication interface having a highly reliable function. It will be easy to convert.
Therefore, the man-hours for designing a highly safe system can be reduced, and the system can be realized in a short period of time.

The control systems described in these examples can be used for various systems such as an elevator control system, a railroad control system, an automobile control system, a construction machine control system, and a power generation control system.

Further, the present invention is not limited to the above-described examples, and includes various modifications.
For example, the above-described embodiment describes the bus interface device in detail and concretely in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one having all the components described. It is also possible to replace some of the components of one embodiment with some of the components of another embodiment. It is also possible to add the constituent requirements of another embodiment to the constituent requirements of one embodiment. It is also possible to add, delete, or replace some of the other components with respect to some of the components of each embodiment.

1, 11, 12, 13, 15 ... IP with bus interface definition, 2, 21, 22, 23, 25 ... IP without bus interface definition, 3 ... Bus interface extraction unit, 4 ... Bus interface conversion generator, 5 ... High Reliable interface generator, 6 ... Bus interface, 7 ... Bus conversion circuit description, 8 ... Highly reliable interface circuit description, 9, 41, 42 ... Bus interface extraction template, 10, 46, 47, 48 ... Highly reliable interface generation template, 19, 29 ... IP database, 31, 32, 33 ... Highly reliable interface, 50, 61, 62 ... Integrated circuit device, 51, 54, 55, 58 ... IP, 52, 56, 59 ... Bus conversion circuit, 53, 57 , 60 ... Highly reliable interface circuit, 63, 64 ... Comparison and collation circuit, 65, 66 ... Majority decision circuit, 100 ... Railway signal control system, 101 ... Railway signal control controller, 102 ... Signal control unit, 103 ... Train position calculation unit, 200 ... plant control system, 201 ... computer, 202 ... HMI (human machine interface), 203 ... control network, 204 ... controller, 208 ... plant management server, 209 ... information network, 301 ... sensor, 302 ... valve

Claims

In a bus interface device that generates a bus interface that shows the input definition and output definition of an electronic device using IP, which is a design asset.
The bus interface is specified from each of the first IP including the definition of the bus interface and the second IP not including the definition of the bus interface, and the first bus interface and the second bus interface in the specified first IP are specified. A bus interface extractor that compares the correspondence of the second bus interface in IP and extracts the second bus interface that needs to be converted into an output signal and the corresponding first bus interface in order to satisfy a predetermined criterion. ,
A bus interface conversion generation unit that generates a bus conversion circuit description for converting an output signal of the second bus interface by using the extracted first bus interface and the second bus interface.
Using the extracted first bus interface and the second bus interface, the converted output signal is input to generate a highly reliable interface circuit description which is a bus interface satisfying the predetermined criteria. A bus interface device having an interface generator.
In the bus interface device according to claim 1,
The bus interface conversion generation unit is characterized in that the correspondence relationship between the signal lines of the first bus interface and the second bus interface is specified by using the bus interface extraction template for extracting the bus interface. Bus interface device.
In the bus interface device according to claim 1 or 2.
The high-reliability interface generation unit applies the high-reliability interface generation template showing the specifications of the high-reliability interface circuit description to the first bus interface corresponding to the extracted second bus interface to the high-reliability interface circuit. A bus interface device characterized by generating a description.
In the bus interface device according to claim 3,
The high-reliability interface generation unit is a bus interface device that performs pattern matching between the first bus interface and the high-reliability interface generation template.
In the bus interface device according to any one of claims 1 to 4.
The bus interface extraction unit is a bus interface device, characterized in that the specified second bus interface determines whether or not conversion of the output signal is necessary, and executes the extraction if necessary.
A bus conversion circuit according to the bus conversion circuit description generated by the bus interface conversion generation unit of the bus interface device according to any one of claims 1 to 5, and the high reliability generated by the bus interface conversion generation unit. An integrated circuit device characterized by having a highly reliable interface circuit according to an interface circuit description.
In the integrated circuit device according to claim 6.
A plurality of the bus conversion circuits according to the bus conversion circuit description,
A plurality of the highly reliable interface circuits according to the description of the highly reliable interface circuit, and a first comparison collation circuit for comparing the outputs of the plurality of bus conversion circuits.
An integrated circuit device comprising a second comparison and collation circuit for comparing the outputs of each of the plurality of highly reliable interface circuits.
In the integrated circuit device according to claim 7.
The plurality of bus conversion circuits and the plurality of highly reliable interface circuits are each composed of three or more.
A first majority decision circuit that collates the outputs of each of the plurality of bus conversion circuits with a majority vote,
An integrated circuit device comprising mounting the output of each of the plurality of highly reliable interface circuits as an integrated circuit device having a second majority decision circuit for majority voting.
A railway signal control system comprising the integrated circuit device according to claim 7 or 8 as a railway signal control controller.
A plant control system comprising the integrated circuit device according to claim 7 or 8 as a controller.