JP7163575B2 - Silicon carbide semiconductor substrate and method for manufacturing silicon carbide semiconductor substrate - Google Patents

Description

The present invention relates to a silicon carbide semiconductor substrate and a method for manufacturing a silicon carbide semiconductor substrate.

Conventionally, a single crystal SiC epitaxial substrate obtained by epitaxially growing a single crystal SiC (hereinafter, epitaxial may be abbreviated as epitaxial) on a single crystal SiC (silicon carbide) substrate has been used as a 1 kV class high voltage Schottky diode, Research and development has progressed as a high voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor: insulated gate field effect transistor) application, leading to practical use.

However, in order to realize an ultra-high breakdown voltage and low loss device of over 10 kV, it is necessary to fabricate a bipolar device that utilizes the conductivity modulation effect due to minority carrier injection based on the formation of a pn junction. A single-crystal SiC epitaxial substrate for such an ultra-high voltage device requires a drift layer with an extremely low dopant concentration of 1×10 ¹⁵ /cm ³ or less, and a thickness of several tens of μm. A thickness of several hundred μm is required. Bipolar devices include PN diodes, bipolar junction transistors (BJTs), and insulated gate bipolar transistors (IGBTs). Attention has been paid.

As a single crystal 4H-SiC bulk substrate for thick film epitaxial growth for manufacturing a single crystal 4H-SiC (four-layer periodic hexagonal silicon carbide) epitaxial substrate for a bipolar device having a pn junction, an n-type single crystal There are two options: 4H-SiC substrates and p-type single crystal 4H-SiC substrates. Relatively high-quality n-type 4H-SiC substrates are mass-produced, so they are easy to obtain, but when using n-type 4H-SiC substrates, p-type thick film epitaxial growth is required for the drift layer. . With this layer structure, the IGBT can be used as a p-channel IGBT (see, for example, Patent Document 1 below). However, thick-film epitaxial growth of low-concentration p-type 4H—SiC epitaxial film is greatly affected by the memory effect, and if the epitaxial growth layer is repeated many times, the doping controllability of the low-doped layer is significantly deteriorated. Therefore, it is difficult to control doping due to epitaxial growth, and the p-type 4H—SiC epitaxial film has a short lifetime.

On the other hand, for p-type 4H-SiC substrates, no mass production method for high-quality p-type 4H-SiC substrates has been established, and low-quality research-grade products with high micropipe density and high resistance are produced in small quantities. stay in the situation. Here, a micropipe is a congenital crystal defect contained in a "seed crystal" when manufacturing a SiC ingot, which is a raw material for manufacturing a SiC substrate, by crystal growth. For this reason, thick-film epitaxial growth of low-concentration n-type 4H—SiC epitaxial film is less affected by the memory effect, is easy to control doping, and has a long carrier lifetime. There is a problem that there is no high-quality p-type 4H-SiC substrate, and research and development of n-channel IGBTs is difficult.

In view of the above circumstances, a method has been disclosed in which an n-type 4H-SiC substrate, rather than a p-type 4H-SiC substrate, is used as a starting material for trial production of an n-channel IGBT (see, for example, the following non-patent document 1). In this method, after epitaxial growth of a thick n ⁻ -type drift layer on the Si surface of an n-type 4H-SiC substrate, a high impurity concentration p-type 4H-SiC epitaxial layer is formed as a substitute for the p-type 4H-SiC substrate. A MOS gate structure is formed on the C-plane side of the 4H-SiC substrate as a self-standing epitaxial substrate by epitaxially growing a thick film as a collector layer, removing the n-type 4H-SiC substrate by polishing, and inverting the preferential plane. is doing. Here, the free-standing epitaxial substrate is a substrate from which the substrate used as a starting material has been removed and whose shape is retained by the epitaxial film itself.

Further, an epitaxial layer having an impurity concentration of 1×10 ¹⁴ /cm ³ or more and 1×10 ¹⁶ /cm ³ or less is formed on a SiC substrate having an impurity concentration of 3×10 ¹⁸ /cm ³ or less, and the SiC substrate is There is a technique for manufacturing an epitaxial wafer by continuously removing all of the SiC substrate and part of the epitaxial layer from the side of the substrate, and manufacturing an n-channel IGBT from this epitaxial wafer (for example, Patent Document 2 below: reference).

Japanese Patent Application Laid-Open No. 2008-211178 JP 2012-253115 A

Xiaokun Wang and James A.M. Cooper, "High-Voltage n-Channel IGBTs on Free-Standing 4H-SiC Epilayers", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, No. 2, FEBRUARY 2010

An example of a method for manufacturing a single-crystal 4H--SiC self-standing epitaxial substrate for an n-channel IGBT will be described. 6 to 8 are cross-sectional views showing a state in the middle of manufacturing a conventional single crystal 4H--SiC self-supporting epitaxial substrate. First, as shown in FIG. 6, as the n-type silicon carbide substrate 5, an n-type 4H—SiC bulk substrate with a set film thickness of about 300 μm is used. An n ⁺ -type buffer layer 6 having a set thickness of about 15 μm and a set carrier concentration of greater than 1×10 ¹⁸ /cm ³ is formed on the Si surface of an n-type silicon carbide substrate 5 by epitaxial growth. The n ⁺ -type buffer layer 6 is, for example, a buffer layer for reducing basal plane dislocations (BPDs).

Next, on the surface of the n ⁺ -type buffer layer 6 opposite to the n-type silicon carbide substrate 5, the n ⁻ -type drift layer 1 is formed with a set carrier concentration of 2×10 ¹⁴ /cm ³ and a set film thickness of about 250 μm. epitaxially grown up to Next, as shown in FIG. 7, the n-type silicon carbide substrate 5 and the n ⁺ -type buffer layer 6 are removed by grinding and polishing.

Next, as shown in FIG. 8, an n ⁺ -type CS layer 4 is epitaxially grown on the C surface of the n ^- -type drift layer 1 at a set carrier concentration of 1.5×10 ¹⁶ /cm ³ to a set film thickness of about 2 μm. Let Next, p ⁺ -type collector layer 3 with a set thickness of about 0.5 μm is formed at a set carrier concentration of 1×10 ¹⁷ /cm ³ by ion implantation of p-type impurities into the Si surface of n ⁻ -type drift layer 1 . do. Thus, a single-crystal 4H--SiC self-standing epitaxial substrate for n-channel IGBT is completed. In addition to the p ⁺ -type collector layer 3, a p ⁺⁺ -type contact layer 15 having a set carrier concentration of 5×10 ¹⁸ /cm ³ to 3×10 ²⁰ /cm ³ and a set film thickness of about 0.05 to 50 μm is formed. You can However, it is necessary to form the p ⁺⁺ -type contact layer 15 closer to the substrate/air interface than the p ⁺ -type collector layer 3 .

However, in the single-crystal 4H--SiC self-supporting epitaxial substrate formed in this way, there is a problem that the p ⁺ -type collector layer 3 does not function. Specifically, a hole current does not flow in the p ⁺ -type collector layer 3, and the p-layer does not function. It is considered that the p ⁺ -type collector layer was deactivated due to scratches on the back side of the self-supporting epitaxial substrate generated during handling of the substrate during the device process and transportation by the automatic transportation system of the process equipment.

In order to solve the above-described problems of the prior art, the present invention provides a silicon carbide semiconductor substrate capable of preventing deactivation of the p ⁺ -type collector layer even if scratches occur on the back side of the self-supporting epitaxial substrate during device processing. and a method for manufacturing a silicon carbide semiconductor substrate.

In order to solve the above problems and achieve the object of the present invention, a silicon carbide semiconductor substrate according to the present invention has the following features. A silicon carbide semiconductor substrate includes a second semiconductor layer of a first conductivity type provided on one main surface of a first semiconductor layer of a first conductivity type and having a carrier concentration higher than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on a surface of a semiconductor layer opposite to the first semiconductor layer; a fifth semiconductor layer of the second conductivity type having a carrier concentration higher than that of the third semiconductor layer and provided on the opposite surface . Further, the total thickness of the second semiconductor layer and the third semiconductor layer is 1 μm or more, the first semiconductor layer is an epitaxial film, and the SORI is 200 μm or less . In this case, the total thickness of the second semiconductor layer, the third semiconductor layer and the fifth semiconductor layer is 1 μm or more.

Further, the silicon carbide semiconductor substrate according to the present invention further includes a first conductivity type fourth semiconductor layer having a carrier concentration higher than that of the first semiconductor layer and provided on the other main surface of the first semiconductor layer. It is characterized by

In the silicon carbide semiconductor substrate according to the present invention, the first semiconductor layer has a thickness of 5 to 500 μm, the second semiconductor layer has a thickness of 0.1 to 30 μm, and the third semiconductor layer has a thickness of 0.1 to 30 μm. The film thickness of the layer is 0.1 to 50 μm, and the film thickness of the fourth semiconductor layer is 0.5 to 30 μm.

In the silicon carbide semiconductor substrate according to the present invention, the first semiconductor layer has a carrier concentration of 1×10 ¹⁴ to 1×10 ¹⁵ /cm ³ , and the second semiconductor layer has a carrier concentration of 1×10 15 /cm 3 . ¹⁵ to 1×10 ¹⁸ /cm ³ , the carrier concentration of the third semiconductor layer is 1×10 ¹⁵ to 1×10 ²⁰ /cm ³ , and the carrier concentration of the fourth semiconductor layer is 1×10 ¹⁵ to 1×10 ¹⁸ /cm ³ .

Further, in the silicon carbide semiconductor substrate according to the present invention, the surface roughness Ra of one main surface and the other main surface of the first semiconductor layer is less than 1 nm, and the second semiconductor of the third semiconductor layer The surface roughness Ra of the surface opposite to the layer side is characterized by less than 5 nm.

Further, the silicon carbide semiconductor substrate according to the present invention is characterized by having a TTV of 50 μm or less .

Moreover, in order to solve the above problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor substrate according to the present invention has the following features. First, a first step of forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide substrate of a first conductivity type is performed. Next, a second step of removing the entire silicon carbide substrate is performed. In this second step, one main surface of the first semiconductor layer may be polished and CMP finished. Next, a third step of forming a first conductivity type second semiconductor layer having a carrier concentration higher than that of the first semiconductor layer on one main surface of the first semiconductor layer is performed. Next, a fourth step of forming a third semiconductor layer of the second conductivity type on the surface of the second semiconductor layer opposite to the first semiconductor layer is performed. Next, after the fourth step, a second conductive layer having a carrier concentration higher than that of the third semiconductor layer is formed on the surface opposite to the main surface of the first semiconductor layer and in contact with the third semiconductor layer. A fifth step of forming a fifth semiconductor layer of the mold is performed. Here, in the third step and the fourth step, the combined film thickness of the second semiconductor layer and the third semiconductor layer is formed to be 1 μm or more .

Further, in the method for manufacturing a silicon carbide semiconductor substrate according to the present invention, the silicon carbide substrate includes, on one main surface of the silicon carbide substrate, a sixth semiconductor of a first conductivity type having a carrier concentration higher than that of the silicon carbide substrate. a layer is provided, and in the first step, the first semiconductor layer is formed on the surface of the sixth semiconductor layer opposite to the silicon carbide substrate side; It is characterized by removing all of the silicon substrate and all of the sixth semiconductor layer.

Further, in the method for manufacturing a silicon carbide semiconductor substrate according to the present invention, after the fourth step, the other main surface of the first semiconductor layer is polished and CMP-finished, and then the other main surface of the first semiconductor layer is finished. The method further includes forming a fourth semiconductor layer of a first conductivity type having a carrier concentration higher than that of the first semiconductor layer.

According to the invention described above, the total thickness of the n ⁺ -type FS layer (second semiconductor layer) and the p ⁺ -type collector layer (third semiconductor layer) is 1 μm or more. As a result, even if scratches occur on the back side of the self-standing epitaxial substrate due to handling of the substrate during the device process, transportation by an automatic transportation system of the process equipment, etc., the n ⁺ type FS layer and the p ⁺ type collector layer are sufficiently scratched. This thickness prevents scratches from reaching the n ^- -type drift layer (first semiconductor layer), thereby preventing deactivation of the p ⁺ -type collector layer. Therefore, the silicon carbide semiconductor substrate of the present invention can prevent deterioration of device characteristics due to leakage defects caused by deactivation of the p ⁺ -type collector layer.

According to the silicon carbide semiconductor substrate and the method for manufacturing a silicon carbide semiconductor substrate according to the present invention, even if scratches occur on the back side of the single-crystal 4H—SiC self-supporting epitaxial substrate for n-channel IGBT during the device process, p ⁺ This has the effect of preventing deactivation of the type collector layer.

1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor substrate according to an embodiment; FIG. 1 is a cross-sectional view showing a state in the middle of manufacturing a silicon carbide semiconductor substrate according to an embodiment (No. 1); FIG. FIG. 12 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor substrate according to the embodiment (No. 2); FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the silicon carbide semiconductor substrate according to the embodiment (No. 3); 1 is a cross-sectional view showing the configuration of an n-channel IGBT using a silicon carbide semiconductor substrate according to an embodiment; FIG. 1 is a cross-sectional view showing a state in the middle of manufacturing a conventional single-crystal 4H—SiC self-supporting epitaxial substrate (No. 1); FIG. FIG. 2 is a cross-sectional view showing a state in the middle of manufacturing a conventional single-crystal 4H—SiC self-supporting epitaxial substrate (No. 2); FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing a conventional single-crystal 4H—SiC self-supporting epitaxial substrate (No. 3);

Preferred embodiments of a silicon carbide semiconductor substrate and a method for manufacturing a silicon carbide semiconductor substrate according to the present invention will be described below in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted.

(Embodiment)
FIG. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor substrate according to an embodiment. The silicon carbide semiconductor substrate in FIG. 1 is, for example, a single-crystal 4H—SiC self-supporting epitaxial substrate for an ultra-high breakdown voltage n-channel IGBT. The silicon carbide semiconductor substrate has an n ⁺ type FS (Field Stop) layer 2 (first conductivity type second semiconductor layer) on the C plane of an n ⁻ type drift layer 1 (first conductivity type first semiconductor layer). be provided. In addition, a p ⁺ type collector layer 3 (second conductivity type third semiconductor layer) is provided on the surface of the n ⁺ type FS layer 2 opposite to the n ⁻ type drift layer 1, and the Si surface of the n ⁻ type drift layer 1 is provided. An n ⁺ type CS (Carrier Storage) layer 4 (first conductivity type fourth semiconductor layer) is provided thereon. Also, the n ⁺ type FS layer 2 may be provided on the Si surface of the n ⁻ type drift layer 1 and the n ⁺ type CS layer 4 may be provided on the C surface of the n ⁻ type drift layer 1 .

The n ⁻ -type drift layer 1 is a layer formed by epitaxial growth on the n-type silicon carbide substrate with an impurity concentration lower than that of the removed n-type silicon carbide substrate in the state of FIG. 1, as described later in the explanation of the manufacturing method. is. For example, the n ⁻ -type drift layer 1 has a set film thickness of 5 to 500 μm and a set carrier concentration of 1×10 ¹⁴ /cm ³ to 1×10 ¹⁵ /cm ³ . Here, the carrier concentration is the net concentration obtained by taking the difference between the n-type impurity and the p-type impurity contained in the n ⁻ -type drift layer 1 . Both the C surface and the Si surface of the n ⁻ -type drift layer 1 are flattened by CMP (Chemical Mechanical Polishing), and both have a surface roughness Ra of less than 1 nm. Here, the surface roughness Ra is the arithmetic mean roughness (Ra) of the surface. The surface opposite ^to the surface on which the n ⁺ type FS layer ² is epitaxially grown is the surface on which the n ⁺ type CS layer 4 is formed ^. CMP finishing may be performed after the layer 3 is deposited. Alternatively, the p ⁺⁺ -type contact layer 15 may be deposited after the p ⁺ -type collector layer 3 is deposited.

The n ⁺ -type FS layer 2 is a layer provided with an impurity concentration higher than that of the n ⁻ -type drift layer 1 . Since the n ⁺ -type FS layer 2 suppresses the depletion layer extending into the high-resistance n ^- -type drift layer 1 when turned off, punch-through can be prevented even if the n ^- -type drift layer 1 is made thin. The n ⁺ -type FS layer 2 has a set film thickness of 0.1 to 30 μm and a set carrier concentration of 1×10 ¹⁵ /cm ³ to 1×10 ¹⁸ /cm ³ . Note that the n ⁺ -type FS layer 2 may be a single layer or a multilayer. good.

The p ⁺ -type collector layer 3 has a set film thickness of 0.1 to 50 μm and a set carrier concentration of 1×10 ¹⁵ /cm ³ to 1×10 ²⁰ /cm ³ . The surface of the p ⁺ -type collector layer 3 opposite to the n ⁺ -type FS layer 2 is at least mirror-finished so that the surface is planarized, and the surface roughness Ra is 1 to less than 5 nm. The surface may also be flattened by CMP finishing, in which case the surface roughness Ra is less than 1 nm. Note that the p ⁺ -type collector layer 3 may be a single layer or a multilayer. good.

Here, the n ⁺ type FS layer ² and the p ⁺ type collector layer 3 each have a set film thickness of 0.1 to 50 μm ^. The film thickness is 1 μm or more. For example, when the n ⁺ -type FS layer 2 is 0.1 μm, the p ⁺ -type collector layer 3 is made larger than 0.9 μm. As a result, the thickness of the n ⁺ type FS layer 2 and the p ⁺ type collector layer 3 is increased, so even if the p ⁺ type collector layer 3 is scratched, the p ⁺ type collector layer 3 is prevented from being deactivated. can. Further, when the p ⁺⁺ -type contact layer 15 is provided, the total thickness of the n ⁺ -type FS layer 2, the p ⁺ -type collector layer 3, and the p ⁺⁺ -type contact layer 15 is preferably 1 μm or more. .

The n ⁺ -type CS layer 4 is a layer provided with an impurity concentration higher than that of the n ⁻ -type drift layer 1 . By providing the n ⁺ -type CS layer 4 on the front surface side of the n ^- -type drift layer 1, the JFET (Junction FET) resistance can be reduced, and the on-resistance can be reduced. The n ⁺ -type CS layer 4 has a set film thickness of 0.5 to 30 μm and a set carrier concentration of 1×10 ¹⁵ /cm ³ to 1×10 ¹⁸ /cm ³ . Further, after the n ⁺ -type CS layer 4 is formed, the surface opposite to the n ⁻ -type drift layer 1 does not need to be polished. Further, the surface opposite to the n ⁻ type drift layer 1 may be planarized by performing CMP processing, and in this case the surface roughness Ra is less than 1 nm. Although the n ⁺ type CS layer 4 is formed in FIG. 1, the n ⁺ type CS layer 4 may not be formed.

Further, it is preferable that the silicon carbide semiconductor substrate has a TTV (Total Thickness Variation) of 50 μm or less and a SORI (warp) of 200 μm or less.

(Manufacturing method of silicon carbide semiconductor substrate according to embodiment)
Next, a method for manufacturing a silicon carbide semiconductor substrate according to an embodiment will be described. 2 to 4 are cross-sectional views showing states in the process of manufacturing the silicon carbide semiconductor substrate according to the embodiment. First, as a substrate for growth of a silicon carbide semiconductor substrate, a semiconductor substrate is prepared in which an n ⁺ type buffer layer 6 is formed on an n type silicon carbide substrate 5 which is a single crystal 4H—SiC substrate. The n ^- type silicon carbide substrate 5 has, for example, a 4-inch diameter with a residual thickness of 367 μm, and the Si surface is subjected to CMP finishing. It is formed at a concentration of 1×10 ¹⁸ /cm ³ . The n ⁺ -type buffer layer 6 is, for example, a buffer layer for reducing basal plane dislocations and carrot defects.

Next, on the n ⁺ -type buffer layer 6, the n ⁻ -type drift layer 1 is epitaxially grown at a set carrier concentration to a set film thickness of, for example, 275 μm. After that, the protrusions on the Si surface of the n ⁺ -type buffer layer 6 are removed, and the semiconductor substrate is hollowed out to a predetermined diameter by, for example, a YAG (Yttrium Aluminum Garnet) laser (fundamental wave). Here, the hollowing process is a process of removing the peripheral portion and leaving only the central portion. After that, the orientation flat is re-formed by grinding, and the diameter of the semiconductor substrate is adjusted within the SEMI (Semiconductor Equipment and Materials International) standard range or the JEITA (Japan Electronics and Information Technology Industries Association) standard range. The state up to this point is described in FIG.

Next, the n-type silicon carbide substrate 5 and the n ⁺ -type buffer layer 6 are all removed and part of the n ^- -type drift layer 1 is removed by processes such as polishing, grinding, and etching. After that, the exposed C-plane of the n ⁻ -type drift layer 1 is subjected to CMP finishing by grinding and polishing. For example, 384 μm is ground and 1 μm is polished by CMP finishing. In this case, the n ⁻ type drift layer 1 is ground by 9 μm and polished by 1 μm, so that the film thickness of the n ⁻ type drift layer 1 is 265 μm. After that, laser marking is performed on the semiconductor substrate to indicate the C plane. The edge of the substrate is beveled to form a bevel (inclination). For example, the bevel shape is an R (round) shape, but it may be a tapered shape, and any combination of the R shape and the tapered shape may be used. The state up to this point is described in FIG. Note that the shape of the end portion of the substrate is omitted in FIG.

Next, the n ⁺ -type FS layer 2 is epitaxially grown on the C-plane of the n ^- -type drift layer 1 at a set carrier concentration to a set film thickness of, for example, 10 μm. Next, on the surface of the n ⁺ -type FS layer 2 opposite to the n ⁻ -type drift layer 1, the p ⁺ -type collector layer 3 is epitaxially grown at a set carrier concentration to a set film thickness of, for example, 20 μm. Next, the Si surface of the n ^- -type drift layer 1 is subjected to pre-grinding or pre-polishing, and then subjected to CMP processing. Here, when the bevel shape is an R shape, the end portion of the substrate may be beveled again to add a tapered shape. The state up to this point is described in FIG. Note that the shape of the end portion of the substrate is omitted in FIG.

Next, on the Si surface of the n ^- -type drift layer 1, the n ⁺ -type CS layer 4 is epitaxially grown at a set carrier concentration to a set film thickness of, for example, 2 μm. Next, the p ⁺ -type collector layer 3 is ground until it has a set film thickness of, for example, 6 μm, and the C surface of the p ⁺ -type collector layer 3 is mirror-finished. Thereby, the silicon carbide semiconductor substrate shown in FIG. 1 is completed. The remaining thickness, TTV, SORI, etc. are measured as the final substrate shape.

In the manufacturing method described above, the n ⁺ type FS layer 2 is formed on the C surface of the n ⁻ type drift layer 1 and the n ⁺ type CS layer 4 is formed on the Si surface of the n ⁻ type drift layer 1 . However, the n ⁺ type FS layer 2 may be formed on the Si surface of the n ⁻ type drift layer 1 and the n ⁺ type CS layer 4 may be formed on the C surface of the n ⁻ type drift layer 1 . Alternatively, the p ⁺⁺ -type contact layer 15 may be deposited after the p ⁺ -type collector layer 3 is deposited.

Here, FIG. 5 is a cross-sectional view showing the configuration of the n-channel IGBT using the silicon carbide semiconductor substrate according to the embodiment. A method of manufacturing the n-channel IGBT of FIG. 5 from the silicon carbide semiconductor substrate manufactured as described above will be described. First, the n ⁻ -type drift layer 1 and the n ⁺ -type CS layer 4 are deposited by epitaxial growth. Also, an ion implantation mask is formed on the surface of the n ⁺ -type CS layer 4 with openings corresponding to the formation regions of the JFET regions 8 . Next, using this ion implantation mask as a mask, p ⁺ -type base layer 7 and JFET region 8 are formed by p-type impurity ion implantation. Next, the ion implantation mask is removed.

Next, an ion implantation mask having an opening corresponding to the formation region of the n ⁺ -type emitter region 9 is formed. Using this ion implantation mask as a mask, n-type impurity ions are implanted to form an n ⁺ -type emitter region 9 in the surface layer of the p ⁺ -type base layer 7 . Next, the ion implantation mask is removed. Next, an ion implantation mask having openings corresponding to regions where the p ⁺⁺ -type contact regions 10 are to be formed is formed. Using this ion implantation mask as a mask, p-type impurity ions are implanted to form a p ⁺⁺ -type contact region 10 in the surface layer of the p ⁺ -type base layer 7 . Next, the ion implantation mask is removed.

The order of ion implantation for forming the n ⁺ -type emitter region 9 and the p ⁺⁺ -type contact region 10 described above can be changed in various ways. Next, activation annealing (heat treatment) is performed to activate the diffusion regions formed by each ion implantation. Next, the front surface (the surface on the p ⁺ -type base layer 7 side) is thermally oxidized to form the gate insulating film 11 . Next, for example, a polycrystalline silicon (poly-Si) layer is formed as the gate electrode 12 on the gate insulating film 11 and patterned.

Next, an interlayer insulating film 13 is formed to cover the gate electrode 12, patterned, and then subjected to heat treatment (reflow). When the interlayer insulating film 13 is patterned, a contact hole is formed and the gate insulating film 11 exposed in the contact hole is also removed to expose the n ⁺ -type emitter region 9 and the p ⁺⁺ -type contact region 10 . Next, an emitter electrode 14 is formed by, for example, a sputtering method so as to fill the contact hole. Next, a passivation protective film is formed on the front surface (the surface on the p ⁺ -type base layer 7 side). Thereafter, the IGBT shown in FIG. 5 is completed by cutting (dicing) the substrate into chips.

As described above, according to the embodiment, the total thickness of at least the n ⁺ -type CS layer and the p ⁺ -type collector layer is 1 μm or more. As a result, even if scratches occur on the back side of the self-standing epitaxial substrate due to handling of the substrate during the device process, transportation by an automatic transportation system of the process equipment, etc., the n ⁺ type FS layer and the p ⁺ type collector layer are sufficiently scratched. Since it has a sufficient thickness, deactivation of the p ⁺ -type collector layer can be prevented. Therefore, the silicon carbide semiconductor substrate of the embodiment can prevent deterioration of device characteristics due to leak failure caused by deactivation of the p ⁺ -type collector layer.

As described above, the present invention can be modified in various ways without departing from the gist of the present invention.

INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor substrate and the method for manufacturing a silicon carbide semiconductor substrate according to the present invention are useful for power semiconductor devices used in power converters and power supply devices for various industrial machines. Suitable for silicon carbide semiconductor substrates for n-channel IGBTs.

1 n ⁻ type drift layer 2 n ⁺ type FS layer 3 p ⁺ type collector layer 4 n ⁺ type CS layer 5 n type silicon carbide substrate 6 n ⁺ type buffer layer 7 p ⁺ type base layer 8 JFET region 9 n ⁺ type emitter Region 10 p ⁺⁺ type contact region 11 gate insulating film 12 gate electrode 13 interlayer insulating film 14 emitter electrode 15 p ⁺⁺ type contact layer

Claims (10)

a second semiconductor layer of the first conductivity type provided on one main surface of the first semiconductor layer of the first conductivity type and having a carrier concentration higher than that of the first semiconductor layer;
a third semiconductor layer of a second conductivity type provided on a surface of the second semiconductor layer opposite to the first semiconductor layer;
a second conductivity type fifth semiconductor layer having a carrier concentration higher than that of the third semiconductor layer and provided on the surface of the third semiconductor layer opposite to the first semiconductor layer;
wherein the total thickness of the second semiconductor layer and the third semiconductor layer is 1 μm or more, the first semiconductor layer is an epitaxial film, and the SORI is 200 μm or less. A silicon carbide semiconductor substrate. 2. The carbonization according to claim 1, further comprising a fourth semiconductor layer of the first conductivity type having a carrier concentration higher than that of the first semiconductor layer and provided on the other main surface of the first semiconductor layer. Silicon semiconductor substrate. 3. The silicon carbide semiconductor substrate according to claim 2, wherein a total thickness of said second semiconductor layer, said third semiconductor layer and said fifth semiconductor layer is 1 [mu]m or more. The film thickness of the first semiconductor layer is 5 to 500 μm,
The film thickness of the second semiconductor layer is 0.1 to 30 μm,
The film thickness of the third semiconductor layer is 0.1 to 50 μm,
The film thickness of the fourth semiconductor layer is 0.5 to 30 μm,
4. The silicon carbide semiconductor substrate according to claim 2, wherein said fifth semiconductor layer has a film thickness of 0.05 to 50 μm. carrier concentration of the first semiconductor layer is 1×10 ¹⁴ to 1×10 ¹⁵ /cm ³ ;
the second semiconductor layer has a carrier concentration of 1×10 ¹⁵ to 1×10 ¹⁸ /cm ³ ;
carrier concentration of the third semiconductor layer is 1×10 ¹⁵ to 1×10 ²⁰ /cm ³ ;
carrier concentration of the fourth semiconductor layer is 1×10 ¹⁵ to 1×10 ¹⁸ /cm ³ ;
5. The silicon carbide semiconductor substrate according to claim 2, wherein said fifth semiconductor layer has a carrier concentration of 5×10 ¹⁸ to 3×10 ²⁰ /cm ³ . The surface roughness Ra of one main surface and the other main surface of the first semiconductor layer is less than 1 nm,
The carbonization according to any one of claims 1 to 5, wherein the surface roughness Ra of the surface of the third semiconductor layer opposite to the second semiconductor layer is less than 5 nm. Silicon semiconductor substrate. 6. The silicon carbide semiconductor substrate according to claim 1 , wherein TTV is 50 μm or less . a first step of forming a first conductivity type first semiconductor layer on a front surface of a first conductivity type silicon carbide substrate;
a second step of removing all of the silicon carbide substrate;
a third step of forming a second semiconductor layer of a first conductivity type having a carrier concentration higher than that of the first semiconductor layer on one main surface of the first semiconductor layer;
a fourth step of forming a third semiconductor layer of a second conductivity type on the surface of the second semiconductor layer opposite to the first semiconductor layer;
After the fourth step, a second conductivity type second conductive layer having a carrier concentration higher than that of the third semiconductor layer is formed on the surface of the first semiconductor layer opposite to the main surface and in contact with the third semiconductor layer. a fifth step of forming five semiconductor layers;
and forming a total thickness of the second semiconductor layer and the third semiconductor layer to be 1 μm or more in the third step and the fourth step. . The silicon carbide substrate is provided with a sixth semiconductor layer of a first conductivity type having a carrier concentration higher than that of the silicon carbide substrate on one main surface of the silicon carbide substrate,
In the first step, the first semiconductor layer is formed on the surface of the sixth semiconductor layer opposite to the silicon carbide substrate side,
9. The method of manufacturing a silicon carbide semiconductor substrate according to claim 8, wherein in said second step, all of said silicon carbide substrate and all of said sixth semiconductor layer are removed. After the fourth step,
After polishing and CMP finishing the other main surface of the first semiconductor layer, a fourth semiconductor layer of a first conductivity type having a carrier concentration higher than that of the first semiconductor layer is formed on the other main surface of the first semiconductor layer. 10. The method of manufacturing a silicon carbide semiconductor substrate according to claim 8, further comprising the step of forming a .

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