JP7150237B2 - Gate drive circuits for semiconductor switching devices - Google Patents

Description

The present invention relates to a gate drive circuit for a semiconductor switching element for driving a high-frequency voltage-controlled semiconductor switching element such as a GaN transistor or a MOSFET.

For example, a switching power supply device disclosed in Patent Document 1 below includes a switching transformer and a switching circuit that outputs a switching pulse to the switching transformer. Also, the switching circuit has a switching element, an oscillation circuit that outputs a drive signal for the switching element, and a switching control circuit that controls continuation/stop of the switching operation of the switching element.

In the normal mode of the switching power supply, the switching circuit continuously performs the switching operation of the switching element, and the switching circuit continuously outputs switching pulses of a predetermined frequency to the primary winding of the switching transformer. As a result, a switching voltage is continuously output from the secondary winding of the switching transformer, the switching voltage is rectified and smoothed, and supplied to the load as a DC voltage.

On the other hand, in the standby mode of the switching power supply, in the switching circuit, the switching operation of the switching element is stopped for a certain period of time at regular intervals. For this reason, a switching pulse of a predetermined frequency is output from the switching circuit to the primary winding of the switching transformer for a predetermined period at regular intervals. That is, the switching circuit is controlled so that the number of times of switching is reduced and the burst state is achieved. A switching voltage is output from the secondary winding of the switching transformer for a predetermined period at regular intervals, and this switching voltage is rectified and smoothed and supplied to the load as a DC voltage (triangular wave voltage).

Japanese Patent Application Laid-Open No. 2009-207289 (pages 4-5, FIG. 1-2)

By the way, in recent years, the switching frequency when switching the switching element of the switching power supply at a predetermined frequency (constant switching frequency) has progressed, and a higher frequency band (HF band (3 MHz to 30 MHz) or VHF band (30 MHz to Switching at 300 MHz)) is becoming desirable.

In this case, it is essential to realize a drive circuit that can stably output such a high-frequency drive signal (drive pulse) to the switching element. Accordingly, the inventors of the present application considered configuring a drive circuit using a self-excited LC oscillator circuit, and used a Colpitts oscillator circuit or a Hartley oscillator circuit, which are well known as self-excited LC oscillator circuits, to achieve this. I tried to realize the drive circuit.

Voltage-controlled semiconductor switching elements for high frequencies, such as GaN transistors and MOSFETs, are suitable as switching elements for switching at such high-frequency band switching frequencies. A gate-to-source capacitance exists, and this gate-to-source capacitance changes according to the operating state of the semiconductor switching element (for example, according to fluctuations in the drain-to-source voltage).

Therefore, a drive circuit configured using a Colpitts oscillation circuit or a Hartley oscillation circuit has a problem that the self-oscillation frequency changes due to the influence of the change in the capacitance between the gate and the source, which is a load. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. It is a main object of the present invention to provide a gate drive circuit for a semiconductor switching element that can stably generate and output to the gate terminal of the semiconductor switching element.

In order to achieve the above object, the present invention provides a semiconductor switching element gate drive circuit for driving a semiconductor switching element, the transistor having a drain terminal or a collector terminal connected to a power supply voltage. a first capacitor and a first inductor connected in series between a gate or base terminal of said transistor element and a reference potential; said gate or base terminal and a source terminal of said transistor element; a Clapp oscillation circuit comprising a second capacitor connected between an emitter terminal and a third capacitor connected between the source terminal or the emitter terminal and the reference potential; and a Clapp oscillation circuit connected in parallel to the third capacitor. an input inductor having one end connected to the source terminal or the emitter terminal; a saturable core connected between the other end of the input inductor and the reference potential; and the saturable core a ferroresonant circuit configured with an output capacitor connected in parallel, wherein an alternating signal generated between the source terminal or the emitter terminal and the reference potential is amplitude-amplified by the ferroresonant circuit. It is output as a drive signal to the semiconductor switching element.

According to this gate drive circuit for a semiconductor switching element, since the third capacitor of the Clapp oscillation circuit is connected in parallel with the gate-source capacitance of the semiconductor switching element, the capacitance is sufficiently large with respect to the gate-source capacitance. By using the third capacitor with the same value, even if the gate-source capacitance changes, the parallel combined capacitance value of the third capacitor and the gate-source capacitance can be kept almost unchanged. In other words, according to this semiconductor switching device gate drive circuit, even if the gate-source capacitance changes, the self-oscillation frequency can be kept almost unchanged. It is possible to stably generate an AC signal and output it between the gate and source of the semiconductor switching element as a drive signal, thereby stably switching the semiconductor switching element at this constant frequency.

Further, according to this gate drive circuit for a semiconductor switching element, since the second inductor is connected in parallel with the third capacitor, even if the capacitance value of the third capacitor is as large as described above, the second inductor Since the combined impedance of the parallel circuit of the and third capacitors can be maintained at a sufficient value, it is possible to generate an AC signal with sufficient amplitude and output a drive signal with sufficient amplitude between the gate and source of the semiconductor switching element. can.

Further, according to this gate drive circuit for a semiconductor switching element, for example, even when the power supply voltage supplied to the drain terminal or the collector terminal of the transistor element is low and therefore the amplitude of the AC signal is also small, the ferroresonant circuit can amplify the amplitude of this AC signal and output it as a drive signal, so it is possible to output a drive signal with sufficient amplitude between the gate and source of the semiconductor switching element to switch the semiconductor switching element at a constant frequency. can be done.

In the semiconductor switching element gate drive circuit according to the present invention, the saturable magnetic core has a primary winding connected to the source terminal or the emitter terminal side and a secondary winding connected to the semiconductor switching element side. It is configured in a two-winding structure with.

According to this gate drive circuit for a semiconductor switching element, the number of turns of the secondary winding is greater than that of the primary winding, so that it can be compared with a ferroresonant circuit having a saturable core composed of a single winding. , the AC signal can be amplitude-amplified into a drive signal with a larger amplification factor and output between the gate and source of the semiconductor switching element.

In the semiconductor switching element gate drive circuit according to the present invention, the input inductor is composed of the leakage inductance of the saturable magnetic core.

According to this semiconductor switching element gate drive circuit, the leakage inductance of the primary winding that constitutes the ferroresonant circuit can be substituted for the input inductor, thereby avoiding signal attenuation due to the resistance component present in the input inductor. Therefore, a driving signal having a larger amplitude can be output between the gate and source of the semiconductor switching element.

According to the present invention, because of the configuration including the Clapp oscillation circuit, even if the capacitance between the gate and the source of the semiconductor switching element changes, the self-excited oscillation frequency can be kept almost unchanged. It is possible to stably generate an AC signal at the included constant frequency and output it as a drive signal between the gate and source of the semiconductor switching element to stably switch the semiconductor switching element at this constant frequency.

1 is a configuration diagram showing a configuration of a semiconductor switching element gate drive circuit 1A; FIG. 1 is a configuration diagram showing a configuration of a semiconductor switching element gate drive circuit 1B; FIG. 1 is a configuration diagram showing a configuration of a semiconductor switching element gate drive circuit 1C; FIG. 1 is a configuration diagram showing a configuration of a semiconductor switching element gate drive circuit 1D; FIG. 1 is a configuration diagram showing a configuration of a semiconductor switching element gate drive circuit 1E; FIG.

Embodiments of a gate drive circuit for a semiconductor switching element will be described below with reference to the accompanying drawings.

First, the configuration of a semiconductor switching element gate drive circuit (hereinafter also referred to as a gate drive circuit) 1A as a semiconductor switching element gate drive circuit will be described with reference to the drawings, and the operation will also be described.

As shown in FIG. 1, the gate drive circuit 1A includes a Clapp oscillation circuit 2A and an inductor (second inductor) 3 to generate an AC signal S1 (AC voltage signal) with a constant frequency f, and to generate an AC signal S1 (AC voltage signal). can be output as a drive signal Vdv to a semiconductor switching element 51 (a high-frequency voltage-controlled semiconductor switching element such as a GaN transistor or a MOSFET) connected to the output terminals 4a and 4b.

The Clapp oscillation circuit 2A includes a transistor element 11, a first capacitor 12, a first inductor 13, a second capacitor 14, a third capacitor 15, and a bias circuit 16.

The transistor element 11 is a field effect transistor (FET) as an example in this example, but may be a bipolar transistor. When the transistor element 11 is a bipolar transistor, the gate terminal (control terminal), drain terminal (input terminal) and source terminal (output terminal) are respectively connected to the base terminal (control terminal), collector terminal (input terminal) and emitter terminal. (output terminal). The transistor element 11, which is an n-channel FET, has a drain terminal connected to a power supply voltage Vdd (positive voltage) and a source terminal connected to the output terminal 4a.

The first capacitor 12 (capacitance value C1) and the first inductor 13 (inductance value L1) are connected in series between the gate terminal of the transistor element 11 and the reference potential portion (ground GND). there is Note that the order of series connection of the first capacitor 12 and the first inductor 13 may be reversed from the order shown in FIG. A second capacitor 14 (capacitance value C2) is connected between the gate terminal and the source terminal of the transistor element 11 . The third capacitor 15 (capacitance value C3) is connected between the source terminal of the transistor element 11 and the ground GND.

The bias circuit 16 includes an inductor 16a having one end connected to the gate terminal of the transistor element 11, and a bias power supply 16b connected between the other end of the inductor 16a and the ground GND. A bias voltage (DC voltage) for excitation operation is applied to the gate terminal (between the gate and the source) of the transistor element 11 . During the self-oscillation operation of the Clapp oscillation circuit 2A, another AC signal having the same frequency as the AC signal S1 having the constant frequency f is generated at the gate terminal of the transistor element 11. FIG. Therefore, the inductor 16a having a high impedance at the frequency f is provided to separate the gate terminal of the transistor element 11 and the bias power supply 16b in terms of alternating current. Also, the bias power supply 16b can be composed of a variable power supply that can change the bias voltage as shown in FIG. 1, or can be composed of a fixed power supply that outputs a known voltage when the applied bias voltage is known. may

The Clapp oscillation circuit 2A configured as described above self-oscillates at a constant frequency f to generate an AC signal S1 at the source terminal of the transistor element 11. The AC signal S1 is connected to the ground GND. A driving signal Vdv based on the potential of the output terminal 4b (reference potential) is output to the output terminal 4a (that is, between the output terminals 4a and 4b). In this case, since the Clapp oscillation circuit 2A is constructed as a grounded drain type, it outputs the AC signal S1 to the source terminal with a low output impedance. In this Clapp oscillation circuit 2A, the frequency f is represented by the following equation (1). In this gate drive circuit 1A, the capacitance value C1, the inductance value L1, the capacitance value C2 and the capacitance value C3 is defined.
f=(1/2π)×√{(1/L1)×(1/C1+1/C2+1/C3)} (1)

The inductor 3 is connected in parallel with the third capacitor 15 . The inductor 3 has a function of connecting (short-circuiting) the source terminal of the transistor element 11 to the ground GND at low impedance in terms of direct current and high impedance in terms of alternating current. Therefore, the AC signal S1 is generated at the source terminal of the transistor element 11 without a DC component. As a result, it is possible to omit a coupling capacitor for DC component removal which is normally connected between the source terminal of the transistor element 11 and the semiconductor switching element 51 .

In this gate drive circuit 1A, as shown in FIG. 1, the source terminal of the transistor element 11 is directly connected to the gate terminal of the semiconductor switching element 51 to be driven through the output terminal 4a. Also, the semiconductor switching element 51 has its source terminal set to the same potential as the ground GND. In addition, the semiconductor switching element 51 of this type has a gate-source capacitance Cgs, and the gate-source capacitance Cgs varies depending on the operating state of the semiconductor switching element 51 (for example, between the drain and the source). It has the characteristic that its capacitance value changes according to voltage fluctuations.

For the gate drive circuit 1A, this gate-source capacitance Cgs is the first factor of the Clapp oscillation circuit 2A whose capacitance value C3 is one element that defines the frequency f, as shown in the above equation (1). 3 is a capacitor connected in parallel with the capacitor 15 . Therefore, in the gate drive circuit 1A, by using this configuration, the third capacitor 15 having a large capacitance value C3 (sufficiently large capacitance value with respect to the capacitance Cgs between the gate and source) is used, thereby Even if the capacitance Cgs between the gate and the source changes, the parallel combined capacitance value of the third capacitor 15 and the capacitance between the gate and the source Cgs hardly changes (that is, even if the capacitance between the gate and the source Cgs changes, the frequency f (Self-oscillation frequency) is kept almost unchanged).

As a result, according to the gate drive circuit 1A, the alternating current is generated at the constant frequency f (frequency included in the high frequency band) shown by the above equation (1) without being affected by the change in the gate-source capacitance Cgs. By stably generating the signal S1 and outputting it between the gate and source of the semiconductor switching element 51 as the drive signal Vdv, the semiconductor switching element 51 can be stably switched at a constant frequency f.

Also, in this gate drive circuit 1A, the inductor 3 is connected in parallel with the third capacitor 15 (that is, connected between the source terminal of the transistor element 11 and the ground GND). Therefore, according to this gate drive circuit 1A, even if the capacitance value C3 of the third capacitor 15 is as large as described above (even if the impedance of the third capacitor 15 alone at the frequency f becomes low) , the combined impedance of the parallel circuit of the inductor 3 and the third capacitor 15 can be maintained at a sufficient value. Can be output between sources.

The gate drive circuit is not limited to the gate drive circuit 1A described above. For example, like the gate drive circuit 1B shown in FIG. 2, a dual-gate MOSFET can be used as the transistor element 11 to configure the Clapp oscillation circuit 2B. The gate drive circuit 1B will be described below. The same reference numerals are assigned to the same configurations as those of the gate drive circuit 1A, and overlapping descriptions are omitted.

As shown in FIG. 2, the gate drive circuit 1B includes a Clapp oscillation circuit 2B and an inductor 3 to generate an AC signal S1 having a constant frequency f, and to drive the semiconductor switching element 51 using the AC signal S1 as a drive signal Vdv. It is configured to be able to output to

The Clapp oscillation circuit 2B includes, as an example, a transistor element 11 configured by an enhancement-type dual-gate MOSFET, and similarly to the Clapp oscillation circuit 2A, a first capacitor 12, a first inductor 13, a second capacitor 14, a second 3 A capacitor 15 and a bias circuit 16 are provided. The Clapp oscillation circuit 2B further includes a fourth capacitor 17 and another bias circuit 18. As shown in FIG.

In the enhancement type dual gate MOSFET, one gate terminal G1 of the two gate terminals G1 and G2 is used as the gate terminal in the Clapp oscillation circuit 2A, and the other gate terminal G2 is used as the source terminal in the AC manner. connected to Thus, in this dual-gate MOSFET, two internal MOSFETs (not shown) are cascode-connected. In order to operate this dual-gate MOSFET, a bias voltage is applied to the other gate terminal G2.

In the Clapp oscillation circuit 2B of this example, the fourth capacitor 17 is connected to the other gate terminal G2 and the source terminal, and the other gate terminal G2 is AC-connected to the source terminal. Another bias voltage is applied from another bias circuit 18 to the other gate terminal G2. Another bias circuit 18 comprises a resistor 18a having one end connected to the gate terminal G2 of the transistor element 11, and another bias power source 18b connected between the other end of the resistor 18a and the ground GND. to apply a bias voltage to the gate terminal G2.

Since one gate terminal G1 is used as a gate terminal in the Clapp oscillation circuit 2A, the first capacitor 12 and the first capacitor 12 are connected to the one gate terminal G1 in the same manner as in the Clapp oscillation circuit 2A. A series circuit of an inductor 13 is connected, a second capacitor 14 is connected, and a bias circuit 16 is connected.

Similarly to the Clapp oscillator circuit 2A, the Clapp oscillator circuit 2B configured as described above also self-oscillates at the constant frequency f to generate an AC signal S1 at the source terminal of the transistor element 11. The signal S1 is output as the drive signal Vdv to the output terminal 4a (between the output terminals 4a and 4b) with a low output impedance to switch the semiconductor switching element 51 at a constant frequency f.

Therefore, the gate drive circuit 1B, like the gate drive circuit 1A, is not affected by changes in the gate-to-source capacitance Cgs, and operates at a constant frequency f given by the above equation (1). The AC signal S1 can be stably generated and output as the drive signal Vdv between the gate and source of the semiconductor switching element 51 to stably switch the semiconductor switching element 51 at a constant frequency f. Also in this gate drive circuit 1B, since the inductor 3 is connected in parallel to the third capacitor 15, even if the capacitance value C3 of the third capacitor 15 is set to a large value as described above, the inductor 3 and the third capacitor 15 are connected in parallel. Since the combined impedance of the parallel circuit of the capacitor 15 can be maintained at a sufficient value, it is possible to generate the AC signal S1 with sufficient amplitude and output the drive signal Vdv with sufficient amplitude between the gate and source of the semiconductor switching element 51. can be done. In this case, in this gate drive circuit 1B, since the transistor element 11 is composed of dual-gate MOSFETs with large mutual conductance, the drive signal Vdv with sufficiently large amplitude is applied between the gate and source of the semiconductor switching element 51 with sufficiently low impedance. can be output to Furthermore, according to the gate drive circuit 1B, the transistor element 11 is composed of a dual-gate MOSFET with an extremely small feedback capacitance existing between the gate terminal G1 and the drain terminal. , that is, a drive signal Vdv having a higher frequency f can be output between the gate and source of the semiconductor switching element 51 .

Also, an example of using an enhancement-type dual-gate MOSFET as the transistor element 11 has been described, but a depletion-type dual-gate MOSFET can also be used as the transistor element 11, or two JFETs can be cascode-connected to form a dual-gate MOSFET. It can also be configured and used as

The configuration of the gate drive circuit is not limited to the configuration in which the source terminal of the transistor element 11 is directly connected to the gate terminal of the semiconductor switching element 51 via the output terminal 4a, as in the gate drive circuits 1A and 1B. . For example, as in the gate drive circuit 1C shown in FIG. 3, a configuration in which a ferroresonant circuit 21A is arranged between the source terminal of the transistor element 11 and the output terminal 4a can be employed. The gate drive circuit 1C will be described below. A configuration in which a ferroresonant circuit is arranged can be applied to both of the gate drive circuits 1A and 1B. explain. Therefore, the same components as those of the gate drive circuit 1A are denoted by the same reference numerals, and overlapping descriptions are omitted.

The gate drive circuit 1C, as shown in FIG. 3, includes a Clapp oscillation circuit 2A, an inductor 3, and a ferroresonant circuit 21A as an example of a ferroresonant circuit, and generates an AC signal S1 of a constant frequency f. The AC signal S1 is amplitude-amplified by the ferroresonant circuit 21A, and can be output to the semiconductor switching element 51 via the output terminals 4a and 4b as a drive signal Vdv having a larger amplitude.

The ferroresonant circuit 21A comprises an input inductor 22, a saturable magnetic core 23A and an output capacitor 24. As shown in FIG. One end of the input inductor 22 is connected to the source terminal of the transistor element 11 . 23 A of saturable magnetic cores are comprised with one magnetic core and one winding|winding formed in this magnetic core although it does not illustrate. The saturable core 23A has one end (one end of the winding) connected to the other end of the input inductor 22 and the other end (the other end of the winding) connected to the ground GND. The output capacitor 24 has one end connected to the other end of the input inductor 22 and the other end connected to the ground GND (that is, connected in parallel to the saturable core 23A).

In this ferroresonant circuit 21A, the resonance frequency determined by the parallel combined capacitance value of the gate-to-source capacitance Cgs of the output capacitor 24 and the semiconductor switching element 51 connected in parallel and the inductance value of the input inductor 22 is the ferroresonant circuit The capacitance value of the output capacitor 24 and the inductance value of the input inductor 22 are predetermined so as to be lower than the frequency f of the AC signal S1 input to 21A. In this configuration, the ferroresonant circuit 21A has an inductive input impedance and a jump phenomenon in its input/output voltage characteristics, thereby outputting an output AC voltage with a larger amplitude than the input AC voltage. In addition, the ferroresonant circuit 21A has a characteristic of low power consumption (extremely small power consumption) common to ferroresonant circuits.

In addition, in the ferroresonant circuit 21A, the capacitance value of the output capacitor 24 satisfies the above-described conditions for the resonance frequency and is set in advance so that the capacitance value is sufficiently large with respect to the parallel-connected gate-source capacitance Cgs. stipulated. Therefore, in the gate drive circuit 1C, the effects of changes in the gate-source capacitance Cgs (effects on the resonance frequency of the ferroresonant circuit 21A and effects on the self-excited oscillation frequency (frequency f) of the clapp oscillator circuit 2A) are ignored. reduced to as low as possible.

In the gate drive circuit 1C configured as described above, the Clapp oscillator circuit 2A self-oscillates at a constant frequency f, and outputs an AC signal S1 of this frequency f to the ferroresonant circuit 21A. The ferroresonant circuit 21A amplifies the AC signal S1 and outputs it as a drive signal Vdv between the gate and source of the semiconductor switching element 51, thereby causing the semiconductor switching element 51 to switch at a constant frequency f.

Therefore, the gate drive circuit 1C, like the gate drive circuit 1A, is not affected by the change in the gate-source capacitance Cgs, and at the constant frequency f shown in the above equation (1). The AC signal S1 is stably generated, amplitude-amplified by the ferroresonant circuit 21A, and output as a drive signal Vdv between the gate and source of the semiconductor switching element 51, thereby stabilizing the semiconductor switching element 51 at a constant frequency f. can be switched by Also in this gate drive circuit 1C, since the inductor 3 is connected in parallel to the third capacitor 15, even if the capacitance value C3 of the third capacitor 15 is set to a large value as described above, the inductor 3 and the third capacitor Since the combined impedance of the parallel circuit of the capacitor 15 can be maintained at a sufficient value, it is possible to generate the AC signal S1 with sufficient amplitude and output the drive signal Vdv with sufficient amplitude between the gate and source of the semiconductor switching element 51. can be done.

Further, according to the gate drive circuit 1C, even when the power supply voltage Vdd supplied to the drain terminal of the transistor element 11 is low and therefore the amplitude of the AC signal S1 is also small, the ferroresonant circuit 21A can drive the AC signal. Since S1 can be amplified in amplitude and output as the drive signal Vdv, the drive signal Vdv with sufficient amplitude is output between the gate and source of the semiconductor switching element 51 to switch the semiconductor switching element 51 at a constant frequency f. can be made

The ferroresonant circuit to be used is the ferroresonant circuit 21A provided with the saturable magnetic core 23A (a saturable magnetic core composed of one magnetic core and one winding formed on this magnetic core). Not limited. For example, a ferroresonant circuit with a saturable core with two windings can be used. A gate drive circuit 1D including a ferroresonant circuit 21B having this configuration will be described below with reference to FIG. Since the gate drive circuit 1D has a configuration in which only the ferroresonant circuit 21A in the gate drive circuit 1C is replaced with a ferroresonant circuit 21B, the same reference numerals are given to the same configurations as those of the gate drive circuit 1C. omit the description.

As shown in FIG. 4, the gate drive circuit 1D includes a Clapp oscillation circuit 2A, an inductor 3, and a ferroresonant circuit 21B as an example of a ferroresonant circuit, and generates an AC signal S1 of a constant frequency f and The AC signal S1 is amplitude-amplified by the ferroresonant circuit 21B and can be output to the semiconductor switching element 51 via the output terminals 4a and 4b as a drive signal Vdv having a larger amplitude.

The ferroresonant circuit 21B comprises an input inductor 22, a saturable magnetic core 23B and an output capacitor 24. As shown in FIG. The saturable magnetic core 23B is composed of one magnetic core (not shown) and two windings W1 and W2 formed on this magnetic core. The winding W1 of these two windings W1 and W2 has one end connected to the other end of the input inductor 22 as a primary winding, and the winding W2 has one end connected to the output terminal 4a as a secondary winding. It is connected. Further, the other ends of the windings W1 and W2 are connected to the ground GND. The output capacitor 24 has one end connected to one end of the winding W2 and the other end connected to the ground GND (that is, connected in parallel to the winding W2 of the saturable magnetic core 23B). Further, in the saturable magnetic core 23B, the number of turns n2 of the winding W2 is set to be greater than the number of turns n1 of the winding W1 so that the amplification factor for the AC signal S1 in the ferroresonant circuit 21B is greater than that in the ferroresonant circuit 21A. stipulated in

In this ferroresonant circuit 21B as well, the occurrence of the jump phenomenon is determined by the parallel combined capacitance value of the output capacitor 24 and the gate-to-source capacitance Cgs of the semiconductor switching element 51 connected in parallel, and the inductance value of the input inductor 22. Similar to the ferroresonant circuit 21A described above, it is necessary to satisfy the condition that the resonance frequency is lower than the frequency f of the AC signal S1 input to the ferroresonant circuit 21B. Regarding this point, in the ferroresonant circuit 21B, the impedance conversion action of the saturable magnetic core 23B composed of the windings W1 and W2 (n1<n2) causes the above-described parallel synthesis on the secondary side of the saturable magnetic core 23B. The capacitance value is converted to a larger capacitance value on the primary side of the saturable core 23B. Therefore, when the inductance value of the input inductor 22 and the capacitance value of the output capacitor 24 constituting the ferroresonant circuit 21B are equivalent to those of the ferroresonant circuit 21A, the resonance frequency of the ferroresonant circuit 21B is higher than the resonance frequency of the ferroresonant circuit 21A. Therefore, the ferroresonant circuit 21B satisfies the above conditions for the occurrence of the jump phenomenon.

In the gate drive circuit 1D configured as described above, the Clapp oscillator circuit 2A self-oscillates at a constant frequency f and outputs an AC signal S1 of this frequency f to the ferroresonant circuit 21B. The ferroresonant circuit 21B amplifies the AC signal S1 and outputs it as a drive signal Vdv between the gate and source of the semiconductor switching element 51, thereby causing the semiconductor switching element 51 to switch at a constant frequency f.

Therefore, the gate drive circuit 1D, like the gate drive circuit 1C, is not affected by the change in the gate-source capacitance Cgs, and at the constant frequency f represented by the above equation (1). The AC signal S1 is stably generated, amplitude-amplified by the ferroresonant circuit 21B, and output as a drive signal Vdv between the gate and source of the semiconductor switching element 51, thereby stabilizing the semiconductor switching element 51 at a constant frequency f. can be switched by Also in this gate drive circuit 1D, since the inductor 3 is connected in parallel to the third capacitor 15, even if the capacitance value C3 of the third capacitor 15 is set to a large value as described above, the inductor 3 and the third capacitor Since the combined impedance of the parallel circuit of the capacitor 15 can be maintained at a sufficient value, it is possible to generate the AC signal S1 with sufficient amplitude and output the drive signal Vdv with sufficient amplitude between the gate and source of the semiconductor switching element 51. can be done.

Furthermore, according to the gate drive circuit 1D, even when the power supply voltage Vdd supplied to the drain terminal of the transistor element 11 is low and therefore the amplitude of the AC signal S1 is also small, the ferroresonant circuit 21B can drive the AC signal. Since S1 can be amplified in amplitude and output as the drive signal Vdv, the drive signal Vdv with sufficient amplitude is output between the gate and source of the semiconductor switching element 51 to switch the semiconductor switching element 51 at a constant frequency f. can be made Further, according to the gate drive circuit 1D, since the ferroresonant circuit 21B is configured with the saturable magnetic core 23B composed of the windings W1 and W2 (n1<n2), it is composed of one winding. Compared to the ferroresonant circuit 21A having the saturable magnetic core 23A, the AC signal S1 can be amplitude-amplified into the drive signal Vdv with a greater amplification factor and output between the gate and source of the semiconductor switching element 51. FIG.

In a ferroresonant circuit including a saturable magnetic core having two windings, such as the ferroresonant circuit 21B described above, the winding (primary winding) located on the inductor 3 side of the two windings is A leakage inductance can also be substituted for the input inductor 22 . A gate drive circuit 1E including a ferroresonant circuit 21C having this configuration will be described below with reference to FIG. The gate drive circuit 1E has a configuration in which only the ferroresonant circuit 21B in the gate drive circuit 1D is replaced with the ferroresonant circuit 21C. omit the description.

As shown in FIG. 5, the gate drive circuit 1E includes a Clapp oscillation circuit 2A, an inductor 3, and a ferroresonant circuit 21C as an example of a ferroresonant circuit, and generates an AC signal S1 of a constant frequency f. The AC signal S1 is amplitude-amplified by the ferroresonant circuit 21C and can be output to the semiconductor switching element 51 via the output terminals 4a and 4b as a drive signal Vdv having a larger amplitude.

The ferroresonant circuit 21C includes a saturable magnetic core 23C and an output capacitor 24. As shown in FIG. The saturable magnetic core 23C is composed of two magnetic cores X1, X2 and two windings W1, W2. The winding W1 of the two windings W1 and W2 is formed as a primary winding so as to bundle the two magnetic cores X1 and X2, and one end of the winding W1 is connected to the source terminal of the transistor element 11. . A winding W2 is formed on the magnetic core X2 as a secondary winding, and one end of the winding W2 is connected to the output terminal 4a. Further, the other ends of the windings W1 and W2 are connected to the ground GND. The output capacitor 24 has one end connected to one end of the winding W2 and the other end connected to the ground GND (that is, connected in parallel to the winding W2 of the saturable magnetic core 23C). In addition, in the saturable magnetic core 23C, the number of turns n2 of the winding W2 is larger than the number of turns n1 of the winding W1 so that the amplification factor for the AC signal S1 in the ferroresonant circuit 21C is greater than that in the ferroresonant circuit 21A. It is stipulated to be

Furthermore, in this ferroresonant circuit 21, the leakage inductance of the winding W1 as the primary winding in the saturable core 23C is set so that it can substitute for the input inductor 22 (the inductance value of the leakage inductance is equal to the inductance value of the input inductor 22). A configuration is adopted in which the leakage flux on the winding W1 side is increased so that the leakage flux is increased to the same degree. In this configuration, a magnetic core made of a magnetic material with a high magnetic permeability μ is used for the magnetic core X2, whereas a magnetic core made of a magnetic material with a low magnetic permeability μ is used for the magnetic core X1. Therefore, it is possible to increase the leakage magnetic flux on the winding W1 side, or use a magnetic core made of a magnetic material with a high magnetic permeability μ for both the magnetic cores X1 and X2, and attach a cap to the magnetic core X1. The configuration may be such that the leakage magnetic flux on the side of the winding W1 is increased by providing it.

Since this ferroresonant circuit 21C also includes a saturable magnetic core 23C composed of windings W1 and W2 (n1<n2), the leakage inductance of the winding W1 constituting the ferroresonant circuit 21C (substitute for the input inductor 22) ) and the capacitance value of the output capacitor 24 are equal to those of the ferroresonant circuit 21A, the resonance frequency of the ferroresonant circuit 21C is always lower than that of the ferroresonant circuit 21A. satisfies the above conditions for manifestation of the jump phenomenon.

In the gate drive circuit 1E configured as described above, the Clapp oscillator circuit 2A self-oscillates at a constant frequency f and outputs an AC signal S1 of this frequency f to the ferroresonant circuit 21C. The ferroresonant circuit 21C amplifies the AC signal S1 and outputs it as a driving signal Vdv between the gate and source of the semiconductor switching element 51, thereby causing the semiconductor switching element 51 to switch at a constant frequency f.

Therefore, the gate drive circuit 1E, like the gate drive circuit 1D, is not affected by the change in the gate-source capacitance Cgs, and at the constant frequency f shown in the above equation (1). The AC signal S1 is stably generated, amplitude-amplified by the ferroresonant circuit 21C, and output as a drive signal Vdv between the gate and source of the semiconductor switching element 51, thereby stabilizing the semiconductor switching element 51 at a constant frequency f. can be switched by Also in this gate drive circuit 1E, since the inductor 3 is connected in parallel with the third capacitor 15, even if the capacitance value C3 of the third capacitor 15 is set to a large value as described above, the inductor 3 and the third capacitor Since the combined impedance of the parallel circuit of the capacitor 15 can be maintained at a sufficient value, it is possible to generate the AC signal S1 with sufficient amplitude and output the drive signal Vdv with sufficient amplitude between the gate and source of the semiconductor switching element 51. can be done.

Further, even when the power supply voltage Vdd supplied to the drain terminal of the transistor element 11 is low and therefore the amplitude of the AC signal S1 is also small, the gate drive circuit 1E also allows the ferroresonant circuit 21C to drive the AC signal S1. can be amplified and output as the driving signal Vdv, the driving signal Vdv with sufficient amplitude is output between the gate and source of the semiconductor switching element 51 to switch the semiconductor switching element 51 at a constant frequency f. be able to. Further, in this gate drive circuit 1E as well, since the ferroresonant circuit 21C is configured with the saturable magnetic core 23C composed of the windings W1 and W2 (n1<n2), Compared to the ferroresonant circuit 21A having the saturable magnetic core 23A, the AC signal S1 can be amplitude-amplified into the drive signal Vdv and output between the gate and source of the semiconductor switching element 51 with a larger amplification factor.

Further, according to the gate drive circuit 1E, the leakage inductance of the winding W1 forming the ferroresonant circuit 21C can be substituted for the input inductor 22, so that the signal attenuation due to the resistance component present in the input inductor 22 can be reduced. Since it can be avoided, a drive signal Vdv having a larger amplitude can be output between the gate and source of the semiconductor switching element 51 .

Further, although the gate drive circuits 1D and 1E described above employ a configuration in which the other ends of the windings W1 and W2 are connected to the common ground GND, the configuration is not limited to this. For example, although not shown, the ground GND of the circuit on the preceding stage side (Clap oscillation circuit 2A side) of the winding W1 in each of the gate drive circuits 1D and 1E is set to the primary side ground GND, and the other end of the winding W1 is set to The ground GND of the circuit connected to this primary side ground GND and on the subsequent stage side (drive target side) of the winding W2 is set to the secondary side ground GND separated from the primary side ground GND, and the winding W2 A configuration in which the other end is connected to the secondary side ground GND can also be adopted. According to the gate drive circuit of this configuration, since the Clapp oscillator circuit 2A and the driven object can be isolated, the potential of the primary side ground GND and the potential of the secondary side ground GND (as in the above example, the driven object is a semiconductor switching In the case of the element 51, the drive target can be driven even when the potential of the source terminal of the element 51 is different. Therefore, according to the gate drive circuit having this configuration, it is possible to drive each driving target constituting the half-bridge circuit and each driving target constituting the full-bridge circuit. In addition, it is advantageous in terms of withstand voltage compared to a configuration in which an IC is used to drive a drive target with a different reference potential.

1A, 1B, 1C, 1D, 1E Gate drive circuit 2A, 2B Clap oscillation circuit
3 second inductor 11 transistor element 12 first capacitor 13 first inductor 14 second capacitor 15 third capacitor 51 semiconductor switching element S1 AC signal Vdv drive signal

Claims (3)

A gate drive circuit for a semiconductor switching element that drives a semiconductor switching element,
a transistor element having a drain terminal or collector terminal connected to a power supply voltage, a first capacitor and a first inductor connected in series between a gate terminal or base terminal of said transistor element and a reference potential, said gate a second capacitor connected between a terminal or said base terminal and a source or emitter terminal of said transistor element, and a third capacitor connected between said source or said emitter terminal and said reference potential. a Clapp oscillator circuit;
a second inductor connected in parallel with the third capacitor;,
An input inductor having one end connected to the source terminal or the emitter terminal, a saturable core connected between the other end of the input inductor and the reference potential, and an output capacitor connected in parallel to the saturable core. and a ferroresonant circuit configured with with
an alternating signal generated between the source terminal or the emitter terminal and the reference potential;Amplified by the ferroresonant circuitA gate drive circuit for a semiconductor switching element that outputs a drive signal to the semiconductor switching element. 3. The saturable magnetic core has a two-winding structure comprising a primary winding connected to the source terminal or the emitter terminal side and a secondary winding connected to the semiconductor switching element side. 2. A gate drive circuit for a semiconductor switching element according to 1 . 3. A gate drive circuit for a semiconductor switching device according to claim 2 , wherein said input inductor comprises leakage inductance of said saturable magnetic core.

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