JP7143182B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

In recent years, with the main objective of further increasing the density of semiconductor devices, there has been progress in the development of techniques for manufacturing semiconductor devices having a three-dimensional structure in which a plurality of semiconductor chips or semiconductor elements are integrated in the thickness direction. ing. A so-called WOW (Wafer on Wafer) process is known as one of such techniques. In the WOW process, a series of steps including a step of bonding and laminating a wafer to another wafer via an adhesive layer and subsequent various processing steps for the laminated wafer are performed a predetermined number of times. . In the wafer bonding process, for example, a thin wafer obtained through a transistor manufacturing process, a wiring forming process, and a thinning process is bonded to a thick base wafer, or another wafer already laminated on the base wafer through a wafer bonding process. It is bonded and laminated to a thin wafer via an adhesive layer. A wafer stack obtained by stacking a predetermined number of wafers is singulated into semiconductor devices having a structure in which a plurality of semiconductor chips are stacked. done by cutting. Such a WOW process is described, for example, in Patent Documents 1 to 3 below.

JP 2015-73128 A JP 2015-119111 A JP 2015-164160 A

In the WOW process, for example, as described above, wafers with different thicknesses are bonded via an adhesive layer, and this bonding is achieved through a predetermined high temperature condition for curing the adhesive layer. . Moreover, the thermal expansion coefficient of the cured adhesive layer is greater than that of the wafer, and the difference between the two thermal expansion coefficients is considerably large. Therefore, in the wafer laminate that has reached room temperature, for example, after the wafer bonding process, warpage is likely to occur due to the difference in coefficient of thermal expansion between the wafer and the adhesive layer. Specifically, an adhesive layer that hardens under a predetermined high-temperature condition between a thick base wafer and a thin wafer laminated thereon and bonds the wafers is, for example, thicker than both wafers in the process of lowering the temperature after the bonding process. For example, when the wafer laminate reaches room temperature, the edge of the laminate tends to warp toward the thin wafer side, where the resistance to shrinkage of the adhesive layer is smaller than that of the base wafer. The degree of this warp tends to increase as the thickness of the wafers laminated via the adhesive layer increases, and tends to increase cumulatively as the number of laminated thin wafers increases. Since there is an upper limit to the degree of warpage that can be allowed for each of the various processing steps for a wafer stack, the WOW process limits the number of wafers that can be stacked, that is, the number of semiconductors that can be multilayered in a semiconductor device for manufacturing purposes. The total number of elements will be constrained by the upper limit.

SUMMARY OF THE INVENTION The present invention has been conceived under the circumstances as described above, and provides a semiconductor device manufacturing method and a semiconductor device suitable for multilayering semiconductor elements.

A first aspect of the present invention provides a semiconductor device manufacturing method. This semiconductor device manufacturing method includes a preparing process, a wafer bonding process, a resin layer forming process, and a removing process. In the preparation step, a first wafer and a reinforced second wafer are prepared. The first wafer has a first side and a second side opposite the first side. The reinforcing second wafer has a laminated structure including a second wafer thinner than the first wafer, a reinforcing supporting substrate, and a temporary adhesive layer between the second wafer and the supporting substrate. The temporary adhesive layer on the reinforcing second wafer is for realizing a temporary adhesive state between the second wafer and the support substrate that can be released later. In the wafer bonding step, the second wafer of the reinforcing second wafer is bonded to the first surface of the first wafer via the adhesive layer. This bonding is achieved, for example, through predetermined high temperature conditions for curing the adhesive layer. Prior to such a wafer bonding step, the first surface of the first wafer and/or the surface to be bonded of the second wafer of the reinforced second wafer is subjected to bonding in order to improve adhesion with the adhesive layer to be formed. A surface treatment such as treatment with a silane coupling agent may be applied. In the resin layer forming step after the wafer bonding step, a resin layer is formed on the second surface of the first wafer. The resin layer is made of, for example, a curable material, and the constituent material of the resin layer may be, for example, an adhesive having the same composition as the adhesive for forming the above-described adhesive layer for bonding wafers. Formation of the resin layer is realized, for example, through predetermined high-temperature conditions for curing the resin layer. Prior to such a resin layer forming step, the second surface of the first wafer may be subjected to surface treatment such as silane coupling agent treatment for improving adhesion to the resin layer to be formed. Then, in the removing step, the temporary adhesive state by the temporary adhesive layer between the supporting substrate and the second wafer is released, and the supporting substrate is removed.

In the above-described wafer bonding step in the semiconductor device manufacturing method, the relatively thin second wafer to which the supporting substrate is bonded via the temporary adhesive layer is bonded to the relatively thick first wafer with an adhesive. Bonded through layers. In the wafer laminate including the first and second wafers (with the support substrate bonded to the second wafer) obtained through such a wafer bonding process, for example, when the temperature is lowered to room temperature, the cured adhesive The resistance of the second wafer itself to shrinkage of the layer is less than the resistance of the first wafer to shrinkage of the same adhesive layer because the second wafer is thinner than the first wafer. However, the support substrate bonding to the second wafer may compensate the second wafer for resistance to shrinkage of the cured adhesive layer. Even if the difference in thickness between the first and second wafers is large, the resistance of the second wafer itself to shrinkage of the cured adhesive layer is considerably less than that of the first wafer. The support substrate bonded to the second wafer on the opposite side of the first wafer bonding side can compensate the second wafer for resistance to shrinkage of the cured adhesive layer. Therefore, in the wafer stack (with the support substrate bonded to the second wafer), the thermal expansion difference between the first and second wafers and the adhesive layer and the difference between both wafers and the adhesive layer The occurrence of warping due to the asymmetrical lamination structure is suppressed.

In addition, in the present semiconductor device manufacturing method, as described above, the resin layer is formed on the second surface of the first wafer before the step of separating and removing the support substrate from the second wafer (removing step). A step (resin layer forming step) is performed. After the resin layer forming step and the subsequent removing step, for example, in the wafer laminate at room temperature, the shrinkage stress of the cured adhesive layer acts on the first surface of the first wafer, The shrinkage stress of the cured resin layer acts on the second surface of the first wafer (the second surface opposite to the first surface). Therefore, even if the thickness difference between the first and second wafers is large, the resistance of the second wafer to shrinkage of the cured adhesive layer is considerably less than that of the first wafer. The shrinkage stress of the post-curing adhesive layer acting on the first surface of the first wafer (which acts on the first wafer to deform the end portion thereof toward the first surface side) is applied to the second surface of the first wafer. It is possible to reduce or cancel out the shrinkage stress of the cured resin layer acting on the surface. Therefore, the above-described configuration in which the resin layer forming step and the subsequent removing step are performed requires a relatively thick first wafer, a relatively thin second wafer, and a thin film between the first and second wafers. and the adhesive layer of the wafer laminate, it is suitable for suppressing the occurrence of warpage after passing through the removal process.

As described above, this semiconductor device manufacturing method is suitable for suppressing the occurrence of warpage in the wafer stack during the manufacturing process. The smaller the degree of warpage in the wafer laminate during the manufacturing process, the easier it is to perform various processing on the wafer laminate with high precision, and the multilayering of the wafer laminate and, in turn, the semiconductor element in the manufactured semiconductor device. It is easy to plan multi-layering. Therefore, this semiconductor device manufacturing method is suitable for multilayering semiconductor elements.

This semiconductor device manufacturing method preferably further comprises at least one wafer adding step, at least one resin layer adding step performed for each wafer adding step, and at least one removing step performed for each wafer adding step. include. In the wafer adding step, the second reinforcing second wafer having a laminated structure including a second wafer thinner than the first wafer, a supporting substrate for reinforcement, and a temporary adhesive layer between the second wafer and the supporting substrate. A wafer is bonded via an adhesive layer to another second wafer on the first wafer. A separate second wafer on the first wafer means the second wafer bonded to the first surface of the first wafer in the wafer bonding process described above, or additionally on the first wafer in the preceding wafer adding process. It is the 2nd wafer laminated|stacked. The temporary adhesive layer on the reinforcing second wafer is for realizing a temporary adhesive state between the second wafer and the support substrate that can be released later. Bonding in the wafer addition process is realized, for example, through predetermined high-temperature conditions for curing the adhesive layer. Prior to such a wafer addition step, the planned bonding surface of the second wafer on the first wafer and/or the planned bonding surface of the second wafer on the reinforcing second wafer is in close contact with the formed adhesive layer. A surface treatment such as a silane coupling agent treatment may be applied to improve the properties. In the resin layer adding step after the wafer adding step, an additional resin layer is formed on the resin layer on the second surface side of the first wafer. The resin layer is made of, for example, a curable material, and the constituent material of the resin layer may be, for example, an adhesive having the same composition as the adhesive for forming the adhesive layer for bonding wafers. Formation of the resin layer is realized, for example, through predetermined high-temperature conditions for curing the resin layer. By such a resin layer adding step, a multilayer resin portion including a plurality of resin layers stacked in the thickness direction of the first wafer and in close contact with the second surface is formed. The number of resin layers included in this multilayer resin portion is the same as the total number of adhesive layers between wafers. Before such a resin layer addition step, the surface of the resin layer on the second surface side of the first wafer is subjected to surface treatment such as treatment with a silane coupling agent for improving adhesion to the resin layer to be additionally formed. may be applied. Then, in the removing step after the resin layer adding step, the temporary bonding state by the temporary adhesive layer between the supporting substrate and the second wafer in the reinforced second wafer that has undergone the wafer adding step is released, and the supporting substrate can be removed. done.

In the above-described wafer adding step in the semiconductor device manufacturing method, the second wafer bonded to the relatively thick first wafer via the adhesive layer in the above-described wafer bonding step or the preceding wafer adding step , a relatively thin new second wafer to which the supporting substrate is bonded via the temporary adhesive layer is bonded via the new adhesive layer. In a wafer stack including a first wafer and a plurality of second wafers (accompanied by a support substrate bonded to the last stacked second wafer) obtained through such a wafer addition process, for example, at room temperature When the temperature is lowered, the resistance of each second wafer itself to shrinkage of each cured adhesive layer is lower than that of the first wafer to shrinkage of the same adhesive layer, because each second wafer is thinner than the first wafer. ,small. However, the support substrate in the reinforcing second wafer may compensate each second wafer for resistance to shrinkage of each cured adhesive layer. Even if the thickness difference between the first and each second wafer is large, the resistance of each second wafer itself to shrinkage of each adhesive layer after curing is considerably less than that of the first wafer. Even so, the supporting substrate in the stiffening second wafer can compensate each second wafer for resistance to shrinkage of each adhesive layer after curing. Therefore, in the wafer stack (accompanied by the support substrate bonded to the last stacked second wafer) obtained through each wafer addition process, the first wafer and the plurality of second wafers exhibiting different thermal expansion coefficients The occurrence of warpage due to the predetermined asymmetric lamination configuration of the wafer and multiple adhesive layers is suppressed.

In addition, in the preferred configuration of the present semiconductor device manufacturing method, before the step of separating and removing the support substrate from the second wafer in the reinforcing second wafer that has undergone the wafer adding step (removing step), the first wafer A step of forming an additional resin layer on the resin layer on the second surface side of the (resin layer adding step) is performed. In a wafer laminate that is at room temperature, for example, after undergoing such a resin layer addition step and a subsequent removal step, the shrinkage stress of each adhesive layer located on the first surface side of the first wafer directly or Indirectly acting on the first surface of the first wafer, the contraction stress of each resin layer of the multi-layered resin portion in close contact with the second surface of the first wafer is combined and acts on the second surface of the first wafer. do. and the total number of adhesive layers on the first surface side of the first wafer and the total number of resin layers on the second surface side of the first wafer when the wafer stack during the manufacturing process is not accompanied by the supporting substrate of the reinforced second wafer. is the same as Therefore, even if the thickness difference between the first and second wafers is large, the resistance of each second wafer to shrinkage of each adhesive layer after curing is considerably less than the resistance of the first wafer. However, the total shrinkage stress of each adhesive layer acting on the first surface side of the first wafer (which acts on the first wafer to deform the end portion thereof toward the first surface side) is It is possible to reduce or cancel out the total shrinkage stress of each resin layer acting on the second surface side of the wafer. Therefore, the above-described configuration in which the resin layer adding step and the subsequent removing step are performed for each wafer adding step is a relatively thick first wafer, a plurality of relatively thin second wafers, and It is suitable for suppressing the occurrence of warpage after the wafer stack including a plurality of adhesive layers interposed between the wafers after the detachment process.

As described above, the preferred configuration of the semiconductor device manufacturing method described above is suitable for suppressing the occurrence of warpage in a wafer stack during a manufacturing process in which a multi-layered wafer is intended. In the WOW process, as the number of stacked wafers increases, the degree of warpage of the wafer stack tends to accumulate. is suitable for suppressing

This semiconductor device manufacturing method preferably further includes a step (grinding step) of thinning the first wafer by grinding the second surface side of the first wafer. By this grinding process, it is possible to thin the first wafer to a predetermined thickness after removing the multilayer resin portion on the second surface of the first wafer.

A second aspect of the present invention provides a semiconductor device. This semiconductor device has a laminated structure including a first wafer, a second wafer, an adhesive layer, and a resin layer. The first wafer has a first side and a second side opposite the first side. The second wafer is located on the first surface side of the first wafer and is thinner than the first wafer. An adhesive layer is interposed between the first wafer and the second wafer. The adhesive layer is, for example, cured through a predetermined high temperature condition. The resin layer is in close contact with the second surface of the first wafer. The resin layer is, for example, hardened through predetermined high-temperature conditions.

In the semiconductor device having such a configuration, for example, at room temperature, the contraction stress of the adhesive layer located on the first surface side of the first wafer acts on the first surface of the first wafer, Contraction stress of the resin layer located on the second surface side acts on the second surface of the first wafer. Therefore, in the present semiconductor device, even if the difference in thickness between the first and second wafers is large, the resistance of the second wafer to contraction of the adhesive layer is much smaller than that of the first wafer. Even if there is a The contraction stress of the resin layer acting on the second surface can be reduced or offset. Therefore, this semiconductor device is suitable for suppressing the occurrence of warpage. This semiconductor device, which is suitable for suppressing the occurrence of warpage, can be easily processed with high precision when further processing is required, and can be appropriately manufactured as a semiconductor device having multiple layers of semiconductor elements. Therefore, this semiconductor device is suitable for multilayering semiconductor elements.

A third aspect of the present invention provides a semiconductor device. This semiconductor device has a laminated structure including a first wafer, a plurality of second wafers, a plurality of adhesive layers, and a multilayer resin portion. The first wafer has a first side and a second side opposite the first side. The plurality of second wafers are each thinner than the first wafer, positioned on the first surface side of the first wafer, and arranged in the thickness direction of the first wafer. Each of the plurality of adhesive layers is interposed between adjacent wafers to bond the wafers together. Each adhesive layer is cured, for example, under predetermined high-temperature conditions. The multilayer resin portion includes a plurality of resin layers stacked in the thickness direction of the first wafer, and is in close contact with the second surface of the first wafer. Each resin layer of the multilayer resin portion is, for example, cured under a predetermined high temperature condition. The number of resin layers contained in such a multilayer resin portion is the same as the total number of adhesive layers interposed between the wafers.

In the semiconductor device having such a configuration, for example, at normal temperature, the contraction stress of each adhesive layer located on the first surface side of the first wafer directly or indirectly acts on the first surface of the first wafer. At the same time, the contraction stress of the multi-layered resin portion positioned on the second surface side of the first wafer acts on the second surface of the first wafer. In this semiconductor device, the total number of adhesive layers on the first surface side of the first wafer is the same as the total number of resin layers included in the multilayer resin portion on the second surface side. Therefore, in the present semiconductor device, even if the thickness difference between the first and second wafers is large, the resistance of each second wafer to shrinkage of each adhesive layer is considerably smaller than that of the first wafer. Even in the case of the It is possible to reduce or cancel out the total shrinkage stress of the multilayer resin portion acting on the second surface of the first wafer. Therefore, this semiconductor device is suitable for suppressing the occurrence of warpage. In the WOW process, as the number of stacked wafers increases, the degree of warping of the wafer stack tends to accumulate. be. This semiconductor device, which is suitable for suppressing the occurrence of warpage, can be easily processed with high precision when further processing is required, and can be appropriately manufactured as a semiconductor device having multiple layers of semiconductor elements. Therefore, this semiconductor device is suitable for multilayering semiconductor elements.

4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention; 4 shows some steps in a semiconductor device manufacturing method according to an embodiment of the present invention;

1 to 9 show a semiconductor device manufacturing method according to one embodiment of the present invention. This manufacturing method is for manufacturing a semiconductor device having a three-dimensional structure in which semiconductor elements are integrated in the thickness direction, and FIGS.

In this semiconductor device manufacturing method, first, as shown in FIG. 1A, a wafer 11 and a reinforcing wafer 12R are prepared (preparation step).

Wafer 11 has a side 11a and an opposite side 11b. The wafer 11 is a semiconductor wafer in which various semiconductor elements (not shown) are already fabricated on the side of the surface 11a, and wiring structures (not shown) necessary for the semiconductor elements are already formed on the surface 11a. be. Semiconductor wafer constituent materials for forming the wafer 11 include, for example, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP). is mentioned. The thickness of such wafer 11 is preferably 300 μm or more, more preferably 500 μm or more, and more preferably 700 μm or more from the viewpoint of ensuring the strength of the wafer stack including the wafer 11 during the manufacturing process. . From the viewpoint of shortening the grinding time in the later-described grinding step, the thickness of the wafer 11 is preferably 1000 μm or less, more preferably 900 μm or less, and more preferably 800 μm or less.

The reinforcing wafer 12R has a laminated structure including the wafer 12, the support substrate S, and the temporary adhesive layer 13 between the wafer 12 and the support substrate S.

Wafer 12 has a side 12a and an opposite side 12b. The wafer 12 is a semiconductor wafer in which various semiconductor elements (not shown) are already fabricated on the side of the surface 12a, and wiring structures and the like (not shown) necessary for the semiconductor elements are already formed on the surface 12a. be. Alternatively, the wafer 12 has various semiconductor elements (not shown) already formed on the side of the surface 12a, and wiring structures necessary for the semiconductor elements are formed later on the surface 12a. There may be. As the constituent material of the semiconductor wafer for forming the wafer 12, for example, those listed above as the constituent material for the semiconductor wafer for forming the wafer 11 can be employed. Also, the wafer 12 is thinner than the wafer 11 described above. The thickness of the wafer 12 is preferably 100 μm or less, more preferably 50 μm or less, more preferably 30 μm or less, and more preferably 10 μm or less from the viewpoint of thinning and miniaturization of the semiconductor device to be manufactured. The thickness of the wafer 12 is preferably 1 μm or more, more preferably 2 μm or more, and still more preferably 2.5 μm or more, from the viewpoint of ensuring the characteristics of the semiconductor elements to be manufactured.

The supporting substrate S in the reinforcing wafer 12R is for reinforcing the thin wafer 12. As shown in FIG. Examples of the support substrate S include a silicon wafer and a glass wafer. The thickness of the support substrate S is preferably 300 μm or more, more preferably 500 μm or more, and more preferably 700 μm or more, from the viewpoint of ensuring the function as a reinforcing element. The thickness of the support substrate S is, for example, 800 μm or less. Such a support substrate S is bonded to the side of the surface 12a of the wafer 12 via the temporary adhesive layer 13 .

The temporary adhesive layer 13 is for realizing a temporary adhesive state between the wafer 12 and the support substrate S that can be released afterward. As an adhesive for forming such a temporary adhesive layer 13, for example, a polymer material that exhibits stickiness or adhesiveness in the temporary adhesive layer 13 in a predetermined temperature range and exceeds the temperature range Containing a polymer material having a softening point in a high temperature range, adhesive strength that can withstand the grinding process described later for forming the wafer 12, heat resistance that can withstand the wafer bonding process that involves heating, etc. described later. Adhesives are used that combine a light release function to facilitate the removal process. As the adhesive for forming the temporary adhesive layer 13, for example, a silicone-based adhesive, an acrylic adhesive, or a wax-type adhesive can be used. As the adhesive for forming the temporary adhesive layer 13, those described in JP-A-2008-13589, JP-A-2008-13590, or JP-A-2008-49443 may be employed. The thickness of the temporary adhesive layer 13 as described above is, for example, 1 to 20 μm.

The reinforcing wafer 12R having such a configuration can be manufactured through the following steps, for example. First, a temporary adhesive layer 13 is formed on a support substrate S, as shown in FIG. Specifically, the adhesive composition for forming the temporary adhesive layer 13 is applied on the support substrate S by, for example, spin coating to form a temporary adhesive composition layer, and the composition layer is dried by heating. , the temporary adhesive layer 13 can be formed. The heating temperature is, for example, 100 to 300° C., and the heating time is, for example, 30 seconds to 30 minutes. Next, as shown in FIGS. 2(b) and 2(c), the supporting substrate S and the wafer 12' are bonded via the temporary adhesive layer 13. Next, as shown in FIG. Wafer 12' has a side 12a and an opposite side 12b'. The wafer 12' is a semiconductor wafer in which various semiconductor elements (not shown) are already fabricated on the side of the surface 12a, and wiring structures and the like (not shown) necessary for the semiconductor elements are already formed on the surface 12a. is. In the main bonding step, for example, after the support substrate S and the wafer 12 ′ are bonded together while being pressurized through the temporary adhesive layer 13 , the temporary adhesive layer 2 is solidified through heating, and the support substrate S and the wafer are bonded together. 12 ′ are adhered by the temporary adhesive layer 2 . In bonding, the pressure is, for example, 300 to 5,000 g/cm ² and the temperature is, for example, 30 to 200°C. Further, in the adhesion by the temporary adhesive layer 13, the heating temperature is, for example, 100 to 300.degree. C., and the heating time is, for example, 30 seconds to 30 minutes. Then, the wafer 12' is thinned to form the above wafer 12 as shown in FIG. 2(d). Specifically, the wafer 12', which is supported by the support substrate S, is ground from the side of the surface 12b' by using a grinder, thereby reducing the wafer 12' to a predetermined thickness. It can be thinned down to a wafer 12 . As described above, the reinforcing wafer 12R having a laminated structure including the wafer 12, the support substrate S, and the temporary adhesive layer 13 therebetween can be manufactured. The surface 12b of the wafer 12 in the reinforcing wafer 12R may be subjected to surface treatment such as silane coupling agent treatment for improving adhesion to the adhesive layer 21 described later.

In this semiconductor device manufacturing method, next, for example, an adhesive layer 21 is formed on the surface 11a of the wafer 11 as shown in FIG. 1B, and then, as shown in FIG. The wafer 11 and the wafer 12 of the reinforcing wafer 12R are bonded via the adhesive layer 21 (wafer bonding step).

The adhesive layer 21 is for achieving a bonding state between the wafers 11 and 12, and is made of a thermosetting adhesive. Examples of the adhesive main component for forming the thermosetting adhesive include polyorganosilsesquioxane, benzocyclobutene (BCB) resin, and novolac epoxy resin. From the viewpoint of realizing good heat resistance and crack resistance that can withstand the temperature environment in this method including various heating conditions and temperature fluctuations, the formation of the adhesive layer 21 includes a polyorganosilsesquioxane-containing thermosetting A mold adhesive is preferably employed. As the polyorganosilsesquioxane-containing thermosetting adhesive, for example, the adhesive described in International Publication No. 2016/204114 can be employed. Regarding the heat resistance of the thermosetting adhesive for forming the adhesive layer 21, the thermal decomposition temperature of the adhesive is preferably 200° C. or higher, more preferably 260° C. or higher, and more preferably 300° C. or higher. . The thermal decomposition temperature is a curve obtained by thermogravimetric analysis performed using a simultaneous differential thermogravimetric measurement device, that is, a curve representing the temperature dependence of thermogravimetry in a predetermined temperature rise range for the sample to be analyzed. , the tangent line of the part where there is no weight loss or a slight gradual decrease at a constant rate at the beginning of the heating process, and the inflection in the part where significant weight loss occurs in the middle of the heating process following the initial stage of the heating process. Let the temperature be the point of intersection with the tangent line at the point. As the simultaneous differential thermogravimetric measurement device, for example, the product name “TG-DTA6300” manufactured by Seiko Instruments Inc. can be used. In forming such an adhesive layer 21, for example, an adhesive composition for forming the adhesive layer 21 is applied to the surface 11a of the wafer 11 by spin coating to form an adhesive composition layer, and the adhesive composition layer is heated. The composition layer is dried and solidified. The heating temperature at this time is, for example, 50 to 150° C., and the heating time is, for example, 5 to 120 minutes. Prior to the formation of the adhesive layer 21, the surface 11a of the wafer 11 may be subjected to surface treatment such as silane coupling agent treatment for improving adhesion to the adhesive layer 21. FIG. Further, in this embodiment, instead of forming the adhesive layer 21 on the surface 11 a of the wafer 11 , the adhesive layer 21 may be formed on the surface 12 b of the wafer 12 .

Specifically, in the wafer bonding process, the wafer 11 and the reinforcing wafers 12R or 12 are pressed together with the adhesive layer 21 interposed therebetween, and then the adhesive layer 21 is cured by heating. In bonding, the pressure is, for example, 300 to 5,000 g/cm ² and the temperature is, for example, 30 to 200°C. In curing the adhesive layer 21, the heating temperature is, for example, 30 to 200° C., and the heating time is, for example, 5 to 120 minutes. Also, the thickness of the adhesive layer 21 is, for example, 0.5 to 20 μm.

In this semiconductor device manufacturing method, next, a resin layer 31 is formed as shown in FIG. 1(d) (resin layer forming step). The resin layer 31 is made of, for example, a curable material, and as a constituent material of the resin layer 31, for example, a thermosetting adhesive having the same composition as the adhesive for forming the adhesive layer 21 can be used. can. In forming the resin layer 31, for example, an adhesive composition for forming the resin layer 31 is applied to the surface 11b of the wafer 11 by spin coating to form an adhesive composition layer, and the composition layer is dried by heating. and cure the curing component in the composition. The heating temperature at this time is, for example, 30 to 200° C., and the heating time is, for example, 5 to 120 minutes. Before forming such a resin layer 31 , the surface 11 b of the wafer 11 may be subjected to surface treatment such as silane coupling agent treatment for improving adhesion to the resin layer 31 .

Next, the temporary adhesive state by the temporary adhesive layer 13 between the wafer 12 and the support substrate S is released, and the support substrate S is removed from the wafer 12 as shown in FIG. 3 (removal step). Specifically, the temporary adhesive layer 13 whose adhesive strength is lowered by heating at a predetermined high temperature is heated for light release, and then the support substrate S is slid, for example, with respect to the wafer 12 . , the support substrate S can be separated and removed from the wafer 12 or the wafer stack including the wafer 12 . In this step, the heating temperature is, for example, 130 to 250° C., and the heating time is, for example, 30 seconds to 15 minutes. In the case where the wafer 12 in the reinforcing wafer 12R described above does not have a wiring structure including an insulating film and a wiring pattern on its surface 12a side, the wiring structure etc. are formed on the surface 12a of the wafer 12 after the main removal process. be done. The same applies after the removal step described later.

Next, as shown in FIG. 4, through electrodes 41 for electrical connection between semiconductor elements formed on different wafers (wafer 11 and wafer 12) are formed in the wafer stack obtained through the removal process. be done. For example, formation of an opening extending through the wafer 12 and the adhesive layer 21 to the wiring structure (not shown) on the wafer 11, formation of an insulating film (not shown) on the inner wall surface of the opening, insulation Formation of a barrier layer (not shown) on the surface of the film, formation of a seed layer (not shown) for electroplating on the surface of the barrier layer, and filling of the openings with a conductive material such as copper by electroplating. , the through electrode 41 can be formed. A wiring structure (not shown) formed on the surface 11a side of the wafer 11 and a wiring structure (not shown) formed on the surface 12a side of the wafer 12 are electrically connected by the through electrodes 41. be done.

In this semiconductor device manufacturing method, next, after the adhesive layer 21 is formed on the surface 12a of the wafer 12 in the wafer laminate obtained as described above, as shown in FIG. As shown in FIG. 5B, the wafer 12 and the wafer 12 of the new reinforcement wafer 12R (additional wafer 12) are bonded via the adhesive layer 21 (wafer addition process).

In forming the adhesive layer 21 in the wafer addition step, for example, an adhesive composition for forming the adhesive layer 21 is applied to the surface 12a of the wafer 12 in the wafer bonded body by spin coating to form an adhesive composition layer. Then, the composition layer is solidified by heating. The heating temperature is, for example, 50 to 150° C., and the heating time is, for example, 5 to 120 minutes. Prior to the formation of the adhesive layer 21, the surfaces 12a of the wafers 12 in the wafer bonded body are subjected to surface treatment such as silane coupling agent treatment for improving adhesion to the adhesive layer 21. good too.

The reinforcement wafer 12R to be subjected to the wafer addition process has a laminated structure including the additional wafer 12, the support substrate S, and the temporary adhesive layer 13 therebetween. The configuration and manufacturing method of the reinforcing wafer 12R are the same as the configuration and manufacturing method of the reinforcing wafer 12R described above regarding the wafer bonding process. The above-described adhesive layer 21 formed in the wafer addition process may be formed on the surface 12b of the additional wafer 12 in such a reinforcing wafer 12R.

Specifically, in the wafer addition process, after the wafer 12 and the new reinforcing wafer 12R or the additional wafer 12 are pressed together with the adhesive layer 21 interposed therebetween, the adhesive layer 21 is removed by heating. Harden. In bonding, the pressure is, for example, 300 to 5,000 g/cm ² and the temperature is, for example, 30 to 200°C. In curing the adhesive layer 21, the heating temperature is, for example, 30 to 200° C., and the heating time is, for example, 5 to 120 minutes. Also, the thickness of the adhesive layer 21 is, for example, 0.5 to 20 μm.

In this semiconductor device manufacturing method, next, as shown in FIG. 5C, an additional resin layer 31 is formed (resin layer adding step). The resin layer 31 is made of, for example, a curable material, and as a constituent material of the resin layer 31, for example, a thermosetting adhesive having the same composition as the adhesive for forming the adhesive layer 21 can be used. can. In forming the resin layer 31, for example, an adhesive composition for forming the resin layer 31 is applied onto the resin layer 31 already formed on the surface 11b side of the wafer 11 by spin coating to form an adhesive composition layer. and heating dries the composition layer and cures the curing component in the composition. The heating temperature at this time is, for example, 30 to 200° C., and the heating time is, for example, 5 to 120 minutes. Prior to the formation of the additional resin layer 31, the surface of the resin layer 31 already formed on the surface 11b side of the wafer 11 is subjected to silane coupling to improve adhesion with the additional resin layer 31. Surface treatment such as agent treatment may be applied. By the resin layer adding process as described above, the multilayer resin portion 30 including a plurality of resin layers 31 stacked in the thickness direction of the wafer 11 and in close contact with the surface 11b is formed. Since the resin layer addition process is performed for each wafer addition process, the number of resin layers 31 included in the multilayer resin portion 30 is the same as the total number of adhesive layers 21 interposed between the wafers.

Next, the temporary adhesive state by the temporary adhesive layer 13 between the wafer 12 and the support substrate S on the reinforcement wafer 12R is released, and as shown in FIG. Removed (removal process). Specifically, the support substrate S is removed in the same manner as the removal step described above with reference to FIG.

Next, as shown in FIG. 7, through electrodes 41 for electrical connection between semiconductor elements formed on different wafers are formed in the wafer stack obtained through the removal process. For example, forming an opening extending through the additional wafer 12 and the adhesive layer 21 immediately below to reach the wiring structure (not shown) on the wafer 12, and forming an insulating film (not shown) on the inner wall surface of the opening. ), forming a barrier layer (not shown) on the surface of the insulating film, forming a seed layer (not shown) for electroplating on the surface of the barrier layer, and depositing a conductive material such as copper into the opening by electroplating. The through electrode 41 can be formed through filling or the like. By means of the through electrodes 41, for example, a wiring structure (not shown) formed on the side of the surface 12a of the additional wafer 12 on the upper side in the drawing and wiring formed on the side of the surface 12a of the wafer 12 on the lower side in the drawing. structures (not shown) are electrically connected.

In this semiconductor device manufacturing method, the wafer addition step described above with reference to FIGS. 5A and 5B, the resin layer addition step described above with reference to FIG. A series of processes including the removal process described above with reference and the through electrode formation process described above with reference to FIG. 7 are performed a predetermined number of times according to the number of laminated semiconductor elements of the semiconductor device to be manufactured. The resin layer adding process and the subsequent removing process are performed for each wafer adding process. FIG. 8 shows, as an example, a wafer stack obtained by performing the series of steps twice.

In this semiconductor device manufacturing method, next, a grinding step is performed as shown in FIG. Specifically, the surface 11b side of the wafer 11 is ground to remove the multilayer resin portion 30, and then the wafer 11 is thinned to a predetermined thickness. The thickness of the wafer 11 after thinning is, for example, 5 to 400 μm. After that, external connection bumps (not shown) may be formed on the surface 12a side of the wafer 12 that is stacked last. Alternatively, through electrodes (not shown) that penetrate the wafer 11 after thinning and are electrically connected to the wiring structure (not shown) on the surface 11a side of the wafer 11 are formed, and the through electrodes are electrically connected. A connecting external connection bump (not shown) may be formed on the surface 11b of the wafer 11 .

As described above, a semiconductor device in which semiconductor elements are multi-layered in the thickness direction can be manufactured. This semiconductor device may be individualized by dicing.

In the wafer bonding step described above with reference to FIGS. Thin wafer 12 is bonded to relatively thick wafer 11 via adhesive layer 21 . In the wafer stack including the wafers 11 and 12 (with the supporting substrate S bonded to the wafer 12) obtained through such a wafer bonding process, for example, when the temperature is lowered to room temperature, the cured adhesive layer 21 The resistance of the wafer 12 itself to shrinkage of the adhesive layer 21 is less than that of the wafer 11 to the shrinkage of the adhesive layer 21 because the wafer 12 is thinner than the wafer 11 . However, the support substrate S bonded to the wafer 12 may compensate the wafer 12 for resistance to shrinkage of the cured adhesive layer 21 . Even if the thickness difference between the wafers 11 and 12 is large and the resistance of the wafer 12 itself to the shrinkage of the adhesive layer 21 after curing is considerably less than the resistance of the wafer 11, the wafer 11, The support substrate S bonded to the side of 12 opposite to the side to which the wafer 11 is bonded can compensate the wafer 12 for resistance to shrinkage of the adhesive layer 21 after curing. Therefore, in the wafer laminate (with the support substrate S bonded to the wafer 12) obtained through the wafer bonding process, the difference in thermal expansion coefficient between the wafers 11 and 12 and the adhesive layer 21 and the wafer 11 , 12 and the adhesive layer 21 are prevented from warping due to the asymmetric lamination structure.

In this semiconductor device manufacturing method, before the step (removal step) of separating and removing the support substrate S from the wafer 12 as described above with reference to FIG. , a step of forming the resin layer 31 on the surface 11b of the wafer 11 (resin layer forming step) is performed. After the resin layer forming step and the subsequent removing step, for example, in the wafer laminate at room temperature, the shrinkage stress of the adhesive layer 21 after curing acts on the surface 11a of the wafer 11, and A contraction stress of the resin layer 31 acts on the surface 11b of the wafer 11 . Therefore, even if the thickness difference between the two wafers 11 and 12 is large and the resistance of the wafer 12 to the shrinkage of the adhesive layer 21 after curing is considerably lower than the resistance of the wafer 11, the wafers 11 and 12 are The shrinkage stress of the adhesive layer 21 after curing acting on the surface 11a of the wafer 11 (acting on the wafer 11 so as to deform the end portion thereof toward the surface 11a) is applied to the surface 11b of the wafer 11. It is possible to reduce or offset the shrinkage stress of the resin layer 31 later. Therefore, the above-described configuration in which the resin layer forming process and the subsequent removing process are performed is a relatively thick wafer 11, a relatively thin wafer 12, and an adhesive layer 21 between these wafers 11 and 12. It is suitable for suppressing the occurrence of warping after the wafer stack including the wafer stack undergoing the removal process. The shrinkage stress of the cured adhesive layer 21 acting on the surface 11a of the wafer 11 is offset or sufficiently reduced by the shrinkage stress of the cured resin layer 31 acting on the surface 11b of the wafer 11. is a parameter related to the stress that the adhesive layer 21 exerts on its adherend, expressed by the coefficient of thermal expansion (α ₁ ), elastic modulus (E ₁ ), and thickness (t ₁ ) of the adhesive layer 21 The resin layer 31 is represented by the coefficient of thermal expansion (α ₂ ), elastic modulus (E ₂ ), and thickness (t ₂ ) of the resin layer 31 with respect to σ ₁ (=α ₁ ×E ₁ ×t ₁ ). The ratio (σ ₂ /σ ₁ ) of the parameter σ ₂ (=α ₂ ×E ₂ ×t ₂ ) relating to the stress acting on the adherend is preferably 0.8 to 1.2, more preferably 0.9 to 1.1, more preferably 0.95 to 1.05.

In the wafer adding process described above with reference to FIGS. 5A and 5B in this semiconductor device manufacturing method, an adhesive is applied onto the relatively thick wafer 11 in the wafer bonding process or the preceding wafer adding process. A relatively thin additional wafer 12 with a support substrate S bonded via a temporary adhesive layer 13 to the wafer 12 bonded via a layer 21 is bonded via a new adhesive layer 21 . are joined together. In the wafer stack including the wafer 11 and the plurality of wafers 12 (accompanied by the support substrate S bonded to the last stacked wafer 12) obtained through such a wafer addition process, the temperature was lowered to room temperature, for example. In that case, the resistance of each wafer 12 itself to shrinkage of each cured adhesive layer 21 is less than the resistance of wafer 11 to shrinkage of the cured adhesive layer 21 because each wafer 12 is thinner than wafer 11 . However, each wafer 12 may be supplemented with a support substrate S in the stiffening wafer 12R for resistance to shrinkage of the cured adhesive layer 21 . Even if the thickness difference between the wafer 11 and each wafer 12 is large, the resistance of each wafer 12 itself to the shrinkage of each adhesive layer 21 after curing is considerably smaller than the resistance of the wafer 11. However, the support substrate S in the reinforcing wafer 12R can compensate each wafer 12 for resistance to shrinkage of each adhesive layer 21 after curing. Therefore, in the wafer stack (accompanied by the support substrate S bonded to the last stacked wafer 12) obtained through each wafer addition step, the wafer 11 and the plurality of wafers 12 exhibiting mutually different thermal expansion coefficients. The occurrence of warping due to the predetermined asymmetric lamination configuration with the plurality of adhesive layers 21 is suppressed.

In this semiconductor device manufacturing method, before the step (removing step) of separating and removing the supporting substrate S from the wafer 12 in the reinforcing wafer 12R that has undergone the wafer adding step (removing step), the resin layer 31 on the surface 11b side of the wafer 11 has A step of forming an additional resin layer 31 (resin layer adding step) is performed. After the resin layer addition process and the subsequent removal process, the shrinkage stress of each adhesive layer 21 located on the surface 11a side of the wafer 11 directly or indirectly affects the wafer laminate at room temperature, for example. The contraction stress of each resin layer 31 of the multilayer resin portion 30 that is in close contact with the surface 11b of the wafer 11 acts on the surface 11a of the wafer 11 and acts on the surface 11b of the wafer 11 together. Then, in a state where the wafer laminate during the manufacturing process does not involve the supporting substrate S of the reinforcing wafer 12R, the total number of the adhesive layers 21 on the surface 11a side of the wafer 11 and the total number of the resin layers 31 on the surface 11b side are are the same. Therefore, even if the difference in thickness between the wafer 11 and each wafer 12 is large, the resistance of each wafer 12 to shrinkage of each adhesive layer 21 after curing is considerably smaller than the resistance of each wafer 11. However, the total shrinkage stress of each adhesive layer 21 acting on the surface 11a side of the wafer 11 (which acts on the wafer 11 so as to deform the end portion thereof toward the surface 11a side) is It is possible to reduce or cancel out the total shrinkage stress of each resin layer 31 acting on the side. Therefore, the above-described configuration in which the resin layer addition step and the subsequent removal step are performed for each wafer addition step requires a relatively thick wafer 11, a plurality of relatively thin wafers 12, and a plurality of relatively thin wafers 12, each of which is interposed between the wafers. It is suitable for suppressing the occurrence of warpage after the detachment process in a wafer laminate including a plurality of adhesive layers 21 which are bonded together. The total shrinkage stress of each adhesive layer 21 acting on the surface 11a of the wafer 11 is offset or sufficiently reduced by the total shrinkage stress of the multilayer resin portion 30 or each resin layer 31 acting on the surface 11b of the wafer 11. From this point of view, the thermal expansion coefficient (α ₁ ), the elastic modulus (E ₁ ), and the thickness (t ₁ ) in one adhesive layer 21 additionally formed in each wafer addition process are represented by The adhesive layer 21 is additionally formed in the resin layer adding process performed according to the wafer adding process with respect to the parameter σ ₁ (=α ₁ ×E ₁ ×t ₁ ) related to the stress acting on the adherend. The resin layer 31 is expressed by the coefficient of thermal expansion (α ₂ ), the modulus of elasticity (E ₂ ), and the thickness (t ₂ ) of the resin layer 31, which is related to the stress acting on the adherend. The value of the ratio (σ ₂ /σ ₁ ) of the parameter σ ₂ (=α ₂ ×E ₂ ×t ₂ ) is preferably 0.8 to 1.2, more preferably 0.9 to 1.1, and more preferably is between 0.95 and 1.05.

As described above, this semiconductor device manufacturing method is suitable for suppressing the occurrence of warpage in the wafer stack during the manufacturing process. In the WOW process, as the number of stacked wafers increases, the degree of warpage of the wafer stack tends to accumulate. It is suitable. Further, the smaller the degree of warpage in the wafer stack during the manufacturing process, the easier it is to perform various processing (for example, the above-described various processing for forming the through electrodes 41) on the wafer stack with high accuracy. It is easy to increase the number of layers in the laminated body and, in turn, increase the number of semiconductor elements in the semiconductor device to be manufactured. Therefore, this semiconductor device manufacturing method is suitable for multilayering semiconductor elements. The wafer laminate or semiconductor device obtained through the resin layer forming step in the present semiconductor device manufacturing method is suitable for multi-layering of semiconductor elements.

[Example 1]
<Preparation of adhesive composition>
100 parts by mass of an epoxy group-containing polyorganosilsesquioxane obtained as described below, 115 parts by mass of propylene glycol monomethyl ether acetate, and an antimony-based sulfonium salt (trade name “SI-150L”, Sanshin Chemical Industry Co., Ltd. Company) 0.1 parts by mass and (4-hydroxyphenyl) dimethylsulfonium methyl sulfite (trade name “San-Aid SI Auxiliary”, manufactured by Sanshin Chemical Industry Co., Ltd.) 0.01 parts by mass are mixed and adhered. An adhesive composition (adhesive composition C) was obtained.

<Synthesis of polyorganosilsesquioxane>
In a 300 mL flask equipped with a reflux condenser, a nitrogen gas inlet, a stirrer, and a thermometer, 161 of 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane was added while introducing nitrogen gas. 5 mmol (39.79 g), 9 mmol (1.69 g) of phenyltrimethoxysilane, and 165.9 g of acetone as a solvent were mixed and heated to 50°C. Next, 4.7 g of a 5% potassium carbonate aqueous solution (1.7 mmol as potassium carbonate) was added dropwise to the mixture over 5 minutes, followed by dropwise addition of 1700 mmol (30.6 g) of water over 20 minutes. No significant temperature rise occurred in the mixture during the dropping operation. After the dropping operation, a polycondensation reaction was performed at 50° C. for 4 hours while introducing nitrogen gas into the flask. Analysis of the product in the reaction solution after the polycondensation reaction revealed a number average molecular weight of 1,900 and a molecular weight dispersity of 1.5. Then, the reaction solution left to stand and cooled was repeatedly washed with water until the lower layer liquid (aqueous phase) generated by phase separation became neutral, and then the upper layer liquid was separated and subjected to solvent treatment under the conditions of 1 mmHg and 40°C. The solvent was distilled off from the upper layer liquid until the amount reached 25% by mass to obtain a colorless and transparent liquid product (epoxy group-containing polyorganosilsesquioxane).

<Fabrication of wafer laminate>
First, a first silicon wafer and a second reinforced silicon wafer were prepared. The first silicon wafer has a diameter of 300 mm and a thickness of 775 μm, and one surface thereof is treated with a silane coupling agent. In the silane coupling agent treatment of the first silicon wafer, a silane coupling agent (trade name “KBE403”, manufactured by Shin-Etsu Chemical Co., Ltd.) was applied to one surface of the first silicon wafer by spin coating, and then Heating at 120° C. for 5 minutes was performed. A reinforced second silicon wafer was produced as follows.

First, on a silicon substrate (300 mm in diameter, 775 μm in thickness) serving as a supporting substrate, an adhesive composition for forming a temporary adhesive layer was applied by spin coating to form a temporary adhesive composition layer, which was heated at 200°C. The composition layer was dried by heating for 2 minutes followed by heating at 230° C. for 4 minutes to form a temporary adhesive layer. The adhesive composition for forming the temporary adhesive layer includes 0.24 parts by mass of diethylene glycol divinyl ether, p-hydroxystyrene/styrene copolymer (trade name "Marukalinker CST-50", p-hydroxystyrene and styrene The molar ratio is 50:50, the weight average molecular weight is 4400, the softening point is 150 ° C., manufactured by Maruzen Petrochemical Co., Ltd.) 5.4 parts by mass, and polyvinyl butyral resin (trade name “S-Lec KS-1”, molecular weight is 2 .7×10 ⁴ , a thermoplastic resin having a softening point of 200° C., manufactured by Sekisui Chemical Co., Ltd.) and 1.8 parts by mass of polycaprolactone (trade name “PLAXEL H1P”, weight average molecular weight of 10,000, softening point of 100 ℃ thermoplastic resin, manufactured by Daicel Co., Ltd.) 1.8 parts by mass, trans cinnamic acid (pKa is 4.44, manufactured by Wako Pure Chemical Industries, Ltd.) 0.18 parts by mass as a polymerization accelerator, and surfactant It was prepared by mixing 0.045 parts by mass of a fluorine-based oligomer (trade name “F-554”, manufactured by DIC Corporation) as an agent and 22 parts by mass of cyclohexanone as a solvent. Next, the silicon substrate and a second silicon wafer (300 mm in diameter, 775 μm in thickness) were bonded via a temporary adhesive layer. Specifically, the silicon substrate and the second silicon wafer are pressed together via a temporary adhesive layer while applying pressure at a temperature of 150° C. and a pressure of 3000 g/cm ² , and then heated at 230° C. for 5 minutes. Then, the silicon substrate and the second silicon wafer were bonded via the temporary adhesive layer. Next, the second silicon wafer was thinned to a thickness of 10 μm by grinding the second silicon wafer supported by the silicon substrate using a grinder (manufactured by Disco Co., Ltd.). . Next, a silane coupling agent (trade name “KBE403”, manufactured by Shin-Etsu Chemical Co., Ltd.) was applied by spin coating to the surface (grinding surface) of the thinned second silicon wafer, and then heated at 120°C for 5 minutes. A minute of heating was performed (silane coupling agent treatment). The above-mentioned reinforced second silicon wafer is produced in this way.

In the production of the wafer laminate, next, the adhesive composition C was applied to the silane coupling agent-treated surface (first surface) of the first silicon wafer by spin coating to form an adhesive composition layer. Afterwards, the first silicon wafer with this composition layer was heated at 80° C. for 4 minutes, followed by heating at 100° C. for 2 minutes. This dried the adhesive composition layer to form an adhesive layer with a thickness of 2.5 μm on the first surface of the first silicon wafer. Next, the first silicon wafer with the adhesive layer and the thinned wafer of the reinforcing wafer are bonded together while applying pressure via the adhesive layer on the first silicon wafer, and then at 150° C. for 30 minutes. followed by heating at 170° C. for 30 minutes to cure and join the adhesive layer. The bonding was performed under conditions of a temperature of 50° C. and a pressure of 3000 g/cm ² .

In the production of the wafer laminate, next, a resin layer was formed on the surface (second surface) of the first silicon wafer opposite to the bonding surface (first surface) of the second silicon wafer. Specifically, first, a silane coupling agent (trade name “KBE403”, manufactured by Shin-Etsu Chemical Co., Ltd.) was first applied to the second surface of the first silicon wafer by spin coating, and then heated at 120° C. for 5 minutes. was performed (silane coupling agent treatment). Next, an adhesive composition C for forming a resin layer was applied to the silane coupling agent-treated surface (second surface) of the first silicon wafer by spin coating to form an adhesive composition layer, and then heated at 80°C. Heating was performed for 4 minutes, followed by heating at 100° C. for 2 minutes to dry the adhesive composition layer. Next, the first silicon wafer with this composition layer was heated at 150° C. for 30 minutes, followed by heating at 170° C. for 30 minutes. Thereby, the adhesive composition layer was dried and cured to form a resin layer having a thickness of 2.5 μm on the second surface of the first silicon wafer.

Next, the temporary adhesive state by the temporary adhesive layer between the silicon substrate serving as the support substrate and the thinned second silicon wafer was released, and the silicon substrate was removed from the second silicon wafer. Specifically, after undergoing a heat treatment at 235° C. for 5 minutes, the silicon substrate was slid against the second silicon wafer at a relative speed of 1 mm/sec to obtain a second silicon wafer or a wafer stack including the same. Removed the silicon substrate from the After that, the temporary adhesive residue on the second silicon wafer was washed off using propylene glycol monomethyl ether. As described above, the wafer laminate of Example 1 was produced.

For the wafer laminate of this example, using a shape measuring device (trade name "LTV-3000", manufactured by Kobelco Research Institute, Inc.), the SORI (warp Amount) was measured to be 9.5 μm. In this measurement, a least-squares reference plane is calculated from the surface shape data of the object to be measured, which is obtained by correcting the self-weight deflection of the object. and the minimum value.

<Film thickness measurement>
The above adhesive composition C was applied onto a silicon wafer (300 mm in diameter, 775 μm in thickness) by spin coating to form an adhesive composition layer. The amount of adhesive composition C used for one spin coating was 20 g, and the rotation speed for spin coating was 1200 rpm. Then, the adhesive composition layer on the substrate was heated at 80° C. for 4 minutes and then at 100° C. for 2 minutes to dry the adhesive composition layer. Next, heating was performed at 150° C. for 30 minutes, followed by heating at 170° C. for 30 minutes, thereby forming a cured coating film on the substrate. The thickness of the formed coating film was measured using a fine shape measuring machine (trade name: "Surfcorder ET 4000A", manufactured by Kosaka Laboratory Ltd.) and found to be 2.5 µm. In addition to including such a cured coating as an adhesive layer bonding the first and second silicon wafers, the above-described wafer stack of Example 1 adheres closely to the second surface of the first silicon wafer. It is also included as a resin layer.

<Thermal expansion coefficient measurement>
After applying the above adhesive composition C on a silicon wafer (diameter 300 mm, thickness 775 μm) by spin coating to form an adhesive composition layer, the adhesive composition layer on the substrate was heated at 80 ° C. for 4 minutes, followed by heating at 100° C. for 2 minutes to dry the adhesive composition layer. Next, heating was performed at 150° C. for 30 minutes, followed by heating at 170° C. for 30 minutes, thereby forming a cured coating film (2.5 μm thick) on the substrate. The coefficient of thermal expansion of this coating film was determined based on film thickness data from 25° C. to 250° C. measured using a thermal expansion coefficient measuring device (trade name “Spectroscopic Ellipsometer”, manufactured by SCI). It was 68 ppm/°C.

<Elastic modulus measurement>
After applying the above adhesive composition C on a silicon wafer (diameter 300 mm, thickness 775 μm) by spin coating to form an adhesive composition layer, heating was performed at 80 ° C. for 4 minutes, followed by 100 ° C. for 2 minutes to dry the adhesive composition layer. Next, the adhesive composition layer on the substrate is heated at 150° C. for 30 minutes, followed by heating at 170° C. for 30 minutes, thereby forming a cured coating film (2.5 μm thick). ) was formed on the substrate. The elastic modulus of this coating film was measured using a microhardness tester (trade name: ENT-2100, manufactured by Elionix Co., Ltd.) and found to be 4.9 GPa.

[Comparative Example 1]
A wafer laminate of Comparative Example 1 was produced in the same manner as the wafer laminate of Example 1, except that the resin layer was not formed on the second surface of the first silicon wafer. For the wafer laminate of this comparative example, the amount of warpage was measured using a shape measuring device (trade name "LTV-3000", manufactured by Kobelco Research Institute, Inc.) in the same manner as for the wafer laminate of Example 1. It was 47.4 μm.

[evaluation]
In the wafer stack of Example 1, the warp was reduced to about 1/5 compared with the wafer stack of Comparative Example 1. Further, in the wafer laminate of Example 1, the thickness (t ₁ ) of the adhesive layer between the wafers was 2.5 μm as described above, and from the results of the above-described thermal expansion coefficient measurement and elastic modulus measurement, As can be seen, the coefficient of thermal expansion (α ₁ ) of the adhesive layer or coating is 68 ppm/° C. and the elastic modulus (E ₁ ) is 4.9 GPa. Along with this, in the wafer laminate of Example 1, the thickness (t ₂ ) of the resin layer formed on the second surface of the first silicon wafer was 2.5 μm as described above, and the heat treatment described above was performed. As can be understood from the results of expansion coefficient measurement and elastic modulus measurement, the resin layer or coating film has a thermal expansion coefficient (α ₂ ) of 68 ppm/°C and an elastic modulus (E ₂ ) of 4.9 GPa. That is, in the wafer laminate of Example 1, the first silicon wafer for the parameter σ ₁ (=α ₁ ×E ₁ ×t ₁ ) relating to the stress that the adhesive layer between the wafers acts on the adherend. The ratio (σ ₂ /σ ₁ ) of the parameter σ ₂ (=α ₂ ×E ₂ ×t ₂ ) relating to the stress acting on the adherend by the resin layers on the two surfaces is one. Therefore, in the wafer laminate of Example 1, the shrinkage stress of the adhesive layer after curing acting on the first surface of the first silicon wafer causes the resin layer after curing acting on the second surface of the first silicon wafer. is sufficiently reduced by the shrinkage stress of .

S support substrate 11 wafer (first wafer)
11a surface (first surface)
11b surface (second surface)
12R reinforced wafer (second reinforced wafer)
12 wafer (second wafer)
12a surface 12b surface 13 temporary adhesive layer 21 adhesive layer 30 multilayer resin portion 31 resin layer 41 through electrode

Claims (5)

A first wafer having a first side and a second side opposite to the first side, a second wafer thinner than the first wafer, a support substrate, and temporary bonding between the second wafer and the support substrate providing a reinforced second wafer having a laminated structure including an agent layer;
bonding the second wafer of the reinforcing second wafer to the first surface of the first wafer via an adhesive layer;
forming a resin layer on the second surface of the first wafer;
and removing the support substrate by releasing the temporary adhesive state between the support substrate and the second wafer by the temporary adhesive layer ,
A parameter σ ₁ related to the stress that the adhesive layer exerts on its adherend, expressed by the coefficient of thermal expansion (α ₁ ), elastic modulus (E ₁ ), and thickness (t ₁ ) of the adhesive layer The resin layer is expressed by the coefficient of thermal expansion (α ₂ ), the elastic modulus (E ₂ ), and the thickness (t ₂ ) of the resin layer with respect to (=α ₁ ×E ₁ ×t ₁ ). A method of manufacturing a semiconductor device, wherein a ratio (σ ₂ /σ ₁ ) of a parameter σ ₂ (=α ₂ ×E ₂ ×t ₂ ) relating to stress acting on an object is 0.8 to 1.2 . The second wafer in the reinforced second wafer having a laminated structure including a second wafer thinner than the first wafer, a support substrate, and a temporary adhesive layer between the second wafer and the support substrate, at least one wafer addition step of bonding to a second wafer on the wafer via an adhesive layer;
forming an additional resin layer on at least one resin layer on the second surface side of the first wafer;
At least one step of removing the support substrate by canceling the temporary adhesive state by the temporary adhesive layer between the support substrate and the second wafer, which is performed for each of the wafer addition steps ;
The adhesive layer , which is expressed by the coefficient of thermal expansion (α ₁ ), the modulus of elasticity (E ₁ ), and the thickness (t ₁ ) of the adhesive layer additionally formed in each wafer addition process, is One resin layer additionally formed in the resin layer adding process performed according to the wafer adding process with respect to the parameter σ ₁ (=α ₁ ×E ₁ ×t ₁ ) related to the stress acting on the adherend A parameter σ ₂ ( ₌ α ₂ × _{_ _} 2. The method of manufacturing a semiconductor device according to claim 1, wherein the ratio (σ ₂ /σ ₁ ) of E ₂ ×t ₂ ) is 0.8 to 1.2 . 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of thinning said first wafer by grinding said second surface of said first wafer. a first wafer having a first side and a second side opposite the first side;
a second wafer located on the first surface side of the first wafer and thinner than the first wafer;
an adhesive layer interposed between the first and second wafers;
and a resin layer in close contact with the second surface of the first wafer ,
A parameter σ ₁ related to the stress that the adhesive layer exerts on its adherend, expressed by the coefficient of thermal expansion (α ₁ ), elastic modulus (E ₁ ), and thickness (t ₁ ) of the adhesive layer The resin layer is expressed by the coefficient of thermal expansion (α ₂ ), the elastic modulus (E ₂ ), and the thickness (t ₂ ) of the resin layer with respect to (=α ₁ ×E ₁ ×t ₁ ). A semiconductor device in which a ratio (σ ₂ /σ ₁ ) of a parameter σ ₂ (=α ₂ ×E ₂ ×t ₂ ) relating to stress acting on an adherent is 0.8 to 1.2 . a first wafer having a first side and a second side opposite the first side;
a plurality of second wafers, each thinner than the first wafer, positioned on the first surface side of the first wafer and arranged in the thickness direction of the first wafer;
a plurality of adhesive layers, each interposed between and bonding adjacent wafers;
a multi-layered resin portion including resin layers stacked in the thickness direction of the first wafer, the same number as the total number of the adhesive layers, and in close contact with the second surface of the first wafer; has a laminated structure containing
The coefficient of thermal expansion (α ₁ ) and the modulus of elasticity ( E ₁ ) and thickness ( t ₁ ) _{, the first _} Expressed by the coefficient of thermal expansion (α ₂ ), the modulus of elasticity (E ₂ ), and the thickness (t ₂ ) of the n-th (n is the same integer as m) resin layer from the second surface side of the wafer The value of the ratio (σ ₂ /σ ₁ ) of the parameter σ ₂ (=α ₂ ×E ₂ ×t ₂ ) related to the stress that the resin layer acts on the adherend is 0.8 to 1. 2 semiconductor device.

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