JP7140718B2 - Solid-state imaging device and method for manufacturing solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device, and more particularly to a pad portion.

2. Description of the Related Art In CCD-type or amplification-type solid-state imaging devices used in digital still cameras, camcorders, etc., miniaturization of pixels is required in order to obtain high-definition images. However, the finer the pixels, the smaller the light-receiving area of the photoelectric conversion elements for detecting the light contained in the pixels, resulting in lower sensitivity.
Patent Document 1 discloses a CMOS-type solid-state imaging device, which is an amplification type, in which a first substrate on which a photoelectric conversion element and a transfer transistor are arranged and a second substrate on which other circuits are arranged in order to secure a light receiving area of the photoelectric conversion element. A configuration is disclosed in which two substrates are bonded to form a solid-state imaging device. In the solid-state imaging device disclosed in Patent Literature 1, a connecting portion penetrating through the second substrate is connected to a pad (input/output pad), and the pad is connected from the rear surface side of the second substrate. This pad is formed on the rear surface of the second substrate after the second substrate is polished to expose the second connecting portion.
In addition, Patent Literature 2 discloses a method of manufacturing an electronic component in which a first substrate having an image sensor and a first conductive area is bonded to a second substrate having an integrated circuit and a second conductive area. . After bonding the first substrate and the second substrate, the first conductive area and the second conductive area are exposed, and a further conductive layer is deposited to electrically connect the first conductive area and the second conductive area. is disclosed to form a A first conductive area or layer is used as a pad (external connection pad).

JP 2006-191081 A Japanese Patent Publication No. 2010-514177

In the configuration as disclosed in Patent Document 1, the electric path connecting the pads and the first substrate becomes long. As a result, there is a possibility that the performance will be degraded due to the increase in connection resistance, or the reliability of the connection between the pad and the first substrate will be degraded. In the configuration as disclosed in Patent Document 2, the reliability of the connection between the pad and the second conductive area is lowered.
Further, in the manufacturing method of Patent Document 1, a step of providing a liner for separating the connection portion and the second substrate, a step of polishing the second substrate, and a step of forming the input/output pads are required. It gets complicated. In the manufacturing method of Patent Document 2, a step of providing openings with different depths for the first conductive area and the second conductive area is required, which complicates the process.
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a solid-state imaging device having a highly reliable connection between a pad and a circuit. It is another object of the present invention to provide a method of manufacturing a solid-state imaging device that allows easy connection between pads and circuits.

The present invention provides a first semiconductor substrate on which a photoelectric conversion element and a first semiconductor element are arranged, a second semiconductor substrate on which a second semiconductor element and a third semiconductor element are arranged, the first semiconductor substrate and the second semiconductor substrate. a first wiring structure arranged between a semiconductor substrate; a second wiring structure arranged between the first wiring structure and the second semiconductor substrate; and the first semiconductor substrate and the second semiconductor substrate. and a pad connected to the third semiconductor element and not connected to the semiconductor element provided on the first semiconductor substrate, the pad being arranged between the first semiconductor element and the second semiconductor element. The method of manufacturing a solid-state imaging device comprises preparing a member electrically connected to a semiconductor element, and forming an opening penetrating through the first semiconductor substrate and reaching the pad.

According to the present invention, it is possible to improve the reliability of the connection between the pad and the semiconductor element . Also, according to the present invention, it becomes possible to easily form the connection between the pad and the semiconductor element .

1 is a schematic cross-sectional view of a solid-state imaging device according to Example 1. FIG. 1 is a schematic plan view of a solid-state imaging device in Example 1. FIG. 1 is a circuit diagram of a solid-state imaging device according to Example 1; FIG. 4A and 4B are cross-sectional schematic diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment; 4A and 4B are cross-sectional schematic diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment; 4A and 4B are cross-sectional schematic diagrams illustrating a method for manufacturing the solid-state imaging device according to the first embodiment; FIG. 10 is a schematic cross-sectional view of a solid-state imaging device according to Example 2; 8A and 8B are a schematic cross-sectional view of a solid-state imaging device according to Example 3 and a schematic cross-sectional view for explaining a method of manufacturing the solid-state imaging device; FIG. 11 is a schematic cross-sectional view of a solid-state imaging device according to Example 4;

The solid-state imaging device of the present invention comprises a first semiconductor substrate having a photoelectric conversion element disposed on its surface and a second semiconductor substrate having at least a part of a circuit for generating a signal based on the charge of the photoelectric conversion element disposed on its surface. a substrate; The surface of the first semiconductor substrate and the surface of the second semiconductor substrate are arranged so as to face each other. A wiring structure is arranged between the first semiconductor substrate and the second semiconductor substrate. The solid-state imaging device has pads to which external terminals are connected, and the external terminals are connected to the first surfaces of the pads.
In the first solid-state imaging device, the first surface of the pad is positioned between a virtual plane including the surface of the first semiconductor substrate and parallel to the surface and the surface of the second semiconductor substrate, and is opposite to the first surface. is located between the first surface and the surface of the second semiconductor substrate. A second surface of the pad is connected to the wiring structure such that the pad connects through the wiring structure to a peripheral circuit disposed on the second semiconductor substrate.
In the second solid-state imaging device, part of the peripheral circuit is arranged on the first semiconductor substrate. The first surface of the pad is positioned between the surface of the first semiconductor substrate and a virtual plane including the surface of the second semiconductor substrate and parallel to the surface, and is the surface opposite to the first surface. The second surface is located between the first surface and the surface of the first semiconductor substrate. The second surface of the pad is connected to the wiring structure such that the pad connects through the wiring structure to a portion of the peripheral circuit disposed on the first semiconductor substrate, and the peripheral circuit disposed on the first semiconductor substrate. A part is connected to a part of the peripheral circuit arranged on the second semiconductor substrate through the wiring structure.
According to such a configuration, it is possible to provide a solid-state imaging device in which the connection between the pads and the peripheral circuit is highly reliable.

Moreover, the manufacturing method of the solid-state imaging device of the present invention has a step of bonding the first member and the second member. The first member has a first semiconductor substrate having a photoelectric conversion element disposed thereon and a first wiring structure disposed on the surface of the first semiconductor substrate. The second member includes a second substrate on which at least part of a peripheral circuit for generating a signal based on the charge of the photoelectric conversion element is arranged, and a second wiring structure arranged on the surface of the second semiconductor substrate. have The laminating step is performed to connect the first wiring structure and the second wiring structure. A step of thinning the first semiconductor substrate from the back surface side of the first semiconductor substrate is provided after the step of laminating. Before the bonding step, the first wiring structure or the second wiring structure is connected with a pad connected to an external terminal, and after the thinning step, the step of exposing the pad to the first semiconductor substrate side is performed. have.
Such a manufacturing method makes it possible to facilitate the formation of connections between pads and peripheral circuits.

Hereinafter, the present invention will be described in detail with reference to the drawings. The above-described first solid-state imaging device will be described using Examples 1 to 3, and the second solid-state imaging device will be described using Example 4. In the description of the embodiments, the principal surface of the first substrate and the principal surface of the second substrate are the surfaces of the substrates. For each substrate, the surface opposite to the main surface (front surface) is the back surface of the first substrate and the back surface of the second substrate. In each substrate, the upward direction is the direction from the rear surface to the main surface (front surface), and the downward direction and the depth direction are the directions from the main surface (front surface) to the rear surface of the substrate. As a solid-state imaging device, it is assumed that the first substrate is arranged on the second substrate in accordance with the display direction of the drawing, and the direction from the second substrate to the first substrate is upward, and from the first substrate to the second substrate. In some cases, the direction toward the

(Example 1)
Embodiment 1 of the present invention will be described with reference to FIGS. 1 to 6. FIG.

First, the circuit of the solid-state imaging device according to the first embodiment will be described with reference to FIG. In this embodiment, the case where the signal charges are, for example, electrons will be described. The solid-state imaging device in FIG. 3 has a pixel portion 301 in which a plurality of photoelectric conversion elements are arranged. In addition, a peripheral circuit portion 302 including peripheral circuits including a readout circuit for reading out signals from the pixel portion 301, a control circuit for driving the pixel portion 301 and the readout circuit, and a signal processing circuit for processing the readout signal is provided. .
In the pixel portion 301, a plurality of photoelectric conversion elements 303, transfer transistors 304, amplification transistors 306, and reset transistors 307 are arranged. A structure including at least one photoelectric conversion element 303 is referred to as a pixel. One pixel of this embodiment includes a photoelectric conversion element 303 , a transfer transistor 304 , an amplification transistor 306 and a reset transistor 307 . The anode of the photoelectric conversion element 303 is grounded. The source of the transfer transistor 304 is connected to the cathode of the photoelectric conversion element 303 , and the drain region of the transfer transistor 304 is connected to the gate electrode of the amplification transistor 306 . The same node as the gate electrode of this amplification transistor 306 is assumed to be a node 305 . The reset transistor connects to node 305 and sets the potential of node 305 to an arbitrary potential (eg, reset potential). Here, the amplification transistor 306 is part of a source follower circuit and outputs a signal corresponding to the potential of the node 305 to the signal line RL. Node 305 may also be referred to as a floating diffusion. A circuit including the transfer transistor 304, the amplification transistor 306, and the reset transistor 307 is a pixel circuit.
A peripheral circuit portion 302 indicates a region other than the pixel portion 301 . Peripheral circuits including a readout circuit and a control circuit are arranged in the peripheral circuit section 302 . The peripheral circuit has a vertical scanning circuit VSR which is a control circuit for supplying control signals to the gate electrodes of the transistors of the pixel section 301 . The peripheral circuit also has a readout circuit RC that holds signals output from the pixel unit 301 and performs signal processing such as amplification, addition, and AD conversion. The peripheral circuit also has a horizontal scanning circuit HSR which is a control circuit for controlling the timing of sequentially outputting signals from the readout circuit RC.

Here, the solid-state imaging device of Example 1 is configured by bonding two members together. The two members are a first member 308 having a first substrate 101 and a second member 309 having a second substrate 121 . Photoelectric conversion elements 303 and transfer transistors 304 of the pixel section 301 are arranged on the first substrate 101 , and amplification transistors 306 and reset transistors 307 of the pixel section 301 and a peripheral circuit section 302 are arranged on the second substrate 121 . and are arranged. A control signal from the peripheral circuit section 302 of the second member 309 to the gate electrode of the transfer transistor 304 of the first member 308 is supplied via the connection section 310 . A configuration of the connection unit 310 will be described later. A signal generated by the photoelectric conversion element 303 of the first member 308 is read out to the drain region of the transfer transistor 304 , ie, the node 305 . Node 305 includes a structure disposed on first member 308 and a structure disposed on second member 309 .
With such a structure, the area of the photoelectric conversion element 303 can be increased and the sensitivity can be improved as compared with the conventional case where all the pixel portions are arranged on one member (that is, one substrate). Become. Further, compared to the conventional case where all the pixel portions are arranged on one member (that is, one substrate), if the areas of the photoelectric conversion elements are the same, more photoelectric conversion elements 303 can be provided. Pixelation becomes possible. Note that at least a photoelectric conversion element may be arranged on the first substrate, and the amplification transistor 306 may be arranged on the first substrate. Alternatively, the photoelectric conversion element may be connected to the gate electrode of the amplification transistor without providing the transfer transistor. In the present invention, the elements arranged on the first substrate can be arbitrarily selected, and the configuration of the pixel circuit can also be arbitrarily selected.

A specific planar layout of such a solid-state imaging device will be described with reference to the schematic plan view of the solid-state imaging device in FIG. FIG. 2A shows the planar layout of the first member 308, namely the first substrate (101), and FIG. 2B shows the planar layout of the second member 309, namely the second substrate (121).

In FIG. 2A, the first member 308 is provided with a pixel portion 301A in which a plurality of photoelectric conversion elements are arranged and a pad portion 312A in which a pad 313 is provided. In the pixel portion 301A, a plurality of photoelectric conversion elements 303, transfer transistors 304, and connection portions 310 and 311 in FIG. 3 are arranged. In addition, a connection portion 314A for connection with the second member 309 is arranged at the same position as the pad 313 in the plane of the pad portion 312A. An external terminal is connected to the pad 313 . An example of the external terminal is a bonding wire connected to the pad 313 by wire bonding. A plurality of pads 313 are arranged in the solid-state imaging device, and include pads (output pads) for outputting signals (image signals) based on charges generated by photoelectric conversion elements, and voltages supplied from the outside for driving peripheral circuits. A pad (input pad) for inputting such as is included.

Next, in FIG. 2B, the second member 309 is provided with a pixel portion 301B, a peripheral circuit portion 302, and a pad portion 312B. A part of the pixel circuit is arranged in the pixel portion 301B, and the amplification transistor 306, the reset transistor 307, the connection portion 310, and the connection portion 311 in FIG. 3 are arranged in plurality. A part of the peripheral circuit is arranged in the peripheral circuit section 302, and a horizontal scanning circuit HSR, a vertical scanning circuit VSR, and a reading circuit RC are arranged. Pad section 312B has protection diode circuit 315 . A connection portion 314B for connection with the first member 308 is arranged in the pad portion 312B at the same position as the protection diode circuit 315 in plan view. The protection diode circuit 315 and the connection portion 314B do not have to be arranged at the same position in a plane. The protection diode circuit 315 is connected with peripheral circuits. Specifically, a plurality of protective diode circuits 315 are provided as shown in FIG. 2B, and the protective diode circuits 315 connected to each pad 313 are connected to the vertical scanning circuit VSR and the horizontal scanning circuit HSE, respectively. , or connected to a readout circuit RC. As described above, the second substrate 121 is provided with the pixel circuits arranged in the pixel section 301, the peripheral circuits arranged in the peripheral circuit section 302, and the protective diode circuits arranged in the pad section 312B. there is These circuits are semiconductor integrated circuits, and are composed of a large number of semiconductor elements including transistors, diodes, resistance elements, capacitive elements, and the like. A signal based on the charge (signal charge) of the photoelectric conversion element 303 is generated by operating the integrated circuit composed of the semiconductor element.

A first member 308 and a second member 309 having the planar layouts shown in FIGS. 2A and 2B are bonded together to form the solid-state imaging device of this embodiment. Specifically, the pixel portion 301A and the pixel portion 301B are arranged so as to overlap each other. The connection portion 314A and the connection portion 314B are connected, and the connection portions 310 and 311 of the first member are connected to the connection portions 310 and 311 of the second member. In FIG. 2, the area of the first member 308 corresponding to the peripheral circuit section 302B of the second member 309 is indicated by the peripheral circuit section 302A. A part of the scanning circuit, that is, a part of the peripheral circuit may be arranged in the peripheral circuit section 302A.

Next, a schematic cross-sectional view of the solid-state imaging device shown in FIGS. 2 and 3 will be described with reference to FIG. In FIG. 1, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals, and descriptions thereof are omitted.

The first member 308 has a first wiring structure 149 and a first substrate 101 . The first substrate 101 is, for example, a silicon semiconductor substrate and has a main surface 102 and a back surface 103 . A transistor is arranged on the main surface 102 of the first substrate. The first wiring structure 149 includes interlayer insulating films 104 to 106, a gate electrode layer 107 including gate electrodes and wiring, wiring layers 109 and 111 including a plurality of wirings, a contact layer 108 including a plurality of contacts or vias, 110. Here, the number of layers of the interlayer insulating film, the wiring layer and the contact layer included in the first wiring structure 149 can be set arbitrarily. In this embodiment, the number of wiring layers is two. Note that the wiring layer 111 of the first wiring structure 149 includes a connecting portion.
In the pixel portion 301 of the first member 308, the n-type semiconductor region 112 constituting the photoelectric conversion element, the n-type semiconductor region 114 that is the drain of the transfer transistor, and the element isolation structure 119 are arranged on the first substrate 101. It is The transfer transistor is composed of an n-type semiconductor region 112 , an n-type semiconductor region 114 , and a gate electrode 113 included in the gate electrode layer 107 . Here, charges accumulated in the n-type semiconductor region 112 are transferred to the n-type semiconductor region 114 by the gate electrode 113 . The potential based on the charges transferred to the n-type semiconductor region 114 is transmitted to the second member 309 through the contact of the contact layer 108, the wiring of the wiring layer 109, the via of the contact layer 110, and the wiring of the wiring layer 111. . The wiring of this wiring layer 111 constitutes the connecting portion 311 . The photoelectric conversion element may be a buried photodiode further having a p-type semiconductor region, or may be a photogate, and can be changed as appropriate.

A planarization layer 115, a color filter layer 116 including a plurality of color filters, a planarization layer 117, and a microlens layer 118 including a plurality of microlenses are arranged in this order on the rear surface 103 side of the first substrate 101 of the pixel section 301. It is In FIG. 1, a plurality of color filters and a plurality of microlenses are arranged corresponding to one photoelectric conversion element, that is, each pixel, but one may be provided for each pixel. . The solid-state imaging device of this embodiment is a so-called back-illuminated solid-state imaging device in which light is incident from the microlens layer 118 side and received by the photoelectric conversion elements.

The pad portion 312 of the first member 308 is provided with a pad 313 and an opening 100 exposing the pad 313 for connection with an external terminal. In this embodiment, the pad 313 will be described as an example of the input pad. The pad 313 is a conductive film and has a first surface 3131 and a second surface 3132 opposite to the first surface. A first surface 3131 of the pad 313 is exposed on the first substrate 101 side, and an external terminal is connected to the first surface 3131 . Also, a connection portion 314A for transmitting the voltage input from the pad 313 to the second member 309 is arranged. The connecting portion 314A is arranged at the same position as the pad 313 in plan view. In the region of the first member 308 corresponding to the peripheral circuit section 302 of the second member 309, an arbitrary circuit element 120 is provided as shown in FIG.

The second member 309 has a second wiring structure 150 and a second substrate 121 . The second substrate 121 is, for example, a silicon semiconductor substrate and has a principal surface 122 and a back surface 123 . A transistor is arranged on the major surface 122 of the second substrate. The second wiring structure 150 includes interlayer insulating films 124 to 127, a gate electrode layer 128 including gate electrodes and wiring, wiring layers 130, 132 and 134 including a plurality of wirings, and a contact layer including a plurality of contacts or vias. 129, 131, 133. Here, the numbers of interlayer insulating films, wiring layers, and contact layers included in the second wiring structure 150 can be set arbitrarily. In this embodiment, the number of wiring layers in the second wiring structure 150 is three, which is more wiring layers than in the first wiring structure 149 . Note that the wiring layer 134 includes a connecting portion.
In the pixel portion 301 of the second member 309, the second substrate 121 includes a well 135 forming an amplifying transistor of the pixel circuit, an n-type semiconductor region 138 forming a source/drain region of the amplifying transistor, and an element isolation structure 136. and are arranged. The amplifying transistor is arranged in the well 135 and is composed of a gate electrode 137 included in the gate electrode layer 128 and an n-type semiconductor region 138 forming source/drain regions. Here, the connection portion 311 of the first member 308 and the gate electrode 137 of the amplification transistor are the wiring of the wiring layer 134, the via of the contact layer 133, the wiring of the wiring layer 132, the via of the contact layer 131, and the wiring of the wiring layer 130. , and contacts of the contact layer 129 . Here, the node 305 in FIG. 3 is the n-type semiconductor region 114 in FIG. , and the gate electrode 137 . Other circuits (eg, reset transistors) of the pixel unit 301 are not shown.

Next, in the peripheral circuit section 302 of the second member 309, at least part of peripheral circuits including control circuits such as horizontal scanning circuits and vertical scanning circuits and readout circuits are arranged. FIG. 1 shows an n-type transistor and a p-type transistor in an arbitrary circuit included in the peripheral circuit. An n-type transistor comprising a gate electrode 140 included in the gate electrode layer 128 and an n-type source/drain region 141 is arranged in the p-type well 139 . A p-type transistor having a gate electrode 143 included in the gate electrode layer 128 and a p-type semiconductor region 144 forming a p-type source/drain region is arranged in the n-type well 142 .
A protection diode circuit 315 for inputting a signal from the pad 313 of the first member 308 and a connection portion 314B for connection with the first member 308 are arranged on the pad portion 312 of the second member 309. ing. The connecting portion 314B and the protection diode circuit 315 are arranged at the same position in a plane. The protection diode circuit 315 of this embodiment includes two diodes 145 and 146 composed of semiconductor regions and two resistors 147 and 148 composed of the gate electrode layer 128 .

Resistor 147 is the input of protection diode circuit 315 and resistor 148 is the output of the protection diode. The protection diode circuit 315 has the following configuration. One end of the resistor 147 is connected to the pad 313 , and the other end of the resistor 147 is connected to the anode of the diode 145 , the cathode of the diode 146 and one end of the resistor 148 via the wiring layer 130 . The other end of the resistor 148 is connected to the circuit element 320 of the subsequent peripheral circuit section 302 (for example, the vertical scanning circuit VSR and the horizontal scanning circuit HSR). That is, at a node represented by the wiring layer 130, the other end of the resistor 147, the anode of the diode 145, the cathode of the diode 146, and one end of the resistor 148 are connected. The cathode of the diode 145 is connected to a predetermined voltage VDD by wiring (not shown), and the anode of the diode 146 is connected to a voltage VSS different from the predetermined voltage by wiring (not shown). Here, the voltage relationship is VDD>input voltage>VSS. Also, VSS may be a voltage lower than VDD, and may be the reference voltage GND. By providing such a protection diode circuit, for example, when a voltage higher than the sum of VDD and the forward voltage drop across the diode 145 is input to the pad 313, the diode 145 is forward biased and the node to VDD. Therefore, it is possible to prevent a voltage higher than the sum of VDD and the forward voltage drop in the diode 145 from being applied to the subsequent circuit. Also, when a voltage smaller than the forward voltage difference between VSS and diode 146 is input to the pad, diode 146 is forward biased and current flows from VSS to the node. Therefore, it is possible to prevent a voltage smaller than the difference between VSS and the forward voltage of the second diode 146 from being applied to the subsequent circuit. Note that the resistors 147 and 148 have the effect of decreasing the input voltage and reducing the absolute value of the voltage applied to the subsequent stage.

The protection diode circuit 315 shown in this embodiment is an example, and a protection diode circuit having a generally used configuration can be applied without being limited to this embodiment. For example, the protection diode circuit 315 is effective when the input voltage is VDD>input voltage>VSS, but a protection diode circuit corresponding to VDD<input voltage or input voltage<VSS may be provided as necessary. . In this case, only one diode may be used in the protection diode circuit. Here, the input pad is taken as an example, but the protection diode circuit 315 can be similarly connected to the output pad as well. In that case, the resistor 148 is used as the input of the protection diode circuit 315, the resistor 147 is used as the output of the protection diode circuit 315, and the other end of the resistor 148 is used as the circuit element 320 of the preceding peripheral circuit section 302 (for example, the readout circuit RC). It can be configured to be connected to Also, a protection diode circuit may be placed in the electrical path between the pixel circuit and the pad. The protection diode circuit 315 connected to the output pad can also suppress output of the abnormal signal to the outside of the device when an abnormal signal occurs inside the solid-state imaging device. A protection circuit such as the protection diode circuit 315 can reduce the entry of external noise from the pad 313 . In addition, it becomes possible to protect the subsequent circuit against erroneous input and surge voltage. Causes of external noise include erroneous inputs, voltage surges, and the like, as described above. In particular, it is very significant to provide the protection diode circuit 315 on the second substrate 121 in order to protect peripheral circuits from voltage surges caused by electrostatic discharge (ESD). A voltage surge due to electrostatic discharge is likely to enter the input pad and the output pad without distinction, so it is desirable that the protection diode circuits are arranged corresponding to both the input pad and the output pad. As an example of a protection circuit arranged to reduce the intrusion of external noise, a protection diode circuit was taken as an example, but it is not limited to protection circuits using diodes, and protection circuits using transistors can also be A similar effect can be obtained. Note that the protection diode circuit 315 may be omitted, the input pad may be connected to the peripheral circuit or the pixel circuit, or the output pad may be connected to the peripheral circuit. However, in terms of improving electrical reliability, it is desirable to provide a protection circuit between the input pad and/or output pad and the peripheral circuit section 302 . Also, the protection circuit may be arranged in the middle of the electrical path between the pixel circuit and the pad.

In the solid-state imaging device of this embodiment, the principal surface 102 of the first substrate 101 and the principal surface 122 of the second substrate 121 are arranged to face each other with the first wiring structure 149 and the second wiring structure 150 interposed therebetween. (opposed arrangement). That is, the first substrate 101, the first wiring structure 149, the second wiring structure 150, and the second substrate 121 are arranged in this order. The upper surface of the first wiring structure 149 and the upper surface of the second wiring structure 150 are bonded together at the bonding surface X. As shown in FIG. That is, the first member 308 and the second member 309 are joined together at the joining surface X. As shown in FIG. The bonding surface X is composed of the top surface of the first wiring structure 149 and the top surface of the second wiring structure 150 . As a result, the first wiring structure 149 and the second wiring structure 150 are integrated to form the wiring structure 151 between the first substrate 101 and the second substrate 121 . The wiring structure 151 will have five wiring layers, wiring layers 109 , 111 , 130 , 132 and 134 . Note that the bonding of the first wiring structure 149 and the second wiring structure 150 may utilize a connection member such as micro-bonding, or may utilize metal bonding. Such bonding is accomplished at connection 311 and connection 314 .

Pads 313 of the solid-state imaging device for exchanging signals with the outside are arranged above the surface of the second substrate 121, which is the main surface 122 of the second member 309, and an opening 100 is provided on the first member 308 side. It is

That is, both the first surface 3131 and the second surface 3132 of the pad 313 are positioned closer to the first substrate 101 than the main surface 122 is. Here, consider a virtual plane 1020 by extending the main surface 102 of the first substrate 101 . The virtual plane 1020 is a virtual extension of the major surface 102 , is parallel to the major surface 102 and includes the major surface 102 . Therefore, a virtual plane 1020 intersects the opening 100 in FIG. Pad 313 is located between main surface 122 of second substrate 121 and imaginary plane 1020 . Specifically, the first surface 3131 of the pad 313 is located between the imaginary plane 1020 and the second surface 3132 , and the second surface 3132 of the pad 313 is located between the first surface 3131 and the main surface of the second substrate 121 . is located between In this embodiment, the pads 313 are arranged in the same layer as the first wiring layer 109 counted from the virtual plane 1020 side among the five wiring layers.

In this manner, the pad 313 is positioned between the main surface 122 of the second substrate 121 and the imaginary plane 1020, so that the distance between the pad 313 and the second substrate 121 is equal to that between the first substrate 101 and the second substrate. 121 can be less than the distance. As a result, the electrical path between pad 313 and the peripheral circuit can be shortened. As a result, signal delay and loss at the input and/or output can be reduced. The distance (interval) between the first substrate 101 and the second substrate 121 is practically in the range of 1 μm or more and 10 μm or less. If the distance between the pad 313 and the second substrate 121 is 5 μm or less, it can be said that the electric path is sufficiently short. The distance (gap) between the first substrate 101 and the second substrate 121 is preferably 1.5 μm to 3.0 μm. can be on the submicron order.

Moreover, since it is not necessary to provide an opening in the second member 309, it is possible to reduce the penetration of moisture into the peripheral circuit section of the second member 309. FIG. In this embodiment, the number of elements arranged in the vicinity of the pad section 312A of the first member 308 can be easily made smaller than the number of elements arranged in the vicinity of the pad section 312B of the second member 309. FIG. Further, the element arranged close to the pad portion of the first member 308 can be separated from the element arranged close to the pad portion of the second member 309 . Therefore, it is possible to further reduce the influence of moisture from the pad opening 100 on the device. In addition, by arranging the external terminals on the rear surface side of the first member 308, connection to the pads 313 is facilitated, and connection failures are reduced.

In the pad portion 312, the pad 313 is connected to the contact layer 110 and the wiring layer 111 (connecting portion 314A) of the first wiring structure 149, and further to the wiring layer 134 (connecting portion 314B) of the second wiring structure 150 and the contact layer. 133 , the wiring layer 132 , the contact layer 131 , the wiring layer 130 , the contact layer 129 and the gate electrode layer 128 are connected to the protection diode circuit 315 . In this manner, the second surface 3132 of pad 313 is connected to wiring structure 151 . With this configuration, the pad 313 is positioned between the main surface 122 of the second substrate 121 and the imaginary plane 1020, and an electrical path is formed from the second surface 3132 of the pad 313, so that the pad 313 and the protection diode The electrical path to and from circuit 315 can be shortened. As a result, the electrical path between pad 313 and the peripheral circuit can also be shortened.

As described above, the pad portion 312B is provided with the connection portion 314B for connection with the first member at the same position as the protection diode circuit 315 in plan view. Furthermore, a connecting portion 314A for connection with the second member 309 is arranged at the same position as the pad 313 in the plane of the pad portion 312A. By connecting the connecting portion 314A and the connecting portion 314B, the protection diode circuit 315 and the pad 313 are also arranged at the same position in a plane, so that the protection diode circuit 315 and the pad 313 overlap each other. Therefore, it becomes possible to connect the protection diode circuit 315 and the pad 313 with the shortest electrical path.
When the protection diode circuit 315 is omitted, the peripheral circuit section 302 and the circuit element 320 are arranged at positions overlapping with the pad 313 and connected to the pad 313 through the wiring structure 151 .

Also, in this embodiment, the pad 313 is connected to a plurality of vias in the contact layer 133 . As described above, the connection between the wiring structure 151 and the pads 313 to which an external force is likely to be applied is made at a plurality of points, so that the force applied to the wiring structure 151 is dispersed, so that the impact on the second substrate 10 and the wiring structure 151 is reduced. is alleviated. Further, even if the connection with any via is lost, the possibility of maintaining the connection between the pad 313 and the wiring structure 151 increases, so reliability is improved.

Next, a method for manufacturing the solid-state imaging device of this embodiment will be described with reference to FIGS. 4 is a schematic cross-sectional view showing the manufacturing process of the first member 308, FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the second member 309, and FIG. It is a cross-sectional schematic diagram which shows the manufacturing process after joining.
A manufacturing process of the first member 308 in FIG. 1 will be described with reference to FIG. In FIG. 4, the structure that will later become the first member 308 of FIG. are 304', 302', 312' and 120'.

First, a semiconductor substrate is prepared and elements are formed on the semiconductor substrate. A semiconductor substrate 401 having a thickness D3 having a main surface 402 and a back surface 403 is prepared. The semiconductor substrate 401 is, for example, a silicon semiconductor substrate. A device isolation structure 119 is formed in a semiconductor substrate 401 . The element isolation structure 119 includes an insulator such as a silicon oxide film and has, for example, a LOCOS or STI structure. Then, an arbitrary conductivity type well (not shown) is formed in the semiconductor substrate 401 . After that, n-type semiconductor regions 112 and 114 and p-type semiconductor regions (not shown), which constitute photoelectric conversion elements and transistors, are formed. Further, a gate electrode layer 107 including gate electrodes including the gate electrode 113 of the transfer transistor is formed. The gate electrode layer is formed, for example, by depositing and patterning a polysilicon layer, and may include not only gate electrodes but also wiring. Here, the method of forming the gate electrode, element isolation, and semiconductor region can be formed by a general semiconductor process, and detailed description thereof will be omitted. As described above, the configuration shown in FIG. 4A is obtained.

Next, a wiring structure is formed on the main surface 402 of the semiconductor substrate 401 . The wiring structure has interlayer insulating films 104 ′, 105 and 106 , contact layers 108 and 110 and wiring layers 109 and 111 . Here, the interlayer insulating film 104' will later become the interlayer insulating film 104 in FIG. The interlayer insulating film 104' covers the gate electrode layer 107, the contact layer 108 is arranged on the interlayer insulating film 104', and the wiring layer 109 and the pad 313 are arranged on the interlayer insulating film 104'. Further, the interlayer insulating film 105 covers the wiring layer 109, the contact layer 110 is arranged on the interlayer insulating film 105, the wiring layer 111 is arranged on the interlayer insulating film 105, and the interlayer insulating film 106 is arranged on the interlayer insulating film 105. and has an opening through which the wiring of the wiring layer 111 is exposed. The top surface of the wiring structure is formed by the top surface of the interlayer insulating film 106 and the top surface of the wiring layer 111 .

Here, the interlayer insulating film is a silicon oxide film. However, the interlayer insulating film may be formed of a silicon nitride film, an organic resin, or the like. The wiring layer is composed of wiring whose main component is aluminum and wiring whose main component is copper. The contacts are made of, for example, tungsten, and the vias can be formed integrally with wires whose main component is tungsten or copper. Here, the wiring layer 111 includes the connecting portions 314A and 311A, and is composed of wiring containing copper as a main component. Also, the wiring layer 109 is composed of a wiring whose main component is aluminum. The pad 313 is arranged in the same layer as the wiring layer 109 and is mainly composed of aluminum. The wiring layer, contact layer, interlayer insulating film, and pad 313 can be manufactured by general semiconductor processes, and detailed description thereof will be omitted. As described above, the configuration shown in FIG. 4B is obtained. 4B, reference numerals 104', 105, 106, 108 to 111 will later become the first wiring structure 149 in FIG. Also, the connecting portion 311A will constitute the connecting portion 311 later.

Next, the manufacturing process of the second member 309 shown in FIG. 1 will be described with reference to FIG. In FIG. 5, 309' denotes a structure that will later become the second member 309 of FIG. , 312′ and 315′.

First, a semiconductor substrate is prepared and elements are formed on the semiconductor substrate. A semiconductor substrate 404 having a thickness D4 having a main surface 405 and a back surface 406 is prepared. Then, an isolation structure 136 is formed on the semiconductor substrate 404 using a LOCOS or STI structure. Also, p-type wells 135 and 139 and an n-type well 142 are formed in the semiconductor substrate 404 . After that, n-type semiconductor regions 138 and 141 and p-type semiconductor regions 144 which can be source/drain regions constituting transistors, and semiconductor regions constituting diodes are formed. Then, a gate electrode layer 128 including gate electrodes 137, 140, 143 of transistors and wiring (resistors) is formed by depositing and patterning a polysilicon layer. Here, the method of forming the gate electrode, element isolation, and semiconductor region can be formed by a general semiconductor process, and detailed description thereof will be omitted. As described above, the configuration shown in FIG. 5A is obtained.

Next, a wiring structure is formed on the major surface 405 of the semiconductor substrate 404 . The wiring structure has interlayer insulating films 124 to 127 , contact layers 129 , 131 and 133 and wiring layers 130 , 132 and 134 . The interlayer insulating film 124 covers the gate electrode layer 128 , the contact layer 129 is arranged on the interlayer insulating film 124 , and the wiring layer 130 is arranged on the interlayer insulating film 124 . Further, the interlayer insulating film 125 covers the wiring layer 130, the contact layer 131 is arranged on the interlayer insulating film 125, the wiring layer 132 is arranged on the interlayer insulating film 125, and the interlayer insulating film 126 covers the wiring layer 132 to provide interlayer insulation. It is placed on the membrane 125 . The contact layer 133 is arranged on the interlayer insulating film 126, the wiring layer 134 is arranged on the interlayer insulating film 126, the interlayer insulating film 127 is arranged on the interlayer insulating film 126, and the wiring of the wiring layer 134 is exposed. have an opening. The upper surface of the wiring structure is formed by the upper surface of the interlayer insulating film 127 and the upper surface of the wiring layer 134 .

Here, the interlayer insulating film is a silicon oxide film. It may be formed of a silicon nitride film, an organic resin, or the like. The wiring layer is composed of wiring whose main component is aluminum and wiring whose main component is copper. Here, the wiring layer 134 includes the connecting portions 314B and 311B, and is composed of a wiring containing copper as a main component. The wiring layer, the contact layer, and the interlayer insulating film can be manufactured by a general semiconductor process, and detailed description thereof will be omitted. As described above, the configuration shown in FIG. 5B is obtained. 5B, reference numerals 124 to 127, 129 to 134, etc. will later become the first wiring structure 150 in FIG. Also, the connecting portion 311B will constitute the connecting portion 311 later.

The first member 308' and the second member 309' shown in FIGS. 4B and 5B are pasted together so that the main surfaces 402 and 405 of the semiconductor substrates face each other. . That is, the top surface of the wiring structure of the first member 308' and the top surface of the wiring structure of the second member 309' are joined. Here, since the connection portions 311A and 311B and the connection portions 314A and 314B are composed of wires containing copper as a main component, they can be laminated by metal bonding of copper.
After the first member 308' and the second member 309' are joined, the semiconductor substrate 401 is thinned from the back surface 403 side of the semiconductor substrate 401 of the first member 308' to thin the semiconductor substrate 401. FIG. Thinning can be performed by CMP (Chemical Mechanical Polishing) or etching. Then, the semiconductor substrate 401 becomes the semiconductor substrate 407, and the thickness changes from D3 to D1 (D1<D3) (FIG. 6A). By thinning the semiconductor substrate 401 to form the semiconductor substrate 407 in this way, incident light can be efficiently incident on the photoelectric conversion element later. At this time, the thickness D1 of the semiconductor substrate 407<thickness D4 of the semiconductor substrate 404 is established.

Next, a flattening layer 409 made of resin, a color filter layer 410, a flattening layer 411 made of resin, and a microlens layer 412 are formed in this order on the back surface 408 of the semiconductor substrate 407 . The method for manufacturing these flattening layer, color filter layer, and microlens layer can be formed by a general semiconductor process, and detailed description thereof will be omitted. Here, the microlens layer may be formed up to the region 312' which becomes the pad portion. Through the above steps, the configuration shown in FIG. 6B is obtained.

An opening 100 for exposing the pad 313 is then formed. Here, a photoresist mask having arbitrary openings is provided on the microlens layer 412 using a photolithographic technique. Then, using a dry etching technique, the microlens layer 412, the planarization layer 411, the color filter layer 410, the planarization layer 409, the semiconductor substrate 407, and the interlayer insulating film 104' are removed to form an opening 100. Pads 313 are exposed through openings 100 .

Then, the microlens layer 118, the planarization layers 117 and 115, the color filter layer 116, the first substrate 101, and the interlayer insulating film 104 are formed. As described above, the configuration shown in FIG. 1 is obtained. The semiconductor substrate 404, main surface 405, back surface 406, and thickness D4 in FIG. 6B correspond to the second substrate 121, main surface 122, back surface 123, and thickness D2 in FIG.
Although there is no difference between the thicknesses D4 and D2, the semiconductor substrate 404 may be thinned so that the thickness D2<D4. By thinning, the number of processes increases, but the size of the solid-state imaging device can be reduced.

As described above, by performing etching for exposing the pads from the back surface 408 side of the thinned semiconductor substrate 407, it is possible to shorten the time required for the etching for forming the pads. Moreover, the pad 313 can be formed in the same process as the wiring of the wiring layer 109, and the number of man-hours can be reduced. Further, the pad 313 is preferably made of a metal containing aluminum as a main component in order to reduce the connection resistance with the external terminal as in this embodiment. Note that the pad 313 can also function as an etching stopper during etching.

The present invention is not limited to the steps described in the manufacturing method of this embodiment, and the order of steps may be changed. Also, the manufacturing order of the first member 308 and the second member 309 can be set as appropriate. Furthermore, it is also possible to purchase the first member 308 and the second member 309 and bond them together. Note that SOI substrates can also be applied to the semiconductor substrates 401 and 402 .

(Example 2)
A second embodiment of the present invention will be described with reference to FIG. 7A and 7B are schematic cross-sectional views of the solid-state imaging device, corresponding to FIG. 1 respectively. In FIG. 7, elements similar to those in FIG. 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

In this embodiment, the configurations different from those of the first embodiment are the opening 700 and the pad 701 in FIG. 7A and the opening 702 and the pad 701 in FIG. 7B. This embodiment has deeper openings 700 and 702 than the first embodiment, and has pads 701 closer to the main surface 122 of the second member 309 than the first embodiment. In this way, the pad can be arranged at any position as long as it is on the first member 308 side of the main surface 122 of the second member 309 and between the imaginary plane 1020 and the main surface 122 . good. However, by arranging the pads close to the second member 309 as in the present embodiment, it is possible to reduce the connection resistance from the pad 701 to the protection diode circuit 315 as compared with the first embodiment. becomes. In this embodiment, the wiring structure 151 has five wiring layers as in the first embodiment. is distributed to In this way, it is preferable to arrange the pads 701 in the wiring layers (wiring layers 134, 132, 130) farther from the virtual plane 1020 than the wiring layers (wiring layers 109, 111) on the virtual plane 1020 side. That is, when the wiring layer number N is an odd number, it is preferable to arrange the pad 701 in the same layer as the (N+1)/2 to N-th wiring layers counted from the virtual plane 1020 side. When the wiring layer number N is an even number, it is preferable to arrange the pad 313 in the same layer as the 1+(N/2) to N-th wiring layers counted from the virtual plane 1020 side. In addition, in FIG. 7B, the shape of the opening 702 is different from the opening 100 of Example 1 and the opening 700 of FIG. 7A. As shown in FIG. 7B, the unnecessary interlayer insulating film and semiconductor substrate outside the pad portion of the first member 308 may be removed. In addition, by making the first member 308 to be manufactured in advance smaller than the second member 309, or by shifting the end surfaces of the first member 308 and the second member 309, the first member 308 can be formed in order to form the opening 702. Part or all of the step of etching the member 308 may be omitted. The opening 702 opens toward the end of the device. It is preferable to provide a through hole in the first substrate 101 so that

Note that the pads 701 are arranged in the same layer as the wiring layer 134 of the second member 309 . Here, the same layer means that it is formed in the same process or has the same height from the main surface. The pad 701 is included in the same layer as the wiring layer 134 and formed in the same process. Therefore, it is preferable that the wiring layer 134 is a wiring containing aluminum as a main component. In this embodiment, the wiring mainly composed of copper is used as in the first embodiment, but since the wiring layer 134 is the same layer as the pad 701, it is more preferable that the wiring layer 134 is a wiring mainly composed of aluminum. In this case, the connecting portion 311 may be joined by a microbump or the like.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. FIG. 8C is a schematic cross-sectional view of the solid-state imaging device of this embodiment and corresponds to FIG. 8A and 8B are schematic cross-sectional views for explaining the manufacturing method of the solid-state imaging device of this embodiment, and are drawings corresponding to FIG. In FIG. 8, the same components as in FIGS. 1 and 6 are denoted by the same reference numerals, and descriptions thereof are omitted.

The configuration of this embodiment different from that of Embodiment 1 is the configuration of the opening 811 and the protective film 806 in FIG. 8C. The protective film 806 of this embodiment covers the side walls (side surfaces) of the first substrate 101 having the opening 811 . In addition, the protective film 806 extends from the sidewalls to cover the periphery of the first surface 3131 of the pad 313 . By having such a protective film 806, it is possible to reduce entry of moisture into the device through the opening 811. FIG. Also, if the external terminal for connection with the pad 313 comes into contact with a conductor such as the first substrate 101, leakage will occur. The protective film 806 prevents the external terminals from coming into contact with conductors and suppresses the occurrence of leakage. Furthermore, the protective film 806 of this embodiment is also arranged on the incident surface of the photoelectric conversion portion of the pixel portion 301 (that is, the rear surface 103 of the first substrate 101), and can also function as an antireflection film. Note that the configuration of the opening is different from that of the first embodiment due to the provision of the protective film 806 . Also, the configurations of the planarization layer 807, the color filter layer 808, the planarization layer 809, and the microlens layer 810 can be changed to configurations different from those of the first embodiment.

The manufacturing method of this embodiment will be described with reference to FIGS. 8(A) and 8(B). Since the method is the same up to FIG. 6A of the first embodiment, the description is omitted. An opening 800 is formed in the semiconductor substrate 407 of FIG. 6A by photolithography and etching techniques to form the first substrate 101 . Opening 800 is formed to expose pad 313 . After that, a silicon nitride film 801 that can serve as a protective film is formed by a method such as plasma CVD so as to cover the side surfaces of the opening 800 and the rear surface 103 of the first substrate 101, thereby obtaining the structure shown in FIG.

After that, a planarizing layer 802 , a color filter layer 803 , a planarizing layer 804 and a microlens layer 805 are formed in this order so as to cover the silicon nitride film 801 . Each material and manufacturing method are the same as in Example 1. Then, an opening 811 is formed. The opening 811 penetrates the silicon nitride film 801 , the planarization layer 802 , the color filter layer 803 , the planarization layer 804 and the microlens layer 805 so that the protective film 806 covers only the periphery of the first surface 3131 of the pad 313 . A portion of the first surface 3131 of the pad 313 is exposed. Here, the silicon nitride film 801, the planarizing layer 802, the color filter layer 803, the planarizing layer 804, and the microlens layer 805 are respectively the protective film 806, the planarizing layer 807, the color filter layer 808, the planarizing layer 809, and the microlens layer. A lens layer 810 is formed. Then, the solid-state imaging device shown in FIG. 8C is manufactured.

(Fourth embodiment)
A third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a schematic cross-sectional view of the solid-state imaging device of this embodiment, corresponding to FIG. In FIG. 9, the same reference numerals are assigned to the same configurations as in FIGS. 1 and 6, and the description thereof is omitted.
This embodiment differs from the first embodiment in that the opening 900 is provided in the second substrate 121 instead of the first substrate 101, and that the protection diode circuit 315 is provided in the first substrate 101 instead of the second substrate 121. There is a difference. These points will be described below.

Pads 313 of the solid-state imaging device for exchanging signals with the outside are arranged below the surface of the first substrate 101, which is the main surface 102 of the first member 308, and an opening 900 is provided on the second member 309 side. there is The pad 313 has a first surface 3131 and a second surface 3132 opposite to the first surface 3131 . A first surface 3131 of the pad 313 is exposed on the second substrate 121 side, and an external terminal is connected to the first surface 3131 . That is, both the first surface 3131 and the second surface 3132 of the pad 313 are located closer to the second substrate 121 than the main surface 102 is. Here, consider a virtual plane 1220 by extending the main surface 122 of the second substrate 121 . A virtual plane 1220 is a virtual extension of the major surface 122 , parallel to the major surface 122 and including the major surface 122 . Therefore, the imaginary plane 1220 intersects the opening 900 in FIG. Pad 313 is located between main surface 122 of first substrate 101 and imaginary plane 1220 . Specifically, the first surface 3131 of the pad 313 is located between the imaginary plane 1220 and the second surface 3132 , and the second surface 3132 of the pad 313 is located between the first surface 3131 and the main surface 102 of the first substrate 101 . is located between In this embodiment, the pads 313 are arranged in the same layer as the first wiring layer 130 counted from the virtual plane 1220 side among the five wiring layers. The wiring layer 130 is composed of wiring containing aluminum as its main component, and the pad 313 also contains aluminum as its main component. The wiring layer 111 includes the connection portions 314A and 311, and the wiring layer 134 includes the connection portions 314B and 311, respectively, each of which is composed of wiring containing copper as a main component.

As in the second embodiment, by arranging the pads 313 in the wiring layers (wiring layers 134, 111, 109) farther from the virtual plane 1220 than the wiring layers (wiring layers 130, 132) on the virtual plane 1220 side, the connection is achieved. It is also possible to reduce the resistance. However, even in this embodiment, the thickness D1 of the first substrate 101<the thickness D2 of the second substrate 121 is satisfied. If the distance between the first surface 3131 of the pad 313 and the back surface 103 of the first substrate 101 becomes extremely small, the mechanical strength of the pad portion 312 will decrease. Therefore, the pad 313 is placed in the same layer as the wiring layers (wiring layers 130 and 132) on the virtual plane 1220 side, and a sufficient distance is secured between the first surface 3131 of the pad 313 and the back surface 103 of the first substrate 101. is preferred.

A protection diode circuit 315 is arranged on the pad portion 312 of the first member 308 . In the peripheral circuit section 302, a circuit element 320 forming a part of the peripheral circuit is arranged on the first substrate 101, and the circuit element 320 is arranged on the second substrate 121 via the wiring structure 151. It is connected to another part of the peripheral circuit. A wiring layer connecting peripheral circuits arranged on both substrates includes at least a wiring layer 111 and a wiring layer 134 including connection portions. In the pad portion 312, the pad 313 is connected through the contact layers 131 and 132 of the second wiring structure 150, the contact layer 133 wiring layer 134 (connection portion 314B), and further the wiring layer 111 (connection portion 314B) of the first wiring structure 149. It is connected to the protection diode circuit 315 via the connection portion 314A), the contact layer 110, the wiring layer 109, the contact layer 108, and the gate electrode layer 107. FIG. The second surface 3132 of the pad 313 is connected to the contact layer 131 at multiple points. Thus, when the protection diode circuit 315, which is a part of the semiconductor integrated circuit, is provided on the first substrate 101, the pads 313 are positioned between the main surface 102 and the virtual plane 1220 and A configuration in which an electrical path is provided from 3132 can be adopted. This configuration can shorten the electrical path between the pad 313 and the protection diode circuit 315, and further between the pad 313 and the peripheral circuitry. Also in this embodiment, the distance between the pad 313 and the first substrate 101 is preferably 5 μm or less.

In this embodiment, the protection diode circuit 315 is connected to a circuit element 320 which is a part of the peripheral circuit, and the circuit element 320 is arranged on the second substrate 121 via the wiring structure 151. connected to another part of However, what is connected to the protection diode circuit 315 is not limited to the circuit element 320 of the peripheral circuit. For example, the protection diode circuit 315 is connected to a pixel circuit (for example, a transfer transistor) arranged on the first substrate 101, and the pixel circuit and the peripheral circuit arranged on the second substrate 121 are connected via the wiring structure 151. You may Alternatively, the protection diode circuit 315 may be directly connected to the peripheral circuit arranged on the second substrate 121 via the wiring structure 151 without going through the peripheral circuit arranged on the first substrate 101 . Also, in the solid-state imaging device of this embodiment, bonding wires can be used as external terminals as in the first embodiment, but flip-chip bonding can also be used. By arranging the external terminals on the rear surface 123 of the second substrate 121, deterioration or damage of the external terminals, or penetration of moisture from the periphery of the pads can be suppressed.

The opening 900 can be formed by etching a portion of the second substrate 121 and the second wiring structure 150 . Note that also in this embodiment, the end portion of the second substrate 121 may be removed as in FIG. 7B described in Embodiment 2, and a protective film may be provided as in Embodiment 3. can.

As described above, according to the solid-state imaging device of this embodiment, it is possible to provide a solid-state imaging device in which the connection between the pads and the circuit is highly reliable.

As an application example of the solid-state imaging device according to each of the above-described embodiments, an imaging system incorporating the solid-state imaging device will be described below. Imaging systems include not only devices such as cameras whose main purpose is photography, but also devices (for example, personal computers and mobile terminals) that have an auxiliary photography function. For example, a camera includes a solid-state imaging device according to the present invention and a processing section that processes signals output from the solid-state imaging device. This processing unit can include, for example, an A/D converter and a processor that processes digital data output from the A/D converter. A signal to be processed is input to the processing unit through an external terminal such as a bonding wire connected to a pad of the solid-state imaging device.

As described above, according to the solid-state imaging device of the present invention, it is possible to provide a solid-state imaging device in which the connection between the pads and the circuit is highly reliable. The present invention also facilitates connection between pads and circuits.

It should be noted that the present invention is not limited to the configuration described in the specification, and the conductivity type and the circuit can be changed, for example, to reverse conductivity type. Also, although the connecting portion has been described as being composed of the wiring of the wiring layer, it may be vias or microbumps, as long as it is possible to ensure conduction. Moreover, it is also possible to appropriately combine the configurations of the respective embodiments.

301 pixel portion 302 peripheral circuit portion 308 first member 309 second member 149 first wiring structure 150 second wiring structure 312 pad portion 313 pad 101 first substrate 121 second substrate 100 opening X connection surface

Claims (27)

a first semiconductor substrate on which a photoelectric conversion element and a first semiconductor element are arranged; a second semiconductor substrate on which a second semiconductor element and a third semiconductor element are arranged; a first wiring structure disposed therebetween; a second wiring structure disposed between the first wiring structure and the second semiconductor substrate; and between the first semiconductor substrate and the second semiconductor substrate. a pad connected to the third semiconductor element and not connected to the semiconductor element provided on the first semiconductor substrate , wherein the first semiconductor element and the second semiconductor element are connected to each other; Prepare electrically connected members,
A method of manufacturing a solid-state imaging device, comprising forming an opening penetrating through the first semiconductor substrate and reaching the pad. A first semiconductor region of the second semiconductor substrate, a second semiconductor region of the second semiconductor substrate, and an insulator positioned between the first semiconductor region and the second semiconductor region overlap the opening. 2. The method of manufacturing of claim 1, wherein: 3. The manufacturing method according to claim 1, wherein said first semiconductor element and said second semiconductor element are transistors, and said third semiconductor element is a diode. 4. The manufacturing method according to claim 1, wherein said pad is connected to said third semiconductor element via a resistor made of a polysilicon layer. 5. The manufacturing method according to claim 1, wherein said third semiconductor element overlaps said pad. The first wiring structure has a first wiring layer, the second wiring structure has a second wiring layer, the main component of the first wiring layer and the main component of the second wiring layer are copper, The manufacturing method according to any one of claims 1 to 5. 7. The manufacturing method according to claim 6, wherein said pad is connected to said third semiconductor element through a wiring included in a third wiring layer positioned between said second wiring layer and said second semiconductor substrate. . 8. The manufacturing method according to claim 6, wherein the first wiring of said first wiring layer and the second wiring of said second wiring layer are metal-bonded. a first semiconductor substrate on which a photoelectric conversion element and a first semiconductor element are arranged; a second semiconductor substrate on which a second semiconductor element and a third semiconductor element are arranged; a first wiring structure disposed therebetween; a second wiring structure disposed between the first wiring structure and the second semiconductor substrate; and between the first semiconductor substrate and the second semiconductor substrate. a pad arranged and connected to the third semiconductor element, the first wiring and the second wiring of the first wiring structure are electrically connected to the first semiconductor element and the second semiconductor element; Prepare a member metal-bonded to the second wiring of the structure,
A method of manufacturing a solid-state imaging device, comprising forming an opening penetrating through the first semiconductor substrate and reaching the pad. the first wiring structure and the second wiring structure are bonded at a bonding surface, and the insulating film included in the first wiring structure and the insulating film included in the second wiring structure are bonded at the bonding surface; 10. The method of claim 9, wherein said metal joints are formed respectively. 11. The method of manufacturing a solid-state imaging device according to claim 9, wherein a main component of said first wiring and a main component of said second wiring are copper. 12. The solid-state imaging device according to claim 9, wherein the pad is not connected to the semiconductor element provided on the first semiconductor substrate, but is connected to the third semiconductor element. Method of manufacturing the device. 13. The manufacturing method according to claim 8, wherein said first wiring is connected to said first semiconductor element, and said second wiring is connected to said second semiconductor element. 14. The manufacturing method according to any one of claims 1 to 13 , wherein the main component of said pad is aluminum. 15. The manufacturing method according to claim 1 , wherein said pad is arranged in the same layer as a wiring layer included in said first wiring structure. 15. The manufacturing method according to claim 1 , wherein said pad is arranged in the same layer as a wiring layer included in said second wiring structure. 17. The manufacturing method according to any one of claims 1 to 16 , wherein said pad is connected to said second wiring structure at a plurality of points. 18. The manufacturing method according to claim 17, wherein the plurality of locations are planarly overlapped with the pad. 19. The manufacturing method according to any one of claims 1 to 18 , wherein said third semiconductor element is included in a protection circuit. 20. The manufacturing method according to claim 1 , wherein said opening is formed with the thickness of said first semiconductor substrate being smaller than the thickness of said second semiconductor substrate. 21. The manufacturing method according to any one of claims 1 to 20 , wherein the thickness of said second semiconductor substrate is reduced after said member is prepared. 22. The manufacturing method according to any one of claims 1 to 21 , wherein the thickness of said first semiconductor substrate is reduced after said member is prepared. 23. The method of claim 1, further comprising forming a microlens layer including a plurality of microlenses on the first semiconductor substrate after forming the opening. 23. The method of claim 1, further comprising forming a microlens layer comprising a plurality of microlenses over the first semiconductor substrate prior to forming the opening. 25. The manufacturing method according to any one of claims 1 to 24, wherein said pads of said member provided are not connected to said first wiring structure, but are connected to said second wiring structure. 26. The manufacturing method according to any one of claims 1 to 25, wherein said pad is a pad that outputs a signal based on charges generated in said photoelectric conversion element to the outside of said solid-state imaging device. The second semiconductor substrate includes a readout circuit that generates a signal based on the charge generated in the photoelectric conversion element, and the pad is a pad that outputs the signal output by the readout circuit to the outside of the solid-state imaging device, 27. The manufacturing method according to claim 26.

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