JP6598825B2 - Solid-state imaging device and method for manufacturing solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, and particularly relates to a pad portion.

  In a CCD-type or amplification-type solid-state imaging device used for a digital still camera, a camcorder, and the like, the pixels are required to be miniaturized to obtain a high-definition image. However, the finer the pixel, the smaller the light receiving area of the photoelectric conversion element for detecting the light contained in the pixel, resulting in lower sensitivity.

  In Patent Document 1, in a CMOS solid-state imaging device that is an amplification type, a first substrate on which a photoelectric conversion element and a transfer transistor are arranged and another circuit are arranged in order to secure a light receiving area of the photoelectric conversion element. The structure which joins 2 board | substrates and forms a solid-state imaging device is disclosed. In the solid-state imaging device of Patent Document 1, a connection portion that penetrates the second substrate is connected to a pad (input / output pad), and the pad is connected from the back side of the second substrate. The pad is formed on the back surface of the second substrate after the second substrate is polished to expose the second connection portion.

  Patent Document 2 discloses a method for manufacturing an electronic component in which an image sensor, a first substrate having a first conductive area, and an integrated circuit and a second substrate having a second conductive area are joined. . After joining the first substrate and the second substrate, the first conductive area and the second conductive area are exposed, and a conductive layer is further deposited to electrically connect the first conductive area and the second conductive area. Is disclosed. The first conductive area or conductive layer is used as a pad (external connection pad).

JP 2006-191081 A Special table 2010-514177 gazette

  In the configuration as in Patent Document 1, the electrical path connecting the pad and the first substrate becomes long. As a result, there is a possibility that the performance is lowered due to an increase in connection resistance, or the reliability of the connection between the pad and the first substrate is lowered. In the configuration as in Patent Document 2, the reliability of connection between the pad and the second conductive area is lowered.

  Further, in the manufacturing method of Patent Document 1, a step of providing a liner for separating the connection portion and the second substrate, a step of polishing the second substrate, and a step of forming input / output pads are required. It becomes complicated. In the manufacturing method of Patent Document 2, a process of providing openings having different depths for each of the first conductive area and the second conductive area is required, which complicates the process.

  Accordingly, an object of the present invention is to provide a solid-state imaging device with high reliability of connection between a pad and a circuit. It is another object of the present invention to provide a method of manufacturing a solid-state imaging device that can easily form a connection between a pad and a circuit.

  An aspect of the present invention provides a first semiconductor substrate on which a photoelectric conversion element and a first semiconductor element are arranged, a second semiconductor substrate on which a second semiconductor element is arranged, the first semiconductor substrate, and the second semiconductor substrate, And a wiring structure including a wiring connected to the first semiconductor element and a wiring connected to the second semiconductor element, wherein a pad is connected to the wiring via a plurality of vias. It is connected to the structure.

  According to the present invention, it is possible to provide an imaging device with high reliability of connection with a pad.

1 is a schematic cross-sectional view of a solid-state imaging device in Embodiment 1. FIG. 1 is a schematic plan view of a solid-state imaging device in Embodiment 1. FIG. 1 is a circuit diagram of a solid-state imaging device in Embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the solid-state imaging device according to Embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the solid-state imaging device according to Embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the solid-state imaging device according to Embodiment 1. FIG. 6 is a schematic cross-sectional view of a solid-state imaging device according to Embodiment 2. FIG. It is a cross-sectional schematic diagram of the solid-state imaging device in Example 3, and a cross-sectional schematic diagram for explaining the manufacturing method thereof. 6 is a schematic cross-sectional view of a solid-state imaging device in Embodiment 4. FIG.

  A solid-state imaging device according to the present invention includes a first semiconductor substrate having a photoelectric conversion element disposed on a surface, and a second semiconductor having at least a part of a circuit for generating a signal based on the charge of the photoelectric conversion element disposed on the surface. And a substrate. And it arrange | positions so that the surface of a 1st semiconductor substrate and the surface of a 2nd semiconductor substrate may oppose. A wiring structure is disposed between the first semiconductor substrate and the second semiconductor substrate. The solid-state imaging device has a pad to which an external terminal is connected, and the external terminal is connected to the first surface of the pad.

  In the first solid-state imaging device, the first surface of the pad is located between a virtual plane including the surface of the first semiconductor substrate and parallel to the surface and the surface of the second semiconductor substrate, and is opposite to the first surface. The second surface is located between the first surface and the surface of the second semiconductor substrate. The second surface of the pad is connected to the wiring structure so that the pad is connected to the peripheral circuit disposed on the second semiconductor substrate via the wiring structure.

  In the second solid-state imaging device, a part of the peripheral circuit is disposed on the first semiconductor substrate. The first surface of the pad is located between the surface of the first semiconductor substrate and a virtual plane including the surface of the second semiconductor substrate and parallel to the surface, and is a surface opposite to the first surface. The second surface is located between the first surface and the surface of the first semiconductor substrate. The second surface of the pad is connected to the wiring structure so that the pad is connected to a part of the peripheral circuit arranged on the first semiconductor substrate via the wiring structure, and the peripheral circuit arranged on the first semiconductor substrate A part of the peripheral circuit is connected to a part of the peripheral circuit disposed on the second semiconductor substrate through a wiring structure.

  According to such a configuration, it is possible to provide a solid-state imaging device with high connection reliability between the pad and the peripheral circuit.

  Moreover, the manufacturing method of the solid-state imaging device of this invention has the process of bonding a 1st member and a 2nd member. The first member has a first semiconductor substrate having a photoelectric conversion element disposed on the surface, and a first wiring structure disposed on the surface of the first semiconductor substrate. The second member includes a second substrate in which at least a part of a peripheral circuit for generating a signal based on the charge of the photoelectric conversion element is disposed on the surface, and a second wiring structure disposed on the surface of the second semiconductor substrate. Have The step of bonding is performed so as to connect the first wiring structure and the second wiring structure. After the bonding step, there is a step of thinning the first semiconductor substrate from the back surface side of the first semiconductor substrate. Before the bonding step, the first wiring structure or the second wiring structure is connected to the pad connected to the external terminal, and after the thinning step, the step of exposing the pad to the first semiconductor substrate side is performed. Have.

  Such a manufacturing method makes it easy to form a connection between the pad and the peripheral circuit.

  Hereinafter, the present invention will be described in detail with reference to the drawings. The first solid-state imaging device described above will be described using Embodiments 1 to 3, and the second solid-state imaging device will be described using Embodiment 4. In the description of the embodiments, the main surface of the first substrate and the main surface of the second substrate are the surfaces of the substrate. For each substrate, the surface opposite to the main surface (front surface) is the back surface of the first substrate and the back surface of the second substrate. In each substrate, the upward direction is a direction from the back surface to the main surface (front surface), and the downward direction and the depth direction are directions from the main surface (front surface) to the back surface of the substrate. In the solid-state imaging device, the first substrate is arranged on the second substrate in accordance with the display direction of the drawing, the direction from the second substrate to the first substrate is upward, and the first substrate to the second substrate. In some cases, the direction toward is down.

Example 1
A first embodiment of the present invention will be described with reference to FIGS.

  First, the circuit of the solid-state imaging device according to the first embodiment will be described with reference to FIG. In this embodiment, the case where the signal charge is, for example, electrons will be described. The solid-state imaging device in FIG. 3 includes a pixel portion 301 in which a plurality of photoelectric conversion elements are arranged. In addition, the peripheral circuit portion 302 includes a readout circuit that reads out signals from the pixel portion 301, a control circuit for driving the pixel portion 301 and the readout circuit, and a peripheral circuit that includes a signal processing circuit that processes the readout signals. .

  In the pixel portion 301, a plurality of photoelectric conversion elements 303, transfer transistors 304, amplification transistors 306, and reset transistors 307 are arranged. A configuration including at least one photoelectric conversion element 303 is a pixel. One pixel of this embodiment includes a photoelectric conversion element 303, a transfer transistor 304, an amplification transistor 306, and a reset transistor 307. The anode of the photoelectric conversion element 303 is grounded. The source of the transfer transistor 304 is connected to the cathode of the photoelectric conversion element 303, and the drain region of the transfer transistor 304 is connected to the gate electrode of the amplification transistor 306. The same node as the gate electrode of the amplification transistor 306 is referred to as a node 305. The reset transistor is connected to the node 305 and sets the potential of the node 305 to an arbitrary potential (for example, a reset potential). Here, the amplification transistor 306 is a part of the source follower circuit, and outputs a signal corresponding to the potential of the node 305 to the signal line RL. Node 305 may also be referred to as a floating diffusion. A circuit including the transfer transistor 304, the amplification transistor 306, and the reset transistor 307 is a pixel circuit.

  A peripheral circuit portion 302 indicates an area other than the pixel portion 301. In the peripheral circuit portion 302, peripheral circuits including a readout circuit and a control circuit are arranged. The peripheral circuit includes a vertical scanning circuit VSR that is a control circuit for supplying a control signal to the gate electrode of the transistor of the pixel portion 301. The peripheral circuit includes a readout circuit RC that holds a signal output from the pixel portion 301 and performs signal processing such as amplification, addition, and AD conversion. The peripheral circuit includes a horizontal scanning circuit HSR that is a control circuit that controls the timing of sequentially outputting signals from the readout circuit RC.

  Here, the solid-state imaging device according to the first embodiment is configured by bonding two members. The two members are a first member 308 having the first substrate 101 and a second member 309 having the second substrate 121. A photoelectric conversion element 303 and a transfer transistor 304 in the pixel portion 301 are arranged on the first substrate 101, and an amplification transistor 306, a reset transistor 307 and a peripheral circuit portion 302 in the pixel portion 301 are arranged on the second substrate 121. And are arranged. A control signal from the peripheral circuit portion 302 of the second member 309 to the gate electrode of the transfer transistor 304 of the first member 308 is supplied via the connection portion 310. The configuration of the connection unit 310 will be described later. A signal generated in the photoelectric conversion element 303 of the first member 308 is read to the drain region of the transfer transistor 304, that is, the node 305. The node 305 includes a configuration disposed on the first member 308 and a configuration disposed on the second member 309.

  With such a configuration, the area of the photoelectric conversion element 303 can be increased and sensitivity can be improved as compared with the case where all the pixel portions are arranged on one conventional member (that is, one substrate). Become. In addition, as compared to the case where all the pixel portions are arranged on one conventional member (that is, one substrate), if the areas of the photoelectric conversion elements are the same, a large number of photoelectric conversion elements 303 can be provided. Pixelization is possible. Note that at least the photoelectric conversion element may be disposed on the first substrate, and the amplification transistor 306 may be disposed on the first substrate. Further, a configuration in which the transfer transistor is not provided and the photoelectric conversion element and the gate electrode of the amplification transistor are connected may be employed. In the present invention, the elements arranged on the first substrate can be arbitrarily selected, and the configuration of the pixel circuit can also be arbitrarily selected.

  A specific planar layout of such a solid-state imaging device will be described with reference to a schematic plan view of the solid-state imaging device in FIG. 2A shows a planar layout of the first member 308, that is, the first substrate (101), and FIG. 2B shows a planar layout of the second member 309, that is, the second substrate (121).

  2A, the first member 308 is provided with a pixel portion 301A in which a plurality of photoelectric conversion elements are arranged, and a pad portion 312A in which a pad 313 is provided. In the pixel portion 301A, a plurality of photoelectric conversion elements 303, transfer transistors 304, and connection portions 310 and 311 in FIG. 3 are arranged. The pad portion 312A is provided with a connection portion 314A for connection to the second member 309 at the same position as the pad 313 in plan view. An external terminal is connected to the pad 313. An example of the external terminal is a bonding wire connected to the pad 313 by a wire bonding method. A plurality of pads 313 are arranged in the solid-state imaging device, and a voltage for driving a pad (output pad) that outputs a signal (image signal) based on charges generated by the photoelectric conversion element and a peripheral circuit supplied from the outside. Etc. are input pads (input pads).

  Next, in FIG. 2B, the second member 309 is provided with a pixel portion 301B, a peripheral circuit portion 302, and a pad portion 312B. A part of the pixel circuit is arranged in the pixel portion 301B, and a plurality of amplification transistors 306, reset transistors 307, connection portions 310, and connection portions 311 in FIG. A part of the peripheral circuit is arranged in the peripheral circuit unit 302, and a horizontal scanning circuit HSR, a vertical scanning circuit VSR, and a readout circuit RC are arranged. The pad portion 312B has a protection diode circuit 315. A connection portion 314B for connection to the first member 308 is disposed on the pad portion 312B at the same position as the protection diode circuit 315 in a plan view. The protection diode circuit 315 and the connection portion 314B may not be disposed at the same position in a plan view. The protection diode circuit 315 is connected to the peripheral circuit. Specifically, a plurality of protection diode circuits 315 are provided as shown in FIG. 2B, and the protection diode circuit 315 connected to each pad 313 includes a vertical scanning circuit VSR and a horizontal scanning circuit HSE, respectively. Or, it is connected to the readout circuit RC. As described above, the second substrate 121 includes the pixel circuit disposed in the pixel portion 301, the peripheral circuit disposed in the peripheral circuit portion 302, and the protection diode circuit disposed in the pad portion 312B. Yes. These circuits are semiconductor integrated circuits, and are composed of a large number of semiconductor elements including transistors, diodes, resistor elements, capacitor elements, and the like. By operating an integrated circuit including a semiconductor element, a signal based on the charge (signal charge) of the photoelectric conversion element 303 is generated.

  Then, the first member 308 and the second member 309 having the planar layout shown in FIGS. 2A and 2B are bonded to each other to constitute the solid-state imaging device of this embodiment. Specifically, the pixel portion 301A and the pixel portion 301B are arranged so as to overlap each other. Then, the connecting portion 314A and the connecting portion 314B are connected, and the connecting portion 310 of the first member, the connecting portion 311 and the connecting portion 310 of the second member, and the connecting portion 311 are connected. In FIG. 2, the region of the first member 308 corresponding to the peripheral circuit portion 302B of the second member 309 is indicated by the peripheral circuit portion 302A. A part of the scanning circuit, that is, a part of the peripheral circuit may be arranged in the peripheral circuit portion 302A.

  Next, a schematic cross-sectional view of the solid-state imaging device shown in FIGS. 2 and 3 will be described with reference to FIG. In FIG. 1, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof is omitted.

  The first member 308 includes a first wiring structure 149 and a first substrate 101. The first substrate 101 is, for example, a silicon semiconductor substrate, and has a main surface 102 and a back surface 103. Transistors are arranged on the main surface 102 of the first substrate. The first wiring structure 149 includes interlayer insulating films 104 to 106, a gate electrode layer 107 including a gate electrode and a wiring, wiring layers 109 and 111 including a plurality of wirings, a contact layer 108 including a plurality of contacts or vias, 110. Here, the number of interlayer insulating films, wiring layers, and contact layers included in the first wiring structure 149 can be arbitrarily set. In this embodiment, the number of wiring layers is two. Note that the wiring layer 111 of the first wiring structure 149 includes a connection portion.

  In the pixel portion 301 of the first member 308, an n-type semiconductor region 112 that constitutes a photoelectric conversion element, an n-type semiconductor region 114 that is a drain of a transfer transistor, and an element isolation structure 119 are arranged on the first substrate 101. Has been. The transfer transistor includes an n-type semiconductor region 112, an n-type semiconductor region 114, and a gate electrode 113 included in the gate electrode layer 107. Here, the charge accumulated in the n-type semiconductor region 112 is transferred to the n-type semiconductor region 114 by the gate electrode 113. The potential based on the charge transferred to the n-type semiconductor region 114 is transmitted to the second member 309 via the contact of the contact layer 108, the wiring of the wiring layer 109, the via of the contact layer 110, and the wiring of the wiring layer 111. . The wiring of this wiring layer 111 constitutes a connection portion 311. The photoelectric conversion element may be a buried photodiode having a p-type semiconductor region or a photogate, and can be changed as appropriate.

  On the back surface 103 side of the first substrate 101 of the pixel portion 301, a planarizing layer 115, a color filter layer 116 including a plurality of color filters, a planarizing layer 117, and a microlens layer 118 including a plurality of microlenses are arranged in this order. Has been. In FIG. 1, each of the plurality of color filters and the plurality of microlenses corresponds to one photoelectric conversion element, that is, is arranged for each pixel, but may be provided for each of the plurality of pixels. . The solid-state imaging device of the present embodiment is a so-called back-illuminated solid-state imaging device in which light enters from the microlens layer 118 side and is received by a photoelectric conversion element.

  The pad portion 312 of the first member 308 is provided with a pad 313 and an opening 100 that exposes the pad 313 for connection to an external terminal. In the present embodiment, the pad 313 will be described as an example of the input pad. The pad 313 is a conductive film and has a first surface 3131 and a second surface 3132 which is a surface opposite to the first surface. The first surface 3131 of the pad 313 is exposed to the first substrate 101 side, and an external terminal is connected to the first surface 3131. In addition, a connection portion 314 </ b> A that transmits the voltage input from the pad 313 to the second member 309 is disposed. The connection portion 314A is disposed at the same position as the pad 313 in plan view. In the first member 308, an arbitrary circuit element 120 is provided in a region corresponding to the peripheral circuit portion 302 of the second member 309 as shown in FIG.

  The second member 309 includes the second wiring structure 150 and the second substrate 121. The second substrate 121 is a silicon semiconductor substrate, for example, and has a main surface 122 and a back surface 123. Transistors are disposed on the main surface 122 of the second substrate. The second wiring structure 150 includes an interlayer insulating films 124 to 127, a gate electrode layer 128 including gate electrodes and wirings, wiring layers 130, 132, and 134 including a plurality of wirings, and a contact layer including a plurality of contacts or vias. 129, 131, 133. Here, the number of interlayer insulating films, wiring layers, and contact layers included in the second wiring structure 150 can be arbitrarily set. In the present embodiment, the number of wiring layers of the second wiring structure 150 is 3, and there are more wiring layers than the first wiring structure 149. Note that the wiring layer 134 includes a connection portion.

  In the pixel portion 301 of the second member 309, the second substrate 121 includes a well 135 that forms an amplification transistor of the pixel circuit, an n-type semiconductor region 138 that forms a source / drain region of the amplification transistor, and an element isolation structure 136. And are arranged. The amplification transistor is arranged in the well 135 and includes a gate electrode 137 included in the gate electrode layer 128 and an n-type semiconductor region 138 that constitutes a source / drain region. Here, the connection portion 311 of the first member 308 and the gate electrode 137 of the amplification transistor include the wiring of the wiring layer 134, the via of the contact layer 133, the wiring of the wiring layer 132, the via of the contact layer 131, and the wiring of the wiring layer 130. And are connected through contacts of the contact layer 129. Here, the node 305 in FIG. 3 includes the n-type semiconductor region 114 in FIG. 1, the wiring in the wiring layers 109, 111, 134, 132, and 130, and the contacts or vias in the contact layers 108, 110, 133, 131, and 129. And a gate electrode 137. Other circuits (for example, a reset transistor) of the pixel portion 301 are not shown.

  Next, in the peripheral circuit portion 302 of the second member 309, at least a part of a peripheral circuit including a control circuit such as a horizontal scanning circuit and a vertical scanning circuit and a reading circuit is disposed. FIG. 1 shows an n-type transistor and a p-type transistor in an arbitrary circuit included in the peripheral circuit. An n-type transistor including a gate electrode 140 included in the gate electrode layer 128 and an n-type source / drain region 141 is disposed in the p-type well 139. A p-type transistor having a gate electrode 143 included in the gate electrode layer 128 and a p-type semiconductor region 144 constituting a p-type source / drain region is disposed in the n-type well 142.

  The pad portion 312 of the second member 309 is provided with a protective diode circuit 315 for inputting a signal from the pad 313 of the first member 308 and a connection portion 314B for connecting to the first member 308. ing. The connection portion 314B is arranged at the same position as the protection diode circuit 315 in plan view. The protection diode circuit 315 according to the present embodiment includes two diodes 145 and 146 each including a semiconductor region, and two resistors 147 and 148 each including a gate electrode layer 128.

  The resistor 147 is an input of the protection diode circuit 315, and the resistor 148 is an output of the protection diode. The protection diode circuit 315 has the following configuration. The pad 313 and one end of the resistor 147 are connected, and the other end of the resistor 147 is connected to the anode of the diode 145, the cathode of the diode 146, and one end of the resistor 148 through the wiring layer 130. The other end of the resistor 148 is connected to the circuit element 320 of the peripheral circuit section 302 (for example, the vertical scanning circuit VSR or the horizontal scanning circuit HSR) at the subsequent stage. That is, at the node typified by the wiring layer 130, the other end of the resistor 147, the anode of the diode 145, the cathode of the diode 146, and one end of the resistor 148 are connected. The cathode of the diode 145 is connected to a predetermined voltage VDD by a wiring (not shown), and the anode of the diode 146 is connected to a voltage VSS different from the predetermined voltage by a wiring (not shown). Here, the voltage relationship is VDD> input voltage> VSS. Further, VSS may be a voltage lower than VDD, and may be a reference voltage GND. By providing such a protection diode circuit, for example, when a voltage larger than the sum of VDD and the forward voltage drop in the diode 145 is input to the pad 313, a forward bias is applied to the diode 145, and the node Current flows from VDD to VDD. Therefore, it is possible to prevent a voltage larger than the sum of VDD and the forward voltage drop in the diode 145 from being applied to the subsequent circuit. Further, when a voltage smaller than the difference between the forward voltage of VSS and the diode 146 is input to the pad, a forward bias is applied to the diode 146, and a current flows from VSS to the node. Therefore, it is possible to prevent a voltage smaller than the forward voltage difference between VSS and the second diode 146 from being applied to the subsequent circuit. Note that the resistors 147 and 148 have an effect of dropping the input voltage and reducing the absolute value of the voltage applied to the subsequent stage.

  The protection diode circuit 315 shown in this embodiment is an example, and the protection diode circuit having a configuration generally used is applicable without being limited to this embodiment. For example, the protection diode circuit 315 is effective when the input voltage is VDD> input voltage> VSS, but a protection diode circuit corresponding to VDD <input voltage or input voltage <VSS may be provided as necessary. . In this case, only one diode may be used for the protection diode circuit. Here, the input pad is taken as an example, but the protection diode circuit 315 can be similarly connected to the output pad. In that case, the resistor 148 is used as the input of the protection diode circuit 315, the resistor 147 is used as the output of the protection diode circuit 315, and the other end of the resistor 148 is used as the circuit element 320 of the peripheral circuit section 302 (for example, the readout circuit RC) in the preceding stage. It can be set as the structure connected with. In addition, the protection diode circuit may be arranged in an electrical path between the pixel circuit and the pad. The protection diode circuit 315 connected to the output pad can also suppress the output of the abnormal signal to the outside of the apparatus when an abnormal signal is generated inside the solid-state imaging device. A protection circuit such as the protection diode circuit 315 can reduce mixing of external noise from the pad 313. Further, it becomes possible to protect the subsequent circuit against erroneous input and surge voltage. As described above, the cause of external noise includes erroneous input, voltage surge, and the like. In particular, in order to protect a peripheral circuit from a voltage surge caused by electrostatic discharge (ESD), it is very significant to arrange the protection diode circuit 315 on the second substrate 121. Since there is a high possibility that a voltage surge due to electrostatic discharge will be mixed without distinction between the input pad and the output pad, it is desirable that the protection diode circuit is arranged corresponding to both the input pad and the output pad. In addition, as an example of a protection circuit arranged to reduce the introduction of external noise, a protection diode circuit is given as an example. However, the protection circuit using a transistor is not limited to a protection circuit using a diode. Similar effects can be obtained. Note that the protection diode circuit 315 may be omitted, and the input pad may be connected to the peripheral circuit or the pixel circuit, or the output pad may be connected to the peripheral circuit. However, in terms of improving electrical reliability, it is desirable to provide a protection circuit between the input pad and / or output pad and the peripheral circuit portion 302. Further, the protection circuit may be arranged in the middle of the electrical path between the pixel circuit and the pad.

  In the solid-state imaging device according to the present embodiment, the main surface 102 of the first substrate 101 and the main surface 122 of the second substrate 121 are arranged to face each other via the first wiring structure 149 and the second wiring structure 150. (Opposed arrangement). That is, the first substrate 101, the first wiring structure 149, the second wiring structure 150, and the second substrate 121 are arranged in this order. The upper surface of the first wiring structure 149 and the upper surface of the second wiring structure 150 are bonded to each other at the bonding surface X. That is, the first member 308 and the second member 309 are joined at the joining surface X. The bonding surface X is constituted by the upper surface of the first wiring structure 149 and the upper surface of the second wiring structure 150. As a result, the first wiring structure 149 and the second wiring structure 150 are integrated to form a wiring structure 151 between the first substrate 101 and the second substrate 121. The wiring structure 151 includes five wiring layers 109, 111, 130, 132, and 134. In addition, for bonding the first wiring structure 149 and the second wiring structure 150, a connection member such as micro bonding may be used between them, or metal bonding may be used. Such joining is achieved at the connection portion 311 and the connection portion 314.

  A pad 313 of the solid-state imaging device for exchanging signals with the outside is disposed on the upper surface of the second substrate 121, which is the main surface 122 of the second member 309, and an opening 100 is provided on the first member 308 side. It has been.

  That is, both the first surface 3131 and the second surface 3132 of the pad 313 are located closer to the first substrate 101 than the main surface 122. Here, the principal plane 102 of the first substrate 101 is expanded to consider a virtual plane 1020. The virtual plane 1020 is a surface obtained by virtually extending the main surface 102, and is parallel to the main surface 102 and includes the main surface 102. Therefore, the virtual plane 1020 crosses the opening 100 in FIG. The pad 313 is located between the main surface 122 of the second substrate 121 and the virtual plane 1020. Specifically, the first surface 3131 of the pad 313 is located between the virtual plane 1020 and the second surface 3132, and the second surface 3132 of the pad 313 is formed between the first surface 3131 and the main surface of the second substrate 121. Located between. In this embodiment, the pad 313 is arranged in the same layer as the first wiring layer 109 counted from the virtual plane 1020 side among the five wiring layers.

  As described above, the pad 313 is positioned between the main surface 122 of the second substrate 121 and the virtual plane 1020, so that the distance between the pad 313 and the second substrate 121 is set to be the first substrate 101 and the second substrate. It can be less than 121. As a result, the electrical path between the pad 313 and the peripheral circuit can be shortened. As a result, signal delay and loss at the input and / or output can be reduced. The distance (interval) between the first substrate 101 and the second substrate 121 is actually in the range of 1 μm to 10 μm. If the distance between the pad 313 and the second substrate 121 is 5 μm or less, it can be said that the electrical path is sufficiently short. The distance (interval) between the first substrate 101 and the second substrate 121 is preferably 1.5 μm to 3.0 μm. In this case, the electrical path from the pad 313 to the protection diode circuit 315 is several μm or less, and Can be on the order of submicrons.

  In addition, since it is not necessary to provide an opening in the second member 309, it is possible to reduce the intrusion of moisture into the peripheral circuit portion of the second member 309. In the present embodiment, the number of elements arranged in the vicinity of the pad portion 312A of the first member 308 can be easily made smaller than the number of elements arranged in the vicinity of the pad portion 312B of the second member 309. The element arranged close to the pad portion of the first member 308 can be separated from the element arranged close to the pad portion of the second member 309. Therefore, it is possible to further reduce the influence of moisture from the opening 100 for the pad on the element. Further, since the external terminals are arranged on the back surface side of the first member 308, the connection to the pad 313 is facilitated, and the connection failure is reduced.

  In the pad portion 312, the pad 313 passes through the contact layer 110 and the wiring layer 111 (connection portion 314 </ b> A) of the first wiring structure 149, and further, the wiring layer 134 (connection portion 314 </ b> B) and the contact layer of the second wiring structure 150. 133, the wiring layer 132, the contact layer 131, the wiring layer 130, the contact layer 129, and the gate electrode layer 128 are connected to the protection diode circuit 315. In this way, the second surface 3132 of the pad 313 is connected to the wiring structure 151. With such a configuration, the pad 313 is positioned between the main surface 122 of the second substrate 121 and the virtual plane 1020, and an electrical path is formed from the second surface 3132 of the pad 313, whereby the pad 313 and the protection diode are formed. An electrical path to the circuit 315 can be shortened. As a result, the electrical path between the pad 313 and the peripheral circuit can also be shortened.

  As described above, the pad portion 312B is provided with the connection portion 314B for connection to the first member at the same position as the protection diode circuit 315 in plan view. Further, the pad portion 312A is provided with a connection portion 314A for connection to the second member 309 at the same position as the pad 313 in plan view. By connecting the connection portion 314A and the connection portion 314B, the protection diode circuit 315 and the pad 313 are also arranged at the same position in a plan view, so that the protection diode circuit 315 and the pad 313 overlap each other. Therefore, the protection diode circuit 315 and the pad 313 can be connected by the shortest electrical path.

  In the case where the protection diode circuit 315 is omitted, the peripheral circuit portion 302 and the circuit element 320 may be disposed at a position overlapping with the pad 313 and connected to the pad 313 via the wiring structure 151.

  In this embodiment, the pad 313 is connected to a plurality of vias of the contact layer 133. As described above, since the connection between the wiring structure 151 and the pad 313 where external force is easily applied is made at a plurality of locations, the force applied to the wiring structure 151 is dispersed, so that the impact on the second substrate 10 and the wiring structure 151 is reduced. Is alleviated. Further, even if the connection with any of the vias is impaired, the connection between the pad 313 and the wiring structure 151 is more likely to be maintained, so that the reliability is improved.

  Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS. 4 is a schematic cross-sectional view showing the manufacturing process of the first member 308, FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the second member 309, and FIG. 6 shows the first member 308 and the second member 309. It is a cross-sectional schematic diagram which shows the manufacturing process after joining.

  A manufacturing process of the first member 308 of FIG. 1 will be described with reference to FIG. In FIG. 4, a configuration that later becomes the first member 308 in FIG. 1 is 308 ′, and the pixel portion 301, the peripheral circuit portion 302, the pad portion 312, and the circuit element 120 that is a part of the peripheral circuit in FIG. 304 ′, 302 ′, 312 ′, and 120 ′.

  First, a semiconductor substrate is prepared, and an element is formed on the semiconductor substrate. A semiconductor substrate 401 having a thickness D3 having a main surface 402 and a back surface 403 is prepared. The semiconductor substrate 401 is a silicon semiconductor substrate, for example. An element isolation structure 119 is formed on the semiconductor substrate 401. The element isolation structure 119 includes an insulator such as a silicon oxide film, and has, for example, a LOCOS or STI structure. Then, an arbitrary conductivity type well (not shown) is formed in the semiconductor substrate 401. Thereafter, n-type semiconductor regions 112 and 114 and a p-type semiconductor region (not shown) constituting the photoelectric conversion element and the transistor are formed. In addition, the gate electrode layer 107 including the gate electrode including the gate electrode 113 of the transfer transistor is formed. The gate electrode layer is formed, for example, by depositing and patterning a polysilicon layer, and may include not only the gate electrode but also a wiring. Here, the formation method of the gate electrode, element isolation, and semiconductor region can be formed by a general semiconductor process, and detailed description thereof is omitted. As described above, the configuration of FIG. 4A is obtained.

  Next, a wiring structure is formed on the main surface 402 of the semiconductor substrate 401. The wiring structure includes interlayer insulating films 104 ′, 105, and 106, contact layers 108 and 110, and wiring layers 109 and 111. Here, the interlayer insulating film 104 ′ will later become the interlayer insulating film 104 of FIG. 1. The interlayer insulating film 104 ′ covers the gate electrode layer 107, the contact layer 108 is disposed on the interlayer insulating film 104 ′, and the wiring layer 109 and the pad 313 are disposed on the interlayer insulating film 104 ′. The interlayer insulating film 105 covers the wiring layer 109, the contact layer 110 is disposed on the interlayer insulating film 105, the wiring layer 111 is disposed on the interlayer insulating film 105, and the interlayer insulating film 106 is disposed on the interlayer insulating film 105. And an opening through which the wiring of the wiring layer 111 is exposed. The upper surface of the wiring structure is formed by the upper surface of the interlayer insulating film 106 and the upper surface of the wiring layer 111.

  Here, the interlayer insulating film is a silicon oxide film. However, the interlayer insulating film may be formed of a silicon nitride film or an organic resin. The wiring layer is made of wiring mainly composed of aluminum or wiring mainly composed of copper. The contact may be formed of tungsten, for example, and the via may be formed integrally with a wiring mainly composed of tungsten or copper. Here, the wiring layer 111 includes connection portions 314A and 311A, and is composed of wiring mainly composed of copper. Further, the wiring layer 109 is composed of wiring mainly composed of aluminum. The pad 313 is arranged in the same layer as the wiring layer 109 and contains aluminum as a main component. The manufacturing method of the wiring layer, contact layer, interlayer insulating film, and pad 313 can be formed by a general semiconductor process, and detailed description thereof is omitted. As described above, the configuration of FIG. 4B is obtained. In FIG. 4B, reference numerals 104 ', 105, 106, and 108 to 111 later become the first wiring structure 149 in FIG. Further, the connecting portion 311A constitutes the connecting portion 311 later.

  Next, the manufacturing process of the 2nd member 309 of FIG. 1 is demonstrated using FIG. In FIG. 5, the configuration that will later become the second member 309 in FIG. 1 is 309 ′, and the portions that become the pixel portion 301, the peripheral circuit portion 302, the pad portion 312, and the protection diode circuit 315 in FIG. , 312 ′, 315 ′.

  First, a semiconductor substrate is prepared, and an element is formed on the semiconductor substrate. A semiconductor substrate 404 having a thickness D4 having a main surface 405 and a back surface 406 is prepared. Then, an element isolation structure 136 is formed on the semiconductor substrate 404 using a LOCOS or STI structure. In addition, p-type wells 135 and 139 and n-type well 142 are formed in the semiconductor substrate 404. Thereafter, n-type semiconductor regions 138 and 141 and p-type semiconductor region 144 that can serve as source / drain regions constituting a transistor, and a semiconductor region constituting a diode are formed. Then, a gate electrode layer 128 including gate electrodes 137, 140, and 143 and wiring (resistance) of the transistor is formed by depositing and patterning a polysilicon layer. Here, the formation method of the gate electrode, element isolation, and semiconductor region can be formed by a general semiconductor process, and detailed description thereof is omitted. As described above, the configuration of FIG. 5A is obtained.

  Next, a wiring structure is formed on the main surface 405 of the semiconductor substrate 404. The wiring structure includes interlayer insulating films 124 to 127, contact layers 129, 131, and 133, and wiring layers 130, 132, and 134. The interlayer insulating film 124 covers the gate electrode layer 128, the contact layer 129 is disposed on the interlayer insulating film 124, and the wiring layer 130 is disposed on the interlayer insulating film 124. In addition, the interlayer insulating film 125 covers the wiring layer 130, the contact layer 131 is disposed on the interlayer insulating film 125, the wiring layer 132 is disposed on the interlayer insulating film 125, and the interlayer insulating film 126 covers the wiring layer 132 and interlayer insulating Disposed on the film 125. The contact layer 133 is disposed on the interlayer insulating film 126, the wiring layer 134 is disposed on the interlayer insulating film 126, the interlayer insulating film 127 is disposed on the interlayer insulating film 126, and the wiring of the wiring layer 134 is exposed. Has an opening. The upper surface of the wiring structure is formed by the upper surface of the interlayer insulating film 127 and the upper surface of the wiring layer 134.

  Here, the interlayer insulating film is a silicon oxide film. It may be formed of a silicon nitride film or an organic resin. The wiring layer is made of wiring mainly composed of aluminum or wiring mainly composed of copper. Here, the wiring layer 134 includes connection portions 314B and 311B, and is composed of wiring mainly composed of copper. The wiring layer, contact layer, and interlayer insulating film manufacturing method can be formed by a general semiconductor process and will not be described in detail. Thus, the configuration of FIG. 5B is obtained. In FIG. 5B, reference numerals 124 to 127, 129 to 134, etc. later become the first wiring structure 150 in FIG. Further, the connecting portion 311B configures the connecting portion 311 later.

  The first member 308 ′ and the second member 309 ′ shown in FIGS. 4B and 5B are bonded to each other so that the main surface 402 and the main surface 405 of the semiconductor substrates face each other. . That is, the uppermost surface of the wiring structure of the first member 308 'and the uppermost surface of the wiring structure of the second member 309' are joined. Here, since the connection portions 311A and 311B and the connection portions 314A and 314B are composed of wiring mainly composed of copper, it is possible to perform bonding by copper metal bonding.

  After the first member 308 ′ and the second member 309 ′ are joined, the semiconductor substrate 401 is thinned from the back surface 403 side of the semiconductor substrate 401 of the first member 308 ′, and the semiconductor substrate 401 is thinned. Thinning can be performed by CMP (chemical mechanical polishing) or etching. Then, the semiconductor substrate 401 becomes the semiconductor substrate 407, and the thickness becomes D3 to D1 (D1 <D3) (FIG. 6A). By thinning the semiconductor substrate 401 in this manner to form the semiconductor substrate 407, incident light can be efficiently incident on the photoelectric conversion element later. At this time, the thickness D1 of the semiconductor substrate 407 <the thickness D4 of the semiconductor substrate 404.

  Next, a planarizing layer 409 made of resin, a color filter layer 410, a planarizing layer 411 made of resin, and a microlens layer 412 are formed in this order on the back surface 408 of the semiconductor substrate 407. About the manufacturing method of these planarization layer, a color filter layer, and a micro lens layer, it can form with a general semiconductor process, and detailed description is abbreviate | omitted. Here, the microlens layer may be formed up to the region 312 'serving as a pad portion. Through the above steps, the structure shown in FIG. 6B is obtained.

  Then, an opening 100 for exposing the pad 313 is formed. Here, a photoresist mask having an arbitrary opening is provided on the microlens layer 412 by using a photolithography technique. Then, using a dry etching technique, the microlens layer 412, the planarizing layer 411, the color filter layer 410, the planarizing layer 409, the semiconductor substrate 407, and the interlayer insulating film 104 ′ are removed, and an opening 100 is formed. The pad 313 is exposed from the opening 100.

  Then, the microlens layer 118, the planarization layers 117 and 115, the color filter layer 116, the first substrate 101, and the interlayer insulating film 104 are formed. As described above, the configuration of FIG. 1 is obtained. Note that the semiconductor substrate 404, the main surface 405, the back surface 406, and the thickness D4 in FIG. 6B correspond to the second substrate 121, the main surface 122, the back surface 123, and the thickness D2 in FIG.

  Here, the thicknesses D4 and D2 are not changed, but the semiconductor substrate 404 may be thinned so that the thickness D2 <D4. Although thinning increases the number of steps, it is possible to reduce the size of the solid-state imaging device.

  As described above, by performing the etching for exposing the pads from the side of the back surface 408 of the thinned semiconductor substrate 407, it is possible to reduce the time required for etching for pad formation. Further, the pad 313 can be formed in the same process as the wiring of the wiring layer 109, and the number of steps can be reduced. The pad 313 is preferably made of a metal mainly composed of aluminum in order to reduce the connection resistance with the external terminal as in this embodiment. Note that the pad 313 can also function as an etching stopper during etching.

  This invention is not limited to the process demonstrated in the manufacturing method of a present Example, The process order may be changed. The manufacturing order of the first member 308 and the second member 309 can be set as appropriate. Furthermore, the first member 308 and the second member 309 can be purchased and bonded to each other. Note that an SOI substrate can be applied to the semiconductor substrates 401 and 402.

(Example 2)
A second embodiment of the present invention will be described with reference to FIG. 7A and 7B are schematic cross-sectional views of the solid-state imaging device, each corresponding to FIG. In FIG. 7, elements similar to those in FIG.

  In this embodiment, different structures from the first embodiment are an opening 700 and a pad 701 in FIG. 7A and an opening 702 and a pad 701 in FIG. 7B. In this embodiment, the opening 700 and the opening 702 are deeper than those in the first embodiment, and the pad 701 is closer to the main surface 122 of the second member 309 than in the first embodiment. As described above, the pad is located on the first member 308 side with respect to the main surface 122 of the second member 309, and may be disposed at any position as long as it is disposed between the virtual plane 1020 and the main surface 122. Good. However, the connection resistance from the pad 701 to the protection diode circuit 315 can be reduced as compared with the first embodiment by arranging the pads close to the second member 309 as in the present embodiment. It becomes. In this embodiment, the wiring structure 151 has five wiring layers as in the first embodiment, but the pad 701 is the same layer as the third wiring layer 134 counted from the virtual plane 1020 side among the five wiring layers. It is arranged in. As described above, it is preferable to arrange the pad 701 in a wiring layer (wiring layers 134, 132, 130) farther from the virtual plane 1020 than the wiring layer (wiring layers 109, 111) on the virtual plane 1020 side. That is, when the number N of wiring layers is an odd number, it is preferable to place the pads 701 on the same layer as the (N + 1) / 2 to Nth wiring layers counted from the virtual plane 1020 side. When the number N of wiring layers is an even number, it is preferable to place the pads 313 on the same layer as the 1+ (N / 2) to Nth wiring layers counted from the virtual plane 1020 side. 7B, the shape of the opening 702 is different from the opening 100 of the first embodiment and the opening 700 of FIG. 7A. As shown in FIG. 7B, an unnecessary interlayer insulating film and semiconductor substrate located outside the pad portion of the first member 308 may be removed. Further, the first member 308 manufactured in advance is made smaller than the second member 309, or the end surfaces of the first member 308 and the second member 309 are shifted, so that the first member 308 is provided in order to provide the opening 702. Part or all of the step of etching the member 308 can be omitted. Although the opening 702 opens toward the end of the apparatus, in order to suppress the intrusion of moisture or the like into the pad portion, a space in which the opening 700 is surrounded by the first substrate 101 as shown in FIG. It is preferable to provide a through hole in the first substrate 101 so that

  The pad 701 is disposed on the same layer as the wiring layer 134 of the second member 309. Here, the same layer is a case where they are formed in the same process or have the same height from the main surface. The pad 701 is included in the same layer as the wiring layer 134 and is formed in the same process. Therefore, the wiring layer 134 is preferably a wiring mainly composed of aluminum. In this embodiment, the wiring is mainly composed of copper as in the first embodiment. However, since it is the same layer as the pad 701, the wiring layer 134 is more preferably a wiring mainly composed of aluminum. In this case, the connection part 311 may be joined by a micro bump or the like.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIG. FIG. 8C is a schematic cross-sectional view of the solid-state imaging device of the present embodiment and corresponds to FIG. FIGS. 8A and 8B are schematic cross-sectional views for explaining the method of manufacturing the solid-state imaging device according to the present embodiment, and are drawings corresponding to FIG. 8, the same components as those in FIGS. 1 and 6 are denoted by the same reference numerals, and the description thereof is omitted.

  In this embodiment, a different structure from the first embodiment is a structure of the opening 811 and the protective film 806 in FIG. The protective film 806 of this embodiment covers the side wall (side surface) of the first substrate 101 having the opening 811. Further, the protective film 806 extends from the side wall and covers the periphery of the first surface 3131 of the pad 313. By including such a protective film 806, it is possible to reduce the intrusion of moisture from the opening 811 into the apparatus. Further, when an external terminal for connecting to the pad 313 comes into contact with a conductor such as the first substrate 101, a leak occurs. The protective film 806 prevents the external terminal from coming into contact with the conductor and suppresses the occurrence of leakage. Furthermore, the protective film 806 of this embodiment is also disposed on the incident surface of the photoelectric conversion unit of the pixel unit 301 (that is, the back surface 103 of the first substrate 101), and can also function as an antireflection film. In addition, by having the protective film 806, the configuration of the opening is different from that of the first embodiment. In addition, the configurations of the planarization layer 807, the color filter layer 808, the planarization layer 809, and the microlens layer 810 can be changed to configurations different from those in the first embodiment.

  The manufacturing method of this example will be described with reference to FIGS. 8A and 8B. Since the method is the same up to FIG. 6A of the first embodiment, the description is omitted. An opening 800 is formed in the semiconductor substrate 407 in FIG. 6A by photolithography and etching techniques, whereby the first substrate 101 is formed. The opening 800 is formed so that the pad 313 is exposed. After that, a silicon nitride film 801 that can serve as a protective film is formed so as to cover the side surface of the opening 800 and the back surface 103 of the first substrate 101 by a method such as plasma CVD, thereby obtaining the configuration of FIG.

  Thereafter, a planarization layer 802, a color filter layer 803, a planarization layer 804, and a microlens layer 805 are formed in this order so as to cover the silicon nitride film 801. Each material and manufacturing method are the same as in Example 1. Then, an opening 811 is formed. The opening 811 penetrates the silicon nitride film 801, the planarization layer 802, the color filter layer 803, the planarization layer 804, and the microlens layer 805, and the protective film 806 covers only the periphery of the first surface 3131 of the pad 313. A part of the first surface 3131 of the pad 313 is exposed. Here, the silicon nitride film 801, the planarization layer 802, the color filter layer 803, the planarization layer 804, and the microlens layer 805 are respectively a protective film 806, a planarization layer 807, a color filter layer 808, a planarization layer 809, and a microlens layer 805. The lens layer 810 is formed. Then, the solid-state imaging device shown in FIG. 8C is manufactured.

(Fourth embodiment)
A third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a schematic cross-sectional view of the solid-state imaging device of the present embodiment and corresponds to FIG. 9, the same components as those in FIGS. 1 and 6 are denoted by the same reference numerals, and the description thereof is omitted.

  In this embodiment, the first embodiment is different from the first embodiment in that the opening 900 is provided in the second substrate 121 instead of the first substrate 101, and the protection diode circuit 315 is arranged in the first substrate 101 instead of the second substrate 121. Is different. Hereinafter, these points will be described.

  A pad 313 of a solid-state imaging device for exchanging signals with the outside is disposed below the surface of the first substrate 101 which is the main surface 102 of the first member 308, and an opening 900 is provided on the second member 309 side. Yes. The pad 313 has a first surface 3131 and a second surface 3132 which is a surface opposite to the first surface 3131. The first surface 3131 of the pad 313 is exposed to the second substrate 121 side, and an external terminal is connected to the first surface 3131. That is, both the first surface 3131 and the second surface 3132 of the pad 313 are located closer to the second substrate 121 than the main surface 102. Here, a virtual plane 1220 is considered by extending the main surface 122 of the second substrate 121. The virtual plane 1220 is a surface obtained by virtually extending the main surface 122, and is parallel to the main surface 122 and includes the main surface 122. Therefore, the virtual plane 1220 crosses the opening 900 in FIG. The pad 313 is located between the main surface 122 of the first substrate 101 and the virtual plane 1220. Specifically, the first surface 3131 of the pad 313 is located between the virtual plane 1220 and the second surface 3132, and the second surface 3132 of the pad 313 is the first surface 3131 and the main surface 102 of the first substrate 101. Is located between. In this embodiment, the pad 313 is arranged in the same layer as the first wiring layer 130 among the five wiring layers, counting from the virtual plane 1220 side. The wiring layer 130 is composed of wiring mainly composed of aluminum, and the pad 313 is also composed mainly of aluminum. The wiring layer 111 includes a connection portion 314A and a connection portion 311, and the wiring layer 134 includes a connection portion 314B and a connection portion 311. Each of the wiring layers 111 includes a wiring mainly composed of copper.

  As in the second embodiment, the pads 313 are arranged on the wiring layers (wiring layers 134, 111, 109) that are further away from the virtual plane 1220 than the wiring layers (wiring layers 130, 132) on the virtual plane 1220 side. It is also possible to reduce the resistance. However, also in this embodiment, the thickness D1 of the first substrate 101 <the thickness D2 of the second substrate 121. When the distance between the first surface 3131 of the pad 313 and the back surface 103 of the first substrate 101 becomes extremely small, the mechanical strength of the pad portion 312 decreases. Therefore, the pad 313 is arranged on the same layer as the wiring layer (wiring layers 130 and 132) on the virtual plane 1220 side, and a sufficient distance is secured between the first surface 3131 of the pad 313 and the back surface 103 of the first substrate 101. It is preferable.

  The protection diode circuit 315 is disposed on the pad portion 312 of the first member 308. Further, in the peripheral circuit unit 302, a circuit element 320 constituting a part of the peripheral circuit is disposed on the first substrate 101, and the circuit element 320 is disposed on the second substrate 121 via the wiring structure 151. Connected to another part of the peripheral circuit. A wiring layer connecting peripheral circuits arranged on both substrates includes at least a wiring layer 111 including a connecting portion and a wiring layer 134. In the pad portion 312, the pad 313 passes through the contact layer 131 and the wiring layer 132 of the second wiring structure 150, and the contact layer 133 wiring layer 134 (connecting portion 314 </ b> B), and further, the wiring layer 111 ( The connection portion 314A) is connected to the protective diode circuit 315 through the contact layer 110, the wiring layer 109, the contact layer 108, and the gate electrode layer 107. The second surface 3132 of the pad 313 is connected to the contact layer 131 at a plurality of locations. As described above, when the protection diode circuit 315 which is a part of the semiconductor integrated circuit is provided on the first substrate 101, the pad 313 is located between the main surface 102 and the virtual plane 1220, and the second surface. A configuration in which an electrical path is provided from 3132 can be employed. With this configuration, the electrical path between the pad 313 and the protection diode circuit 315 and between the pad 313 and the peripheral circuit can be shortened. Also in this embodiment, the distance between the pad 313 and the first substrate 101 is preferably 5 μm or less.

  In this embodiment, the peripheral circuit is connected from the protective diode circuit 315 to the circuit element 320 which is a part of the peripheral circuit, and the circuit element 320 is arranged on the second substrate 121 via the wiring structure 151. Connected to another part of. However, the connection to the protection diode circuit 315 is not limited to the circuit element 320 of the peripheral circuit. For example, the protection diode circuit 315 is connected to a pixel circuit (for example, a transfer transistor) disposed on the first substrate 101, and the pixel circuit and a peripheral circuit disposed on the second substrate 121 are connected via the wiring structure 151. May be. Further, the protection diode circuit 315 may be directly connected to the peripheral circuit disposed on the second substrate 121 via the wiring structure 151 without passing through the peripheral circuit disposed on the first substrate 101. In the solid-state imaging device of this embodiment, a bonding wire can be used as an external terminal as in the first embodiment, but flip-chip bonding can also be used. By disposing external terminals on the back surface 123 of the second substrate 121, deterioration or damage of the external terminals or intrusion of moisture from around the pad can be suppressed.

  The opening 900 can be formed by etching a part of the second substrate 121 and the second wiring structure 150. In this embodiment, the end portion of the second substrate 121 may be removed as in FIG. 7B described in the second embodiment, or a protective film may be provided as in the third embodiment. it can.

  As described above, according to the solid-state imaging device of the present embodiment, it is possible to provide a solid-state imaging device with high connection reliability between the pad and the circuit.

  Hereinafter, as an application example of the solid-state imaging device according to each of the embodiments described above, an imaging system in which the solid-state imaging device is incorporated will be exemplarily described. The imaging system includes not only a device such as a camera whose main purpose is photographing but also a device (for example, a personal computer or a portable terminal) that is supplementarily provided with a photographing function. For example, the camera includes a solid-state imaging device according to the present invention and a processing unit that processes a signal output from the solid-state imaging device. The processing unit may include, for example, an A / D converter and a processor that processes digital data output from the A / D converter. A signal to be processed is input to the processing unit via an external terminal such as a bonding wire connected to the pad of the solid-state imaging device.

  As described above, according to the solid-state imaging device of the present invention, it is possible to provide a solid-state imaging device with high connection reliability between the pad and the circuit. Further, according to the present invention, the connection between the pad and the circuit can be facilitated.

  Note that the present invention is not limited to the configuration described in the specification, and the conductivity type and the circuit can be changed to the reverse conductivity type. Moreover, although the connection part demonstrated the structure which consists of wiring of a wiring layer, a via | veer and a micro bump may be sufficient as long as it is the structure which can ensure conduction | electrical_connection. Moreover, it is also possible to combine the structure of each Example suitably.

301 Pixel part 302 Peripheral circuit part 308 First member 309 Second member 149 First wiring structure 150 Second wiring structure 312 Pad part 313 Pad 101 First substrate 121 Second substrate 100 Opening X Connection surface

Claims (20)

A first semiconductor substrate on which the photoelectric conversion element and the first semiconductor element are arranged;
A second semiconductor substrate on which a second semiconductor element is disposed and overlaps the first semiconductor substrate;
A first wiring disposed between the first semiconductor substrate and the second semiconductor substrate and connected to the first semiconductor element;
A pad to which an external terminal is connected;
A second wiring connected to the second semiconductor element,
The first semiconductor substrate includes a first portion and a second portion;
The photoelectric conversion element and the first semiconductor element are arranged in the first portion,
The pad is arranged such that the external terminal is located between the first part and the second part , and the pad is located between the external terminal and the second semiconductor substrate ,
The second wiring is disposed between the pad and the second semiconductor substrate;
A wiring layer including the second wiring is disposed between the first semiconductor substrate and the second semiconductor substrate;
The first semiconductor substrate has a first surface facing the second semiconductor substrate, and a second surface opposite to the first surface, and the second semiconductor substrate is the first semiconductor. A third surface facing the substrate; and a fourth surface opposite to the third surface, wherein a distance from the third surface to the pad is from the third surface to the second surface. And the distance from the third surface to the fourth surface,
The imaging device, wherein the pad is connected to the second wiring at a plurality of locations, and is connected to the second semiconductor element via the plurality of locations and the second wiring. The imaging device according to claim 1, wherein a wiring layer including the first wiring is disposed between the first semiconductor substrate and a wiring layer including the pad .   The imaging device according to claim 1, wherein a third wiring is disposed between the second wiring and the second semiconductor substrate.   The imaging device according to claim 3, wherein the second wiring is located between the pad and the third wiring.   The imaging device according to claim 1, wherein a main component of the pad is aluminum, and a main component of the second wiring is copper.   The imaging device according to claim 1, wherein a distance between the pad and the second semiconductor substrate is smaller than a distance between the first semiconductor substrate and the second semiconductor substrate. .   The imaging device according to claim 1, wherein the second wiring has a portion overlapping the first semiconductor substrate.   The imaging device according to claim 1, wherein the second semiconductor element overlaps the pad.   The imaging according to any one of claims 1 to 8, wherein a film having an opening for connecting the external terminal to the pad is disposed between the first portion and the second portion. apparatus.   The second semiconductor substrate is disposed between the first semiconductor region overlapping the pad, the second semiconductor region overlapping the pad, the first semiconductor region and the second semiconductor region, and the insulating layer overlapping the pad. The imaging device according to claim 1, further comprising a body.   The imaging device according to claim 1, wherein a thickness of the first semiconductor substrate is smaller than a thickness of the second semiconductor substrate.   The imaging device according to claim 1, wherein the second semiconductor element is included in a protection circuit.   The imaging device according to claim 1, wherein a transistor of a source follower circuit is disposed on the first semiconductor substrate. The first semiconductor element is connected to the photoelectric conversion element;
The imaging device according to claim 1, wherein a transistor of a signal processing circuit is disposed on the second semiconductor substrate.   The imaging according to any one of claims 1 to 14, wherein an insulating film is provided between the pad and the second wiring, and the insulating film is located between the plurality of portions. apparatus. The number of wiring layers positioned between the wiring layer including the second wiring and the first semiconductor substrate is a wiring layer positioned between the wiring layer including the second wiring and the second semiconductor substrate. less than the number of image pickup apparatus according to claim 1. The number of wiring layers positioned between the wiring layer including the second wiring and the first semiconductor substrate is a wiring layer positioned between the wiring layer including the second wiring and the second semiconductor substrate. The imaging device according to claim 1 , wherein the imaging device is larger than the number of the imaging devices.   The imaging device according to claim 3, wherein the pad is connected to the second semiconductor element through the second wiring and the third wiring.   A third semiconductor element is disposed on the second semiconductor substrate, and the first semiconductor element is connected to the third semiconductor element through a connection portion formed by metal bonding of wirings mainly composed of copper. The image pickup apparatus according to claim 1, wherein the image pickup apparatus is used. An imaging device according to any one of claims 1 to 19,
A processing unit that processes a signal output from the imaging device.

Images