JP7131409B2 - Manufacturing method of trench gate type switching element - Google Patents

Description

The technology disclosed in this specification relates to a method for manufacturing a trench gate type switching element.

Patent Document 1 discloses a trench gate type switching element. This switching element has a gate insulating film covering the inner surface of the trench and a gate electrode arranged in the trench. The switching element switches by changing the potential of the gate electrode.

JP-A-10-270683

15 and 16 illustrate the trench gate formation process. 16 shows a cross section along line XVI--XVI of FIG. 15, and FIG. 15 shows a cross section along line XV--XV of FIG. In the step of forming a trench gate, a trench 100 is formed on the surface of the semiconductor substrate and a gate insulating film 112 is formed on the inner surface of the trench 100 . After that, the trench 100 is filled with the gate electrode 110 . At this time, voids 130 are likely to be formed in the interior of the trench 100 in the vicinity of the longitudinal side surfaces 102 of the trench 100 and in the vicinity of the bottom surface 104 of the trench 100 (hereinafter referred to as corner portions). Since the corner portion is surrounded by the longitudinal side surface 102, the bottom surface 104, and the lateral side surfaces 106 and 108 of the trench 100, the corner portion is difficult to be filled with the gate electrode 110. FIG. Therefore, voids 130 are likely to be formed in the corner portions. This specification proposes a technique of forming a gate electrode while suppressing the formation of voids at the corners of trenches.

A method for manufacturing a wrench gate type switching element disclosed in the present specification includes an n-type region forming step, a trench forming step, a sacrificial oxide film forming step, a sacrificial oxide film removing step, a gate insulating film forming step, and a gate electrode forming step. have a process. In the n-type region forming step, an n-type region exposed on the surface of the semiconductor substrate is formed by implanting an n-type impurity into the semiconductor substrate. In the trench forming step, trenches are formed in the surface of the semiconductor substrate. In the sacrificial oxide film forming step, after the n-type region forming step and the trench forming step, the inner surface of the trench is oxidized to form a sacrificial oxide film covering the inner surface of the trench. In the sacrificial oxide film removing step, the width of the trench is expanded by removing the sacrificial oxide film after the sacrificial oxide film forming step. In the gate insulating film forming step, a gate insulating film covering the inner surface of the trench is formed after the sacrificial oxide film removing step. In the gate electrode forming step, the trench is filled with a gate electrode after the gate insulating film forming step. The n-type region forming step and the trench forming step are performed so that the ends of the trench in the longitudinal direction are located in the n-type region on the surface of the semiconductor substrate, and the trench is positioned in the n-type region in the thickness direction of the semiconductor substrate. It is carried out so as to penetrate the mold area. In the sacrificial oxide film forming step, the sacrificial oxide film is formed to be thicker in the exposed area of the n-type region of the inner surface of the trench than in the lower area. In the step of removing the sacrificial oxide film, the width of the trench becomes wider in the exposed range of the n-type region than in the range below it.

Either the n-type region forming step or the trench forming step may be performed first.

In this manufacturing method, in the n-type region forming step and the trench forming step, the longitudinal ends of the trench are located in the n-type region on the surface of the semiconductor substrate, and the trench penetrates the n-type region in the thickness direction of the semiconductor substrate. A trench and an n-type region are formed so as to. After that, when the inner surface of the trench is oxidized in the sacrificial oxide film forming process, accelerated oxidation is obtained in the exposed range of the n-type region implanted with the n-type impurity. Therefore, in the sacrificial oxide film forming step, the sacrificial oxide film is formed to be thicker in the exposed area of the n-type region of the inner surface of the trench than in the lower area. After that, when the sacrificial oxide film is removed in the sacrificial oxide film removing process, the width of the trench is expanded. At this time, since the thickness of the sacrificial oxide film to be removed is thicker in the exposed range of the n-type region than in the range below it, the exposed range of the n-type region has a greater depth of trench than in the range below it. becomes wider. That is, the width of the upper portion of the trench is wider than the width of the lower portion of the trench at the longitudinal ends of the trench. After that, the gate electrode forming process is performed after the gate insulating film forming process. In the gate electrode forming step, the trench is filled with the gate electrode. Since the width of the upper portion (that is, the opening portion) of the trench is wide at the ends of the trench in the longitudinal direction, the trench is easily filled with the gate electrode at the ends of the trench in the longitudinal direction in the step of forming the gate electrode. Therefore, according to this manufacturing method, voids are less likely to be formed at the corners of the trench. Thus, according to this manufacturing method, the gate electrode can be formed while suppressing the formation of voids at the corners of the trench.

The top view of MOSFET of embodiment. Sectional drawing in the II-II line of FIG. Sectional drawing in the III-III line of FIG. Sectional drawing in the IV-IV line of FIG. 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; 4A to 4C are cross-sectional views for explaining a manufacturing process of the MOSFET of the embodiment; FIG. 4 is a cross-sectional view showing voids formed at corners; FIG. 4 is a cross-sectional view showing voids formed at corners;

1 to 4 show a trench gate type MOSFET (metal oxide semiconductor field effect transistor) 10 manufactured by the manufacturing method of the embodiment. As shown in FIGS. 2 to 4, the MOSFET 10 has a semiconductor substrate 12 and a conductive film, an insulating film, etc. provided on the upper surface 12a and the lower surface 12b of the semiconductor substrate 12. As shown in FIGS. In FIG. 1, illustration of a conductive film and an insulating film on the upper surface 12a of the semiconductor substrate 12 is omitted. In the following description, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is called the x direction, the direction parallel to the upper surface 12a and perpendicular to the x direction is called the y direction, and the thickness direction of the semiconductor substrate 12 is called the z direction. As shown in FIG. 1, a plurality of trenches 22 are provided in the upper surface 12a of the semiconductor substrate 12. As shown in FIG. Each trench 22 extends linearly in the x direction. The multiple trenches 22 are spaced apart in the y direction. The semiconductor substrate 12 has an element region 30 around the central portion of the trench 22 in the longitudinal direction. The element region 30 is a region for switching current. The semiconductor substrate 12 also has termination regions 50 around the longitudinal ends of the trenches 22 .

As shown in FIGS. 1 and 2, the element region 30 is provided with a plurality of source regions 32 and body regions 34 . Each source region 32 is an n-type region and is arranged in a range exposed to the upper surface 12 a of the semiconductor substrate 12 . Body region 34 is a p-type region and is arranged below each source region 32 . A part of the body region 34 extends to the upper surface 12a of the semiconductor substrate 12 in a range where the source region 32 does not exist, and is exposed on the upper surface 12a. A portion of body region 34 near upper surface 12 a has a higher p-type impurity concentration than a portion of body region 34 below source region 32 .

As shown in FIG. 2, an n-type drift region 36 is arranged below the body region 34 . A drift region 36 is separated from each source region 32 by a body region 34 . The drift region 36 is distributed up to the outside of the device region 30 . As shown in FIG. 1, the drift region 36 is exposed on the upper surface 12a outside the element region 30. As shown in FIG.

As shown in FIG. 2, an n-type drain region 38 is arranged below the drift region 36 . Drain region 38 has a higher n-type impurity concentration than drift region 36 . The drain region 38 is distributed outside the element region 30 . The drain region 38 is exposed all over the bottom surface 12b of the semiconductor substrate 12 .

As shown in FIG. 2 , within the device region 30 , each trench 22 extends to the drift region 36 in the thickness direction (z direction) of the semiconductor substrate 12 . That is, each trench 22 extends through the corresponding source region 32 and body region 34 to the drift region 36 . The inner surface of each trench 22 is covered with a gate insulating film 70 . A gate electrode 72 is disposed within each trench 22 . Gate electrode 72 is insulated from semiconductor substrate 12 by gate insulating film 70 . An upper surface of the gate electrode 72 is covered with an interlayer insulating film 74 . A contact hole 74 a is provided in the interlayer insulating film 74 . Contact hole 74 a is located above source region 32 and body region 34 . A source electrode 14 is arranged on the interlayer insulating film 74 . The source electrode 14 covers the surface of the interlayer insulating film 74 and the upper surface 12a of the semiconductor substrate 12 in the contact hole 74a. The source electrode 14 is in ohmic contact with the source region 32 and the body region 34 within the contact hole 74a. The source electrode 14 is insulated from the gate electrode 72 by an interlayer insulating film 74 . A lower surface 12 b of the semiconductor substrate 12 is covered with a drain electrode 16 . Drain electrode 16 is in ohmic contact with drain region 38 .

When the potential of the gate electrode 72 is made higher than the threshold, a channel is formed in the body region 34 near the gate insulating film 70 and the channel connects the source region 32 and the drift region 36 . Electrons then flow from the source region 32 to the drain region 38 via the channel and the drift region 36 . That is, the MOSFET 10 is turned on. When the potential of the gate electrode 72 is lowered below the threshold, the channel disappears and the flow of electrons stops. That is, the MOSFET 10 is turned off. Thus, switching is performed within the element region 30 .

As shown in FIG. 1, the termination region 50 is provided with an oxidation enhancement region 52 and a deep region 54 . As shown in FIGS. 3 and 4, the oxidation accelerating region 52 is an n-type region and is arranged in a range exposed on the upper surface 12a of the semiconductor substrate 12. As shown in FIGS. As shown in FIG. 1, the longitudinal ends of each trench 22 are located within an oxidation enhancement region 52 on the upper surface 12a. As shown in FIGS. 3 and 4, deep region 54 is a p-type region and is located below oxidation enhancing region 52 . The deep region 54 extends deeper than the body region 34 . The deep region 54 extends from the bottom edge of the oxidation enhancing region 52 to the top edge of the drain region 38 . As shown in FIG. 1, deep region 54 is separated from body region 34 by drift region 36 .

As shown in FIGS. 3 and 4 , within termination region 50 , each trench 22 extends in the thickness direction (z-direction) of semiconductor substrate 12 to deep region 54 . That is, each trench 22 penetrates through the oxidation accelerating region 52 and reaches the deep region 54 . A gate insulating film 70 and a gate electrode 72 are arranged in each trench 22 also in the termination region 50 . As shown in FIG. 3 , in the termination region 50 , the upper surface of the gate electrode 72 and the upper surface 12 a of the semiconductor substrate 12 (that is, the upper surface of the oxidation enhancing region 52 ) are covered with an interlayer insulating film 74 . As shown in FIG. 4, the gate electrode 72 is connected to a gate lead-out line 76 at the longitudinal end of each trench 22 . The gate electrode 72 is connected to a pad (not shown) via a gate lead line 76 .

Little current flows in the termination region 50 . Deep region 54 reduces electric field concentration at the longitudinal ends of trench 22 when MOSFET 10 is off.

Next, a method for manufacturing the MOSFET 10 will be described with reference to FIGS. 5 to 14, the drawings on the left side show cross sections corresponding to FIG. 3, and the drawings on the right side show cross sections corresponding to FIG. First, as shown in FIG. 5, the drift region 36 is epitaxially grown on the drain region 38 (base wafer). Next, as shown in FIG. 6, a deep region 54 is formed in the termination region 50 by selectively implanting p-type impurity ions into the semiconductor substrate 12 .

Next, as shown in FIG. 7, a body region 34 is formed within the device region 30 by selectively implanting p-type impurities into the semiconductor substrate 12 . Furthermore, by selectively implanting an n-type impurity (for example, arsenic, nitrogen, phosphorus, etc.) into the semiconductor substrate 12, a source region 32 is formed in the element region 30 and an oxidation acceleration region 52 is formed in the termination region 50. to form The source region 32 and oxidation enhancing region 52 are formed by one ion implantation. Therefore, the source region 32 and the oxidation enhancing region 52 have substantially the same depth and substantially the same n-type impurity concentration.

Next, as shown in FIG. 8, a mask layer 80 (for example, a silicon oxide layer) is formed on the upper surface 12a of the semiconductor substrate 12, and then an opening 82 is formed in the mask layer 80 by dry etching. An opening 82 is formed over the area where the trench 22 is to be formed. Next, the trenches 22 are formed by etching the upper surface 12a of the semiconductor substrate 12 (that is, the upper surface 12a within the openings 82) through the mask layer 80 by RIE (reactive ion etching). After the trenches 22 are formed, the mask layer 80 is removed using hydrofluoric acid or the like.

Next, the semiconductor substrate 12 is heated to oxidize its surface. As a result, a sacrificial oxide film 84 is formed on the surface of the semiconductor substrate 12, as shown in FIG. That is, the sacrificial oxide film 84 is formed on the upper surface 12 a of the semiconductor substrate 12 and the inner surface of the trench 22 . N-type impurities (ie, arsenic, nitrogen, phosphorous, etc.) increase the oxidation rate of semiconductor substrate 12 . As described above, since the n-type impurity is implanted into the oxidation enhancing region 52, the oxidation enhancing region 52 contains the n-type impurity at a high concentration. Therefore, when the semiconductor substrate 12 is oxidized, the surface of the oxidation accelerating region 52 is rapidly oxidized. Therefore, the sacrificial oxide film 84 becomes thicker on the surface of the oxidation accelerating region 52 . At the corners between the side surfaces of the trench 22 and the upper surface 12a of the semiconductor substrate 12, the sacrificial oxide film 84 becomes particularly thick because the oxidation progresses from both the side surface side and the upper surface side. On the other hand, the surface of the deep region 54 is slowly oxidized. Therefore, the sacrificial oxide film 84 becomes thin on the surface of the deep region 54 . Therefore, the sacrificial oxide film 84 is formed thicker in the exposed area of the oxidation accelerating region 52 of the inner surface of the trench 22 than in the area below it (that is, the exposed area of the deep region 54). Although not shown, within the element region 30, the exposed region of the source region 32 of the inner surface of the trench 22 is thicker than the region below it (the exposed region of the body region 34 and the drift region 36). An oxide film 84 is formed.

Next, as shown in FIG. 10, the sacrificial oxide film 84 is removed by etching the sacrificial oxide film 84 with hydrofluoric acid. Thereby, the width of the trench 22 is increased. Since the thick sacrificial oxide film 84 is removed in the depth range of the oxidation enhancing region 52, the amount of expansion of the width of the trench 22 is increased. Therefore, the width of the trench 22 is wider in the exposed range of the oxidation enhancing region 52 than in the range below it (that is, the exposed range of the deep region 54). That is, the trench 22 has a shape wider near the opening (upper end) than near the bottom. Although not shown, in the element region 30, the width of the trench 22 is wider in the exposed range of the source region 32 than in the range below it (the exposed range of the body region 34 and the drift region 36).

Next, as shown in FIG. 11, a gate insulating film 70 is formed by CVD (chemical vapor deposition). Here, a gate insulating film 70 is formed on the upper surface 12 a of the semiconductor substrate 12 and the inner surface of the trench 22 .

Next, as shown in FIG. 12, a polysilicon layer 86 is formed by depositing polysilicon in the trench 22 and on the semiconductor substrate 12 (that is, the surface of the gate insulating film 70) by CVD. At this time, since the width of the vicinity of the opening of the trench 22 is wide, the raw material gas for CVD easily reaches the corners 22a of the trench 22 (portion in the vicinity of the interface between the longitudinal side surface and the bottom surface of the trench 22). Therefore, polysilicon can be appropriately deposited on the corner portion 22a. Therefore, the polysilicon layer 86 is formed without gaps in the entire trench 22 including the corner portion 22a. Formation of voids in the vicinity of the corner portion 22a can be suppressed.

Next, as shown in FIG. 13, portions of the polysilicon layer 86 on the upper surface 12a of the semiconductor substrate 12 which are not used as the gate lead lines 76 are removed by etching. Polysilicon layer 86 remains in trench 22 . The polysilicon layer 86 remaining in the trench 22 becomes the gate electrode 72 . Here, the etching amount is adjusted so that the upper end of the gate electrode 72 is located above the lower ends of the source region 32 and the oxidation accelerating region 52 .

Next, as shown in FIG. 14, an interlayer insulating film 74 is formed to cover the upper surface of the wafer. Next, a contact hole 74a (see FIG. 2) is formed in the interlayer insulating film 74 in the element region 30. Next, as shown in FIG. Next, the source electrode 14 (see FIGS. 2 and 4) is formed in the element region 30. Next, as shown in FIG. Next, a drain electrode 16 (see FIGS. 2 to 4) is formed on the lower surface 12b of the semiconductor substrate 12. Next, as shown in FIG. Through the above steps, the MOSFET 10 shown in FIGS. 1 to 4 is completed.

As described above, in this manufacturing method, the trenches 22 are formed so that the ends of the trenches 22 in the longitudinal direction are positioned within the oxidation acceleration regions 52 on the upper surface 12a. Then, a sacrificial oxide film 84 is formed on the inner surface of the trench 22, and the sacrificial oxide film 84 is removed. As a result, the width near the opening of the trench 22 (the depth range of the oxidation enhancing region 52) is reduced to the width near the bottom of the trench 22 (the depth range of the deep region 54) at the ends in the longitudinal direction of the trench 22. narrower than Therefore, the corner portions 22a of the trenches 22 can be filled with the gate electrode without gaps, and the formation of voids in the corner portions 22a can be suppressed.

In the above-described embodiment, the trenches 22 are formed after forming the oxidation enhancing regions 52 , but the oxidation enhancing regions 52 may be formed after forming the trenches 22 . In this case, after the trenches 22 are formed, n-type impurities are implanted around the longitudinal ends of the trenches 22 to form the oxidation enhancement regions 52 . can be located within

Moreover, although the method of manufacturing a MOSFET has been described in the above embodiments, the technique disclosed in this specification may be applied to other trench gate type switching elements such as IGBTs (insulated gate bipolar transistors).

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

12: Semiconductor substrate 14 : Source electrode 16 : Drain electrode 22 : Trench 22a : Corner portion 30 : Element region 32 : Source region 34 : Body region 36 : Drift region 38 : Drain region 50 : Termination region 52 : Oxidation acceleration region 54 : deep region 70 : gate insulating film 72 : gate electrode 74 : interlayer insulating film 76 : gate lead-out line 84 : sacrificial oxide film

Claims (1)

A method for manufacturing a trench gate type switching element, comprising:
an n-type region forming step of forming an n-type region exposed on the surface of the semiconductor substrate by implanting an n-type impurity into the semiconductor substrate;
a trench forming step of forming a trench in the surface of the semiconductor substrate;
a sacrificial oxide film forming step of forming a sacrificial oxide film covering the inner surface of the trench by oxidizing the inner surface of the trench after the n-type region forming step and the trench forming step;
a sacrificial oxide film removing step of expanding the width of the trench by removing the sacrificial oxide film after the sacrificial oxide film forming step;
a gate insulating film forming step of forming a gate insulating film covering the inner surface of the trench by CVD (chemical vapor deposition) after the sacrificial oxide film removing step;
a gate electrode forming step of filling the trench with a gate electrode after the gate insulating film forming step;
has
The n-type region forming step and the trench forming step are performed so that the ends of the trench in the longitudinal direction are located in the n-type region on the surface of the semiconductor substrate, and the trench is positioned in the n-type region in the thickness direction of the semiconductor substrate. Executed to penetrate the mold area,
In the step of forming a sacrificial oxide film, the sacrificial oxide film is formed to be thicker in an exposed area of the n-type region than in a lower area of the inner surface of the trench,
In the step of removing the sacrificial oxide film, the width of the trench becomes wider in the exposed range of the n-type region than in the range below it.
Production method.

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