JP7121539B2 - Display driver and semiconductor device - Google Patents

Description

The present invention relates to a display driver for driving a display device and a semiconductor device including the display driver.

A display driver for driving a display device such as a liquid crystal display panel generates a group of analog grayscale voltages corresponding to an input digital video signal and applies them to a plurality of data lines of the liquid crystal display panel. Further, as a display driver, a data driver having a decoder circuit that selects a reference voltage corresponding to a digital video signal from among a plurality of reference voltages having different potentials and obtains the selected reference voltage as the grayscale voltage is provided. It has been proposed (see Patent Document 1, for example).

The decoder circuit described in Patent Document 1 is provided with 62 Nch transistor switches as a selector for selecting one of 32 reference voltages based on a 5-bit digital video signal. .

By the way, generally, the voltage value of the reference voltage (gradation voltage) is higher than the voltage value of the digital video signal. Therefore, in order to reliably switch the Nch transistor switch to the ON or OFF state according to the digital video signal, the voltage value of the digital video signal must be set to the highest voltage among a plurality of reference voltages (gradation voltages). need to be level-shifted to a value.

Therefore, the decoder circuit described in Patent Document 1 is provided with a level shifter that performs such level shift on the digital video signal.

JP 2013-218021 A

By the way, in the decoder circuit described in Patent Document 1, a plurality of Nch transistor switches included in the selector are simultaneously turned on/off by a 1-bit signal in the digital video signal.

Therefore, as a level shifter, each bit signal in the digital video signal can be level-shifted as described above, and an output current of a current amount capable of reliably setting a plurality of Nch transistor switches to an ON state or an OFF state can be sent. something is required.

However, the number of transistor switches for each bit signal to be driven by the level shifter increases as the number of reference voltages (gradation voltages) increases, and the amount of output current required accordingly increases.

Therefore, since a large output current is required, there is a problem that both the scale of the device and the current consumption of the level shifter are increased.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a display driver and a semiconductor device capable of suppressing device scale and current consumption.

A display driver according to the present invention converts display data representing a luminance level by J bits (J is a positive integer) into a gradation voltage having a voltage value corresponding to the luminance level, and applies the grayscale voltage to a display device. a level shift unit including first to Jth level shifters for outputting first to Jth shift bit signals obtained by individually level-shifting the signal levels of the bit signals of the J-bit display data; a reference voltage generation unit that generates 2 ^J reference voltages having different voltage values; 1st to Jth decoders connected in cascade with each other and receiving from a corresponding one of the J level shifters, the 2 ^J references according to the first to Jth shift bit signals; a decoder section for selecting one reference voltage from the voltages and outputting it as the gradation voltage, wherein the first decoder responds to the shift bit signal received by the 2 ^J decoder; selects a reference voltage group that is a part of the reference voltages and outputs it as a selected voltage group, and each of the second to (J-1)th decoders receives the shift bit According to the signal, a part of the selected voltage group output from the preceding decoder is selected and output as a selected voltage group, and the J-th decoder responds to the shift bit signal received by itself. one selected voltage is selected from the selected voltage group output from the decoder in the preceding stage and output as the grayscale voltage, and each of the first to Jth level shifters is a bias responsible for the respective output current. a bias current generation unit including a transistor for generating a current; 1st to Jth bias setting circuits for supplying bias voltages to the gates of the transistors included in the bias current generation units of the respective level shifters, wherein the first to Jth bias setting circuits By individually setting the current values to flow through the first to Jth lines, the current values of the output currents of the first to Jth level shifters are adjusted, and among the first to Jth decoders, The output current of the level shifter that supplies the shift bit signal to the decoder arranged in the subsequent stage supplies the shift bit signal to the decoder arranged in the preceding stage among the first to J-th decoders. It is configured to be smaller than the output current of the level shifter that supplies the low signal.

Further, the semiconductor device according to the present invention converts display data representing a luminance level by J bits (J is a positive integer) into a gradation voltage having a voltage value corresponding to the luminance level and applies it to the display device. A semiconductor device including a display driver, comprising first to J-th level shifters for outputting first to J-th shift bit signals obtained by individually level-shifting signal levels of respective bit signals of the J-bit display data. and a reference voltage generator for generating 2 ^J reference voltages with different voltage values, each of which supplies a corresponding one of the first to J-th shift bit signals. , first to J-th decoders connected in cascade with each other and receiving from corresponding one of the first to J-th level shifters, according to the first to J-th shift bit signals. a decoder that selects one reference voltage from the 2 ^J reference voltages and outputs it as the gradation voltage, wherein the first decoder receives the shift bit signal; selects a reference voltage group, which is a part of the 2 ^J reference voltages, and outputs it as a selected voltage group, and each of the second to (J−1)th decoders itself selects and outputs a part of the selected voltage group output from the preceding decoder as a selected voltage group according to the shift bit signal received by the J-th decoder, and the J-th decoder receives the According to the shift bit signal, one selected voltage is selected from the selected voltage group output from the preceding decoder and output as the gradation voltage, and each of the first to J-th level shifters a bias current generator including a transistor for generating a bias current responsible for the output current of the level shifter, wherein the level shifter includes first to Jth lines individually connected to the first to Jth level shifters. 1st to Jth bias setting circuits for supplying bias voltages to the gates of the transistors included in the bias current generation units of the 1st to Jth level shifters, respectively, via the first to Jth level shifters; The bias setting circuit adjusts the current value of the output current of each of the first to Jth level shifters by individually setting the current value to be passed through the first to Jth lines . The output current of the level shifter that supplies the shift bit signal to the decoder arranged in the latter stage among the J decoders is the decoder arranged in the preceding stage among the first to J-th decoders. less than the output current of the level shifter that supplies the shift bit signal to the decoder.

In the present invention, one of the 2 ^J reference voltages is selected according to the first to J-th shift bit signals obtained by level-shifting the signal level of each bit signal representing the luminance level in J bits. is applied to the display device as a gradation voltage, and the level shifter for generating the first to J-th shift bit signals have the following configurations.

That is, the decoder section includes first to J-th decoders connected in cascade, each of which is supplied with a corresponding one of the first to J-th shift bit signals from the level shift section. , one of the 2 ^J reference voltages is selected according to the first to J-th shift bit signals and applied to the display device as a gradation voltage.

The level shifter includes first to Jth level shifters that generate first to Jth shift bit signals. At this time, the output current of the level shifter that supplies the shift bit signal to the decoder arranged in the latter stage among the first to Jth decoders is supplied to the decoder arranged in the preceding stage. It is configured to be smaller than the output current of the level shifter that supplies the shift bit signal.

As a result, it is possible to reduce the circuit scale and current consumption of the level shifter while suppressing the delay amount of each of the first to Jth shift bit signals within a specified range.

1 is a block diagram showing the configuration of a display device 10 including a display driver according to the invention; FIG. 2 is a block diagram showing the internal configuration of a data driver 13; FIG. 3 is a block diagram showing internal configurations of a level shift section 132 and a decoder section 133; FIG. 3 is a circuit diagram showing an internal configuration of a decoder 30; FIG. 3 is a circuit diagram showing an internal configuration of a bias setting section 40; FIG. 2 is a circuit diagram showing an internal configuration of a level shifter 41; FIG. 3 is a circuit diagram showing the internal configuration of bias current generators BGp and BGn included in the level shifter 41; FIG. 3 is a circuit diagram showing the internal configuration of bias current generators BGp and BGn included in the level shifter 45; FIG. 3 is a circuit diagram showing the internal configuration of bias current generators BGp and BGn included in the level shifter 48; FIG. 3 is a block diagram showing an example of internal configurations of a level shift section 132a and a decoder section 133; FIG. 4 is a block diagram showing the internal configuration of a bias setting unit 40a; FIG. 4 is a circuit diagram showing the internal configuration of each of bias setting circuits 401-408. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a display device 10 including a display driver according to the invention. As shown in FIG. 1, the display device 10 has a drive control section 11, a scanning driver 12, a data driver 13, and a display device 20 consisting of a liquid crystal or organic EL panel.

The display device 20 has m (m is a natural number of 2 or more) horizontal scanning lines S1 to Sm each extending in the horizontal direction of the two-dimensional screen, and n (n) each extending in the vertical direction of the two-dimensional screen. Data lines D1 to Dn are formed, where n is a natural number of 2 or more. Further, display cells serving as pixels are formed at each intersection of the horizontal scanning lines and the data lines.

Based on the input video signal VS, the drive control unit 11 supplies the data driver 13 with a video data signal VD including a column of display data PD representing the luminance level to be displayed in each display cell. Each display data PD includes 1st to 8th bit signals representing the luminance level by, for example, 8 bits.

Further, the drive control section 11 detects a horizontal synchronizing signal from the input video signal VS and supplies it to the scanning driver 12 .

The scanning driver 12 generates a horizontal scanning pulse in synchronization with the horizontal synchronization signal supplied from the drive control section 11, and sequentially and alternatively applies it to each of the scanning lines S1 to Sm of the display device 20. .

FIG. 2 is a block diagram showing the internal configuration of the data driver 13 as a display driver. The data driver 13 is formed by being divided into a single semiconductor chip or a plurality of semiconductor chips.

As shown in FIG. 2, the data driver 13 includes a data latch unit 131, a level shift unit 132, a decoder unit 133, a reference voltage generator 134 and an output amplifier unit 135. FIG.

The data latch section 131 sequentially captures each of the display data PD included in the video data signal VD supplied from the drive control section 11 . Here, each time display data PD for one horizontal scanning line (n pieces) is fetched, the data latch unit 131 converts the fetched n pieces of display data PD into display data Q1 to Qn to the level shift unit. 132.

The level shifter 132 shifts the signal level of each of the 8-bit bit signals included in the display data Q to the voltage value of the high voltage VH used to drive the display device 20 for each of the display data Q1 to Qn. level shift.

For example, the level shifter 132 shifts the signal level of each of the first to eighth bit signals included in the display data Q1, that is, the signal level corresponding to the voltage value of the power supply voltage for the logic circuit, to the voltage value of the high voltage VH. to obtain level-shifted display data P1. The level shifter 132 obtains the display data P2-Pn by subjecting the display data Q2-Qn to the same level shift processing as the display data Q1. The level shift section 132 then supplies the display data P1 to Pn to the decoder section 133 .

The reference voltage generation unit 134 divides the high voltage VH to generate reference voltages Y1 to Y256 for 256 gradations having different voltage values, and supplies the reference voltages Y1 to Y256 to the decoder unit 133 .

The decoder unit 133 selects, for each of the display data P1 to Pn, the reference voltage corresponding to the luminance represented by the 8-bit bit signal included in the display data P from among the reference voltages Y1 to Y256. Then, the decoder 133 supplies the n reference voltages obtained by selecting each of the display data P1 to Pn to the output amplifier section 135 as the gradation voltages V1 to Vn.

The output amplifier unit 135 applies n voltages obtained by individually amplifying the gradation voltages V1 to Vn with a gain of 1 to the data lines D1 to Dn of the display device 20 as the display driving voltages G1 to Gn. .

Detailed configurations and operations of the level shift section 132 and the decoder section 133 will be described below.

The level shift section 132 and the decoder section 133 are composed of n channels for generating the gradation voltage V(r) based on the display data Q(r) (r is an integer from 1 to n). At this time, since each channel has the same configuration, one channel will be extracted from n channels in the level shift section 132 and the decoder section 133, and its configuration and operation will be described below.

FIG. 3 is a block diagram showing the internal configuration of the level shift section 132 and the decoder section 133 for one channel corresponding to the display data Q1 and the gradation voltage V1.

As shown in FIG. 3, the level shift section 132 has a bias setting section 40 and level shifters (LS) 41-48.

A bias setting unit 40 generates a p-channel side bias voltage Bp and an n-channel side bias voltage Bn for setting a bias current to flow in each of the level shifters 41 to 48, and supplies the bias voltage Bp and the n-channel side bias voltage Bn via lines Lp and Ln, respectively. are supplied to each of the level shifters 41-48.

The level shifters 41 to 48 individually level-shift the signal levels of the 8-bit bit signals d8 to d1 each having a voltage value for a logic circuit, which are included in the display data Q1, to the voltage value of the high voltage HV. Generate e8 to e1. It is assumed that the bit signal d8 among the bit signals d8 to d1 corresponds to the most significant bit and the bit signal d1 corresponds to the least significant bit for expressing luminance of 256 gradations.

Further, the level shifters 41 to 48 generate inverted shift bit signals i8 to i1 by inverting the phases of these shift bit signals e8 to e1, respectively.

That is, the level shifter 41 receives the bit signal d8 and generates a shift bit signal e8 by level-shifting the signal level and an inverted shift bit signal i8 by inverting the phase of the shift bit signal e8. The level shifter 42 receives the bit signal d7 and generates a shift bit signal e7 by level-shifting the signal level and an inverted shift bit signal i7 by inverting the phase of the shift bit signal e7. The level shifter 43 receives the bit signal d6 and generates a shift bit signal e6 by level-shifting the signal level and an inverted shift bit signal i6 by inverting the phase of the shift bit signal e6. The level shifter 44 receives the bit signal d5 and generates a shift bit signal e5 by level-shifting the signal level and an inverted shift bit signal i6 by inverting the phase of the shift bit signal e5.

The level shifter 45 receives the bit signal d4 and generates a shift bit signal e4 by level-shifting the signal level and an inverted shift bit signal i4 by inverting the phase of the shift bit signal e4. The level shifter 46 receives the bit signal d3 and generates a shift bit signal e3 by level-shifting the signal level and an inverted shift bit signal i3 by inverting the phase of the shift bit signal e3. The level shifter 47 receives the bit signal d2 and generates a shift bit signal e2 by level-shifting the signal level and an inverted shift bit signal i2 by inverting the phase of the shift bit signal e2. The level shifter 48 receives the bit signal d1 and generates a shift bit signal e1 obtained by level-shifting the signal level and an inverted shift bit signal i1 obtained by inverting the phase of the shift bit signal e1.

The level shifters 41 to 48 supply the display data P1 including the shift bit signals e8 to e1 and the inverted shift bit signals i8 to i1 to the decoder section 133. FIG.

The decoder unit 133 includes decoders (DEC) 30-39.

The decoder 30 divides the reference voltages Y256 to Y1 for 256 gradations into four, the reference voltages Y1 to Y64, the reference voltages Y65 to Y128, the reference voltages Y129 to Y192, and the reference voltage Y193 to Y256. ˜Y64 and Y129-Y192. The decoder 30 selects one of the reference voltages Y1 to Y64 and the reference voltages Y129 to Y192 based on the shift bit signal e8 and the inverted shift bit signal i8 generated by the level shifter 41, and selects the selected voltage group. are output as the selection voltages U1 to U64.

The decoder 31 receives Y65 to Y128 and Y193 to Y256 of the reference voltages Y1 to Y64, Y65 to Y128, Y129 to Y192 and Y193 to Y256. The decoder 31 selects one of the reference voltages Y65 to Y128 and the reference voltages Y193 to Y256 based on the shift bit signal e8 and the inverted shift bit signal i8, and converts the selected voltage group to the selection voltage W1. ~W64 is output.

The decoder 32 receives lower selection voltages U1 to U32 among the above selection voltages U1 to U64 and higher selection voltages W33 to W64 among the above selection voltages W1 to W64. The decoder 32 selects one of the selected voltages U1 to U32 and the selected voltages W33 to W64 based on the shift bit signal e7 and the inverted shift bit signal i7 generated by the level shifter 42, and selects the selected voltage group. are output as selection voltages T1 to T32.

The decoder 33 receives upper selection voltages U33 to U64 among the above selection voltages U1 to U64 and lower selection voltages W1 to W32 among the above selection voltages W1 to W64. The decoder 33 selects one voltage group from the selection voltages U33 to U64 and the selection voltages W1 to W32 based on the shift bit signal e7 and the inverted shift bit signal i7, and converts the selected voltage group into the selection voltages R1 to R1. Output as R32.

The decoder 34 receives the selection voltages T1-T32 and the selection voltages R1-R32. The decoder 34 selects one of the selected voltages T1 to T32 and the selected voltages R1 to R32 based on the shift bit signal e6 and the inverted shift bit signal i6 generated by the level shifter 43, and selects the selected voltage group. are supplied to the decoder 35 as selection voltages M1 to M32.

Based on the shift bit signal e5 and the inverted shift bit signal i5 generated by the level shifter 44, the decoder 35 selects the lower selected voltages M1 to M16 and the higher selected voltages M17 to M32 from among the selected voltages M1 to M32. select one of the voltage groups. The decoder 35 then supplies the selected voltage group to the decoder 36 as selected voltages K1 to K16.

Based on the shift bit signal e4 and the inverted shift bit signal i4 generated by the level shifter 45, the decoder 36 selects between the lower selected voltages K1 to K8 and the higher selected voltages K9 to K16 among the above selected voltages K1 to K16. select one of the voltage groups. The decoder 36 then supplies the selected voltage group to the decoder 37 as selected voltages E1 to E8.

Based on the shift bit signal e3 and the inverted shift bit signal i3 generated by the level shifter 46, the decoder 37 selects between the lower selection voltages E1 to E4 and the higher selection voltages E5 to E8 among the above selection voltages E1 to E8. select one of the voltage groups. The decoder 37 then supplies the selected voltage group to the decoder 38 as selected voltages F1 to F4.

Based on the shift bit signal e2 and the inverted shift bit signal i2 generated by the level shifter 47, the decoder 38 selects between the lower selected voltages F1 and F2 and the higher selected voltages F3 and F4 among the above-described selection voltages F1 to F4. select one of the voltage groups. The decoder 38 then supplies the selected voltage group to the decoder 39 as selected voltages C1 and C2.

The decoder 39 selects one of the selection voltages C1 and C2 based on the shift bit signal e1 and the inverted shift bit signal i1 generated by the level shifter 48, and outputs it as the gradation voltage V1.

In this way, the decoder section 133 includes eight decoders, that is, decoders (30, 31) each receiving a corresponding one of shift bit signals e1 to e8 (or inverted shift bit signals i1 to i8). ), decoders (32, 33), and decoders 34 to 39 are connected in series. Each decoder receives one corresponding shift bit signal and receives a voltage group input consisting of 128, 64, 32, 16, 8, 4 or 2 voltages, It selects and outputs half of the input voltage group according to one shift bit signal it receives.

Next, circuit configurations of the decoders 30 to 39, the bias setting section 40, and the level shifters 41 to 48 will be described.

Each of the decoders 30 to 39 is a selector that selects and outputs half of the voltages received by each decoder. circuit configuration is the same.

Therefore, the decoder 30 is extracted from among the decoders 30 to 39, and its internal circuit configuration will be described.

FIG. 4 is a circuit diagram showing an example of the internal configuration of the decoder 30. As shown in FIG.

As shown in FIG. 4, the decoder 30 includes n-channel MOS (Metal-Oxide-Semiconductor) type transistors QA1 to QA64 and QB1 to QB64.

Transistors QA1-QA64 individually receive reference voltages Y1-Y64 at their respective sources. The drains of transistors QA1-QA64 are connected to lines L1-L64, and the inverted shift bit signal i8 is supplied to the gates of each of transistors QA1-QA64.

Transistors QA1-QA64 are off when the inverted shift bit signal i8 has a ground potential corresponding to logic level 0, and on when the inverted shift bit signal i8 has a high voltage HV corresponding to logic level 1. state. Transistors QA1-QA64 output reference voltages Y1-Y64 as selection voltages U1-U64 via lines L1-L64 when set to the ON state.

Transistors QB1-QB64 individually receive reference voltages Y129-Y192 at their respective sources. The drains of the transistors QB1-QB64 are connected to the lines L1-L64, and the gates of the transistors QB1-QB64 are supplied with the shift bit signal e8.

The transistors QB1 to QB64 are turned off when the shift bit signal e8 has a ground potential corresponding to logic level 0, and turned on when the shift bit signal e8 has a high voltage HV corresponding to logic level 1. set. Transistors QB1-QB64 output reference voltages Y129-Y192 as selection voltages U1-U64 via lines L1-L64 when set to the ON state.

As shown in FIG. 4, the decoder 30 is ON/OFF-controlled by an inverted shift bit signal i8 in order to select one of the reference voltage group (Y1 to Y64) and the reference voltage group (Y129 to Y192). and 64 transistors QB1 to QB64 that are on/off controlled by a shift bit signal e8.

Similarly to the decoder 31, the decoder 31 has 64 transistors QA1-QA64 ON/OFF controlled by the inverted shift bit signal i8 and 64 transistors QB1-QB64 ON/OFF controlled by the shift bit signal e8.

That is, in the decoders 30 and 31, a total of 128 transistors are on/off controlled by the inverted shift bit signal i8, and a total of 128 transistors are on/off controlled by the shift bit signal e8.

Decoders 32 and 33 at the next stage of decoders 30 and 31 receive 64 selection voltages U1 to U64 and 64 selection voltages W1 to W64 output from decoders 30 and 31, respectively. Therefore, in the decoders 32 and 33, the number of transistors to be turned on/off controlled by the inverted shift bit signal i7 is 64 in total, and the number of transistors to be turned on/off by the shift bit signal e7 is also 64 in total.

A decoder 34 in the next stage of these decoders 32 and 33 receives 32 selection voltages T1-T32 and 32 selection voltages R1-R32 output from the decoders 32 and 33. FIG. Therefore, in the decoder 34, the number of transistors ON/OFF controlled by the inverted shift bit signal i6 and the number of transistors ON/OFF controlled by the shift bit signal e6 are 32 each.

Similarly, in the decoder 35, the number of transistors ON/OFF controlled by the inverted shift bit signal i5 and the number of transistors ON/OFF controlled by the shift bit signal e5 are 16 each. In the decoder 36, the number of transistors ON/OFF controlled by the inverted shift bit signal i4 and the number of transistors ON/OFF controlled by the shift bit signal e4 are eight. In the decoder 37, the number of transistors ON/OFF controlled by the inverted shift bit signal i3 and the number of transistors ON/OFF controlled by the shift bit signal e3 are four. In the decoder 38, the number of transistors ON/OFF controlled by the inverted shift bit signal i2 and the number of transistors ON/OFF controlled by the shift bit signal e2 are two. In the decoder 39, the number of transistors ON/OFF controlled by the inverted shift bit signal i1 and the number of transistors ON/OFF controlled by the shift bit signal e1 are both one.

FIG. 5 is a circuit diagram showing an example of the internal configuration of the bias setting section 40. As shown in FIG. In the example shown in FIG. 5, the bias setting section 40 includes a bias setting circuit BSp, a bias setting circuit BSn, and a constant current generation circuit CG.

The bias setting circuit BSp has a configuration in which eight p-channel MOS transistors TP having their gates and drains connected to each other are connected in parallel. As shown in FIG. 5, a high voltage HV is applied to the sources of the eight transistors TP, and the drains of the transistors TP are connected to the constant current generation circuit CG via the node LLp.

The bias setting circuit BSn has a configuration in which eight n-channel MOS transistors TN having their gates and drains connected to each other are connected in parallel. As shown in FIG. 5, a ground potential is applied to the sources of the eight transistors TN, and the drains of the transistors TN are connected to the constant current generating circuit CG via the node LLn.

The constant current generation circuit CG generates a predetermined constant current, and passes it through the bias setting circuit BSp, nodes LLp and LLn to the bias setting circuit BSn. As a result, the voltage generated at the gate of the transistor TP included in the bias setting circuit BSp is supplied to the level shifters 41 to 48 as the p-channel side bias voltage Bp. Furthermore, the voltage generated at the gate of the transistor TN included in the bias setting circuit BSn is supplied to the level shifters 41 to 48 as the bias voltage Bn on the n-channel side.

The level shifters 41-48 have the same basic internal configuration. Therefore, the level shifter 41 will be extracted and the internal configuration of the level shifter will be described below.

FIG. 6 is a circuit diagram showing the internal configuration of the level shifter 41. As shown in FIG.

As shown in FIG. 6, the level shifter 41 includes a differential input section DIP and an output section OPT.

The differential input part DIP includes an inverter IV1, p-channel MOD transistors MP1 and MP2, and n-channel MOS transistors MN1 and MN2.

A high voltage HV is applied to the sources of the transistors MP1 and MP2. The drain of transistor MP1 and the gate of transistor MP2 are connected to the drain of transistor MN1 through node LL1. The drain of transistor MP2 and the gate of transistor MP1 are connected to the drain of transistor MN2 through node LL2.

A ground potential is applied to the sources of the transistors MN1 and MN2. A bit signal d8 is supplied to the gate of the transistor MN1. The inverter IV1 supplies an inverted bit signal obtained by inverting the phase of the bit signal d8 to the gate of the transistor MN2.

The output unit OPT includes bias current generators BGp and BGn, p-channel MOS transistors MP3 and MP4, and n-channel MOS transistors MN3 and MN4.

Based on the high voltage HV, the bias current generation unit BGp generates a bias current IBa with a constant current amount corresponding to the bias voltage Bp supplied from the bias setting unit 40, and supplies it to the sources of the transistors MP3 and MP4 via the node LLa. supply to

The gate of the transistor MP3 is connected to the node LL1 of the differential input section DIP, and its drain is connected to the node LL3. The gate of the transistor MP4 is connected to the node LL2 of the differential input section DIP, and its drain is connected to the node LL4.

With the above configuration, the transistor MP3 outputs the first current of the first and second currents obtained by dividing the bias current IBa by the ratio of the magnitudes of the voltages of the nodes LL1 and LL2. Send to LL3. Transistor MP4 delivers the aforementioned second current to node LL4.

The gate of the transistor MN3 is connected to the node LL1 of the differential input section DIP, and the gate of the transistor MN4 is connected to the node LL2 of the differential input section DIP. The sources of the transistors MN3 and MN4 are connected to the bias current generator BGn through the node LLb.

The bias current generation unit BGn is connected to the ground potential, and supplies a constant bias current IBb corresponding to the bias voltage Bn supplied from the bias setting unit 40 from the sources of the transistors MN3 and MN4 via the node LLb. Pull out.

With the above configuration, the transistor MN3 outputs the third current out of the third and fourth currents obtained by dividing the bias current IBa by the ratio of the magnitudes of the voltages of the nodes LL1 and LL2. Pull out from LL3. Transistor MN4 draws this fourth current from node LL4.

The output part OPT outputs a signal having the voltage generated at the node LL3 due to the current flowing through the node LL3 as the shift bit signal e8, and also outputs a signal having the voltage generated at the node LL4 due to the current flowing through the node LL4. is output as the inverted shift bit signal i8.

That is, for example, the output part OPT of the level shifter 41 supplies an output current of a constant amount corresponding to the bias currents IBa and IBb to the gates of the 128 transistors QB included in the decoders 30 and 31 as loads through the node LL3. supply. As a result, the signal having the voltage generated at the node LL3 and the gates of the 128 transistors QB becomes the shift bit signal e8, and the 128 transistors QB are simultaneously turned on/off according to the voltage of the shift bit signal e8.

Further, the output part OPT of the level shifter 41 supplies the output current of the current amount corresponding to the bias currents IBa and IBb to the gates of the 128 transistors QA included in the decoders 30 and 31 as loads through the node LL4. . As a result, the signal having the voltage generated at the node LL4 and the gates of the 128 transistors QA becomes the inverted shift bit signal i8, and the 128 transistors QA are simultaneously on-off controlled according to the voltage of the inverted shift bit signal i8. be.

Here, not only the level shifter 41 but also each of the level shifters 42 to 48 has the same circuit configuration as the differential input section DIP and the output section OPT shown in FIG.

The bias current generators BGp and BGn included in each of the level shifters 42 to 48 individually set the amount of bias current according to the load amount of the decoder connected to the level shifters.

7 is a circuit diagram showing an example of the internal configuration of the bias current generators BGp and BGn of the level shifter 41, and FIG. 8 is a circuit diagram showing an example of the internal configuration of the bias current generators BGp and BGn of the level shifter 45. As shown in FIG. be. 9 is a circuit diagram showing an example of the internal configuration of the bias current generators BGp and BGn of the level shifter 48. As shown in FIG.

As shown in FIG. 7, the bias current generator BGp of the level shifter 41 has a structure in which eight p-channel MOS transistors TP having their gates and drains connected to each other are connected in parallel. As shown in FIG. 7, a high voltage HV is applied to the sources of the eight transistors TP, and the drains of the transistors TP are connected to the node LLa. A bias voltage Bp generated by the bias setting circuit BSp of the bias setting unit 40 shown in FIG. 5 is applied to the gate of each of the eight transistors TP.

The bias current generator BGn of the level shifter 41 has a configuration in which eight n-channel MOS transistors TN having their gates and drains connected to each other are connected in parallel. As shown in FIG. 7, the ground potential is applied to the sources of the eight transistors TN, and the drains of the transistors TN are connected to the node LLb. A bias voltage Bn generated by the bias setting circuit BSn of the bias setting unit 40 shown in FIG. 5 is applied to the gate of each of the eight transistors TN.

That is, in the level shifter 41, the bias setting circuit BSp shown in FIG. 5 and the bias current generator BGp shown in FIG. 7 constitute a current mirror circuit with a current mirror ratio of 1:1. Here, if Isd is the source-drain current of the transistor TP, the bias current generator BGp generates a current (8·Isd) that is the sum of the currents Isd flowing through the eight transistors TP included in the bias setting circuit BSp. is generated as the bias current IBa.

Further, in the level shifter 41, the bias setting circuit BSn shown in FIG. 5 and the bias current generator BGn shown in FIG. 7 form a current mirror circuit with a current mirror ratio of 1:1. Here, if Isd is the source-drain current of the transistor TN, the bias current generator BGn generates a current (8·Isd) that is the sum of the currents Isd flowing through the eight transistors TN included in the bias setting circuit BSn. is generated as the bias current IBb.

As a result, the voltages generated by the currents obtained by dividing the current (8·Isd) by two flowing through the nodes LL3 and LL4 are supplied to the decoders 30 and 31 as the shift bit signal e8 and the inverted shift bit signal i8.

Therefore, the level shifter 41 controls on/off of the 128 transistors QA included in the decoders 30 and 31 by the shift bit signal e8 based on the current (8·Isd). Further, the level shifter 41 controls on/off of the 128 transistors QB included in the decoders 30 and 31 by an inverted shift bit signal i8 based on the current (8·Isd).

The number of transistors ON/OFF-controlled by each of the shift bit signal e7 and the inverted shift bit signal i7 output from the level shifter 42 is 64, which is less than 128, as described above. That is, the amount of load to be on/off controlled by the shift bit signal e7 and the inverted shift bit signal i7 is smaller than that of the shift bit signal e8 and the inverted shift bit signal i8.

Therefore, in the level shifter 42, even if the current amounts of the bias currents IBa and IBb are reduced, the delay amounts of the shift bit signal e7 and the inverted shift bit signal i7 can be made equal to those of the shift bit signal e8 and the inverted shift bit signal i8. can.

Therefore, in the bias current generator BGp of the level shifter 42, the eight transistors TP connected in parallel in the bias current generator BGp shown in FIG. 7 are reduced to, for example, seven. Similarly, in the bias current generator BGn of the level shifter 42, the eight transistors TN connected in parallel in the bias current generator BGn shown in FIG. 7 are reduced to, for example, seven.

Similarly, in each of the level shifters 43 to 48 as well, the smaller the load amount to be on/off controlled, the more transistors (TP, TN) connected in parallel in the bias current generators (BGp, BGn). reduce the number.

For example, the number of transistors ON/OFF-controlled by each of the shift bit signal e4 and the inverted shift bit signal i4 output from the level shifter 45 is eight as described above. That is, the amount of load to be on/off controlled by the shift bit signal e4 and the inverted shift bit signal i4 is smaller than the shift bit signals e8 to e5 and the inverted shift bit signals i8 to e5.

Therefore, in the level shifter 45, even if the amounts of the bias currents IBa and IBb are reduced, the delay amounts of the shift bit signal e4 and the inverted shift bit signal i4 are equal to those of the shift bit signals e8 to e5 and the inverted shift bit signals i8 to e5. can be

Therefore, in the bias current generator BGp of the level shifter 45, as shown in FIG. 8, four transistors TP are connected in parallel. Similarly, in the bias current generator BGn of the level shifter 45, as shown in FIG. 8, four transistors TN are connected in parallel.

That is, in the level shifter 45, the bias setting circuit BSp shown in FIG. 5 and the bias current generator BGp shown in FIG. 8 form a current mirror circuit with a current mirror ratio of 2:1. Further, in the level shifter 45, the bias setting circuit BSn shown in FIG. 5 and the bias current generator BGn shown in FIG. 8 constitute a current mirror circuit with a current mirror ratio of 2:1.

Further, for example, the number of transistors ON/OFF-controlled by each of the shift bit signal e1 and the inverted shift bit signal i1 output from the level shifter 48 is one as described above. That is, the amount of load to be on/off controlled by the shift bit signal e1 and the inverted shift bit signal i1 is smaller than the shift bit signals e8 to e2 and the inverted shift bit signals i8 to e2.

Therefore, in the level shifter 48, even if the current amounts of the bias currents IBa and IBb are reduced, the delay amounts of the shift bit signal e1 and the inverted shift bit signal i1 are equal to those of the shift bit signals e8 to e2 and the inverted shift bit signals i8 to e2. can be

Therefore, in the bias current generator BGp of the level shifter 48, as shown in FIG. 9, two transistors TP are connected in parallel. Similarly, in the bias current generator BGn of the level shifter 48, as shown in FIG. 9, two transistors TN are connected in parallel.

That is, in the level shifter 48, the bias setting circuit BSp shown in FIG. 5 and the bias current generator BGp shown in FIG. 9 form a current mirror circuit with a current mirror ratio of 4:1. Further, in the level shifter 48, the bias setting circuit BSn shown in FIG. 5 and the bias current generator BGn shown in FIG. 9 form a current mirror circuit with a current mirror ratio of 4:1.

As described above, the level shifters 41 to 48 employ a configuration in which the current amount of each output current is individually set in correspondence with the load amount of the decoders connected thereto. That is, decoders (30, 31), (32, 33), 34 to 39, 35, 36, and 37 connected in cascade as shown in FIG. The amount of load on the arranged decoder is small.

Therefore, in the level shifters 41 to 48, the output current of the level shifter that supplies the shift bit signal (inverted shift bit signal) to the decoder arranged in the latter stage among these cascaded decoders is arranged in the preceding stage. It is configured to be smaller than the output current of the level shifter that supplies the shift bit signal to the decoder.

As a result, the circuit scale and current consumption can be reduced as compared with the case where the circuit configuration shown in FIG. becomes.

In the above embodiment, the number of parallel-connected transistors included in the bias current generation units (BGp, BGn) of each of the level shifters 41 to 48 determines the amount of output current of each level shifter. The amount of current is adjusted to correspond to the amount of load.

However, such adjustment of the output current may also be performed on the bias setting section 40 side.

FIG. 10 is a block diagram showing part of the configuration of the level shift section 132a and the decoder section 133, which has been made in view of this point. As in FIG. 3, FIG. 10 also shows only the configuration of the level shift section 132a and the decoder section 133 for one channel corresponding to the display data Q1 and the gradation voltage V1.

10 employs a level shifter 132a instead of the level shifter 132 shown in FIG. 3, and the decoder 133 is the same as that shown in FIG.

The level shifter 132a adopts the bias setter 40a instead of the bias setter 40, and the configuration of the level shifters 41 to 48 is the same as that shown in FIG.

FIG. 11 is a block diagram showing the internal configuration of the bias setting section 40a.

The bias setting section 40a has bias setting circuits 401-408 provided corresponding to the level shifters 41-48, respectively. The bias setting circuit 401 supplies the generated bias voltages Bp and Bn to the level shifter 41 through lines Lp8 and Ln8, respectively. The bias setting circuit 402 supplies the generated bias voltages Bp and Bn to the level shifter 42 via lines Lp7 and Ln7, respectively. The bias setting circuit 403 supplies the generated bias voltages Bp and Bn to the level shifter 43 through lines Lp6 and Ln6, respectively. The bias setting circuit 404 supplies the generated bias voltages Bp and Bn to the level shifter 44 through lines Lp5 and Ln5, respectively. The bias setting circuit 405 supplies the generated bias voltages Bp and Bn to the level shifter 45 via lines Lp4 and Ln4, respectively. The bias setting circuit 406 supplies the generated bias voltages Bp and Bn to the level shifter 46 via lines Lp3 and Ln3, respectively. The bias setting circuit 407 supplies the generated bias voltages Bp and Bn to the level shifter 47 via lines Lp2 and Ln2, respectively. The bias setting circuit 408 supplies the generated bias voltages Bp and Bn to the level shifter 48 via lines Lp1 and Ln1, respectively.

The bias setting circuits 401-408 have a common internal configuration.

FIG. 12 is a circuit diagram showing an example of the internal configuration of each of the bias setting circuits 401-408.

As shown in FIG. 12, each of the bias setting circuits 401 to 408 employs a bias setting circuit BSXp instead of the bias setting circuit BSp shown in FIG. 5, and employs a bias setting circuit BSXn instead of the bias setting circuit BSn. It is. Incidentally, the constant current generation circuit CG is the same as that shown in FIG.

The bias setting circuit BSXp has a configuration in which k p-channel MOS transistors TP1 to TP(k) (where k is an integer equal to or greater than 2) are connected in parallel. That is, the sources of the transistors TP1 to TP(k) are connected to each other, and a high voltage HV is applied to each source. Also, the drains of the transistors TP1 to TP(k) are connected to each other, and each drain is connected to the constant current generating circuit CG through the node LLp.

In the bias setting circuit BSXp, switch elements Sa1 to Sa ( k) is provided. Further, the bias setting circuit BSXp is provided with switch elements Sb1 to Sb(k) that connect the gates of the transistors TP1 to TP(k) to the node LLp in the ON state and cut off the connection in the OFF state. there is

The bias setting circuit BSXn has a configuration in which k n-channel MOS transistors TN1 to TN(k) are connected in parallel. That is, the sources of the transistors TN1 to TN(k) are connected to each other, and the ground potential is applied to each source. Also, the drains of the transistors TN1 to TN(k) are connected to each other, and each drain is connected to the constant current generation circuit CG through the node LLn.

In the bias setting circuit BSXn, switch elements Sc1 to Sc(k) apply a ground potential to the gates of the transistors TN1 to TN(k) in the ON state and cut off the application of the ground potential in the OFF state. is provided. Further, the bias setting circuit BSXn is provided with switching elements Sd1 to Sd(k) that connect the gates of the transistors TN1 to TN(k) to the node LLn in the ON state and cut off the connection in the OFF state. there is

The bias setting circuit 401 having the configuration shown in FIG. 12 supplies the bias voltage Bp generated at the node LLp to the level shifter 41 through the line Lp8, and the bias voltage Bn generated at the node LLn to the level shifter 41 through the line Ln8. supply to Similarly, the bias setting circuits 402 to 408 apply the bias voltages Bp and Bn generated by the respective level shifters 42 to 48 via lines (Lp7 to Lp1, Ln7 to Ln1) provided exclusively for the level shifters 42 to 48. .about.48, respectively.

Here, in each of the bias setting circuits 401 to 408, a plurality of switch elements included in the bias setting circuits BSXp and BSXn are individually set to the ON state or the OFF state.

That is, the bias setting circuit BSXp sets all of the switching elements Sa1 to Sa(k) to the OFF state. Among the switch elements Sb1 to Sb(k) included in the bias setting circuit BSXp, the number of switches to be set to the ON state is one of the current mirror circuits composed of the bias setting circuit BSXp and the bias current generator BGp. Adjust the amount of current flowing on the next side. At this time, the more switches among the switch elements Sb1 to Sb(k) that are set to the ON state, the more the amount of current flowing through the primary side of the current mirror circuit, that is, the bias setting circuit BSXp. The current amount of the bias current IBa generated by the current generator BGp also increases. In short, the current amount of the bias current IBa can be set according to the number of switches to be turned on among the switch elements Sb1 to Sb(k).

Similarly, the bias setting circuit BSXn sets all of the switch elements Sc1 to Sc(k) to the OFF state. Among the switch elements Sd1 to Sd(k) included in the bias setting circuit BSXn, the number of switches to be set to the ON state is one of the current mirror circuits composed of the bias setting circuit BSXn and the bias current generator BGn. Set the amount of current to flow on the next side. At this time, the more switches among the switch elements Sd1 to Sd(k) that are set to the ON state, the more the amount of current flowing through the primary side of the current mirror circuit, that is, the bias setting circuit BSXn. The current amount of the bias current IBb generated by the current generator BGn also increases. In short, the current amount of the bias current IBb can be set by the number of switches to be turned on among the switch elements Sd1 to Sd(k). This makes it possible to individually and accurately adjust the amount of output current of each of the level shifters 42 to 48 and the amount of delay of each of the shift bit signals e1 to e8 (inverted shift bit signals i1 to i8). Through such adjustment, through current, current consumption, and EMI (electro-magnetic interference) can be reduced.

In the bias current generators (BGp, BGn) described above, as shown in FIGS. Sets the amount of output current. However, the amount of output current of each level shifter may be set by changing the size (channel length, channel width) of the transistor that generates the bias current for each level shifter.

In the above-described embodiment, the number of cascade-connected decoders and the number of level shifters are set to eight as an example of the case where the luminance level is represented by 256 8-bit gradations, but the present invention is not limited to such a configuration. Further, in the above embodiment, each of the decoders 30 to 39 selects and outputs a half voltage from a plurality of voltages (reference voltages or selection voltages) according to the shift bit signal it receives. However, the number of voltages selected may be more or less than half. In other words, each decoder (30 to 39) may select and output a part of the voltages it receives according to the shift bit signal it receives.

In short, the display device (20) converts the display data (for example, Q1) representing the luminance level by J bits (J is a positive integer) into a gradation voltage (for example, V1) having a voltage value corresponding to the luminance level. As the display driver (13) to be applied to the display driver (13), one including the following reference voltage generation section, level shift section and decoder section may be employed.

That is, the reference voltage generator (134) generates 2 ^J reference voltages (for example, Y1 to Y256) having different voltage values. A level shifter (132) outputs first to J-th shift bit signals (e1 to e8, for example) obtained by individually level-shifting the signal levels of bit signals (eg, bit signals d1 to d8) of J-bit display data. It includes first to Jth level shifters (eg, level shifters 41 to 48) that output.

Each of the decoder units (133) receives a supply of a corresponding one of the first to Jth shift bit signals from a corresponding one of the first to Jth level shifters. , includes first to Jth decoders (eg, decoders 30 to 39) cascaded together. The decoder section selects one reference voltage from 2 ^J reference voltages according to the first to J-th shift bit signals and outputs it as a gradation voltage (eg, V1).

Note that the first decoder (for example, decoders 30 and 31) selects a reference voltage group, which is a part of the 2 ^J reference voltages, according to the shift bit signal (for example, e8) received by itself, and are output as the selected voltage group. Each of the second to (J−1)th decoders (eg, decoders 32 to 38) receives a select voltage group output from the preceding decoder in accordance with a shift bit signal (eg, e7 to e2) received by itself. A part of them is selected as a selection voltage group and output. The J-th decoder (for example, decoder 39) selects one selection voltage from the selection voltage group output from the preceding decoder according to the shift bit signal received by itself, and converts it to a gradation voltage (for example, V1).

The first to Jth level shifters supply the shift bit signal to the decoder arranged in the latter stage among the first to Jth decoders. is configured to be smaller than the output current of the level shifter that supplies .

30 to 39 decoders 40 and 40a bias setting units 41 to 48 level shifter 132 level shift unit 133 decoder units BGp and BGn bias current generation units TP and TN transistors

Claims (4)

A display driver that converts display data representing a luminance level by J bits (J is a positive integer) into a grayscale voltage having a voltage value corresponding to the luminance level and applies the grayscale voltage to a display device,
a level shift unit including first to Jth level shifters for outputting first to Jth shift bit signals obtained by individually level-shifting the signal levels of the bit signals of the J-bit display data;
a reference voltage generator that generates 2 ^J reference voltages with different voltage values;
each receiving a corresponding one of the first to Jth shift bit signals supplied from a corresponding one of the first to Jth level shifters, connected in cascade to each other; 1st to Jth decoders that select one reference voltage from the 2 ^J reference voltages according to the 1st to Jth shift bit signals and use it as the gradation voltage. and a decoder unit that outputs
the first decoder selects a reference voltage group, which is a part of the 2 ^J reference voltages, according to the shift bit signal received by itself, and outputs it as a selected voltage group;
Each of the second to (J-1)th decoders selects a part of the selected voltage group output from the preceding decoder as a selected voltage group in accordance with the shift bit signal received by itself. and output
the J-th decoder selects one selected voltage from a group of selected voltages output from the preceding decoder according to the shift bit signal received by itself and outputs it as the gradation voltage;
each of the first to J-th level shifters has a bias current generation unit including a transistor that generates a bias current responsible for the respective output current;
The level shifter is included in the bias current generator of each of the first to Jth level shifters via first to Jth lines individually connected to the first to Jth level shifters. including first to J-th bias setting circuits that supply bias voltages to the gates of the transistors;
The first to Jth bias setting circuits adjust the current values of the output currents of the first to Jth level shifters by individually setting current values to be supplied to the first to Jth lines. death,
An output current of the level shifter that supplies the shift bit signal to a decoder arranged at a later stage among the first to Jth decoders is arranged at an earlier stage among the first to Jth decoders. A display driver characterized in that it is configured to be smaller than the output current of the level shifter that supplies the shift bit signal to a decoder. 2. The method according to claim 1, wherein the current value of the output current is set according to the number of parallel-connected transistors included in the bias current generator for each of the first to J-th level shifters. Display driver. 2. The display driver according to claim 1, wherein the current value of the output current is set according to the size of the transistor included in the bias current generator for each of the first to Jth level shifters. A semiconductor device including a display driver that converts display data representing a luminance level by J bits (J is a positive integer) into a grayscale voltage having a voltage value corresponding to the luminance level and applies the grayscale voltage to a display device,
a level shift unit including first to Jth level shifters for outputting first to Jth shift bit signals obtained by individually level-shifting the signal levels of the bit signals of the J-bit display data;
a reference voltage generator that generates 2 ^J reference voltages with different voltage values ;
each receiving a corresponding one of the first to Jth shift bit signals supplied from a corresponding one of the first to Jth level shifters, connected in cascade to each other; 1st to Jth decoders that select one reference voltage from the 2 ^J reference voltages according to the 1st to Jth shift bit signals and use it as the gradation voltage. and a decoder unit that outputs
the first decoder selects a reference voltage group, which is a part of the 2 ^J reference voltages, according to the shift bit signal received by itself, and outputs it as a selected voltage group;
Each of the second to (J-1)th decoders selects a part of the selected voltage group output from the preceding decoder as a selected voltage group in accordance with the shift bit signal received by itself. and output
the J-th decoder selects one selected voltage from a group of selected voltages output from the preceding decoder according to the shift bit signal received by itself and outputs it as the gradation voltage;
each of the first to J-th level shifters has a bias current generation unit including a transistor that generates a bias current responsible for the respective output current;
The level shifter is included in the bias current generator of each of the first to Jth level shifters via first to Jth lines individually connected to the first to Jth level shifters. including first to J-th bias setting circuits that supply bias voltages to the gates of the transistors;
The first to Jth bias setting circuits adjust the current values of the output currents of the first to Jth level shifters by individually setting current values to be supplied to the first to Jth lines. death,
An output current of the level shifter that supplies the shift bit signal to a decoder arranged at a later stage among the first to Jth decoders is arranged at an earlier stage among the first to Jth decoders. A semiconductor device , wherein the output current is smaller than the output current of the level shifter that supplies the shift bit signal to a decoder .

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