JP2013218021A - Data driver device and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data driver device which allows for suppressing an increase in the number of transistors in a decoder circuit, and to provide a display device equipped with a data driver device.SOLUTION: For adjacent first through third gradation voltages V0, V1, V2 on a section of a characteristic curve where input/output characteristics between an input digital signal and an output gradation voltage is non-linear, a second reference voltage corresponding to the second gradation voltage V1 is omitted and a third correction reference voltage V2_D corresponding to a correction voltage obtained from an external division of the first gradation voltage V0 and the second gradation voltage V1 is provided thereto. A decoder circuit 10 outputs two outputs by selecting the first gradation voltage and the third correction reference voltage when outputting the second gradation voltage in response to an input digital signal and, when outputting the first gradation voltage and the third gradation voltage, outputs two outputs by double-selecting the first reference voltage and by double-selecting the third reference voltage, respectively. An amplifier circuit 20 is fed with the two reference voltages for the two outputs selected by the decoder circuit 10 and outputs an interpolation of the two reference voltages.

Description

  The present invention relates to a display device, and more particularly, to a data driver including a digital-analog conversion circuit that outputs a gradation voltage based on a digital signal and a display device including the data driver.

  Recently, liquid crystal display devices (LCD) characterized by thinness, light weight, and low power consumption have been widely used as display devices, and mobile phones such as mobile phones (mobile phones, cellular phones), PDAs (personal digital assistants), and notebook PCs. It has been widely used in the display section of equipment. Recently, however, the technology for increasing the screen size and moving images of liquid crystal display devices has been increasing, and it has become possible to realize not only mobile applications but also stationary large screen display devices and large screen liquid crystal televisions. As these liquid crystal display devices, active matrix drive type liquid crystal display devices capable of high-definition display are used. In addition, an active matrix driving type display device using an organic light emitting diode (OLED) as a thin display device has been developed.

  With reference to FIG. 7, a typical configuration of an active matrix driving type thin display device (liquid crystal display device) will be outlined. FIG. 7A is a diagram showing an essential circuit configuration of a main part of the thin display device.

  Referring to FIG. 7A, an active matrix driving type thin display device includes a power supply circuit 940, a display controller 950, a display panel 960, a gate driver 970, and a data driver 980 as typical configurations. In the display panel 960, unit pixels including the pixel switch 964 and the display element 963 are arranged in a matrix (for example, in the case of a color SXGA panel, 1280 × 3 pixel columns × 1024 pixel rows). In the display panel 960, scanning lines 961 that send scanning signals output from the gate driver 970 to each unit pixel and data lines 962 that send gradation voltage signals output from the data driver 980 are wired in a grid pattern. . The gate driver 970 and the data driver 980 are controlled by the display controller 950, and necessary clocks CLK, control signals, and the like are supplied from the display controller 950, respectively. The video data is supplied to the data driver 980. Currently, digital data is the mainstream of video data. The power supply circuit 940 supplies necessary power to the gate driver 970 and the data driver 980. The display panel 960 includes a semiconductor substrate. As a display panel 960 such as a large screen display device, a semiconductor substrate in which a thin film transistor (a pixel switch or the like) is formed over an insulating substrate is widely used.

  In the display device of FIG. 7, when the pixel switch 964 is turned on / off by a scanning signal and the pixel switch 964 is turned on (electrically conductive), a gradation voltage signal corresponding to video data is displayed on the display element. When the luminance of the display element 963 is changed in accordance with the gradation voltage signal, an image is displayed. Rewriting of data for one screen is performed, for example, in one frame period (usually about 0.017 seconds when driven at 60 Hz), and each scanning line 961 sequentially selects (for each TFT 964) one pixel row (each line). The grayscale voltage signal is supplied from each data line 962 to the display element 963 via the pixel switch 964 within the selection period.

  In the liquid crystal display device, as shown in FIG. 7B, a display panel 960 includes a semiconductor substrate in which pixel switches 964 and transparent pixel electrodes 973 are arranged in a matrix as unit pixels, and one transparent surface on the entire surface. It has a structure in which a counter substrate on which an electrode 974 is formed and a liquid crystal sealed between the two substrates facing each other. The display element 963 constituting the unit pixel includes a pixel electrode 973, a counter substrate electrode 974, a liquid crystal capacitor 971, and an auxiliary capacitor 972. A backlight is provided as a light source on the back of the display panel.

  When the pixel switch 964 is turned on by a scanning signal from the scanning line 961, a gradation voltage signal from the data line 962 is applied to the pixel electrode 973, and a potential difference between each pixel electrode 973 and the counter substrate electrode 974 is generated. Even after the transmittance of the backlight that transmits the liquid crystal changes and the pixel switch 964 is turned off (non-conducting), the potential difference is held in the liquid crystal capacitor 971 and the auxiliary capacitor 972 for a certain period.

  In the driving of the liquid crystal display device, in order to prevent the deterioration of the liquid crystal, the driving (reversal driving) is performed to switch the voltage polarity (positive or negative) with a period of one frame for each pixel with respect to the common voltage of the counter substrate electrode 974. For this reason, the data line 962 is also driven by dot inversion driving in which the voltage polarity is changed in units of pixels or column inversion driving in which the voltage polarity is changed in units of frames.

  The data driver 980 includes a decoder circuit that receives reference voltage groups having different potentials and selects a reference voltage corresponding to the video digital signal, and an amplifier circuit (output circuit) that amplifies the output voltage of the decoder circuit. Note that a circuit block including a decoder circuit and an amplifier circuit outputs an analog signal voltage (gray scale voltage) corresponding to an input digital signal, and thus this circuit block is also referred to as a digital-analog conversion circuit. When the reference voltage and the output gradation voltage correspond to 1: 1, when the input digital signal is 6 bits, 64 reference voltages are required, and when the input digital signal is 8 bits, 256 reference voltages are Needed.

  In order to reduce the number of reference voltages and reduce the circuit area, the configuration includes a selector (decoder circuit) and an interpolation amplifier (buffer) that outputs a voltage obtained by interpolating two voltages selected by the selector. (See, for example, Patent Documents 1 and 2).

  In the configuration using the above-mentioned interpolation amplifier, for example, when the input digital signal is 6 bits, the reference voltage is 33 of V0, V2, V4,... V62, V64 corresponding to the output gradation voltage levels 0 to 63. You only have to prepare it.

FIG. 8 is a diagram illustrating a typical configuration example (related technology) of an interpolation amplifier type digital-analog conversion circuit in which an input digital signal = 6 bits and a reference voltage number = 33. Referring to FIG. 8, a first reference voltage group 20A (V0, V4, V8,..., V64) having an interval of 4 levels from V0 to V64, and a second reference voltage group having an interval of 4 levels from V2 to V62. 20B (V2, V6, V10,..., V62) and a decoder circuit 10 ′ that outputs two reference voltages based on a 6-bit input digital signal D5-D0, and two signals selected by the decoder circuit 10 ′ V (T1) and V (T2) are input, and the voltage obtained by internally dividing (interpolating) the two signal voltages at an internal ratio of 1: 1 Vout = {V (T1) + V (T2)} / 2
Is provided with an amplifying circuit (interpolation amplifier) 30 for outputting the signal. The bits D5 to D0 of the digital signal also include the complementary signals D5B to D0B (D5B to D0B are omitted).

  The decoder circuit 10 ′ receives 32 reference voltages (V0, V4, V8,..., V60, V64) of the first reference voltage group 20A, and tournaments based on the 5-bit input digital signal D5-D1. The selector 11A that selects one according to the method (A) and 32 reference voltages (V2, V6, V10,..., V58, V62) of the second reference voltage group 20B are input, and an input digital signal Based on D5-D2, a selector 11B that selects one according to the tournament method (B) and outputs from the selectors 11A, 11B are input, and V (T1), V based on the lower 2-bit digital signals D0, D1 (T2) includes a selector 12 that outputs two selected reference voltages.

  FIG. 9 is a diagram illustrating a configuration example of the tournament selector 11A of FIG. As shown in FIG. 9, in a switch group stage connected to (V0, V4, V8,..., V64) and controlled to be turned on / off by digital signals D1B and D1, when D1B = 1, 16 of V0, V4, V8,... V60) are selected, and when D1 = 1, 16 of (V4, V8,... V64) are selected. In the stage of the switch group connected to D2B and D2, 8 out of the 16 selected in the switch group connected to D1B and D1 in the previous stage are selected, and in the stage of the switch group connected to D3B and D3, 4 are selected from the 8 selected by the switch group connected to D2B and D2, and the switch group connected to D4B and D4 is selected by the switch group connected to D3B and D3 in the previous stage. Two of the four are selected, and in the stage of the switch group connected to D5B and D5, one of the two selected by the switch group connected to D4B and D4 in the previous stage is selected, and VS1 Is output. In FIG. 9, each switch is composed of an Nch transistor, and is turned on when the digital signal input to the gate is High (1) and turned off when the digital signal is Low (0). The number of switches (Nch transistors) in the selector 11A is 32 + 16 + 8 + 4 + 2 = 62.

  FIG. 10 is a diagram illustrating a configuration example of the tournament selector 11B of FIG. As shown in FIG. 10, in the stage of the switch group connected to (V2, V6, V10,..., V62) and turned on / off for D2B, D2, when D2B = 1, (V2, V10, V14) ,..., V50, V58) are selected, and when D2 = 1, eight of (V6, V14,..., V54, V62) are selected and connected to D3B and D3. In the stage, four of the eight selected by the switch group connected to the previous stage D2B and D2 are selected, and in the stage of the switch group connected to D4B and D4, the switch connected to the previous stage D3B and D3 Two of the four selected in the group are selected. In the stage of the switch group connected to D5B and D5, one of the two selected in the switch group connected to D4B and D4 in the previous stage is one. Selected and output to VS2. The number of switches (Nch transistors) in the selector 11B is 16 + 8 + 4 + 2 = 30.

  In FIGS. 9 and 10, each switch is composed of an Nch transistor, and is turned on when the digital signal input to the gate is High (1) and turned off when the digital signal is Low (0). The same applies to the other drawings.

  FIG. 11 is a diagram illustrating a configuration example of the selector 12. As shown in FIG. 11, the selector 12 receives the output VS1 of the selector 11A and the output VS2 of the selector 11B, and outputs a signal selected based on the lower two bits (D1, D0) (V (T1), V As shown in Fig. 11, a switch that is controlled to be turned on and off by inputting D0 and D1B to the gate terminals in a two-branch path between VS1 and V (T1), as shown in FIG. Each of the two branch paths between VS2 and V (T2) is provided with a switch in which D1 is input to the gate terminal and ON / OFF is controlled, and between V (T1) and V (T2), D0B 11, each switch is composed of an Nch transistor, and when the digital signal input to the gate is High (1), it is on, and when it is Low (0). , It is off.

When (D1, D0) = (0, 0), (V (T1), V (T2)) = (VS1, VS1),
When (D1, D0) = (0, 1), (V (T1), V (T2)) = (VS1, VS2),
When (D1, D0) = (1, 0), (V (T1), V (T2)) = (VS2, VS2),
When (D1, D0) = (1, 1), (V (T1), V (T2)) = (VS1, VS2) is selected.

  FIG. 18 is a diagram illustrating a configuration of the amplifier circuit (interpolation amplifier) 30. As shown in FIG. 18, the amplifier circuit (interpolation amplifier) 30 has a commonly connected source connected to a current source 113, a gate connected to a terminal T1 (voltage V (T1)), and an output terminal 3 (output terminal voltage Vout). ) Connected to the current source 114 and the gate connected to the terminal T2 (voltage V (T2)) and the output terminal 3, respectively. A second differential pair composed of connected Nch transistors 103 and 104, a Pch transistor 111 connected between a commonly connected drain of the Nch transistors 101 and 103 and the power supply VDD, and a common connection of the Nch transistors 102 and 104 Connected to the power source VDD, the gate and the drain are connected, and the gate is connected to the Pch transistor 1 1, the connection point of the Pch transistor 112 connected to the gate of 1, the drain of the Pch transistor 111 and the commonly connected drain of the Nch transistors 101 and 103 is connected to the input terminal, and the output terminal is connected to the output terminal 3. And an amplification stage 109. The Pch transistors 111 and 112 constitute a current mirror. The Nch transistors 101, 102, 103, and 104 have the same size, and the current values of the current sources 113 and 114 are equal. The drain currents of the Nch transistors 101, 102, 103, and 104 are given by ID1, ID2, ID3, and ID4 as follows.

ID1 = (β / 2) (V (T1) −V _TH ) ² (1)
ID2 = (β / 2) (Vout−V _TH ) ² (2)
ID3 = (β / 2) (V (T2) −V _TH ) ² (3)
ID4 = (β / 2) (Vout−V _TH ) ² (4)

However, in the above formulas (1) to (4), V _TH is a threshold voltage. β is a gain coefficient and is given by
β = μ (W / L) (εx / tox)
Where μ is the effective electron mobility, εx is the dielectric constant of the gate insulating film, tox is the thickness of the gate insulating film, W is the channel width, and L is the channel length.

  The current ID2 + ID4 is a current (input current) flowing through the Pch transistor 112 on the input side of the current mirror, and the current ID1 + ID3 is a current (output current) flowing through the Pch transistor 111 on the output side of the current mirror circuit. The current is controlled to be equal to the output current.

ID1 + ID3 = ID2 + ID4 (5)

Expanding the parentheses in Equations (1) to (4) and substituting them into Equation (5), assuming that both sides are equal with respect to the primary term of VTH,
V (T1) + V (T2) = 2 × Vout, that is,
Vout = {V (T1) + V (T2)} / 2 (6)
It becomes.

  Alternatively, ID1-ID2 = gm (V (T1) -Vout) and ID3-ID4 = gm (V (T2) -Vout) are expressed by Equation (5) where gm is the mutual conductance of the first and second differential pairs. (6) is derived by substituting for.

  12A and 12B are diagrams showing a list of conversion specifications of the circuit of FIG.

(1) When (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V0, V2),
Output of selector 12 (V (T1), V (T2)) = (V0, V0)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V0 + V0) / 2 = V0
It is. Note that the decoder selection voltages VIN1 and VIN2 in FIG. 12 are equal to the output voltages V (T1) and V (T2) of the selector 12.

(2) When (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 1),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V0, V2),
Output of selector 12 (V (T1), (V (T2)) = (V0, V1)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V0 + V2) / 2 = V1 (synthesis)
It becomes.

(3) When (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 1, 0),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V4, V2),
Output of selector 12 (V (T1), (V (T2)) = (V2, V2)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V2 + V2) / 2 = V2
It becomes.

(4) When (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 1, 1),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V4, V2),
Output of selector 12 (V (T1), (V (T2)) = (V4, V2)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V4 + V2) / 2 = V3 (synthesis)
It becomes.

(5) When (D5, D4, D3, D2, D1, D0) = (0, 0, 1, 0, 0),
Outputs of the selectors 11A and 11B ((VS1, VS2) = (V4, V6),
Output of selector 12 (V (T1), (V (T2)) = (V4, V4)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V4 + V4) / 2 = V4
It becomes.

(6) When (D5, D4, D3, D2, D1, D0) = (0, 0, 1, 0, 1),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V4, V6),
Output of selector 12 (V (T1), (V (T2)) = (V4, V6)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V4 + V6) / 2 = V5 (synthesis)
It becomes.

(7) When (D5, D4, D3, D2, D1, D0) = (0, 0, 1, 1, 0),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V8, V6),
Output of selector 12 (V (T1), (V (T2)) = (V6, V6)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V6 + V6) / 2 = V6
It becomes.

(8) When (D5, D4, D3, D2, D1, D0) = (0, 0, 1, 1, 1),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V8, V6),
Output V (T1), (V (T2)) of selector 12 = (V8, V6)
And
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V8 + V6) / 2 = V7 (synthesis)
It becomes. The same applies to (D5, D4, D3, D2, D1, D0) = (0, 1, 0, 0, 0) and thereafter.

(9) When (D5, D4, D3, D2, D1, D0) = (1, 1, 1, 1, 0, 0),
Outputs of selectors 11A and 11B (VS1, VS2) = (V60, V58),
Outputs of selectors 11A and 11B (V (T1), (V (T2)) = (V60, V60),
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V60 + V60) / 2 = V60
Become

(10) When (D5, D4, D3, D2, D1, D0) = (1, 1, 1, 1, 0, 1),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V60, V62),
Outputs of the selectors 11A and 11B (V (T1), (V (T2)) = (V60, V62),
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V60 + V62) / 2 = V61 (synthesis)
It becomes.

(11) When (D5, D4, D3, D2, D1, D0) = (1, 1, 1, 1, 1, 0),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V64, V62),
The output of the selector 12 (V (T1), (V (T2)) = (V62, V62),
The output (amplifier output) of the amplifier circuit 30 is Vout = (V62 + V62) / 2 = V62.
It becomes.

(12) When (D5, D4, D3, D2, D1, D0) = (1, 1, 1, 1, 1, 1),
Outputs of the selectors 11A and 11B (VS1, VS2) = (V64, V62),
The output of the selector 12 (V (T1), (V (T2)) = (V64, V62),
The output (amplifier output) of the amplifier circuit 30 is
Vout = (V64 + V62) / 2 = V63 (synthesis)
It becomes.

  FIG. 13 is a diagram illustrating input / output characteristics of the gradation data (input digital signal: horizontal axis) of the display device and the output voltage value (output gradation voltage: vertical axis) of the data driver. V0 to V7 non-linear region A (input / output relationship is not proportional (linear) relationship, non-linear), V56 to V63 non-linear region C, and V8 to V55 linear region B (region where input / output relationship is proportional) ). Non-linear areas A and C correspond to the gamma characteristic (correction) of the display device.

  FIG. 14 is a diagram showing a configuration (prototype example) of a decoder circuit corresponding to the display characteristics of FIG. The reference voltage group 21D1 (V56, V58, V60, V62) of the non-linear region C is input to the selector 11D1, and one of them is selected based on the digital signal D5-D0, and the two inputs VS1, VS2 is commonly input, and the selected voltage is commonly input to the input terminals V (T1) and V (T2) of the amplifier circuit 30, and the voltage of the level selected by the selector 11D1 is input from the amplifier circuit 30. Is output.

  The reference voltage group 21D2 (V0, V2, V4, V6) in the non-linear region A is input to the selector 11D2, and one of them is selected based on the digital signal D5-D0, and the two inputs VS1, VS2 is commonly input, and the selected voltage is commonly input to the input terminals V (T1) and V (T2) of the amplifier circuit 30, and the voltage of the level selected by the selector 11D2 is input from the amplifier circuit 30. Is output.

  The reference voltage 21D3 (V1, V3, V5, V7) of the non-linear region A is input to the selector 11D3, and one of them is selected based on the digital signal D5-D0, and the two inputs VS1, VS2 of the selector 12 are selected. And the amplifier circuit 30 input terminals V (T1) and V (T2) receive the selected voltage in common, and the amplifier circuit 30 outputs the voltage at the level selected by the selector 11D4. Is done.

  The reference voltage group 21D4 (V57, V59, V61, V63) in the non-linear region C is input to the selector 11D4, and one of them is selected based on the digital signal D5-D0, and the two inputs VS1, VS2 of the selector 12 are selected. And the amplifier circuit 30 input terminals V (T1) and V (T2) receive the selected voltage in common, and the amplifier circuit 30 outputs the voltage at the level selected by the selector 11D4. The As described above, the voltages of the non-linear region A (V0-V7) and the non-linear region C (V56-V63) are commonly input to the two input terminals VIN1 and VIN2 of the amplifier circuit 30. A voltage obtained by internally dividing the voltage (the same voltage) input in common to the two terminals V (T1) and V (T2) into 1: 1 is output.

  The reference voltage group 21A (V8, V12, V16,... V64) in the linear region B is input to the selector 11A ′, and one of them is selected based on the digital signal D5-D1, and the reference voltage group 21A (V8, V12, V16,. Entered.

  The reference voltage 21B (V10, V14, V18,... V62) of the linear region B is input to the selector 11B ′, and one of them is selected based on the digital signal D5-D1, and is input to VS2 of the selector 12. The

As described above, the selector 12 is based on the digital signals D1 and D0.
When (D1, D0) = (0, 0), (V (T1), V (T2)) = (VS1, VS1),
When (D1, D0) = (0, 1), (V (T1), V (T2)) = (VS1, VS2),
When (D1, D0) = (1, 0), (V (T1), V (T2)) = (VS2, VS2),
When (D1, D0) = (1, 1), (V (T1), V (T2)) = (VS1, VS2) is output. For example, when the selector 11D1 outputs one of the reference voltage group 21D1 (V56, V58, V60, V62) of the non-linear region C to the VS1 and VS2 of the selector 12 based on the input digital signal D5-D1, the other The outputs of the selectors 11D2, 11A ′, 11B ′, 11D3, and 11D4 are turned off. The same applies to the selectors 11D2, 11D3, and 11D4. The selectors 11A ′ and 11B ′ are simultaneously selected.

  FIG. 15A is a diagram showing a configuration example (prototype example) of the selector 11A ′ in FIG. Referring to FIG. 15, when D1B = 1 (D1 = 0), (V8, V12,... V52), when D1 = 1 (D1B = 0), (V12, V16,... V56). 12 are selected, 6 out of 12 are selected in D2B and D2, and 4 out of 6 are selected in D3B and D3, and 2 out of 4 are selected in D4B and D4. Is selected, and one of the two is selected in D5B and D5. The number of switches (Nch transistors) in the selector 11A ′ is 24 + 12 + 6 + 4 + 2 = 48.

  FIG. 15B is a diagram showing a configuration example (prototype example) of the selector 11B ′ in FIG. When D2B = 1 (D2 = 0), (V10, V18, V26, V34, V42, V50), when D2 = 1 (D2B = 0), (V14, V22, V30, V38, V46, V54) 6 are selected, 4 are selected from 6 at D3B and D3, 2 are selected from 4 at D4B and D4, and 1 is selected from 2 at D5B and D5 Is selected. The number of switches (Nch transistors) in the selector 11B ′ is 12 + 6 + 4 + 2 = 24.

  FIG. 16A is a diagram illustrating a configuration example (prototype example) of the selector 11D2 in FIG. As shown in FIG. 16A, two of (V0, V4) or (V2, V6) are selected by D1B and D1 from the reference voltage group (V0, V2, V4, V6), and D2B, D2 Thus, one of the two selected by D1B and D1 is selected, and when D3B = 1, D4B = 1, D5B = 1, and D0B = 1, they are input to VS1 and VS2 of the selection circuit 12. The number of switches (Nch transistors) in the selector 11D2 is 4 + 2 + 4 = 10.

  FIG. 16B is a diagram illustrating a configuration example (prototype example) of the selector 11D1 of FIG. As shown in FIG. 16 (B), two of D1B and D1 (V56, V60) or (V58, V62) are selected from the reference voltage group (V56, V58, V60, V62), and D2B, D2 are selected. One of the two selected by D1B and D1 is selected, and when D3 = 1, D4 = 1, D5 = 1, and D0B = 1, they are input to VS1 and VS2 of the selector 12. The number of switches (Nch transistors) in the selector 11D1 is 4 + 2 + 4 = 10.

  FIG. 16C is a diagram showing a configuration (prototype example) of the selector 11D3 in FIG. As shown in FIG. 16C, from the reference voltage group (V1, V3, V5, V7), D1B, D1 (V1, V5) or (V3, V7) are selected, and D2B, D2 are selected. When one of the two selected by D1B and D1 is selected and D3B = 1, D4B = 1, D5B = 1, and D0 = 1, the data is input to VS1 and VS2 of the selector 12. The number of switches (Nch transistors) in the selector 11D3 is 4 + 2 + 4 = 10.

  FIG. 16D is a diagram showing a configuration (prototype example) of the selector 11D4 in FIG. As shown in FIG. 16D, from the reference voltage group (V57, V59, V61, V63), D1B, D1 (V57, V61) or (V59, V63) are selected, and D2B, D2 are selected. When one of the two is selected and D3 = 1, D4 = 1, D5 = 1, and D0 = 1, they are input to VS1 and VS2 of the selector 12. The number of switches (Nch transistors) in the selector 11D4 is 4 + 2 + 4 = 10.

  FIG. 17 is a diagram showing conversion specifications of the circuit of FIG. Several combinations of input digital signals and output voltages will be described.

For V0 to V7 of the non-linear region A and V56 to V63 of the non-linear region C,
(VS1, VS2) = (Vi, Vi),
(V (T1), V (T2)) = (Vi, Vi)
Vout = (Vi + Vi) / 2 = Vi (where i = 0 to 7, 56 to 63)
It is said.

For V8 to V55 in the linear region B,
(VS1, VS2) is selected by the selectors 11A ′, 11B ′ that input the reference voltage groups 21A, 21B, respectively, and (V (T1), V (T2)) is output from the selector 12 to the amplifier circuit 30.

That is, for the non-linear region A,
When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 0, 0, 0), (VS1, VS2) = (V0, V0), (V (T1), V ( T2)) = (V0, V0), output voltage Vout = V0,
When (0, 0, 0, 0, 0, 1), (VS1, VS2) = (V1, V1), (V (T1), V (T2)) = (V1, V1), output voltage Vout = V1,
When (0, 0, 0, 0, 1, 0), (VS1, VS2) = (V2, V2), (V (T1), V (T2)) = (V2, V2), output voltage Vout = V2,
When (0, 0, 0, 0, 1, 1), (VS1, VS2) = (V3, V3), (V (T1), V (T2)) = (V3, V3), output voltage Vout = V3,
When (0, 0, 0, 1, 0, 0), (VS1, VS2) = (V4, V4), (V (T1), V (T2)) = (V4, V4), output voltage Vout = V4,
When (0, 0, 0, 1, 0, 1), (VS1, VS2) = (V5, V5), (V (T1), V (T2)) = (V5, V5), output voltage Vout = V5,
When (0, 0, 0, 1, 1, 0), (VS1, VS2) = (V6, V6), (V (T1), V (T2)) = (V6, V6), output voltage Vout = V6,
When (0, 0, 0, 1, 1, 1), (VS1, VS2) = (V7, V7), (V (T1), V (T2)) = (V7, V7), output voltage Vout = V7
It becomes.

For linear region B,
(D5, D4, D3, D2, D1, D0)
When (0, 0, 1, 0, 0, 0), (VS1, VS2) = (V8, V10), (V (T1), V (T2)) = (V8, V8), output voltage Vout = V8,
When (0, 0, 1, 0, 0, 1), (VS1, VS2) = (V8, V10), (V (T1), V (T2)) = (V8, V10), output voltage Vout = V9,
When (0, 0, 1, 0, 1, 0), (VS1, VS2) = (V12, V10), (V (T1), V (T2)) = (V12, V10), output voltage Vout = V9,
When (0, 0, 1, 0, 1, 1), (VS1, VS2) = (V12, V10), (V (T1), V (T2)) = (V12, V10), output voltage Vout = V10
It becomes. Similarly,
(D5, D4, D3, D2, D1, D0)
When (1, 1, 0, 1, 1, 0), (VS1, VS2) = (V56, V54), (V (T1), V (T2)) = (V54, V54), output voltage Vout = V54,
When (1, 1, 0, 1, 1, 1), (VS1, VS2) = (V56, V54), (V (T1), V (T2)) = (V56, V54), output voltage Vout = V55
It becomes.

For the non-linear region C,
(D5, D4, D3, D2, D1, D0)
When (1, 1, 1, 0, 0, 0), (VS1, VS2) = (V56, V56), (V (T1), V (T2)) = (V56, V56), output voltage Vout = V56,
When (1, 1, 1, 0, 0, 1), (VS1, VS2) = (V57, V57), (V (T1), V (T2)) = (V57, V57), output voltage Vout = V57,
When (1, 1, 1, 0, 1, 0), (VS1, VS2) = (V58, V58), (V (T1), V (T2)) = (V58, V58), output voltage Vout = V58,
When (1, 1, 1, 0, 1, 1), (VS1, VS2) = (V58, V58), (V (T1), V (T2)) = (V59, V59), output voltage Vout = V59,
When (1, 1, 1, 0, 1, 1), (VS1, VS2) = (V60, V60), (V (T1), V (T2)) = (V60, V60), output voltage Vout = V60,
When (1, 1, 1, 1, 0, 0), (VS1, VS2) = (V61, V61), (V (T1), V (T2)) = (V61, V61), output voltage Vout = V61,
When (1, 1, 1, 1, 0, 1), (VS1, VS2) = (V62, V62), (V (T1), V (T2)) = (V62, V62), output voltage Vout = V62,
When (1, 1, 1, 1, 1, 0), (VS1, VS2) = (V63, V63), (V (T1), V (T2)) = (V63, V63), output voltage Vout = V63
It becomes.

  Note that the outputs of the selectors 11D1, 11D2, 11D3, and 11D4 may be connected to the outputs V (T1) and V (T2) of the selector 12.

JP 2001-34234 A JP 2000-183747 A

  In the configuration shown in FIG. 14, the 1: 1 interpolation method cannot be used as it is in a region where the input / output characteristics are non-linear. That is, in the non-linear region, the output gradation voltage corresponding to the thinned reference voltage cannot be generated by internally dividing the reference voltages on both sides of the thinned reference voltage with an internal division ratio of 1: 1. For this reason, in the non-linear region, it is necessary to provide a reference voltage for each step.

  Furthermore, in the configuration shown in FIG. 14, the reference voltage group in the non-linear region cannot be selected using a selector that decodes the reference voltage in the linear region by a tournament method. For this reason, a selector (11D, 11D2, 11D3, 11D4 in FIG. 14) for decoding the reference voltage in the non-linear region is separately required. As a result, the number of switch transistors increases.

According to one aspect of the embodiment, the input to output characteristics between the input digital signal and the gradation voltage output in response to the input digital signal are adjacent to each other on the nonlinear characteristic curve. For the gradation voltage of
First and third reference voltages corresponding to the first and third gradation voltages, respectively;
As a reference voltage corresponding to the second gradation voltage between the first and third gradation voltages, the second reference voltage between the first and third reference voltages is thinned out, A third correction reference voltage corresponding to a correction gradation voltage determined by an external component of the first gradation voltage and the second gradation voltage, instead of the subtracted second reference voltage;
A decoder circuit that selects a reference voltage from a plurality of reference voltages according to the input digital signal and outputs it to two outputs, according to the input digital signal,
In outputting the second gradation voltage, the first gradation voltage and a third correction reference voltage are selected and output to the two outputs,
In outputting the first gray scale voltage and the third gray scale voltage, respectively, the first reference voltage is redundantly selected, and the third reference voltage is redundantly selected and output to the two outputs. A decoder circuit to
There are provided a data driver device including an amplifier circuit that receives and interpolates and outputs the reference voltages of the two outputs selected by the decoder circuit, and a display device including the data driver device.

According to another aspect, a first reference voltage group including a plurality of different reference voltages,
A second reference voltage group including a plurality of reference voltages different from the reference voltage of the first reference voltage group and different from each other,
A first selector that selects one reference voltage from the first reference voltage group based on a first bit group of the input digital signal in a tournament manner;
A second selector that selects one reference voltage from the second reference voltage group based on the first bit group of the input digital signal in a tournament manner;
Based on the second bit group of the input digital signal, either of the two reference voltages selected by the first and second selectors is output, or one of the two reference voltages is overlapped with two. A third selector for selecting and outputting one;
A decoder circuit comprising:
An amplifier circuit that outputs an output voltage obtained by interpolating the two reference voltages output from the third selector;
With
The first gradation voltage on a characteristic curve in which the input / output characteristics relating to the input digital signal and the output gradation voltage are nonlinear; the second gradation voltage adjacent to the first gradation voltage; For the third gradation voltage adjacent to the second gradation voltage,
The first and third reference voltages corresponding to the first and third gradation voltages are provided in the first or second reference voltage group, respectively, and the third corrected reference voltage is provided in the first and second reference voltages. 3 on the reference voltage group side to which the reference voltage 3 belongs,
In response to the input digital signal corresponding to the second grayscale voltage, the first and second selectors and the third selector cause the first reference voltage and the third corrected reference voltage to be changed. And the second gradation voltage obtained by interpolating the first reference voltage and the third correction reference voltage is output from the amplifier circuit,
Tournament method of the decoder circuit The first and second selectors and the third selector are data driver devices that are commonly used in a region where the input / output characteristics are linear and a region where the input / output characteristics are nonlinear. In addition, a display device including the data driver device is provided.

  According to the embodiment, it is possible to output the gradation voltage in the non-linear region with the input / output characteristics by the interpolation method similarly to the linear region, and as a result, the increase in the number of transistors in the decoder circuit is suppressed. It is possible.

It is a figure which shows the structure of one Embodiment. It is a figure explaining the synthesis | combination of the gradation voltage in one Embodiment. It is a figure which shows the structure of the selector 11A of FIG. It is a figure which shows the structure of the selector 11B of FIG. (A), (B) is a figure which shows the specification of the conversion operation | movement of one Embodiment. It is a figure which shows the structure of the data driver of one Embodiment. It is a figure explaining a liquid crystal display device. It is a figure which shows an example of a structure of the digital-analog converting circuit of related technology. It is a figure which shows an example of a structure of the selector 11A of FIG. It is a figure which shows an example of a structure of the selector 11B of FIG. It is a figure which shows an example of a structure of the selector 12 of FIG. (A), (B) is a figure which shows the specification of the conversion operation | movement of the related technique 1. FIG. It is a figure which shows the relationship between an input digital signal and an output voltage value. It is a figure which shows an example (prototype example) of a structure of a digital analog conversion circuit. (A), (B) is a figure which shows an example (prototype example) of a structure of selector 11A 'of FIG. 14, 11B'. It is a figure which shows an example (prototype example) of a structure of selector 11D1-D4 of FIG. (A), (B) is a figure which shows an example of the specification of the conversion operation | movement of FIG. It is a figure which shows the structural example of an amplifier circuit.

  Embodiments will be described. According to some embodiments, among the plurality of gradation voltages (including the first to third gradation voltages) in a region where the input / output characteristics are nonlinear, the first and third gradation voltages are respectively set. First and third reference voltages corresponding to each other, and a reference voltage corresponding to the second gradation voltage between the first and third gradation voltages is the first and third reference voltages. The second reference voltage is thinned out, and instead of the thinned second reference voltage, the corrected gradation voltage determined by the external division of the first gradation voltage and the second gradation voltage A first reference voltage adjacent to the thinned second reference voltage is converted to a second gradation voltage corresponding to the thinned second reference voltage. And a third corrected reference voltage corresponding to the thinned second reference voltage. More specifically, with respect to the first to third gradation voltages (refer to V0, V1, and V2 in FIG. 2) on the nonlinear characteristic curve, the input / output characteristics between the input digital signal and the output gradation voltage are First and third reference voltages corresponding to the first and third gradation voltages (V0 and V2), respectively, and a second reference voltage corresponding to the second gradation voltage (V1) is thinned out. In addition, a third correction reference voltage corresponding to a correction gradation voltage obtained by extrapolating (extrapolating) the first gradation voltage (V0) and the second gradation voltage (V1) (see FIG. 2 V2_D).

  The decoder circuit (10 in FIG. 1) redundantly selects the first reference voltage (V0) according to the first value of the input digital signal and outputs it to two outputs. The first gray scale voltage (V0) is generated by interpolation (for example, with an internal ratio of 1: 1) by an amplifier circuit (30) that receives two outputs.

  The decoder circuit (10 in FIG. 1) selects the first reference voltage (V0) and the third corrected reference voltage (V2_D) in accordance with the second value of the input digital signal. The second grayscale voltage (V2) is output by one amplifier and interpolating (for example, internally dividing at an internal ratio of 1: 1) by the amplifier circuit (30) receiving the two outputs of the decoder circuit (10). ) Is generated.

  The decoder circuit (10 in FIG. 1) redundantly selects the third reference voltage (V2) according to the third value of the input digital signal and outputs it to two outputs. The third gradation voltage (V2) is generated by interpolating with an amplifier circuit (30) that receives two outputs.

  Of the gradation voltages in the region where the input / output characteristics are non-linear, the gradation voltage corresponding to the thinned reference voltage is expressed as one reference voltage adjacent to the thinned reference voltage and the interpolated reference voltage. Insert and output. That is, according to the embodiment, the input / output characteristic between the input digital signal and the output gradation voltage corresponds to the thinned reference voltage in the non-linear region as well as the linear region of the input / output characteristic. The gradation voltage to be synthesized is output using a reference voltage adjacent to the thinned reference voltage.

  According to one embodiment, the first reference voltage group (20A, 20C) including a plurality of different reference voltages and the reference voltage of the first reference voltage group (20A, 20C) are different from each other. And a second reference voltage group (20B, 20D) including the reference voltage, and the decoder circuit (10) generates a first bit group of the input digital signal from the first reference voltage group. Based on the first selector (11A) for selecting one reference voltage by a tournament method and one reference voltage based on the first bit group of the input digital signal from the second reference voltage group Whether to output both of the two reference voltages selected by the first selector and the second selector based on the second bit group of the input digital signal based on the second selector (11B) for selecting the video by the tournament method ,or , A, a third selector for two selected outputs (12) overlapping one of said two reference voltages.

  The amplifier circuit (30) outputs an output voltage having an intermediate potential obtained by interpolating the two reference voltages output from the third selector (12).

  The first gray scale voltage, the second gray scale voltage, and the third gray scale voltage that are adjacent on the characteristic curve in which the input / output characteristics relating to the input digital signal and the output gray scale voltage are non-linear are the first gray scale voltage. , First and third reference voltages respectively corresponding to the third gradation voltage are provided in the first or second reference voltage group, and the third corrected reference voltage is provided as the third reference voltage. A reference voltage group to which the voltage belongs is provided.

  In response to the input digital signal corresponding to the second gradation voltage, the first and second selectors (11A, 11B) and the third selector (12) Two of the third correction reference voltages are selected, and the second gradation voltage obtained by interpolating the first reference voltage and the third correction reference voltage from the amplifier circuit (30). Is output. With this configuration, the first to third selectors of the decoder circuit are used in common in a region where the input / output characteristics are linear and a region where the input / output characteristics are nonlinear.

  According to one embodiment, the third corrected reference voltage is provided before the at least one of the first and second selectors (11A / B) according to a predetermined bit of the input digital signal. Or a switch circuit (40A / B) that selects one of the third reference voltages and supplies it to the input of the one selector.

According to one embodiment, the third selector (12), according to four combinations of lower 2 bits (D1, D0) forming the second bit group of the input digital signal,
In the first combination, two reference voltages selected by the first selector (11A) are duplicated,
In the second combination, two reference voltages respectively selected by the first and second selectors (11A, 11B)
In the third combination, two reference voltages selected by the second selector (11B) are duplicated,
In the fourth combination, the two reference voltages respectively selected by the first and second selectors (11A, 11B) are selectively output.

According to one embodiment, the third gradation voltage and the fourth gradation voltage corresponding to the third reference voltage (V2), the input / output characteristics of which are adjacent on a nonlinear characteristic curve. For (V3) and the fifth gradation voltage corresponding to the fifth reference voltage (V4),
A fifth correction reference voltage (V4_D) corresponding to a correction voltage obtained by extrapolating the third gradation voltage (V2) and the fourth gradation voltage (V3);
The first reference voltage (V0), the fifth interpolation reference voltage (V4_D), and the fifth reference voltage (V4) are supplied to the first selector (11A),
The third correction reference voltage (V2_D) and the third reference voltage (V2) are supplied to the second selector (11B) via the switch circuit (40B),
In response to a first value of the input digital signal corresponding to the first gradation voltage (V0),
The first selector selects the first reference voltage (V0),
The second selector selects the third correction reference voltage (V2_D) selected by the switch circuit (40B),
Two first reference voltages (V0) are output in duplicate from the third selector (12), and the first reference voltage (V0) is interpolated between the first reference voltages (V0) from the amplifier circuit. Is output,
In response to a second value of the input digital signal corresponding to the second gradation voltage,
The first selector (11A) selects the first reference voltage (V0),
The second selector (11B) selects the third correction reference voltage (V2_D) selected by the switch circuit (40B),
The first selector (12) outputs the first reference voltage (V0) and the third corrected reference voltage (V2_D), and the amplifier circuit (30) outputs the first reference voltage (V0). And the second gradation voltage obtained by interpolating the third correction reference voltage (V2_D),
In response to a third value of the input digital signal corresponding to the third gradation voltage,
The first selector (11A) selects the fifth correction reference voltage (V4_D),
The second selector (11B) selects the third reference voltage (V2) selected by the switch circuit (40B),
Two third reference voltages (V2) are output redundantly from the third selector (12), and the two third reference voltages (V0) are interpolated from the amplifier circuit (30). The third gradation voltage is output,
In response to a fourth value of the input digital signal corresponding to the fourth gradation voltage,
The first selector (11A) selects the fifth correction reference voltage (V4_D),
The second selector (11B) selects the third reference voltage (V2) selected by the switch circuit (40B),
The third selector (12) outputs the fifth corrected reference voltage (V4_D) and the third reference voltage (V2),
The fourth gradation voltage obtained by interpolating the fifth corrected reference voltage (V4_D) and the third reference voltage (V2) is output from the amplifier circuit (30).

  According to one embodiment, the amplifying circuit (30) has an intermediate potential gradation voltage obtained by interpolating the two reference voltages output from the third selector at an internal division ratio of 1: 1. The first and third grayscale voltages output are equal to the voltage levels of the first and third reference voltages, respectively. The third correction reference voltage (V2_D) is obtained by dividing the first gradation voltage (V0) and the second gradation voltage (V1) by 2: 1. The first, third, and fifth gradation voltages are equal to the voltage levels of the first, third, and fifth reference voltages, respectively. The fifth correction reference voltage (V4_D) is obtained by dividing the third gradation voltage (V2) and the fourth gradation voltage (V3) by 2: 1.

  According to one embodiment, in the region where the input / output characteristics are linear, the first and second reference voltage groups are provided with reference voltages on both sides of the grayscale voltage corresponding to the thinned reference voltage. Are selected by the first and second selectors (11A, 11B) and the third selector (12), supplied to the amplifier circuit, and a gradation voltage corresponding to the thinned reference voltage is output. . Exemplary embodiments are described below with reference to the drawings. In the following, in order to facilitate comparison with FIGS. 8 and 14, the input digital signal is described as 6 bits, but it is needless to say that the input digital signal is not limited to 6 bits.

  FIG. 1 is a diagram illustrating a configuration of an exemplary embodiment. Referring to FIG. 1, reference voltages are grouped, and reference voltage group 20A (V0, V4, V8,... V64) and reference voltage group 20B (V2, V6, V10,. A voltage group 20D (V2_D, V6_D, V58_D, V62_D) and a reference voltage group 20C (V4_D, V8_D, V60_D, V64_D) are provided. Furthermore, pre-stage circuits 40A and 40B, a decoder 10, and an amplifier circuit 30 (interpolation amplifier) are provided. The decoder 10 includes a tournament system (A) selector 11A, a tournament system (B) selector 11B, and a selector 12.

  The selector 11A receives the output of the pre-stage circuit 40A that inputs the reference voltage groups 20A and 20C, selects one reference voltage based on the digital signal D5-D1, and outputs the selected reference voltage to VS1. The bits D5 to D0 of the digital signal also include the complementary signals D5B to D0B (D5B to D0B are omitted).

  The selector 11B receives the output of the pre-stage circuit 40B that inputs the reference voltage groups 20B and 20D, selects one reference voltage based on the digital signal D5-D1, and outputs the selected reference voltage to VS2.

  The selector 12 receives the outputs VS1 and VS2 from the selector 11A and the selector 11B, and outputs the voltages selected according to the values of the lower 2 bits D1 and D0 of the digital signal to the output terminals V (T1) and V (T2). . The selector 12 in FIG. 1 has the same configuration as the selector 12 shown in FIG.

  The amplifier circuit 30 (interpolation amplifier) outputs an output voltage Vout obtained by internally dividing the voltages of VIN1 and VIN2 at an internal division ratio of 1: 1, and has the configuration shown in FIG. 18, for example.

FIG. 2 is a diagram illustrating the voltage relationship of the non-linear regions (V0, V1, V2, V2_D). V2_D is obtained by extrapolating (extrapolating) V0 and V1 (line segment V0-V1) at a ratio of 2: 1 (line segment V0-V2_D: line segment V2_D-V1 = 2: 1). At this time, V1 is obtained by internally dividing V0 and V2_D with an internal ratio of 1: 1. That is, the horizontal direction in FIG. 2 is the value of the input digital signal, the vertical direction is the output gradation voltage (output voltage value), and the difference between the values of the digital signals corresponding to V0 and V1 is Δx, the output gradation voltage. When the difference between V0 and V1 is Δy, the difference between the values of the input digital signals corresponding to V1 and V2 (V2_D) is Δx, and the difference between the output gradation voltages V0 and V2_D is Δy.
V0−V1 = V1−V2_D (= Δy)
１ V1 = (V0 + V2_D) / 2
V1 is generated by internally dividing V0 and V2_D (correction voltage) with an internal ratio of 1: 1.

  In a region where the output voltage value does not change linearly with respect to the input digital signal (gradation data) (for example, when the output voltage value deviates by 20 to 30% or more from the linear region), a correction voltage (V2_D) different from the reference voltage V2 V0 and the voltage (V1) synthesized from this V2_D are used as the output voltage of the amplifier circuit 30.

Similarly, in the non-linear region A of FIG.
V3 is generated with an internal ratio (V2 + V4_D) / 2 of an internal ratio of V2 and V4_D of 1: 1,
V5 is generated with an internal ratio (V4 + V6_D) / 2 of an internal ratio of 1: 1 between V4 and V6_D,
V7 is generated with an internal division (V8_D + V6) / 2 of an internal division ratio of V8_D and V6 of 1: 1.

On the other hand, in the non-linear region A of FIG.
V0 is generated with an internal ratio (V0 + V0) / 2 of an internal ratio of V0 and V0 of 1: 1, and similarly,
V2 is generated at an internal ratio (V2 + V2) / 2 of an internal ratio of 1: 1 between V2 and V2,
V4 is generated with an internal ratio (V4 + V4) / 2 of an internal ratio of 1: 1 between V4 and V4,
V6 is generated with an internal ratio (V6 + V6) / 2 of an internal ratio of 1: 1 between V6 and V6.

  Similarly, V58_D, V60_D, V62_D, and V64_D are provided for V58, V60, V62, and V64 in the non-linear region C of FIG.

V57 is generated with an internal ratio (V56 + V58_D) / 2 of an internal ratio of V56 and V58_D of 1: 1,
V59 is generated with an internal ratio (V60 + V58_D) / 2 of an internal ratio of 1: 1 between V60 and V58_D,
V61 is generated with an internal ratio (V60 + V62_D) / 2 of an internal ratio of 1: 1 between V60 and V62_D,
V63 is generated with an internal division (V63 + V64_D) / 2 of an internal division ratio of 1: 1 between V64_D and V62.

V58 of the non-linear region C in FIG. 13 is generated with an internal ratio (V58 + V58) / 2 of an internal ratio of V58 and V58 of 1: 1,
V60 is generated with an internal ratio (V60 + V60) / 2 of an internal ratio of 1: 1 between V60 and V60,
V62 is generated with an internal ratio (V62 + V62) / 2 of an internal ratio of 1: 1 between V62 and V62.

  FIG. 3 is a diagram showing the configuration of the pre-stage circuit 40A and the selector 11A in FIG. Although not particularly limited, in the example of FIG. 3, the pre-stage circuit 40 </ b> A of FIG. 1 includes a wiring that connects each reference voltage to the selector 11 </ b> A. That is, V0 to V64_D pass through the pre-stage circuit 40A (without passing through the switch) and are input to the corresponding switch of the selector 11A.

  The selector 11A inputs V0, V4_D, V4, V8_D, V8, V12, V16, V20, V24, V28, V32, V36, V40, V44, V48, V52, V56, V60_D, V60, V64_D from the previous stage circuit 40A. Then, by 32 switches (Nch transistors) that are turned on / off by the values of D1B and D1, when D1B = 1 (D1 = 0), (V0, V4, V8, V12, V16, V20, V24, V28) , V32, V36, V40, V44, V48, V52, V56, V60), and when D1 = 1 (D1B = 0), (V4_D, V8_D, V12, V16, V20, V24, V28, V32, V36) , V40, V44, V48, V52, V56, V60_D, V64_D).

  The selector 11A selects 8 reference voltages from 16 reference voltages selected based on D1B and D1, based on 16 switches (Nch transistors) that are turned on / off by the values of D2B and D2. Four reference voltages are selected from eight reference voltages based on eight switches (Nch transistors) that are turned on / off by the values of D3B and D3, and the values of D4B and D4 are selected from the four reference voltages. The two reference voltages are selected based on the four switches (Nch transistors) that are turned on / off by the two switches, and the two switches that are turned on / off by the values of D5B and D5 from the two reference voltages ( One reference voltage is selected based on the Nch transistor) and output to VS1.

  FIG. 4 is a diagram showing the configuration of the pre-stage circuit 40B and the selector 11B of FIG. The pre-stage circuit 40B inputs V2_D, V2, V6_D, V6, V10, V14, V18, V22, V26, V30, V34, V38, V42, V46, V50, V54, V58_D, V58, V62_D, V62, and D1B, The eight switches (Nch transistors) that are turned on / off by D1 output (V2_D, V6_D, V10,..., V50, V54, V58_D, V62_D) to selector 11B when D1B = 1, and D1 When = 1, (V2, V6, V10,..., V50, V54, V58, V62) are output to the selector 11B. Note that V2_D and V2, V6_D and V6, V58_D and V58, and V62_D and V62 are input to the corresponding switches of the selector 11B through switches that are turned on / off by D1B and D1, respectively. , V22, V26, V30, V34, V38, V42, V46, V50, and V54 pass through the preceding circuit 40B (without passing through the switch) and are input to the corresponding switch of the selector 11B.

  The selector 11B has eight references based on 16 switches (Nch transistors) that are turned on / off by the values of D2B and D2 from the 16 reference voltages selected based on D1B and D1 in the previous circuit 11B. A voltage is selected, and four reference voltages are selected from the eight reference voltages based on eight switches (Nch transistors) that are turned on / off by the values of D3B and D3. From the two reference voltages, two reference voltages are selected based on four switches (Nch transistors) that are turned on / off by the values of D4B and D4, and are turned on / off by D5B and D5. Based on the two switches (Nch transistors), one of the reference voltages is selected and output to VS2.

  The selector 12 has the configuration shown in FIG. 11, and selects and outputs as follows according to the combination of the values of the lower two bits D1 and D0 of the digital signal.

When (D1, D0) = (0, 0), (V (T1), V (T2)) = (VS1, VS1),
When (D1, D0) = (0, 1), (V (T1), V (T2)) = (VS1, VS2),
When (D1, D0) = (1, 0), (V (T1), V (T2)) = (VS2, VS2),
When (D1, D0) = (1, 1), (V (T1), V (T2)) = (VS1, VS2)
Is output.

  FIG. 5 is a diagram showing the specifications of the conversion operation of the circuit of FIG. For the non-linear region and the linear region, the conversion operation will be described according to some input digital signals.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 0, 0, 0),
V0 is output from the selector 11A to VS1,
V2_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V0, V0),
From the input (VIN1, VIN2) = (V0, V0) of the amplifier circuit 30, the output voltage is
Vout = (V0 + V0) / 2 = V0
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 0, 0, 1),
V0 is output from the selector 11A to VS1,
V2_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V0, V2_D),
From the input (VIN1, VIN2) = (V0, V2_D) of the amplifier circuit 30, the output voltage is Vout = (V0 + V2_D) / 2 = V1.
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 0, 1, 0),
V4_D is output from the selector 11A to VS1,
V2 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V2, V2),
From the input (VIN1, VIN2) = (V2, V2) of the amplifier circuit 30, the output voltage is
Vout = (V2 + V2) / 2 = V2
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 0, 1, 1),
V4_D is output from the selector 11A to VS1,
V2 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V4_D, V2),
From the input (VIN1, VIN2) = (V4_D, V2) of the amplifier circuit 30, the output voltage is Vout = (V4_D + V2) / 2 = V3.
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 1, 0, 0),
V4 is output from the selector 11A to VS1.
V6_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V4, V4),
From the input (VIN1, VIN2) = (V4, V4) of the amplifier circuit 30, the output voltage is
Vout = (V4 + V4) / 2 = V4
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 1, 0, 1),
V4 is output from the selector 11A to VS1.
V6_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V4, V6_D),
From the input (VIN1, VIN2) = (V4, V6_D) of the amplifier circuit 30, the output voltage is Vout = (V4 + V6_D) / 2 = V5.
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 1, 1, 0),
V8_D is output from the selector 11A to VS1,
V6 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V6, V6),
From the input (VIN1, VIN2) = (V6, V6) of the amplifier circuit 30, the output voltage is
Vout = (V6 + V6) / 2 = V6
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 0, 1, 1, 1),
V8_D is output from the selector 11A to VS1,
V6 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V8_D, V6),
From the input (VIN1, VIN2) = (V8_D, V6) of the amplifier circuit 30, the output voltage is
Vout = (V8_D + V6) / 2 = V7
It becomes.

  The above corresponds to the conversion of the non-linear region A in FIG.

  The conversion of the linear region B of the output voltage levels V8 to V56 is the same as the output voltage levels V8 to V56 of FIG.

That is, when (D5, D4, D3, D2, D1, D0) is (0, 0, 1, 0, 0, 0),
V8 is output from the selector 11A to VS1,
V6 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V8, V8),
From the input (VIN1, VIN2) = (V8, V8) of the amplifier circuit 30, the output voltage is
Vout = (V8 + V8) / 2 = V8
It becomes.

When (D5, D4, D3, D2, D1, D0) is (0, 0, 1, 0, 0, 0),
V8 is output from the selector 11A to VS1,
V10 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V8, V10),
From the input (VIN1, VIN2) = (V8, V10) of the amplifier circuit 30, the output voltage is
Vout = (V8 + V10) / 2 = V9
It becomes. Similarly,
When (D5, D4, D3, D2, D1, D0) is (1, 1, 0, 1, 0, 0),
V52 is output from the selector 11A to VS1.
V50 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V52, V52),
From the input (VIN1, VIN2) = (V52, V52) of the amplifier circuit 30, the output voltage is
Vout = (V52 + V52) / 2 = V52
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 0, 1, 0, 1),
V52 is output from the selector 11A to VS1.
V54 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V52, V54),
From the input (VIN1, VIN2) = (V52, V54) of the amplifier circuit 30, the output voltage is
Vout = (V52 + V54) / 2 = V53
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 0, 1, 1, 0),
V56 is output from the selector 11A to VS1,
V54 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V54, V54),
From the input (VIN1, VIN2) = (V54, V54) of the amplifier circuit 30, the output voltage is
Vout = (V54 + V54) / 2 = V54
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 0, 1, 1, 1),
V56 is output from the selector 11A to VS1,
V54 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V56, V54),
From the input (VIN1, VIN2) = (V56, V54) of the amplifier circuit 30, the output voltage is Vout = (V56 + V54) / 2 = V55.
It becomes.

  The above is the conversion operation of the linear region B. The conversion operation of the non-linear region C is as follows.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 0, 0, 0)
V56 is output from the selector 11A to VS1,
V58_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V56, V54),
From the input (VIN1, VIN2) = (V56, V54) of the amplifier circuit 30, the output voltage is
Vout = (V56 + V56) / 2 = V56
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 0, 0, 0)
V56 is output from the selector 11A to VS1,
V58_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V56, V56),
From the input (VIN1, VIN2) = (V56, V56) of the amplifier circuit 30, the output voltage is
Vout = (V56 + V56) / 2 = V56
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 0, 0, 1)
V56 is output from the selector 11A to VS1,
V58_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V56, V58_D),
From the input (VIN1, VIN2) = (V56, V58_D) of the amplifier circuit 30, the output voltage is
Vout = (V56 + V58_D) / 2 = V57
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 0, 1, 0),
V60_D is output from the selector 11A to VS1,
V58 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V58, V58),
From the input (VIN1, VIN2) = (V58, V58) of the amplifier circuit 30, the output voltage is
Vout = (V58 + V58) / 2 = V58
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 0, 1, 1) (= 59)
V60_D is output from the selector 11A to VS1,
V58 is output from the selector 11B to VS2.
The selector 12 outputs (V (T1), V (T2)) = (V60_D, V58),
From the input (VIN1, VIN2) = (V60_D, V58) of the amplifier circuit 30, the output voltage is
Vout = (V60_D + V58) / 2 = V59
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 1, 0, 0) (= 60)
V60 is output from the selector 11A to VS1,
V62_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V60, V60),
From the input (VIN1, VIN2) = (V60, V60) of the amplifier circuit 30, the output voltage is
Vout = (V60 + V60) / 2 = V60
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 1, 0, 1) (= 61)
V60 is output from the selector 11A to VS1,
V62_D is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V60, V62_D),
From the input (VIN1, VIN2) = (V60, V62_D) of the amplifier circuit 30, the output voltage is
Vout = (V60 + V62_D) / 2 = V61
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 1, 1, 0) (= 62)
V64_D is output from the selector 11A to VS1,
V62 is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V62, V62),
From the input (VIN1, VIN2) = (V62, V62) of the amplifier circuit 30, the output voltage is
Vout = (V62 + V62) / 2 = V62
It becomes.

When (D5, D4, D3, D2, D1, D0) is (1, 1, 1, 1, 1, 1) (= 62)
V64_D is output from the selector 11A to VS1,
V62 is output from the selector 11B to VS2,
The selector 12 outputs (V (T1), V (T2)) = (V64_D, V62),
From the input (VIN1, VIN2) = (V64_D, V62) of the amplifier circuit 30, the output voltage is
Vout = (V64_D + V62) / 2 = V63
It becomes.

  As in the configuration shown in FIG. 14 (prototype example), in the configuration in which the number of reference voltages is reduced by synthesizing an intermediate voltage between two voltages with an interpolation amplifier, basically only the linear region can be handled. Therefore, with respect to the non-linear region, reference voltages are prepared corresponding to all gradations and DA conversion is performed. For this reason, dedicated decode circuits (selectors 11D1 to 11D4) are required for the non-linear region. . That is, it is necessary to separately prepare a selector having a configuration different from that of a normal tournament type selector. As a result, in the configuration shown in FIG. 14, it is difficult to reduce the layout area.

  On the other hand, according to the present embodiment, similarly to the linear region, it is possible to interpolate the non-linear region using a 1: 1 interpolation method. By sharing the tournament selectors (11A, 11B), an increase in the number of transistors in the decoder circuit can be avoided.

  In the present embodiment, by using the correction voltage as a reference voltage for the non-linear region, the digital-analog conversion circuit can be decoded by the ½ interpolation method for the entire output voltage range. The size can be reduced. Although the pre-stage circuits 40A and 40B are added between the selectors 11A and 11B and the reference voltage group, the number of added transistors and the number of reference voltages are small.

  For example, in the configuration of FIG. 14 (prototype example), the number of switches (Nch transistors) of the selectors 11A ′, 11B ′, 11D1, 11D2, 11D3, and 11D4 is 48, 24, 10, 10, 10, and 10 in total 112, respectively. It is a piece. The number of reference voltages is 45 in total, 8 in the non-linear region A, 8 in the non-linear region C, and 29 in the linear region B.

  In the present embodiment, as in FIG. 14, the number of switches (Nch transistors) of the pre-stage circuit 40A + selector 11A and the pre-stage circuit 40B + selector 11B is a total of 100, 62 and 38, respectively. From FIG. 1, FIG. 3, and FIG. 4, the total number of reference voltages is 40. The difference in the number of switches of the decoder becomes more prominent as the number of bits of the input digital signal increases, and an increase in the size of the decoder circuit can be suppressed and a reduction effect can be expected.

  FIG. 6 is a diagram showing an example of a main configuration of a data driver of a display device to which the present invention is applied. Referring to FIG. 6, this data driver includes a reference voltage generation circuit 804, a decoder circuit group 805, an interpolation circuit group 806, a latch address selector 801, a latch group 802, and a level shifter group 803. Composed. The reference voltage generation circuit 804 generates each reference voltage of the reference voltage aggregate 20 (20A, 20B, 20C, 20D) in FIG. Although not particularly limited, the reference voltage generation circuit 804 receives a buffer or the like (voltage follower or the like) from each connection point (tap) of a resistor group (ladder resistor) connected between the first and second reference voltages (not shown). Is taken out through. Each decoder circuit of the decoder circuit group 805 includes the decoder 10 shown in FIG. Although the internal configuration of the interpolating circuit group 806 is not illustrated, the interpolating circuit group 806 includes a plurality of amplifier circuits (interpolating circuits) 30 illustrated in FIG. 1 corresponding to the number of outputs. The decoder circuit of the decoder circuit group 805 and the amplifier circuit (interpolation circuit) corresponding to the decoder circuit in the interpolation circuit group 806 constitute a digital-analog conversion circuit that inputs a digital signal and outputs an analog signal voltage.

  The latch address selector 801 determines the data latch timing based on the clock signal CLK. The latch group 802 latches the video digital data based on the timing determined by the latch address selector 801, and outputs the digital data to the decoder circuit group 805 via the level shifter group 803 according to the STB signal (strobe signal). To do. For each output, the decoder circuit group 805 selectively outputs two voltages V (T1) and V (T2) from the reference voltage set generated by the reference voltage generation circuit 804 in accordance with the input digital data. .

  The interpolating circuit group 806 includes a plurality of the amplifying circuits 30 shown in FIG. 1, and each amplifying circuit 30 outputs a voltage obtained by interpolating two voltages V (T1) and V (T2) one-on-one. The output terminal group of the interpolation circuit group 806 is connected to the data line of the display device. The latch address selector 801 and the latch group 802 are logic circuits, and are generally configured with a low voltage (for example, 0 V to 3.3 V) and supplied with a corresponding power supply voltage. The level shifter group 803, the decoder circuit group 805, and the interpolation circuit group 806 are generally configured with a high voltage (for example, 0V to 18V) necessary for driving the display element, and are supplied with corresponding power supply voltages.

  Realizes a data driver and display device that can reduce the decoder area by reducing the number of transistor switches that make up the decoder circuit in a 1: 1 interpolation type digital-to-analog converter circuit corresponding to the non-linear region. It is possible.

Note that in the example shown in FIG.
Vout = (V (T1) + V (T2)) / 2
As a gradation voltage that is amplified with a gain α in the amplifier circuit 30 or in another amplifier circuit subsequent to the amplifier circuit 30 and output to the data line (display element),
Vout = α × {(V (T1) + V (T2)) / 2}
Of course, it is also possible.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) can be combined or selected within the scope of the claims of the present invention. . That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

10, 10 ′, 10 ″ decoder circuit 11A, 11A ′, 11B, 11B ′, 11D1, 11D2, 11D3, 11D4, 12 selector 20A, 20B, 21A, 21B, 21D1, 21D2, 21D3, 21D4 Reference voltage group 30 Amplifier circuit 40A, 40B Pre-stage circuit

Claims (9)

Input / output characteristics between the input digital signal and the gradation voltage output in response to the input digital signal are adjacent to the first to third gradation voltages adjacent to each other on the nonlinear characteristic curve.
First and third reference voltages corresponding to the first and third gradation voltages, respectively;
As a reference voltage corresponding to the second gradation voltage between the first and third gradation voltages, the second reference voltage between the first and third reference voltages is thinned out, A third correction reference voltage corresponding to a correction gradation voltage determined by an external component of the first gradation voltage and the second gradation voltage, instead of the subtracted second reference voltage;
A decoder circuit that selects a reference voltage from a plurality of reference voltages according to the input digital signal and outputs it to two outputs, according to the input digital signal,
In outputting the second gradation voltage, the first gradation voltage and a third correction reference voltage are selected and output to the two outputs,
In outputting the first gray scale voltage and the third gray scale voltage, respectively, the first reference voltage is redundantly selected, and the third reference voltage is redundantly selected and output to the two outputs. A decoder circuit to
An amplifier circuit which receives and interpolates and outputs a reference voltage of the two outputs selected by the decoder circuit;
A data driver device comprising: A first reference voltage group including a plurality of different reference voltages;
A second reference voltage group including a plurality of reference voltages different from and different from the reference voltage of the first reference voltage group;
With
The decoder circuit includes:
A first selector that selects one reference voltage from the first reference voltage group based on a first bit group of the input digital signal in a tournament manner;
A second selector that selects one reference voltage from the second reference voltage group based on the first bit group of the input digital signal in a tournament manner;
Based on the second bit group of the input digital signal, either of the two reference voltages selected by the first and second selectors is output, or one of the two reference voltages is overlapped with two. A third selector for selecting and outputting one;
With
The amplifier circuit outputs an output voltage obtained by interpolating the two reference voltages output from the third selector;
The first gradation voltage on a characteristic curve in which the input / output characteristics relating to the input digital signal and the output gradation voltage are nonlinear; the second gradation voltage adjacent to the first gradation voltage; For the third gradation voltage adjacent to the second gradation voltage,
The first and third reference voltages corresponding to the first and third gradation voltages are provided in the first or second reference voltage group, respectively, and the third corrected reference voltage is provided in the first and second reference voltages. 3 on the reference voltage group side to which the reference voltage 3 belongs,
In response to the input digital signal corresponding to the second grayscale voltage, the first and second selectors and the third selector cause the first reference voltage and the third corrected reference voltage to be changed. And the second gradation voltage obtained by interpolating the first reference voltage and the third correction reference voltage is output from the amplifier circuit,
The tournament scheme of the decoder circuit, wherein the first and second selectors and the third selector are commonly used in a region where the input / output characteristics are linear and a region where the input / output characteristics are nonlinear. The data driver device according to 1.   In accordance with a predetermined bit of the input digital signal, one of the third correction reference voltage and the third reference voltage is selected before the at least one of the first and second selectors. The data driver device according to claim 2, further comprising a switch circuit that supplies an input of the one selector. The third selector, according to four combinations of lower 2 bits forming the second bit group of the input digital signal,
In the first combination, two reference voltages selected by the first selector are duplicated,
In the second combination, two reference voltages respectively selected by the first and second selectors,
In the third combination, two reference voltages selected by the second selector are duplicated,
4. The data driver device according to claim 3, wherein in the fourth combination, the two reference voltages respectively selected by the first and second selectors are selectively output. The fifth gradation voltage, the fourth gradation voltage, and the fifth reference voltage corresponding to the third reference voltage, the input / output characteristics of which are adjacent on the nonlinear characteristic curve. For the gradation voltage of
A fifth correction reference voltage corresponding to a correction voltage obtained by extrapolating the third gradation voltage and the fourth gradation voltage;
The first reference voltage, the fifth corrected reference voltage, and the fifth reference voltage are supplied to the first selector;
The third correction reference voltage and the third reference voltage are supplied to the second selector via the switch circuit;
In response to a first value of the input digital signal corresponding to the first gradation voltage,
The first selector selects the first reference voltage,
The second selector selects the third correction reference voltage selected by the switch circuit,
The first selector voltage is output in duplicate from the third selector, and the first gray scale voltage obtained by interpolating the two first reference voltages is output from the amplifier circuit,
In response to a second value of the input digital signal corresponding to the second gradation voltage,
The first selector selects the first reference voltage,
The second selector selects the third correction reference voltage selected by the switch circuit,
The first reference voltage and the third corrected reference voltage are output from the third selector, and the second reference signal in which the first reference voltage and the third corrected reference voltage are interpolated from the amplifier circuit. Is output,
In response to a third value of the input digital signal corresponding to the third gradation voltage,
The first selector selects the fifth correction reference voltage,
The second selector selects the third reference voltage selected by the switch circuit,
Two third reference voltages are output in duplicate from the third selector, and the third grayscale voltage obtained by interpolating the two third reference voltages is output from the amplifier circuit.
In response to a fourth value of the input digital signal corresponding to the fourth gradation voltage,
The first selector selects the fifth correction reference voltage,
The second selector selects the third reference voltage selected by the switch circuit,
The fifth correction reference voltage and the third reference voltage are output from the third selector,
5. The data driver device according to claim 4, wherein the fourth gradation voltage obtained by interpolating the fifth correction reference voltage and the third reference voltage is output from the amplifier circuit. The amplifier circuit outputs a grayscale voltage having an intermediate potential obtained by interpolating the two reference voltages output from the third selector at an internal ratio of 1: 1,
The first and third gradation voltages are equal to the voltage levels of the first and third reference voltages, respectively.
3. The data driver device according to claim 1, wherein the third correction reference voltage is obtained by dividing the first gradation voltage and the second gradation voltage by 2: 1. The amplifier circuit outputs a grayscale voltage having an intermediate potential obtained by interpolating the two reference voltages output from the third selector at an internal ratio of 1: 1,
The first, third, and fifth gradation voltages are equal to the voltage levels of the first, third, and fifth reference voltages, respectively.
The third correction reference voltage is obtained by dividing the first gradation voltage and the second gradation voltage by 2: 1.
6. The data driver device according to claim 5, wherein the fifth correction reference voltage is obtained by dividing the third gradation voltage and the fourth gradation voltage by 2: 1.   In the region where the input / output characteristics are linear, the reference voltage adjacent to the gradation voltage corresponding to the thinned reference voltage is selected by the first and second selectors and the third selector and is supplied to the amplifier circuit. The data driver device according to claim 2, wherein the grayscale voltage corresponding to the thinned reference voltage is supplied and output. A display panel including a unit pixel including a pixel switch and a display element at an intersection of the data line and the scanning line, and a signal of the data line written to the display element via the pixel switch turned on by the scanning line;
A data driver device for driving the data line;
A display device comprising the driver according to claim 1, wherein the data driver device comprises:

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