JP7108350B1 - Narrow frame display module and data output device - Google Patents

Abstract

A low-cost narrow frame display is provided. A COF module (10) includes a driver chip (20) having a plurality of connection terminals (21), and a plurality of driver chips (10) having one end connected to the connection terminal (21) of the driver chip (20) and the other end connected to an output terminal (13) to a display panel. signal lines 31 and 32 are provided. The driver chip 20 has connection terminals 21 arranged in a plurality of rows. The plurality of connection terminals 21 belonging to a certain row include those connected so that the first source line group 31 is led out in the direction toward the output terminal 13 . Either the signal line is not connected to the connection terminal 21 belonging to the row next to the output terminal 13 after a certain row, or the second source line group 32 is oriented in a direction different from that of the first source line group 31 . Including those connected so as to be drawn out. [Selection drawing] Fig. 10

Description

The present invention relates to a narrow frame display module and a data output device therefor. Specifically, the present invention relates to a COF (Chip On Film) wiring technology for realizing a narrow frame of a display panel.

In the mobile device market, such as notebook computers and tablet computers, there is a constant demand for lower power consumption and lower costs. On the other hand, as the resolution of the panel and the image quality of the display improve, the amount of data processed and the operating frequency continue to increase, and the reduction of power consumption and the reduction of cost have become major issues that contradict each other. Circuits that input drawing data signals to the display panel of laptops and tablet PCs are CPUs (Central Processing Units) and GPUs (Graphics Processing Units) that are in charge of drawing data calculations, various arithmetic processing, and graphics processing. A processor, a timing controller (TCON) that controls the timing of the display panel and performs image processing with drawing data sent from the processor as input, and drawing data from the timing controller as input and drawing according to the specifications of the display panel. It is composed of a driver chip such as a source driver (SD) for analog output of data.

In mobile devices such as notebook computers and tablet computers, the timing controller and source driver are often separated. For example, the FHD (Full High Definition: 1920×1080 pixels) display panel shown in FIG. 1 often requires one timing controller and four source drivers. Also, in the case of a 4K2K panel (a panel with a resolution close to 4000×2000 pixels), one timing controller and eight source drivers are often required. Furthermore, as shown in Fig. 1, FPCs (Flexible Printed Cables) connecting the timing controller and the source drivers are required for the number of source drivers. was a factor. Furthermore, an interface must be provided between the timing controller and the source driver, which consumes power. Against this background, it has been difficult to reduce costs and power consumption with the circuit configuration shown in FIG.

Therefore, in order to reduce the number of parts and power consumption, a so-called system driver (TCON+SD) in which the timing controller and the source driver are integrated into one chip as shown in FIGS. 2 and 3 can also be considered. FIG. 2 shows a configuration in which two system drivers are provided, and FIG. 3 shows a configuration in which one system driver is integrated. By using a system driver, the number of parts can be reduced and the cost can be reduced. Furthermore, since there is no interface between the timing controller and the source driver, power consumption can be reduced. In particular, from the viewpoint of reducing the number of parts and power consumption, it is preferable to use only one system driver as shown in FIG. However, the system driver is mounted on the glass of the liquid crystal panel like the conventional source driver. Rendering data is directly input from the processor (CPU/GPU) to the system driver via the eDP interface or the MIPI interface.

Here, the liquid crystal panel is composed of source lines and gate lines. In the case of an FHD panel, 1920×3 (RGB) source lines are required and 1080 gate lines are required. The source lines are lines (data lines) for analog output of drawing data from the source driver, and are wired in parallel with each other at predetermined intervals. The gate lines are control lines that drive the drawing data of the source lines while temporally shifting one gate line at a time. A display picture element (pixel) is provided at each intersection of the gate line and the source line. At present, a so-called COG (Chip On the Glass) method, in which source drivers and system drivers are mounted on liquid crystal glass, is the mainstream.

FIG. 4 shows a model of the source line of the liquid crystal panel (display panel). A liquid crystal panel is divided into a fan out area where a source driver is mounted and an active area where liquid crystal pixels are arranged in an array. The area from the active area to the edge portion of the glass module including the fan-out area is called the frame area of the liquid crystal panel, and the narrower the frame area, the higher the commercial value.

As shown in FIG. 4, when four source drivers are provided, the number of wirings of source lines on the COG required to be driven by one source driver can be reduced. For example, in the case of an FHD panel, there are 1920×3 (RGB)=5860 source lines, but if four source drivers are provided, each one drives 1440 lines. For example, Patent Document 1 shows a configuration in which four source drivers are provided. On the other hand, as shown in FIGS. 2, 3, and 5, when the timing controller (TCON) and the source driver (SD) are integrated, or when the integration of the source driver advances, the number of parts becomes one. Alternatively, if there are two of them, the number of source line wirings on the COG that must be driven by one source driver increases, causing a problem that the height of the frame area increases.

Here, the configuration of the frame area of the display panel (liquid crystal panel) will be described with reference to FIG. In the center of the frame area, there is a driver chip in which a timing controller and a source driver are integrated, and source lines are wired from the upper side of this driver chip toward the active area. Further, the wiring of the source lines is generally arranged at a constant angle θ from the leftmost or rightmost line to the central line of the panel. In this specification, the area between the connection portion of the driver chip and the source line and the active area is defined as a "fan-out area", and in the figure, the height of the fan _- out area is indicated by H1. there is In addition, the picture frame area includes an area located farther from the active area than the fan-out area, and this area is defined as a "fan-in area" in the present specification. In this fan-in area, gate signal drive lines extending horizontally from the lower side of the chip are wired in the horizontal direction of the panel, and test pads are arranged in the left and right portions of the frame area. In the fan-in area, test lines for source lines and their test pads, gate drive control signal lines and their test pads, and the like are arranged. The height of this fan _- in region is indicated by H2 in the figure. The value of H ₁ +H ₂ is the height of the entire frame area. Therefore, the applicant of the present application has proposed a technique for reducing the height of the fan _- out region indicated by H1 by devising the wiring of signal lines such as source lines in the frame region of the display panel. (Patent Document 2).

JP 2005-031332 A JP 2018-072783 A

As described above, as shown in FIGS. 2, 3, and 5, when the timing controller (TCON) and the source driver (SD) are integrated, or when the integration of the source driver advances, the number of parts becomes one. If the number is 1 or 2, the number of source line wirings on the COG that must be driven by one source driver increases, and the height of the frame area increases. Especially in such a case, it becomes difficult to reduce the height of the fan _- out area indicated by H1 in the frame area.

Here, referring to FIG. 7, _a method of obtaining the height H1 of the frame region will be described by taking the wiring structure of a conventional liquid crystal panel as an example. First, P _pix is the wiring pitch of the source lines in the active region, P _w is the wiring pitch of the source lines in the fan-out region, P bp is the pitch of the connecting portions (output pads) of the source lines on the driver chip, and P _bp is the pitch of the source lines on the driver chip. _{Let Dx} be the distance from the extreme connection point to the extreme source line of the display panel. Here, since P _pix >P _bp , a part of the source line connecting the driver chip and the active region needs to be tilted at a certain angle. The angle θ between the endmost source line wiring located in the fan-out region and the orthogonal direction axis orthogonal to the extending direction of the source lines in the active region is θ=sin−1(P _w /P _pix ). is represented by Then, the height H ₁ of the fan-out area in the area frame is H ₁ =D _x ·tan θ=D _x ·tan(sin−1(P _w /P _pix )).

Thus, it can be seen that the numerical value of _H1 depends _{on Dx} , and the larger the value of _Dx , the larger the numerical value of H1. Also, it can be seen that the value of _H1 increases as θ increases. Furthermore, the larger _Pw , the larger the numerical value of _H1 . Since P _pix is a value determined by the size and resolution of the display panel, it can be said to be a fixed value that cannot be changed when wiring the source lines. _If P _pix is constant, the larger _Pw is, the larger θ will be, and accordingly H1 will also be larger. Thus, θ is a value determined by P _w and P _pix .

Conventionally, when a large number of source drivers are mounted on _one panel, the value of _Dx can be reduced, so the value of H1 can also be reduced. However, if the source driver and _TCON are integrated and integrated on a single chip, there will be only _one source driver mounted on the panel. There has occurred.

COF (Chip On Film) mounting is known as another technique for reducing the frame size. The effect of reducing the frame size by COF compared to COG is explained in FIG.

As mentioned above, for the COG implementation, the value of H ₁ is determined by H ₁ =D _x ·tan θ. Since _Dx is determined by the size from both ends of the panel to the horizontal direction of the chip size, the smaller the number of chips _mounted on the panel, the larger the value of _Dx and the larger the value of H1. Also, the value of H2 is determined by the _total size of the vertical size of the chip and the wiring area drawn out to the bottom of the panel. For example, if the horizontal size of a 14-inch display panel is 309 mm and the chip size is 30 mm, the value of Dx is 309 mm/2-30 mm/2 ₌ 139.5 mm. If the wiring pitch Pw on the panel is ₄ mm, H1 becomes 5.2 mm. The angle θ becomes 2.1 degrees. Assuming that the vertical size of the chip is 1 mm and the wiring area under the panel is 1 mm, H2 is ₂ mm. Therefore, the _total panel frame size of H1 and H2 is 7.2 _mm .

On the other hand, in the case of COF packaging, the horizontal size of the film can be increased. The lateral size of commonly distributed COF films is about 60 mm, and the value of Dx is 309 mm/2-60 mm/2 ₌ 124.5 mm. Assuming that the number of inches of the panel, the wiring pitch, and θ are the same as in the case of COG mounting, the value of H ₁ is determined by H ₁ =D _x ·tan θ, so it can be shortened to 4.6 mm. In addition, in the case of COF mounting, the vertical size of the chip in H2 required in COG mounting is not required, so H2 in COF can be _{1 mm} . Therefore, the _total panel frame size of H1 and H2 can be reduced to 5.6 _mm . In addition, since the COF film is a thin film and can be folded to the rear surface of the display, the longitudinal size of the COF film does not affect the frame size of the panel.

Using the COF mounting technique in this way has the effect of reducing the frame size. However, when mounting a chip having a large number of source driver output channels on a COF, a film having a two-layer wiring structure has been necessary due to the restriction of the wiring pitch of the COF film. As a result, the manufacturing cost is much higher than that of the one-layer COF, and it has not been widely used.

Conventional COF mounting using a film having a two-layer wiring structure will be described with reference to FIG. Assuming that the number of channels of the COG-mounted multi-channel source driver is 2880, the COF wiring pitch of the portion drawn from the chip (enlarged view A) must be at least 10 μm. Assuming that the lateral size of a commonly distributed COF film is 60 mm, the minimum wiring pitch at the end of the COF film (enlarged view B) is 60 mm/2880=20.8 μm. Most of the currently distributed COFs have a one-layer wiring structure, and the minimum pitch of the one-layer wiring is limited to about 20 μm. Therefore, the COG-mounted multi-channel source driver cannot be mounted on a COF having a one-layer wiring structure. There is also a COF with a two-layer wiring structure on the market, and if two-layer wiring is used as shown in FIG. 8, it becomes possible to mount a COG-mounted multi-channel source driver designed at a pitch of 10 μm. However, since the COF with a two-layer wiring structure is significantly more expensive than the COF with a one-layer wiring structure, it has hardly been used.

Therefore, the present invention mainly provides a technology for mounting a chip having a large number of source driver output channels used in COG mounting on a COF with a single-layer wiring structure, thereby realizing an inexpensive narrow-frame display. purpose.

The inventors of the present invention, as a result of intensive studies on means for solving the above problems, have adopted a driver chip in which a plurality of connection terminals are arranged in a plurality of rows, and have connected terminals belonging to one row and the next row. It is possible to mount a driver chip having a large number of source driver output channels on a COF having a one-layer wiring structure by making the signal line lead-out method different between the connection terminals belonging to the . Based on the above findings, the inventors of the present invention conceived that the problems of the prior art can be solved, and completed the present invention. The configuration of the present invention will be specifically described below.

A first aspect of the present invention relates to a data output device (10) for outputting drawing data to a display panel such as a liquid crystal panel. This data output device (10) is preferably a COF (Chip On Film) mounted module. A data output device (10) according to the present invention comprises a driver chip (20) and a plurality of signal lines (31, 32, 41) connected thereto. A driver chip (20) has a plurality of connection terminals (21, 22). The driver chip (20) may be a source driver, a gate driver, or a so-called system driver in which a source driver and a timing controller are integrated. In the present invention, it is preferable that only one driver chip (20) is arranged on the film (11). may have been In addition, the plurality of signal lines (31, 32, 41) are connected at one end to connection terminals (21, 22) of the driver chip (20) and at the other end for outputting signals to the display panel. It is connected to terminal (13). Thus, the signal lines (31, 32, 41) are wired to connect the connection terminals (21, 22) and the output terminal (13) on the film (11). The signal lines (31, 32, 41) may be source lines connected to source drivers or gate lines connected to gate drivers.

Here, in the driver chip (20), connection terminals (21, 22) are arranged in a plurality of rows. That is, in the drawings of the present application, the direction in which the plurality of output terminals (13) to the display panel are arranged is indicated by the "x-axis", and the direction perpendicular thereto is indicated by the "y-axis" (see FIG. 10, for example). In this case, the rows of the connection terminals (21, 22) extend along the x-axis direction and are arranged in multiple stages in the y-axis direction. In this case, the plurality of connection terminals (21) belonging to a certain row includes those connected so that the signal line (31) is led out in the direction toward the output terminal (13). It should be noted that the signal line (31) does not need to be drawn out from all of the plurality of connection terminals (21) belonging to a certain row, and the signal line (31) may be drawn from some of the connection terminals (21) toward the output terminal (13). 31) may be pulled out. On the other hand, the connection terminal (21) belonging to the row next to the output terminal (13) after a certain row is not connected to the signal line or is connected to the row with the signal line (32). The signal line (31) connected to the terminal (21) includes those connected so as to be led out in a direction different from that of the signal line (31). In addition, the signal line (32) does not need to be drawn out from all of the plurality of connection terminals (21), and the signal line (32) is drawn out from some of the connection terminals (21) in the different directions described above. may The direction in which the signal line is "pulled out" from the connection terminal here means the direction in which the portion of the signal line closest to the connection terminal is wired, and it means the wiring direction of the entire signal line. is not. Further, the “direction different” from the signal line (31) connected to the connection terminal (21) belonging to a certain row is, for example, the direction away from the output terminal (13) or the direction in which the output terminals (13) are arranged. Includes parallel orientation.

As in the above configuration, with respect to the connection terminals (21) provided in a plurality of rows on the driver chip (20), the connection terminals (21) in one row and the connection terminals (21) in the next row, By changing how the signal lines (31, 32, 41) are led out, the space on the film where the driver chip (20) and the signal lines (31, 32, 41) are arranged can be effectively utilized. As a result, it is possible to realize a narrow frame of the display module at a low cost.

In the data output device (10) according to the present invention, it is preferable that the connection terminals (21) of the driver chip (20) are arranged in four or more rows. In this case, if the aforementioned "certain row" is the first row, the signal lines (31) are led out in the direction toward the output terminals (13) to the plurality of connection terminals (21) belonging to the odd rows. It is preferably included that is connected so as to be Further, the plurality of connection terminals (21) belonging to the even rows are not connected to signal lines, or the signal lines (32) are connected to the connection terminals (21) belonging to the odd rows. ) are preferably included so as to be pulled out in a different direction. In this way, the connection terminals (21) are arranged in four or more rows on the driver chip (20), and the signal lines (31, 32) are led out differently depending on the connection terminals (21) in the odd-numbered rows and the even-numbered rows. This allows for more efficient use of space on the film.

In the data output device (10) according to the present invention, output terminals ( 13) may be pulled out from the connection terminal (21) in the direction away from the output terminal (13) and then wired in the direction toward the output terminal (13). As a result, the space behind the driver chip (20) (opposite to the output terminals) can be effectively utilized.

In the data output device (10) according to the present invention, output terminals ( 13) may be pulled out from the connection terminal (21) in a direction parallel to the arrangement direction (x-axis direction) of 13) and then wired in a direction toward the output terminal (13). Thereby, the space on the side of the driver chip (20) can be effectively utilized.

In the data output device (10) according to the present invention, a virtual line parallel to the direction (y-axis direction) from the plurality of connection terminals (21) of the driver chip (20) to the output terminal (13) to the display panel is drawn. In this case, each connection terminal (21) is preferably arranged so that the imaginary line does not overlap other connection terminals (21). In other words, in each row, the connection terminals (21) are offset so as to be staggered. This makes it easier to pull out the signal lines (31, 32, 41) from each connection terminal (21) so that all the signal lines (31, 32, 41) do not interfere with each other.

A second aspect of the invention relates to a display module. A display module according to the present invention comprises the data output device (10) according to the first aspect described above, and a display panel to which signal lines (31, 32, 41) are connected via output terminals (13).

According to the present invention, a narrow frame display can be realized at low cost by providing a technology for mounting a chip having a large number of source driver output channels used in COG mounting on a COF with a single-layer wiring structure. In addition, since a chip designed for COG mounting can be COF mounted without changing the design, development costs for semiconductor manufacturers can be reduced, and panel manufacturers and PC manufacturers can reduce chip re-evaluation time and costs. be able to.

Conventionally, when the number of drivers is reduced, it has been difficult to narrow the frame of the display panel. For example, in a 14-inch FHD panel, the frame size can be reduced from 7.2 mm in the conventional technology to 5.6 mm, and the frame size can be reduced by about 20 to 30%.

[Prior Art] FIG. 1 is a block diagram showing the overall configuration of a display module in which a timing controller and a source driver are separated. [Prior Art] FIG. 2 is a block diagram showing the overall configuration of a display module in which a timing controller and a source driver are integrated. [Prior Art] FIG. 3 is a block diagram showing the overall configuration of a display module in which a timing controller and a source driver are integrated. [Prior Art] FIG. 4 is a diagram showing an active area and a frame area of a display panel in a display module in which a timing controller and a source driver are separated. [Prior Art] FIG. 5 is a diagram showing an active area and a frame area of a display panel in a display module in which a timing controller and a source driver are integrated. [Prior Art] FIG. 6 is a diagram showing a conventional wiring system for source lines of a display panel. [Prior Art] FIG. 7 is an enlarged view of the left half from the center of the display panel shown in FIG. . [Prior Art] FIG. 8 is a diagram showing a configuration of COF mounting of a driver chip having multi-channel source driver outputs. [Prior Art] FIG. 9 is a diagram showing a configuration of COF mounting using a film having a two-layer wiring structure. [Present Invention] FIG. 10 is a diagram showing a first embodiment of the present invention. [Present Invention] FIG. 11 is a diagram showing a second embodiment of the present invention. [Present Invention] FIG. 12 is a diagram showing a third embodiment of the present invention.

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated using drawing. The present invention is not limited to the embodiments described below, and includes appropriate modifications within the scope obvious to those skilled in the art from the following embodiments. The present invention can appropriately combine each embodiment described below, or can use each embodiment alone.

[First embodiment]
FIG. 10 shows a first embodiment of the invention. This embodiment relates to a COF module 10 for realizing a narrow frame liquid crystal panel by COF technology. The COF module 10 can be applied to, for example, a notebook computer or a tablet computer, and contributes to narrowing the frame of the liquid crystal panel.

As shown in FIG. 10, the COF module 10 basically comprises a film 11, a driver chip 20 and a plurality of signal lines 31, 32, 41 and 51. As shown in FIG. The signal lines include source lines 31 and 32, a gate signal drive line 41, and an input line 51 for video signals and power. In this COF module 10, the driver chip 20 and the plurality of signal lines 31, 32, 41, 51 are mounted on the film 11 functioning as a wiring circuit board. The film 11 is not particularly limited, and any known material can be used as appropriate.

The driver chip 20 is a combination of a timing controller (TCON) and a source driver (SD), and controls the function of outputting drawing data to the source lines of the display panel and the timing of outputting the drawing data. It has the function of In the example shown in FIG. 8, the driver chip 20 functions as both a timing controller and a source driver. there is However, the driver chip 20 may simply have the function of the source driver and the timing controller may exist separately. If the driver chip 20 functions only as a source driver, the gate signal drive line 41 may be connected to a separately provided timing controller.

A timing controller (part of the functions of the driver chip 20) receives drawing data sent from a processor such as a CPU or GPU, and performs timing control and image processing of the display panel. A source driver (part of the function of the driver chip 20) is a circuit for driving the source lines of the display panel. The source driver inputs the drawing data from the timing controller and analog-outputs the drawing data according to the specifications of the display panel. A source driver is connected to a plurality of source lines and applies a drive voltage (gradation display voltage) to each source line. A display module can be equipped with a plurality of source drivers for one display panel, but from the viewpoint of reducing the number of parts and power consumption, it is possible to equip only one source driver for one display panel. preferred. Also, although illustration is omitted, the display module may include a gate driver for driving the gate lines of the display panel in addition to the source driver. A gate driver sequentially applies a scanning signal to each gate line to turn on a TFT (Thin Film Transistor). When an operation signal is applied to the gate line by the gate driver to turn on the TFT, and a drive voltage is applied to the source line from the source driver, charges are accumulated in the display element located at the intersection of the TFTs. As a result, the light transmittance of the display element changes according to the driving voltage applied to the source line, and image display is performed through the display element.

A display panel is generally composed of source lines, gate lines, and display pixels. A plurality of source lines are provided parallel to each other at predetermined intervals on a panel substrate made of glass or the like. A plurality of gate lines are provided parallel to each other at predetermined intervals along a direction perpendicular to the source lines on the same panel substrate. A display pixel is provided at each intersection of the source line and the gate line. A TFT as a switching element is connected to each display pixel. For example, an FHD liquid crystal panel requires 1920×3 (RGB) source lines and 1080 gate lines.

As shown in FIG. 10, a plurality of input terminals 12 and a plurality of output terminals 13 are provided on the film 11 . Assuming that the film 11 has a rectangular shape, a plurality of input terminals 12 are provided along the lower side of the film 11 along the x-axis direction, and a plurality of output terminals 13 are provided along the upper side of the film 11 along the x-axis direction. are arranged side by side. The upper side of the film 11 referred to here is the side on the display panel side, and the lower side of the film 11 is the side opposite to the display panel. The input terminal 12 is connected to an input line 51 for receiving a video signal from a processor and an input line 51 for receiving power from a power supply. Output Terminal 13 The output terminal 13 is for outputting the video signal processed by the driver chip 20 to the display panel, and the output terminal 13 is connected to the gate line and the source line of the display panel.

The driver chip 20 also has a plurality of connection terminals 21 , 22 and 23 for electrically connecting to the input terminal 12 and the output terminal 13 on the film 11 . The multiple connection terminals include multiple source connection terminals 21 , multiple gate connection terminals 22 , and multiple input connection terminals 23 . Each source connection terminal 21 is electrically connected to the output terminal 13 by source lines 31 and 32 . That is, one ends of the source lines 31 and 32 are connected to the source connection terminal 21 and the other ends of the source lines 31 and 32 are connected to the output terminal 13 . Each gate connection terminal 22 is electrically connected to the output terminal 13 by a gate signal drive line 41 . That is, one end of the gate signal drive line 41 is connected to the gate connection terminal 22 and the other end of the gate signal drive line 41 is connected to the output terminal 13 . Each input connection terminal 23 is connected to the output terminal 13 by an input signal line. Assuming that the driver chip 20 has a rectangular shape, the gate connection terminals 22 and the input connection terminals 23 are arranged side by side along the x-axis direction on the lower side of the film 11 . On the other hand, the source connection terminals 21 are arranged side by side in a plurality of rows in a plane area on the driver chip 20 .

The arrangement of the source connection terminals 21 will be specifically described. As shown in FIG. 10, the source connection terminals 21 are arranged in multiple rows. In the example shown in FIG. 10, the source connection terminals 21 are arranged in four rows. In FIG. 10, the first row of the source connection terminals 21 is white, the second row is black, the third row is white, and the fourth row is black, in order to make the concept of the rows of the source connection terminals 21 easier to understand. , the odd rows are shown in white and the even rows in black. The first row of the source connection terminals 21 is the row closest to the output terminal 13, and the second, third, and fourth rows are connected to the output terminal 13 in this order. distance is increasing. The rows of the source connection terminals 21 extend along the x-axis direction in FIG. 10, and each row can be said to form a step in the y-axis direction.

Also, the source connection terminals 21 belonging to each row are offset so as to be alternated. That is, when a virtual line parallel to the y-axis is drawn so as to pass through the center of each source connection terminal 21 , it is preferable that each virtual line does not overlap another source connection terminal 21 . In other words, the interval (pitch) in the x-axis direction between the source connection terminals 21 belonging to a certain row is preferably N times or more the width of the source connection terminals 21 (N is the number of rows of the source connection terminals 21). This makes it easier to pull out the source lines 31 and 32 from each source connection terminal 21 .

Here, in the present embodiment, those connected to the plurality of source connection terminals 21 belonging to the first and third rows are referred to as a first source line group 31 . The first source line group 31 is drawn out from the source connection terminal 21 toward the output terminal 13 and connected to the output terminal 13 as it is. In particular, the first source line group 31 drawn from the source connection terminals 21 belonging to the first row all extend straight toward the output terminals 13 . Note that the first source line group 31 drawn from the source connection terminals 21 belonging to the third row includes those wired so as to bypass the source connection terminals 21 of the second row. However, it also includes those extending in a straight line toward the output terminal 13 .

On the other hand, in the present embodiment, those connected to the plurality of source connection terminals 21 belonging to the second and fourth rows are referred to as a second source line group 32 . A second source line group 32 is pulled out from the source connection terminals 21 belonging to the second and fourth rows in a direction away from the output terminal 13 . The second source line group 32 is pulled out from the source connection terminal 21 in the direction away from the output terminal 13 in this way, advances parallel to the y-axis, and then advances outward in the left-right direction (x-axis direction). , and furthermore, wiring is made so as to proceed in parallel with the y-axis direction toward the output terminal 13 thereafter. At this time, the second source line group 32 is connected to the output terminal 13 so as not to interfere with the other source lines 31 and 32 after proceeding at least to the left and right outside of the plurality of source connection terminals 21 in the first row. It is wired so as to advance in a straight line. Note that the second source line group 32 drawn from the source connection terminals 21 belonging to the second row includes those wired so as to bypass the source connection terminals 21 of the third row. is Thus, in the present embodiment, the lead-out directions of the source lines 31 and 32 are different between the source connection terminals 21 (white) belonging to the odd-numbered rows and the source connection terminals 21 (black) belonging to the even-numbered rows.

Further, as shown in FIG. 10, the first source line group 31 is drawn out from all of the source connection terminals 21 on the first and third rows. On the other hand, the second source line group 32 is not led out from all of the source connection terminals 21 in the second and fourth rows, and some located outside the driver chip 20 on the left and right sides. A second source line group 32 is drawn only from the source connection terminal 21 . In the illustrated example, among the source connection terminals 21 on the second and fourth rows, only four source connection terminals 21 on the left and right sides of each row (eight in each row in total) are connected to the second source line group 32. pulled out. Thus, it is not always necessary to connect the source lines 31 and 32 to all the source connection terminals 21 . Regarding the second and fourth rows, the number of source connection terminals 21 connecting the second source line group 32 is not limited to four on the left and right, and may be two on the left and right, for example. Alternatively, the number may be five or more on the left and right. The number can be adjusted as appropriate.

As shown in FIG. 10, on the film 11, by providing a first source line group 31 extending in a direction toward the output terminal 13 and a second source line group 32 extending in a direction away from the output terminal 13, Even if the pitch of the source connection terminals 21 of the driver chip 20 is, for example, 10 μm, the wiring pitch on the film 11 can be doubled to 20 μm. The second source line group 32 can be connected to the source lines of the display panel panel by wiring in such a manner as to extend downward, then laterally, and then upward. Next, in the first source line group 31 , there are only wirings drawn upward on the film 11 . When the pitch of the source connection terminals 21 of the driver chip 20 is, for example, 10 μm, the wiring pitch on the film 11 is doubled to 20 μm, for example, by skipping one stage and leading upward. In the lower part of the driver chip 20, there are wirings 51 such as video input lines, power input lines, etc., which are input to the driver chip 20. Therefore, the first and second source line groups 31 and 32 cannot be led out. Can not.

For example, if the total number of channels of the output terminals 13 of the COG-mounted multi-channel driver chip 20 is 2880, the second source line group 32 is for example 800 channels on the left and right sides, and the first source line group 31 is on the center. A total of 2,240 channels of source lines can be drawn out, for example, 640 channels of the unit. For example, in an FHD panel, an LTPS panel or an OXIDE panel having a multiplexer configuration needs to draw out 1920 channels of source lines from the driver chip 20, but in this embodiment, if 2240 channels can be drawn out, it is possible to deal with this. As a result, a chip having a large number of source driver output channels used in COG mounting can be mounted on a COF with a one-layer wiring structure, and a narrow frame display can be realized at low cost.

In addition, as shown in FIG. 10, a plurality of gate connection terminals 22 are provided on the lower side of the driver chip 20 . A gate signal drive line 41 is connected to each of the gate connection terminals 22 . The gate signal drive line 41 is pulled out from the gate connection terminal 22 in a direction away from the output terminal 13 . Further, the gate signal drive line 41 is wired so as to be drawn out from the gate connection terminal 22 in the direction away from the output terminal 13 in this way, then proceed outward to the left and right, and then proceed toward the output terminal 13 . It will be done. The gate signal driving line 41 is finally connected to the output terminal 13 (Gate Output) located outside the output terminal 13 to which the plurality of source lines 31 and 32 are connected. connected to

[Second embodiment]
Next, a COF module 10 according to a second embodiment of the invention will be described with reference to FIG. The description of the second embodiment will focus on the differences from the above-described first embodiment. In the second embodiment, the same elements as in the first embodiment are assigned the same reference numerals, and the description thereof is omitted.

The second source line group 32 described in the first embodiment is not used in the COF module 10 according to the second embodiment. Therefore, in the second embodiment, only the first source line group 31 is used to output video signals to the source lines of the display panel. That is, as shown in FIG. 11, the first source line group 31 is led out from all the source connection terminals 21 belonging to the first and third rows, while the second and fourth rows are connected to the first source line group 31. No signal line is connected to the source connection terminal 21 belonging to the eye. Other components of the second embodiment are the same as those of the first embodiment.

For example, if the number of channels of the COG-mounted multi-channel source driver is 2880, half of the 2880 channels of the first source line group 31 are drawn upward, so that a total of 1440 source lines are drawn. be able to. For example, in an FHD panel, when two COF modules 10 are mounted, a display panel having a dual-gate structure requires 2800 channels of source lines to be pulled out from the driver chip 20 . In this case, a narrow frame display can be realized by connecting two COF modules 10 according to the present embodiment to the display panel.

[Third embodiment]
Next, a COF module 10 according to a third embodiment of the invention will be described with reference to FIG. The description of the third embodiment will also focus on the differences from the above-described first embodiment.

In the third embodiment, of the source connection terminals 21 belonging to the second row and the fourth row, the second source line group 32 is led out only from the source connection terminals 21 located on the outermost left and right sides. there is The second source line group 32 extends straight from each source connection terminal 21 laterally (in the x-axis direction) and then straightly extends toward the output terminal 13 . As described above, in the third embodiment, the second source line group 32 has only portions wired laterally and upwardly on the film 11, and portions wired downward. does not have In this case, the area of the COF module 10 in the vertical direction (y-axis direction) can be reduced, and the area and cost of the COF module 10 can be reduced.

In the specification of the present application, the embodiments of the present invention have been described with reference to the drawings in order to express the content of the present invention. However, the present invention is not limited to the above embodiments, and includes modifications and improvements that are obvious to those skilled in the art based on the matters described in this specification.

10 ... COF module (data output device)
DESCRIPTION OF SYMBOLS 11... Film 12... Input terminal 13... Output terminal 20... Driver chip 21... Source connection terminal 22... Gate connection terminal 23... Input connection terminal 31... First source line group (signal line)
32 Second source line group (signal line)
41... Gate signal drive line (signal line)
51 input line

Claims (5)

a driver chip having a plurality of connection terminals;
a plurality of signal lines, one end of which is connected to the connection terminal of the driver chip and the other end of which is connected to an output terminal to a display panel;
A data output device,
The driver chip has the connection terminal3linethat's allare arranged side by side withIn the case of the first, second, and third rows in order of proximity to the output terminal,
first linesecond and third linethe plurality of connection terminals belonging to include those connected so that the signal line is drawn out in a direction toward the output terminal;
second lineeyebelong topluralThe signal line is connected to the connection terminalfirstlineeyeincludes those connected so as to be led out in a different direction from the signal lines connected to the connection terminals belonging to and
The signal lines drawn from the connection terminals belonging to the second row include those passing between the connection terminals belonging to the third row, and the signal lines drawn from the connection terminals belonging to the third row The signal lines include those passing between the connection terminals belonging to the first row and the second row.
Data output device. The driver chip has four or more rows of connection terminals.in line withis placed in the If the first, second, third, and fourth rows are arranged in order of proximity to the output terminal,
The signal lines drawn from the connection terminals belonging to the second row include those passing between the connection terminals belonging to the third and fourth rows.
The data output device according to claim 1. second lineeyethe plurality of signal lines connected to the connection terminal belonging to the above include those drawn out from the connection terminal in a direction away from the output terminal and then wired in a direction toward the output terminal
The data output device according to claim 1. When imaginary lines are drawn parallel to the direction from the plurality of connection terminals of the driver chip to the output terminals of the display panel, the connection terminals are arranged so that the imaginary lines do not overlap other connection terminals. are placed.
The data output device according to claim 1. The data output device according to claim 1;
A display module comprising a display panel to which the signal line is connected via the output terminal.

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