JP7100941B2 - アプリケーションによって制御された早期書込み確認応答をサポートするメモリ・アクセス・ブローカ・システム - Google Patents

アプリケーションによって制御された早期書込み確認応答をサポートするメモリ・アクセス・ブローカ・システム Download PDF

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JP7100941B2
JP7100941B2 JP2020518635A JP2020518635A JP7100941B2 JP 7100941 B2 JP7100941 B2 JP 7100941B2 JP 2020518635 A JP2020518635 A JP 2020518635A JP 2020518635 A JP2020518635 A JP 2020518635A JP 7100941 B2 JP7100941 B2 JP 7100941B2
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ewack
memory
write request
memory access
write
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JP2020537227A (ja
JP2020537227A5 (enExample
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シルベリス、ディミトリオス
レアーレ、アンドレア
カトリニス、コスタス
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Hardware Redundancy (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
JP2020518635A 2017-10-13 2018-10-10 アプリケーションによって制御された早期書込み確認応答をサポートするメモリ・アクセス・ブローカ・システム Active JP7100941B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/783,069 2017-10-13
US15/783,069 US10423563B2 (en) 2017-10-13 2017-10-13 Memory access broker system with application-controlled early write acknowledgment support and identification of failed early write acknowledgment requests to guarantee in-order execution of memory requests of applications
PCT/IB2018/057834 WO2019073394A1 (en) 2017-10-13 2018-10-10 MEMORY ACCESS BROKER SYSTEM WITH APPLICATION-EARLY WRITTEN RECEIVING RECEIPT SUPPORT

Publications (3)

Publication Number Publication Date
JP2020537227A JP2020537227A (ja) 2020-12-17
JP2020537227A5 JP2020537227A5 (enExample) 2021-02-12
JP7100941B2 true JP7100941B2 (ja) 2022-07-14

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JP2020518635A Active JP7100941B2 (ja) 2017-10-13 2018-10-10 アプリケーションによって制御された早期書込み確認応答をサポートするメモリ・アクセス・ブローカ・システム

Country Status (6)

Country Link
US (1) US10423563B2 (enExample)
JP (1) JP7100941B2 (enExample)
CN (1) CN111201521B (enExample)
DE (1) DE112018004220T5 (enExample)
GB (1) GB2580275B (enExample)
WO (1) WO2019073394A1 (enExample)

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US10911308B2 (en) * 2017-09-18 2021-02-02 Rapyuta Robotics Co., Ltd. Auto-determining and installing missing components to a to-be-managed device by a single execution of unique device setup command
US11025445B2 (en) 2018-06-08 2021-06-01 Fungible, Inc. Early acknowledgment for write operations
US11099993B2 (en) 2018-10-15 2021-08-24 Texas Instruments Incorporated Multi-processor bridge with cache allocate awareness
US11921637B2 (en) * 2019-05-24 2024-03-05 Texas Instruments Incorporated Write streaming with cache write acknowledgment in a processor
US11354455B2 (en) 2019-09-11 2022-06-07 International Business Machines Corporation Maintenance of access for security enablement on a host system
US11308243B2 (en) 2019-09-11 2022-04-19 International Business Machines Corporation Maintenance of access for security enablement in a storage device
US11410417B2 (en) * 2020-08-17 2022-08-09 Google Llc Modular system for automatic hard disk processing and verification
US11855831B1 (en) 2022-06-10 2023-12-26 T-Mobile Usa, Inc. Enabling an operator to resolve an issue associated with a 5G wireless telecommunication network using AR glasses
US11886767B2 (en) 2022-06-17 2024-01-30 T-Mobile Usa, Inc. Enable interaction between a user and an agent of a 5G wireless telecommunication network using augmented reality glasses

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2001216259A (ja) 2000-02-04 2001-08-10 Hitachi Ltd マルチプロセッサシステム及びそのトランザックション制御方法
JP2003098947A (ja) 2001-09-26 2003-04-04 Toshiba Corp 学習支援装置および学習支援方法
JP2012529094A (ja) 2009-06-02 2012-11-15 インターナショナル・ビジネス・マシーンズ・コーポレーション ペリフェラル・コンポーネント・インターコネクト（ｐｃｉ）エクスプレス・ネットワークにおける損失されたポステッド・ライト・パケットおよび順序の狂ったポステッド・ライト・パケットの検出
WO2016039198A1 (ja) 2014-09-10 2016-03-17 ソニー株式会社 アクセス制御方法、バスシステム、および半導体装置

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US5537555A (en) 1993-03-22 1996-07-16 Compaq Computer Corporation Fully pipelined and highly concurrent memory controller
US6279065B1 (en) 1998-06-03 2001-08-21 Compaq Computer Corporation Computer system with improved memory access
US7111153B2 (en) * 2003-09-30 2006-09-19 Intel Corporation Early data return indication mechanism
US9189441B2 (en) * 2012-10-19 2015-11-17 Intel Corporation Dual casting PCIE inbound writes to memory and peer devices
US10073626B2 (en) * 2013-03-15 2018-09-11 Virident Systems, Llc Managing the write performance of an asymmetric memory system
US9235521B2 (en) 2013-07-22 2016-01-12 Avago Technologies General Ip (Singapore) Pte Ltd Cache system for managing various cache line conditions
US20150261677A1 (en) 2014-03-12 2015-09-17 Silicon Graphics International Corp. Apparatus and Method of Resolving Protocol Conflicts in an Unordered Network
GB2533808B (en) * 2014-12-31 2021-08-11 Advanced Risc Mach Ltd An apparatus and method for issuing access requests to a memory controller
US10037220B2 (en) 2015-11-20 2018-07-31 International Business Machines Corporation Facilitating software-defined networking communications in a container-based networked computing environment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001216259A (ja) 2000-02-04 2001-08-10 Hitachi Ltd マルチプロセッサシステム及びそのトランザックション制御方法
JP2003098947A (ja) 2001-09-26 2003-04-04 Toshiba Corp 学習支援装置および学習支援方法
JP2012529094A (ja) 2009-06-02 2012-11-15 インターナショナル・ビジネス・マシーンズ・コーポレーション ペリフェラル・コンポーネント・インターコネクト（ｐｃｉ）エクスプレス・ネットワークにおける損失されたポステッド・ライト・パケットおよび順序の狂ったポステッド・ライト・パケットの検出
WO2016039198A1 (ja) 2014-09-10 2016-03-17 ソニー株式会社 アクセス制御方法、バスシステム、および半導体装置

Also Published As

Publication number Publication date
GB2580275B (en) 2021-03-03
US20190114284A1 (en) 2019-04-18
JP2020537227A (ja) 2020-12-17
US10423563B2 (en) 2019-09-24
GB202006359D0 (en) 2020-06-17
DE112018004220T5 (de) 2020-05-07
CN111201521B (zh) 2023-09-15
CN111201521A (zh) 2020-05-26
GB2580275A (en) 2020-07-15
WO2019073394A1 (en) 2019-04-18

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