JP7096854B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine such as a ball-and-ball gaming machine and a rotating body gaming machine, and more particularly to a staging control in the gaming machine .

In gaming machines such as bullet gaming machines (so-called pachinko gaming machines) and spinning machine gaming machines (so-called slot gaming machines), games are played using game media such as spheres and medals, and certain conditions such as big hits are met. A game medium is given to the player according to the establishment.

In the game machine, as one of the effects for enlivening the game, the number of game media given to the player (the number acquired for the player) is displayed on an image display device such as a liquid crystal display device. (For example, see Patent Document 1 below).
Specifically, in the gaming machine of Patent Document 1, for each game ball winning in the variable winning opening (large winning opening: attacker), the cumulative number of gaming balls acquired including the number acquired by the winning is imaged. It is displayed on the display device. In this case, the numerical value displayed as the number of winnings will gradually increase by the number of winnings (for example, "15") for each winning in the variable winning opening.

Japanese Unexamined Patent Publication No. 2013-106805

Here, in gaming machines, the diversification of staging is progressing so as not to make the player bored, but the processing load related to the staging control tends to increase accordingly. Therefore, it is desired to improve the efficiency of the processing related to the staging and to realize appropriate staging control.

The present invention has been made in view of the above circumstances, and an object of the present invention is to realize appropriate staging control .

The gaming machine according to the present invention includes a plurality of effect means including a display unit for displaying an effect image, and a control unit for controlling the operation of the plurality of effect means in response to a received command. Performs image control processing for displaying the effect image based on the frame synchronization signal used for transferring display data to the display means, and is displayed by the display means defined by the frame synchronization signal. It is configured to analyze the received command within one frame period of the image, and the analysis process elapses a predetermined time from the frame start timing within one frame period of the image displayed by the display means. It is started only in the period on the front end side of the frame until the image is completed , and can be executed a plurality of times within the one frame period . After the analysis process is performed and before the next frame period starts, the sound control information output process based on the command is performed.

According to the present invention, appropriate staging control can be realized .

It is a perspective view of the pachinko gaming machine of embodiment which concerns on this invention. It is a front view of the board surface of the pachinko gaming machine of an embodiment. It is a block diagram of the control composition of the pachinko gaming machine of embodiment. It is a block diagram of the staging control unit of an embodiment. It is a block diagram of the display control system of the staging control unit of an embodiment. It is explanatory drawing of the driver configuration of an embodiment. It is explanatory drawing of the LED driver of an embodiment. It is a flowchart of the main control main process of embodiment. It is a flowchart of the main control timer interrupt processing of embodiment. It is explanatory drawing of the command of embodiment. It is explanatory drawing of the scenario registration information, the lamp data registration information, and the motor data registration information of an embodiment. It is explanatory drawing of the sound data registration information of an embodiment. It is explanatory drawing of the main scenario table of an embodiment. It is explanatory drawing of the sub-scenario table of embodiment. It is a flowchart of the staging control main process of embodiment. It is a flowchart of the frame end processing of an embodiment. It is a flowchart of the command analysis processing in the staging control of an embodiment. It is a flowchart of the command correspondence processing in the effect control of embodiment. It is a flowchart of the effect control timer interrupt process of embodiment. It is explanatory drawing of the display control timing of an embodiment. It is a figure which illustrated the display form of the cumulative grant number. It is a functional block diagram schematically showing the function which concerns on the granting number display method as the first example in Embodiment. It is a flowchart which showed the process corresponding to the 1st display update in an embodiment. It is a flowchart which showed the process corresponding to the 2nd display update as the 1st example in Embodiment. It is a figure for demonstrating the execution condition example of the 2nd display update as a 1st example. It is a figure for demonstrating the example of the display update form of the cumulative grant number. It is a flowchart which showed the process corresponding to the 2nd display update as a 2nd example in an embodiment. It is a block diagram which showed the control structure of the pachinko gaming machine as a modification which adopted the 2 CPU structure. It is a functional block diagram in the case of adopting the granting number display method as an embodiment in a 2 CPU configuration. It is a functional block diagram in the case of adopting the addition number display method as an embodiment in one CPU configuration in which the program modules of the staging control and the liquid crystal control are separately mounted.

Hereinafter, a pachinko gaming machine will be taken as an example as an embodiment of the gaming machine according to the present invention, and will be described in the following order.
<1. Structure of pachinko machine>
<2. Control configuration of pachinko machine>
<3. Configuration of staging control unit>
<4. Overview of operation>
[Design fluctuation display game]
[Game state]
[About hit]
<5. Main control processing>
<6. Processing of the staging control unit>
<7. Display of the number of grants of the embodiment>
[7-1. First example]
[7-2. Second example]
[7-3. Third example]
<8. Summary of Embodiments and Modifications>

<1. Structure of pachinko machine>

First, with reference to FIGS. 1 and 2, the configuration of the pachinko gaming machine 1 as the embodiment according to the present invention will be schematically described.
FIG. 1 is a front perspective view showing the appearance of the pachinko gaming machine 1 of the embodiment, and FIG. 2 is a front view of the gaming board.
The pachinko gaming machine 1 shown in FIGS. 1 and 2 mainly includes a “frame portion” and a “game board portion”.
The "frame portion" includes a front frame 2, an outer frame 4, a glass door 5, and an operation panel 7, which will be described below. The "game board section" is composed of the game board 3 of FIG. In the following description, the "frame portion" or "frame side" is a general term for the front frame 2, the outer frame 4, the glass door 5, and the operation panel 7. Further, the "board portion" or "board side" indicates the game board 3.

As shown in FIG. 1, in the pachinko gaming machine 1, a frame-shaped front frame 2 is attached to the front surface of a wooden outer frame 4 so as to be openable and closable. Although not shown, a game board storage frame is formed on the back surface of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the gaming area 3a formed on the surface of the gaming board 3 faces the front side of the gaming machine of FIG. 1 from the opening 2a of the front frame 2.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the player side on the front side via the transparent glass.

The glass door 5 is attached to the front frame 2 so as to be openable and closable by the shaft support mechanism 6. Then, by operating a door unlocking key cylinder (not shown) provided at a predetermined position of the glass door 5, the locked state of the glass door 5 with respect to the front frame 2 can be released, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can be released by operating the door lock release key cylinder.
Further, on the front surface side of the glass door 5, light emitting portions 20w are provided in various places as light emitting means on the frame side. For example, the light emitting unit 20w performs a light emitting operation for staging, a light emitting operation for error notification, a light emitting operation according to an operating state, and the like as a light emitting operation by an LED.

An operation panel 7 is provided on the lower side of the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a shaft support mechanism (not shown).
The operation panel 7 is provided with an upper saucer unit 8, a lower saucer unit 9, and a firing operation handle 10.

The upper saucer unit 8 is formed with an upper saucer 8a for storing a game ball to be used for a bullet. The lower saucer unit 9 is formed with a lower saucer 9a for storing game balls that cannot be stored in the upper saucer 8a.
Further, the upper saucer unit 8 is provided with a ball removal button 16 for pulling out the game ball stored in the upper saucer 8a toward the lower saucer 9a. The lower tray unit 9 is provided with a ball pulling lever 17 for pulling out the gaming ball stored in the lower tray 9a below the gaming machine.
Further, the upper tray unit 8 has a ball lending button 14 for requesting the payout of the game ball to the game ball lending device (not shown), and a card for requesting the return of the valuable medium inserted in the game ball lending device. A return button 15 is provided.
Further, the upper tray unit 8 is provided with effect buttons 11 and 12, and a cross key 13. The effect buttons 11 and 12 are push buttons that can be operated by turning on the built-in lamp during a predetermined input acceptance period and can bring about a change in the effect by pressing the built-in lamp when the built-in lamp is lit. Further, the cross key 13 is an operator for the player to perform an operation according to the effect situation, an operation for setting the effect, and the like.

The firing operation handle 10 is provided on the right end side of the operation panel 7, and is an operator for the player to operate the launching device 56 shown in FIG. 3 for the ball.
Further, speakers 25 for acoustically outputting the effect sound are provided on both sides of the upper portion of the front frame 2 and in the vicinity of the firing operation handle 10.

Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or a resin board. A ball guide rail 31 for guiding the launched game ball is annularly mounted on the game board 3 as a board surface partition member, and a substantially circular region surrounded by the ball guide rail 31 is referred to as a game area 3a. It has become.

A main liquid crystal display device 32M (LCD: Liquid Crystal Display) is provided in a substantially central portion of the game area 3a, and a sub liquid crystal display device 32S is provided on the right side of the main liquid crystal display device 32M.
In the main liquid crystal display device 32M, under the control of the staging control unit 51, which will be described later,, for example, three decorative symbols, left, middle, and right, are variablely displayed on the background image. In addition, various production images such as normal production, reach production, and super reach production are also displayed. Similarly, the sub-liquid crystal display device 32S also displays according to various effects.

Further, in the game area 3a, a center decoration 35C is provided so as to surround the periphery of the display surface of the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The center decoration 35C not only exerts a decorative effect due to its design, but also has a function of protecting the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S from surrounding game balls. Further, the center decoration 35C also functions as a member that enables the left and right strikes of the flow path of the game ball according to the launch strength or the stroke length of the game ball. That is, the flow path of the game ball launched to the upper part of the game area 3a via the ball guide rail 31 flows down either the left game area 3b or the right game area 3c divided by the center decoration 35C. In the case of so-called left-handed, the game ball flows down the left game area 3b, and in the case of right-handed, the game ball flows down the right game area 3c.

Further, a lower left decoration 35L is provided below the left game area 3b to exert a decorative effect and define a range as the left game area 3b.
Similarly, a lower right decoration 35R is provided below the right game area 3c to exert a decorative effect and define the range as the left game area 3b.
In the game area 3a (left game area 3b and right game area 3c), nails 49 and windmills 47 are provided at required locations to form various flow paths of the game ball.
Further, a center stage 35S is provided below the main liquid crystal display device 32M, which exerts a decorative effect and functions as a floating area of a game ball.
Although not shown, the center decoration 35C is provided with a movable body accessory that exerts a visual effect at a suitable place.

A symbol display unit 33 using a dot display formed by arranging a plurality of LEDs is provided near the upper right edge of the game area 3a.
In the symbol display unit 33, a first special symbol display unit, a second special symbol display unit, and a normal symbol display unit are formed by a predetermined dot area, and the first special symbol, the second special symbol, and the ordinary symbol are formed. Each fluctuation display operation (variation display operation that sets fluctuation start and fluctuation stop) is performed.
The main liquid crystal display device 32M variablely displays the decorative symbol by the image in synchronization with the variable display of the first and second special symbols by the symbol display unit 33.

Below the center decoration 35C, a winning device having an upper starting port 41 (first special symbol starting port) is provided, and further below, a lower starting port 42a (second special symbol starting port) is provided. A variable winning device 42 is provided.
Inside the upper start port 41 and the lower start port 42a, detection sensors (upper start port sensor 71 and lower start port sensor 72 shown in FIG. 3) for detecting the passage of the game ball are formed.

The upper starting port 41 is a winning opening related to the starting condition of the variable display operation of the first special symbol in the symbol display unit 33, and has a fixed winning rate without a starting opening opening / closing means (means for opening or expanding the starting port). It is a type of winning device.

The ordinary variable winning device 42 having the lower starting opening 42a is configured as a winning rate variable winning device in which the winning rate of the game ball at the starting opening can be changed by the starting opening opening / closing means. That is, it is a so-called electric tulip-type winning device provided with a pair of left and right movable wing pieces (movable members) 42b that open or expand the lower starting port 42a.
The lower starting port 42a of the normal variable winning device 42 is a winning opening related to the starting condition of the variable display operation of the second special symbol in the symbol display unit 33. The winning rate of the lower starting port 42a varies depending on the operating state of the movable wing piece 42b. That is, when the movable wing piece 42b is open, winning is easy, and when the movable wing piece 42b is closed, winning is difficult or impossible.

Further, a plurality of general winning openings 43 are provided on the left and right sides of the ordinary variable winning device 42. A detection sensor (general winning opening sensor 74 shown in FIG. 3) for detecting the passage of a game ball is formed inside each general winning opening 42.
Further, on the lower side of the right game area 3c, a normal symbol start port 44 composed of a gate (specific passage area) through which the game ball can pass is provided. The normal symbol start port 44 is a winning opening related to the fluctuation display operation of the normal symbol in the symbol display unit 33, and a sensor (gate sensor 73 shown in FIG. 3) for detecting a passing game ball is formed inside the winning opening. Has been done.

A first special variable winning device 45 (special electric accessory) is provided in the middle of the flow path from the normal symbol starting port 44 in the right game area 3c to the normal variable winning device 42.
The first special variable winning device 45 has a structure in which the first large winning opening 45a is closed / opened by a retractable open door 45b. Further, a sensor (the first large winning opening sensor 75 in FIG. 3) for detecting the passage of the game ball to the first large winning opening 45a is formed inside the sensor.
Around the first large winning opening 45a, the lower right decoration 35R is in a state of bulging from the surface of the game board 3, and the upper side of the bulging portion and the upper surface of the open door 45b guide the downstream of the right flow path 3c. Forming a part. Therefore, when the open door 45b is pulled into the inside of the board, the game ball that has reached the downstream guide portion easily enters the first large winning opening 45a.

Further, a second special variable winning device 46 (special electric accessory) is provided below the normal variable winning device 42. The second special variable winning device 46 has a structure in which the second large winning opening 46a inside is closed / opened by an open door 46b whose lower portion is pivotally supported and can be opened and closed. Further, a sensor (second large winning opening sensor 76 in FIG. 3) for detecting the passage of the game ball to the second large winning opening 46a is formed inside the sensor.
When the open door 46b is opened, the second big winning opening 46a is opened. In this state, the game ball that has flowed down the left game area 3b or the right game area 3c has a high probability of entering the second large winning opening 46a.

As described above, the upper starting opening 41, the lower starting opening 42a, the normal symbol starting opening 44, the first major winning opening 45a, the second major winning opening 46a, and the general winning opening 43 are formed in the game area of the board surface. Has been done.
In the pachinko gaming machine 1 of the present embodiment, if there is a prize in a prize opening other than the normal symbol start opening 44 among these winning openings, a prize per winning ball set for each winning opening is awarded. The number of balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the number of prize balls is set such that the upper start opening 41 and the lower start opening 42a are 3, the first big winning opening 45a, the second big winning opening 46a are 15, and the general winning opening 43 is 10.
The game balls that do not win in each of these winning openings are discharged from the gaming area 3a via the out opening 48.
Here, "winning" means that the winning opening takes in the game ball inside the winning opening or the game ball passes through the gate. Actually, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated as if a "winning" has occurred in the winning opening. The game ball related to this prize is also referred to as a "winning ball".

On the board as described above, the center decoration 35C, the lower left decoration 35L, the lower right decoration 35R, the center stage 35S, the first special variable winning device 45, the second special variable winning device 46, and the movable body accessory (not shown). Although not shown in detail, light emitting units 20b using, for example, LEDs are provided in various places as light emitting means on the board side.
The light emitting unit 20b performs a light emitting operation for staging, a light emitting operation for error notification, a light emitting operation according to an operating state, and the like.

In the following, for the sake of explanation, the light emitting unit 20w on the board side and the light emitting unit 20b on the frame side may be referred to as “light emitting unit for staging”.

<2. Control configuration of pachinko machine>

Next, the configuration of the control system of the pachinko gaming machine 1 will be described. FIG. 3 is a schematic block diagram of the internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 of the present embodiment is mainly provided with a main control board 50, an effect control board 51, a payout control board 53, a launch control board 54, and a power supply board 58 as boards forming the control configuration thereof.

The main control board 50 is equipped with a microcomputer or the like, and performs comprehensive control related to the overall gaming operation of the pachinko gaming machine 1. In the following, the configuration of the main control board 50 including the microcomputer mounted on the main control board 50 will be referred to as “main control unit 50”.
The effect control board 51 is equipped with a microcomputer or the like, and receives an effect control command from the main control unit 50 to perform control for performing various effect operations using an image display, light emission, acoustic output, and a movable body accessory. I do. In the following, the structure of the staging control board 51 including the microcomputer mounted on the staging control board 51 will be referred to as “staging control unit 51”.

The payout control board 53 controls the payout of prize balls by the game ball payout device 55 connected to the pachinko gaming machine 1.
The launch control board 54 controls the launch operation of the game ball by the launch device 56 provided in the pachinko gaming machine 1 of the player.
The power supply board 58 performs AC / DC conversion and further DC / DC conversion from an external power supply (for example, AC24V), and supplies an operating power supply voltage Vcc to each part. The illustration of the power supply path is omitted.

First, the main control unit 50 and its peripheral circuits will be described.
The main control unit 50 is equipped with a microprocessor incorporating a CPU 100 (hereinafter referred to as "main control CPU 100"), a ROM 101 (hereinafter referred to as "main control ROM 101"), a RAM 102 (hereinafter referred to as "main control RAM 102"), and the like. ing.
The main control CPU 100 executes various operations and control processes according to the progress of the game based on the control program.
The main control ROM 101 stores a game operation control program by the main control CPU 100 and various data necessary for the game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processing, and as a buffer area for various input / output data and processing data.
Although not shown, the main control unit 50 includes an interface circuit with each unit, a random number generation circuit for generating lottery random numbers related to special symbol variation display, a CTC (Counter Timer Circuit) for various time counting, and a main control unit. It also has an interrupt controller circuit that gives an interrupt signal to the control CPU 100.

As described above, the main control unit 50 has each winning means (upper starting port 41, lower starting port 42a, normal symbol starting port 44, first large winning opening 45a, second large winning opening 46a, general) in the game area of the board surface. It is configured to receive the detection signal of the sensor provided in the winning opening 43).
That is, the detection signals of the upper start port sensor 71, the lower start port sensor 72, the gate sensor 73, the general winning port sensor 74, the first special winning opening sensor 75, and the second major winning opening sensor 76 are sent to the main control unit 50. Will be supplied.
These sensors (71 to 76) are composed of a detection switch that detects a game ball that has entered, but specifically, a non-contact switch such as a photo switch or a proximity switch, or a contact switch such as a micro switch. It can be configured with a switch.

The main control unit 50 receives the detection signals of the upper start port sensor 71, the lower start port sensor 72, the gate sensor 73, the general winning port sensor 74, the first special winning opening sensor 75, and the second major winning opening sensor 76. Processing is performed according to the above. For example, lottery processing, symbol fluctuation control, prize ball payout control, staging control command transmission control, external data transmission processing, and the like are performed.

Further, a normal electric accessory solenoid 77 for opening and closing the movable wing piece 42b of the lower starting port 42 is connected to the main control unit 50, and the main control unit 50 transmits a control signal according to the progress of the game and is normally electric. The driving operation of the accessory solenoid 77 is executed, and the opening / closing operation of the movable wing piece 42b is executed.
Further, the main control unit 50 has a first large winning opening solenoid 78 for opening and closing the open door 45b of the first large winning opening 45, and a second large winning opening driving for opening and closing the open door 46b of the second large winning opening 46. The mouth solenoid 79 is connected. The main control unit 50 drives and controls the first big winning opening solenoid 78 or the second big winning opening solenoid 79 according to the so-called big hit situation, and opens the first big winning opening 45 or the second big winning opening 46. To execute.

Further, a symbol display unit 33 is connected to the main control unit 50, and a control signal is transmitted to the symbol display unit 33 to execute various symbol displays (LEDs are turned off / on / blinked). As a result, the display operation on the first special symbol display unit 80, the second special symbol display unit 81, and the normal symbol display unit 82 in the symbol display unit 33 is executed.

Further, a frame external terminal board 57 is connected to the main control unit 50. The main control unit 50 can transmit information regarding the progress of the game to a hall computer (not shown) via the frame external terminal board 57. The information regarding the progress of the game is, for example, information such as jackpot winning information, prize ball number information, and symbol variation display execution count information. The hall computer is a management computer that comprehensively manages the gaming machines of the pachinko hall, and is installed outside the gaming machines.

Further, a payout control board 53 is connected to the main control unit 50. The payout control board 53 is connected to a launch control board 54 that controls the launch device 56 and a game ball payout device 55 that pays out the game balls.
The main control unit 50 transmits a control command related to payout (a payout control command for designating the number of prize balls) to the payout control board 53. The payout control board 53 controls the game ball payout device 55 in response to the control command to execute the payout of the game ball.
Further, the payout control board 53 can transmit information (payout state signal) regarding the payout operation state to the main control unit 50. On the main control unit 50 side, whether or not the game ball payout device 55 is functioning normally is monitored by this payout status signal. Specifically, it monitors whether or not a problem such as jamming or insufficient payout of prize balls has occurred during the payout operation of the prize balls.

Further, the main control unit 50 transmits an effect control command including information regarding the special symbol variation display to the effect control unit 51. The transmission of the effect control command from the main control unit 50 to the effect control unit 51 is executed by one-way communication. This is to prevent an illegal signal due to an illegal act from the outside from being input to the main control unit 50 via the staging control unit 51.

Subsequently, the staging control unit 51 and its peripheral circuits will be described.
The staging control unit 51 is equipped with a microprocessor having a built-in CPU 200 (hereinafter referred to as “staging control CPU 200”), ROM 201 (hereinafter referred to as “staging control ROM 201”), and RAM 202 (hereinafter referred to as “staging control RAM 202”). It constitutes a microcomputer.

The staging control CPU 200 performs arithmetic processing for various staging operations and control of each staging means based on the staging control program and the staging control command received from the main control unit 50. In the case of the pachinko gaming machine 1 of the present embodiment, the effect means are a main liquid crystal display device 32M, a sub liquid crystal display device 32S, light emitting units 20w and 20b, a speaker 25, and a movable body accessory (not shown).
Further, the staging control ROM 201 stores a control program for the staging operation by the staging control CPU 200 and various data necessary for the staging operation control.
The staging control RAM 202 (D-RAM 202a in FIG. 4, work memory 202b for built-in CPU) is used as a work area used by the staging control CPU 200 for various arithmetic processes, a table data area, a buffer area for various input / output data and processing data, and the like. Used.
As will be described later, the arithmetic control unit 51 shows an example in which a one-chip microcomputer and its peripheral circuits are mounted, but various configurations of the staging control unit 51 can be considered. For example, in addition to a microcomputer, an interface circuit with each part, a random number generation circuit for generating lottery random numbers for production, a CTC for various time counting, a watchdog timer (WDT) circuit, and an interrupt signal to the production control CPU 200. In some cases, it is equipped with an interrupt controller circuit, a sound source IC for sound production, and the like.

The main roles of the effect control unit 51 are to receive the effect control command from the main control unit 50, determine the selection of the effect based on the effect control command, and control the display of the main liquid crystal display device 32M and the sub liquid crystal display device 32S (display data). Supply), audio output control of the speaker 45, light emission control of the light emitting units 20w and 20b (LED), operation control of the movable body accessory (drive control of the movable body accessory motor 65), and the like.

Since the effect control unit 51 also has a function as a control device for the main liquid crystal display device 32M and the sub liquid crystal display device 32S, the effect control unit 51 includes a so-called VDP (Video Display Processor), an image ROM, and a VRAM ( It also has a function as a video RAM), and the effect control CPU 200 also functions as a liquid crystal control unit.
VDP refers to a function that controls overall video output processing such as image development processing and image drawing.
The image ROM refers to a memory in which image data (effect image data) for which VDP performs image expansion processing is stored.
The VRAM is an image memory area that temporarily stores the image data developed by the VDP.

With these configurations, the staging control unit 51 generates various image data based on commands from the main control unit 50 and outputs them to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. As a result, various effect images are displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

Further, a frame driver unit 61 and a board driver unit 62 are connected to the staging control unit 51.
The frame driver unit 61 drives the LED of the lamp unit 63 on the frame side to emit light. The lamp unit 63 is a general representation of the light emitting unit 20w provided on the frame side as shown in FIG.
The panel driver unit 62 drives the LED of the lamp unit 64 on the panel side to emit light. The lamp unit 64 is a general representation of the light emitting unit 20b provided on the panel side as shown in FIG.

Further, a motor driver unit 70 is connected to the staging control unit 51.
The motor driver unit 70 drives the movable body accessory motor 65 to execute the operation of the movable body accessory motor provided on the board side.
As the movable body accessory motor 65, for example, a stepping motor is used.
The origin position is defined for each movable accessory motor 65. The origin position is, for example, a position where the accessory does not normally appear on the board surface of FIG.
The origin switch 68 is provided on each movable accessory motor 65 so that the effect control unit 51 can confirm whether or not each movable accessory motor 65 is at the origin position. For example, a photo interrupter is used. The information of the origin switch 68 is detected by the staging control CPU 200.

Further, details will be described later with reference to FIGS. 6 and 7, but in the case of the present embodiment, the staging control unit 51 uses the light emission drive data and the motor drive data as serial data, and the frame driver unit 61, the panel driver unit 62, and the motor. Output to the driver unit 70.

Further, the staging control unit 51 executes audio output control from the speaker 25. The staging control unit 51 outputs music for staging and audio signals as audio to the amplifier unit 67 as stereo output signals of two channels, for example, Lch and Rch. This audio signal is amplified by the amplifier unit 67 and then given to the speaker 25.
Although only one system of the amplifier unit 67 and the speaker 25 is shown in FIG. 3 for convenience of illustration, the amplifier unit 67 and the speaker 25 are actually provided with output channels corresponding to, for example, Lch and Rch, respectively. , Stereo sound reproduction is possible.

Further, an operation unit 60 that can be operated by the player is connected to the effect control unit 51, and an operation detection signal from the operation unit 60 can be received. The operation unit 60 is the effect buttons 11 and 12 and the cross key 13 described with reference to FIG. 1, and an operation detection mechanism thereof.
The staging control unit 51 can perform various staging controls according to the operation detection signal from the operation unit 60.

The staging control unit 51 determines the staging pattern by lottery or uniquely from a plurality of types of staging patterns prepared in advance based on the staging control command sent from the main control unit 50, and various staging patterns are performed at the required timing. Control the means. As a result, the main liquid crystal display device 32M and the sub liquid crystal display device 32S corresponding to the effect pattern display the effect image, reproduce the sound from the speaker 25, and turn on and blink the LEDs in the lamp units 63 and 64 (light emitting units 20w and 20b). The operation of the movable body accessory by the drive and the movable body accessory motor 65 is realized, and various production patterns are developed in chronological order. As a result, the production according to the "production scenario" is realized.

The function of the staging control command is defined by a 2-byte configuration consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish between MODE and EVENT, Bit7 of MODE is ON and Bit7 of EVENT is OFF.
The effect control command from the main control unit 50 is taken into the command reception buffer by the effect control unit 51. The effect control CPU 200 confirms the command reception buffer at a predetermined timing, analyzes the received effect control command, and determines the effect control to be executed.

<3. Configuration of staging control unit>

FIG. 4 shows a specific configuration example of the staging control unit 51.
The staging control unit 51 of the example of FIG. 4 is configured by externally connecting, for example, the staging control ROM 201, D-RAM 202a, CG-ROM 206, WDT (watchdog timer) circuit 210, etc. to the one-chip microcomputer 250. There is.

The one-chip microcomputer 250 includes a staging control CPU 200, and has functions such as the above-mentioned VDP and VRAM, and further functions of light emission control, motor control, and sound control by each of the illustrated parts.
Each part of the structure will be explained.

The one-chip microcomputer 250 is equipped with a staging control CPU 200. The staging control CPU 200 performs various control processes as described above.
The staging control CPU 200 uses an internal device or an external device of the microcomputer 250 via the CPU interface 203.
That is, the effect control CPU 200 is connected to the host interface 204 via the CPU interface 203, receives commands from the main control unit 50, reads access to the effect control ROM 201, and sends / receives signals to / from the WDT circuit 210 via the host interface 204. , And communicate with each part inside via the bus 251.

The staging control CPU 200 uses the D-RAM 202a and the built-in CPU work memory 202b as the staging control RAM 202 described above.
The D-RAM 202a is connected to the RAM interface 208, and the staging control CPU 200 writes or reads from the D-RAM 202a via the RAM interface 208.

The system control register 205 is a register for initializing the system.
The transfer circuit 212 performs transfer using the internal resources and external peripherals of the microcomputer 250 as input / output.

The CG-ROM 206 is an image ROM and stores character image data to be displayed.
The CG-ROM 206 is connected to the CG bus interface 207 provided in the microcomputer 250. As a result, the required part in the microcomputer 250 can access the CG-ROM 206 via the CG bus interface 207.

The microcomputer 250 has a built-in VRAM 209 having a capacity of, for example, 48 Mbytes. The VRAM 209 stores drawing material and frame data.
Various usage modes of VRAM209 can be set by setting, but in this example, two frame buffers 209A and 209B are set as storage areas for frame data for display, and the frame buffers 209A and 209B are alternately used for each frame. To draw and output display data.

In this embodiment, since two display devices (main liquid crystal display device 32M and sub liquid crystal display device 32S) are used, the frame buffers 209A and 209B are used for the main liquid crystal display device 32M and the sub liquid crystal display device 32S, respectively. It will be prepared accordingly.
That is, the illustrated frame buffer 209A includes a frame buffer area for the main liquid crystal display device 32 and a frame buffer area for the sub liquid crystal display device 32S, and the frame buffer 209B includes a frame buffer area and a sub for the main liquid crystal display device 32. Includes a frame buffer area for the liquid crystal display device 32S.
Image data for one frame for the main liquid crystal display device 32M and the sub liquid crystal display device 32S are generated in the frame buffers 209A and 209B of the VRAM 209, respectively, and the frame buffers 209A and 209B are drawn by a predetermined drawing command. The position is specified.

The index table 211 manages the VRAM 209, such as setting the storage area of the VRAM 209.

The preloader 220, the display circuits 221,222, 223, the GDEC (graphic decoder) 223, and the drawing circuit 225 perform various processes as a video processor (VDP).
The effect control CPU 200 creates a display list for setting the image contents to be displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S in response to the effect control command. This display list is a collection of drawing commands.
The display list consists of a group of drawing commands listed in the order in which they are drawn. The drawing command also includes a command that defines what kind of image is drawn at which position in one frame, and a storage position (source address) such as CG-ROM206 of the image to be drawn is also specified.

The drawing circuit 225 draws a figure in the frame buffer (209A or 209B) on the VRAM 209.
The GDEC 223 decodes the compressed image data used for drawing and develops it in the VRAM 209.

The preloader 220 analyzes the display list transmitted by the data transfer circuit 212, and transfers the image material referred to therein, that is, the image data on the CG-ROM 206, to the designated area of either DRAM 202a or VRAM 209. do.
At this time, the preloader 220 outputs a display list in which the reference destination of the image data is rewritten to the address after transfer. The rewritten display list is transmitted to the drawing circuit 225 by the data transfer circuit 212.

Since random access to the image data occurs during the execution of drawing by the drawing circuit 225, if the image data is directly referred to from the CG-ROM 206, which is vulnerable to random access such as a NAND flash memory, the drawing performance is greatly deteriorated. Therefore, by using the preloader 220 to transfer the image data and the display list to the D-RAM 202a or the built-in VRAM 209 in advance, it is possible to execute moving image decoding and drawing at high speed.

As described above, in the present embodiment, since the preloader 220 is functioning, the reference destination of the image data (CG data as the image material) of the display list is set to D-RAM202a or VRAM209 instead of CG-ROM206. This is the preload area. Therefore, random access to the image data generated during the execution of drawing by the drawing circuit 225 can be quickly executed, which is advantageous for the drawing process even for a high-resolution moving image with a lot of movement.

The display circuits 221, 222, 223 display and output the display data of the frame buffer (209A or 209B) of the VRAM 209 to the outside.
Here, the microcomputer 250 is equipped with three display circuits 221, 222, 223 for three-screen output that enables one system of digital RGB output and two systems of LVDS (Low voltage differential signaling) output. This is because it has a structure. In the case of this example, for example, a digital RGB output is used as a display data output to the main liquid crystal display device 32M, and one LVDS output is used as a display data output to the sub liquid crystal display device 32S.
The display data from the display circuits 221, 222, 223 are selected by the LCD interface 226 and output to external devices, that is, the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

The display circuits 221, 222, 223 output display data as non-interlaced output. Further, the display data is provided with a scaling processing function for enlarging / reducing from 2 times to 1/2 times, a dithering function, and a color correction function.

FIG. 5 shows a block diagram of the display circuits 221,222,223 and the LCD interface 226.
Each display circuit 221, 222, 223 has a synchronization signal generation unit 265, and performs processing in synchronization with an image frame, respectively. The synchronization signal generation unit 265 generates, for example, a V blank signal indicating a vertical blank period (non-effective line scanning period), a horizontal synchronization signal, and a vertical synchronization signal as synchronization signals. These synchronization signals can be used for internal control processing of the microcomputer 250, and are also used for display data transfer and display control operation to the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The synchronization signals used in the display circuits 221, 222, 223 can be synchronized with each other. For example, the display circuits 221, 222, 223 can be forcibly synchronized by using the falling edge of the vertical synchronization signal of an external display such as the main liquid crystal display device 32M as a trigger.

Each display circuit 221, 222, 223 acquires the frame data read from the frame buffer 209A or 209B of the VRAM 210 by the VRAM reading unit 261.
Regarding the display circuits 221,222, it is possible to perform scaling processing on the scaler 262, color correction processing on the color correction unit 263, and dithering processing on the ditherer 264 on the acquired frame data. Then, digital RGB output and LVDS output are performed as outputs after processing by the ditherer 264. The same applies to the display circuit 223, but in the example of this figure, an example is given in which the display circuit 223 does not have the function of the scaler 262.

The LCD interface 226 has a digital RGB output unit 226a and an LVDS output unit 226b.
Display data as digital RGB output from the display circuits 221, 222, 223 is supplied to the digital RGB output unit 226a. The digital RGB output unit 226a selects one digital RGB output of the display circuits 221, 222, 223 and supplies it to the main liquid crystal display device 32M.
Further, display data as LVDS output from the display circuits 221, 222, 223 is supplied to the LVDS output unit 226b. The LVDS output unit 226b can select and output two LVDS outputs from the display circuits 221, 222, 223. In the case of the pachinko gaming machine 1 of the present embodiment, the LVDS output of one of the display circuits 221, 222, 223 is supplied to the sub-liquid crystal display device 32S.
Of course, this is an example, and it is conceivable to supply one LVDS output to the main liquid crystal display device 32M, or to supply the digital RGB output to the sub liquid crystal display device 32S.

The microcomputer 250 of FIG. 4 has a sound controller 230.
The sound controller 230 has, for example, a sound source control unit and a sound data storage unit that stores compressed audio data. Based on the control of the effect control CPU 200, the sound controller 230 decodes the compressed audio data to generate an output audio signal, and an external amplifier. Output to unit 67.
Regardless of whether or not the sound controller 230 is mounted, the staging control CPU 200 may control the sound source IC outside the microcomputer 250 to output the audio signal to the amplifier unit 67.

The microcomputer 250 has a general-purpose port 231. For example, it is an 8-bit input / output port. The general-purpose port 231 enables input / output with various external devices.

The serial output controller 240 outputs the control signal as serial data to the outside. In the case of the present embodiment, the serial output controller 240 is provided with a lamp controller 241 and a motor controller 242, and outputs light emission drive data of the lamp units 63 and 64 and outputs motor drive data of the movable body accessory motor 65. ..
FIG. 6 shows an output system of light emission drive data from the serial output controller 240 (lamp controller 241 and motor controller 242) to the frame driver unit 61 and the panel driver unit 62, and an output system of motor drive data to the motor driver unit 70. ..

In the frame driver unit 61, n LED drivers 90 are connected in parallel to the serial data output channel ch1 of the serial output controller 240.
As the signal line of the serial data output channel ch1, a clock line for supplying the clock signal CLK and a data line for supplying serial data DATA as light emission drive data (also referred to as “LED drive data” or “ramp drive data”) are provided. Has been done. Each of these signal lines is connected so as to supply each signal in parallel to the n LED drivers 90 constituting the frame driver unit 61.
A device ID used by the staging control CPU 200 as a slave address is set in each LED driver 90 of the frame driver unit 61. That is, it is an identifier of each LED driver 90. For the sake of explanation, the device IDs (slave addresses) of each LED driver 90 are tentatively expressed as w1, w2, ... As shown in the figure.

Further, in the panel driver unit 62, m LED drivers 90 are connected in parallel to the serial data output channel ch2 of the staging control CPU 200.
Similar to channel ch1, the signal line of the serial data output channel ch2 is also provided with a clock line for supplying the clock signal CLK and a data line for supplying the serial data DATA as the light emission driving data. Each of these signal lines is connected so as to supply each signal in parallel to the m LED drivers 90 constituting the panel driver unit 62.
A device ID (identifier of each LED driver 90) used as a slave address by the effect control CPU 200 is set in each LED driver 90 of the board driver unit 62. For the sake of explanation, the device IDs (slave addresses) of each LED driver 90 are tentatively referred to as b1, b2 ... As shown in the figure.

The LED driver 90 in the frame driver unit 61 and the panel driver unit 62 is, for example, a 24-channel LED driver and includes 24 current terminals. Therefore, one LED driver 90 can supply LED drive currents to up to 24 series. Specifically, for example, 8 series of R (red) LED drive current supply, 8 series of G (green) LED drive current supply, and 8 series of B (blue) LED drive current supply are performed, and 8 full-color LEDs emit light. It can be driven. Here, one "series" refers to one LED connected to one current terminal or a group of a plurality of LEDs connected in series or in parallel to one current terminal. There is.
The number n of the LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of the light emitting unit 20w). Therefore, n may be 1 or 2 or more. The frame driver unit 61 has one or more LED drivers 90.
Further, the number m of the LED driver 90 in the board driver unit 62 is determined by the number of LED series arranged on the board side (the number of series of the light emitting unit 20b). Therefore, m may be 1 or 2 or more. The board driver unit 62 has one or more LED drivers 90.

FIG. 7 shows a schematic configuration example of a main part of the LED driver 90.
The LED driver 90 includes a serial bus interface 191, an address setting unit 192, a data buffer / PWM controller 193, a D / A converter 194, and a drive current source circuit 195-1 to 195-24.
The drive current source circuits 195-1 to 195-24 are current sources that perform the above-mentioned 24 series drive current outputs from the current terminals 196-1 to 196-24, respectively.

A clock signal CLK and serial data DATA from the serial output controller 240 are input to the serial bus interface 191 in the LED driver 90. The serial bus interface 191 captures serial data DATA at the timing of the clock signal CLK. The serial bus interface 191 converts the captured serial data into parallel data and transfers it to the data buffer / PWM controller 193.
The serial output controller 240 specifies a slave address and transmits LED drive data.
The data buffer / PWM controller 193 confirms the slave address of the parallel data transferred from the serial bus interface 191. When it is confirmed that the slave address included in the parallel data matches the own slave address (either w1 to w (n) or b1 to b (m)) set in the address setting unit 192. , The LED drive data included in the parallel data is stored in the designated register as valid data.

When the data buffer / PWM controller 193 captures the LED drive data of each series, the data buffer / PWM controller 193 uses a value corresponding to the luminance information (gradation value) indicated by the LED drive data as each drive control value of the 24 series, D / A. Output to the converter 194.
The D / A converter 194 converts the value corresponding to the luminance information into an analog signal and uses it as a control signal for each current source circuit 195-1 to 195-24.

A 24-series LED 120 is connected to all (or a part) of the current terminals 196 (196-1 to 196-24). The figure shows a state in which one LED 120 is connected to one series of current terminals 196 for simplification, but there is also a configuration in which a plurality of LEDs are connected to one series of current terminals 196 (for example, series connection). Of course it is possible.
In each series (current terminals 196-1 to 196-24), a power supply voltage Vcc is applied to the series connection of the LED 120 and the resistor R. A current is passed through the LED 120 of each series by the current source circuits 195-1 to 195-24, and light is emitted.
That is, each current source circuit 195-1 to 195-24 operates so as to pass a drive current of a current amount corresponding to the signal supplied from the D / A converter 194 to the corresponding series of LEDs 120.

To specifically describe such LED drive control for one series, the data buffer / PWM controller 193 converts a digital data string corresponding to a pulse duty according to the gradation value of the series into a D / A converter 194. The D / A converter 194 converts the digital data string into a pulse signal as an analog signal and supplies it to the current source circuit 195 of the series. The current source circuit 195 is output controlled by the H / L of the pulse signal, and outputs currents of, for example, 0 mA and 5 mA. For example, in such an operation, a drive current having an average current value corresponding to the gradation value flows through the LED 120 as a result.
In the present embodiment, the current values are set to, for example, 0 mA and 5 mA by the PWM drive method, and the gradation control is performed (integrally) in the time axis direction, but the gradation control is of course limited to this. Needless to say, the current value may actually be changed according to the gradation. Regardless of whether it is duty control or level control, appropriate gradation expression is possible by setting the average current value per unit time to the level according to the gradation.

The number n of the LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of the light emitting unit 20w). Therefore, n may be 1 or 2 or more. The frame driver unit 61 has one or more LED drivers 90.
Further, the number m of the LED driver 90 in the board driver unit 62 is determined by the number of LED series arranged on the board side (the number of series of the light emitting unit 20b). Therefore, m may be 1 or 2 or more. The board driver unit 62 has one or more LED drivers 90.

As the lamp units 63 and 64 using LEDs and the like, an example of one system (one serial data output channel) on the frame side and one system on the panel side is given, but of course, the present invention is not limited to this. A plurality of systems may be provided for the lamp portion 63 on the frame side, or a plurality of systems may be provided for the lamp portion 64 on the panel side.

Next, the output of the motor drive data will be described. As shown in FIG. 6, serial data DATA as motor drive data is output from the serial output controller 240 to the motor driver unit 70.
In the motor driver unit 70, p motor drivers 91 are connected in parallel to the serial data output channel ch3 of the serial output controller 240.
Similarly, the signal line of the serial data output channel ch3 is provided with a clock line for supplying the clock signal CLK and a data line for supplying the serial data DATA as the motor drive data. Each of these signal lines is connected so as to supply each signal in parallel to the p motor drivers 91 constituting the motor driver unit 70.
A device ID (identifier of each motor driver 91) used as a slave address by the staging control CPU 200 is set in each motor driver 91 of the motor driver unit 70. For the sake of explanation, the device IDs (slave addresses) of each motor driver 91 are tentatively expressed as mt1, mt2, ... As shown in the figure.

Each motor driver 91 in the motor driver unit 70 may have the configuration shown in FIG. 7 in the same manner as the LED driver 90. That is, the same driver can be used.
The number p of the motor driver 91 in the motor driver unit 70 is determined by the number of motors used for the movable body accessory 65 and the like. Therefore, p may be 1 or 2 or more. The motor driver unit 70 has one or more motor drivers 91.
A movable body accessory motor 65 (see FIG. 3) for driving a movable body accessory is connected to the motor driver 91.

Since the driver having the configuration described above in FIG. 7 is a circuit that outputs the current indicated by the given command (serial data) from the current terminals 196-1 to 196-24, it is physically a stepping motor, a solenoid, or the like. It can also be used as a motor driver 91 for a movable body drive device.
The operation of the movable body accessory is finely set according to the effect scenario, and the effect control unit 51 controls the drive direction, the drive amount, and the like accordingly. The movable body uses the motor driver 91 in the motor driver unit 70. By driving the accessory, the movable object accessory can be controlled by serial data together with the light emitting units (LEDs 20w, 20b) of the lamp units 63 and 64, and the control process and the configuration can be made efficient.

In one LED driver 90, a method may be adopted in which some current terminals are used for driving the LED and some other current terminals are used for driving a stepping motor, a solenoid, or the like.

In FIG. 4, the staging control unit 51 has a parallel / serial conversion unit 260. The origin switch 68 described with reference to FIG. 3 is arranged correspondingly to each of the movable body accessory motors 65 (stepping motor 121), and the signal from the origin switch 68 is sent to the parallel / serial conversion unit 260. Entered.
FIG. 4 shows an example in which the user's operation information from the operation unit 60 is also input to the parallel / serial conversion unit 260. The user's operation information is a signal corresponding to the operation of the effect buttons 11, 12, the cross key 13, and the like.
The parallel / serial conversion unit 260 is mounted on the staging control unit (effect control board) 51 as an IC separate from the one-chip microcomputer 250, for example, but may be built in the one-chip microcomputer 250.

The parallel / serial conversion unit 260 inputs, for example, 32 systems of signals, converts the input data into serial data Is, and supplies the input data to the motor controller 242.
The operation of the parallel / serial conversion unit 260 is controlled by the control signal CNT from the motor controller 242. The parallel / serial conversion unit 260 transfers serial data using the clock signal CLK.
With this configuration, the serial output controller 240 collects the origin detection state of each movable body accessory motor 65 and the user operations for the operation units 60 such as the effect switches 11 and 12, that is, the inputs required for the effect control are collectively efficient. Can be detected. Therefore, the effect control CPU 200 can efficiently grasp the effect state.

<4. Overview of operation>

The outline of the operation of the pachinko gaming machine 1 will be described.
[Design fluctuation display game]
In the pachinko gaming machine 1, a big hit lottery is performed by a random number lottery in the main control unit 50 on the condition that a predetermined starting condition, specifically, a game ball wins a prize in the upper starting opening 41 or the lower starting opening 42. Based on this lottery result, the special symbol (identification symbol for notifying the jackpot lottery result) is variablely displayed on the first special symbol display unit 80 or the second special symbol display unit 81 to start the special symbol variable display game. After a certain period of time has elapsed, the result is displayed on the special symbol display unit (80 or 81).

In the present embodiment, the big hit lottery based on the winning of the upper starting port 41 and the big hit lottery based on the winning of the lower starting opening 42 are performed independently. Therefore, the jackpot lottery result regarding the upper starting port 41 is derived and displayed on the first special symbol display unit 80 side, and the jackpot lottery result regarding the lower starting opening 42 is derived and displayed on the second special symbol display unit 81 side.
For the sake of explanation, the special symbol variation display game on the first special symbol display unit 80 side is referred to as the "first special symbol variation display game", and the special symbol variation display game on the second special symbol display unit 81 side is referred to as the "second special symbol variation display game". Called a "display game". However, the first and second special symbols are collectively referred to as "special symbol", and the first and second special symbol variation display games are collectively referred to as "special symbol variation display game".

When the special symbol variation display game is started, a decorative symbol variation display game in which a decorative symbol (game symbol) is variablely displayed on the main liquid crystal display device 32M is started, and various effects are displayed accordingly. It will be issued. Then, when the lottery result is displayed on the first and second special symbol display units (80, 81), the result is also displayed on the main liquid crystal display device 32M by the decorative symbol. That is, in this decorative symbol variation display game, an effect display that reflects the lottery result in the special symbol variation display game, that is, an effect that reflects the jackpot lottery result appears.

For example, when the result of the special symbol variation display game is "big hit", the result of the decorative symbol variation display game also reflects the "big hit". Further, the special symbol indicating a big hit is stopped and displayed on the special symbol display unit (80, 81) in a predetermined display mode, and the main liquid crystal display device 32M has "left", "middle", and "right" display areas. In a predetermined display mode in which the decorative symbols reflect the big hit lottery result on the winning effective line (for example, in each display area of "left", "middle", and "right", the three decorative symbols are "7" and "7". It is stopped and displayed in the display state of "7").

In the case of this "big hit", for example, the first big winning opening solenoid 78 or the second big winning opening solenoid 79 is driven, and the opening operation of the first big winning opening 45 or the second big winning opening 46 in a predetermined pattern is performed. It is executed, and a special gaming state (big hit game) that is more advantageous to the player than the normal gaming state occurs. In this big hit game, the big winning opening is opened until a predetermined time elapses, or until a predetermined number of game balls are won in the big winning opening, and the big winning opening is specified on condition that either of them is satisfied. Round games such as time closure are repeated a predetermined number of times.
When the big hit game is started, an opening effect for notifying that the big hit has been started is performed first, and after the opening effect is completed, the above-mentioned round game is performed for a predetermined number of rounds. In addition, during the round game, a round effect corresponding to each round is performed. Then, after the end of the specified number of rounds, an ending effect is performed to notify that the big hit is finished, and the big hit game is finished.

In this way, the special symbol variation display game and the decorative symbol variation display game have almost the same symbol game time (from the start timing to the stop display timing of the variation display), and reflect the result of the special symbol variation display game. Since things are to be expressed in the decorative symbol variation display game, these two symbol variation display games can be regarded as equivalent symbol games. For the sake of explanation, the above two symbol variation display games may be simply referred to as "symbol variation display game".

Further, based on the fact that the game ball has passed through the gate 44 (ordinary symbol start port), the main control unit 50 performs an auxiliary hit lottery by a random number lottery. The normal symbol variable display game is started by variablely displaying the normal symbol represented by the LED of the normal symbol display unit 82 according to the lottery result, and after a predetermined time elapses, the result is specified as whether the LED is on or off. Stop display by combination.

Then, in the case of "auxiliary hit", the normal electric accessory solenoid 77 is activated, the movable wing piece 42b is opened, the lower starting port 42 is opened or expanded, and the game ball is easily flowed in (starting port opened). (State), and an auxiliary gaming state (hereinafter referred to as "solenoid open game") that is more advantageous to the player than the normal gaming state occurs. In this normal electric opening game, the movable wing piece 42b is released until a predetermined time (for example, 0.2 seconds) is released, or a predetermined number (for example, 4) of game balls are won, and then a predetermined time (for example, 4) is released. 0.5 seconds) The operation of closing the movable wing piece 42b is repeated a predetermined number of times. In addition, when the game ball wins a prize in the lower start opening 42 during the Fuden opening game, the above-mentioned special symbol variation display game is also played, and the decorative symbol variation display game is played accordingly.

Here, during a special symbol variation display game, a normal symbol variation display game, a big hit game, a normal electric opening game, etc., further from the upper start port sensor 71, the lower start port sensor 72, or the gate sensor 73. When there is an input of a detection signal and the start condition is satisfied, the game information used for the winning lottery is acquired based on this detection signal, and this is the data related to the start right for playing each variable display game. As (holding data), the maximum number of holding storages (for example, up to 4), which is a predetermined upper limit, can be held and stored, except for those related to the variable display. In order to clarify the number of holdings to the player, the holding display provided as an icon image is lit and displayed on the screen by the holding number display unit 20H or the main liquid crystal display device 32M.
Normally, a variable display game is executed for each reserved ball in the order in which the reserved balls are generated. In the present embodiment, four pieces, which is the same number as the maximum number of reserved symbols, is treated as the upper limit predetermined number, up to four pieces of reserved data related to the first special symbol and the second special symbol are stored, and the fluctuation of the special symbol or the ordinary symbol is confirmed. Hold as the number of times.

[Game state]
The pachinko gaming machine 1 of the present embodiment is configured to be capable of generating a plurality of types of gaming states.
First, the pachinko gaming machine 1 of the present embodiment has a "probability variation (hereinafter referred to as" probability variation ") function" in which the main control unit 50 (CPU100) is responsible for the functional unit. There are two types of this, a probabilistic function related to a special symbol (hereinafter referred to as "special symbol probabilistic function") and a probabilistic function related to a normal symbol (hereinafter referred to as "ordinary symbol probabilistic function").

The special symbol probability change function changes the lottery probability of a big hit from a low probability (for example, 1/399) of a predetermined probability (normal probability) to a high probability (for example, 1 / 39.9), which is more advantageous than the normal gaming state. It is a function to generate a "high probability state". Under this high probability state, the jackpot lottery probability is high, so that jackpots are likely to occur.
The normal symbol probability variation function is more advantageous than the normal gaming state by changing the lottery probability per auxiliary from a low probability (for example, 1/256) to a high probability (for example, 255/256), which is a predetermined probability (normal probability). It is a function to generate a "probability change state per auxiliary". Under this auxiliary hit probability variation state, the auxiliary hit lottery probability becomes a high probability state, so that auxiliary hits are likely to occur, and the open-air game occurs more frequently, and the movable wing per unit time is higher than in the normal game state. The operation rate of the piece 42b is improved, and the operation rate is improved.

Further, the pachinko gaming machine 1 of the present embodiment has a "variable time reduction (hereinafter referred to as" time reduction ") function" in which the main control unit 50 is responsible for the functional unit. There are two types of this: a time saving function related to a special symbol (hereinafter referred to as "special symbol time saving function") and a time saving function related to a normal symbol (hereinafter referred to as "ordinary symbol time saving function").

The special symbol time reduction function shortens the average time required for one special symbol variation display game (the time from when the special symbol starts to fluctuate until it is confirmed and displayed, that is, the fluctuation time of the special symbol). It is a function to generate a "time saving state". Under the special symbol time reduction state, the average fluctuation time of the special symbol in one special symbol variation display game is shortened, and the number of big hit lottery per unit time is improved as compared with the normal game state.
In the pachinko gaming machine 1, the variation display time of the special symbol may be shortened due to the difference in the number of holdings, but in this case, the special symbol time reduction state does not occur and it is due to another control process. It is a thing.

The normal symbol time reduction function shortens the average time required for one normal symbol fluctuation display game (the time from the start of fluctuation of the normal symbol to the final display, that is, the fluctuation time of the normal symbol). It is a function to generate a "time saving state". Under the normal symbol time reduction state, the average fluctuation time of the normal symbol in one normal symbol variation display game is shortened, and the number of lottery per auxiliary per unit time is improved as compared with the normal game state. ..

Further, the pachinko gaming machine 1 of the present embodiment has an "open extension function" in which the main control unit 50 is responsible for its functional unit.
The open extension function is a function to generate an "open extension state" in which the period for opening the movable wing piece 42b and the number of times the movable wing piece 42b is opened are extended. This open extension state is a so-called "electric chew support state". Under the open extension state, the open operation period (starting opening open state time) of the movable wing piece 42b is extended from, for example, 0.2 seconds to 1.7 seconds, and the number of times of opening and closing thereof is changed from, for example, once to twice. It is extended, and the operating rate is improved, in which the operating rate of the movable wing piece 42b per unit time is improved as compared with the normal gaming state.

By operating one or a plurality of types of each of the above functions, it is possible to bring about a change in the internal gaming state of the gaming machine.
In the present embodiment, the operation start conditions of the normal symbol probability change function, the normal symbol time reduction function, and the open extension function are the same as the operation start conditions of the special symbol time reduction function, and each function operates at the same trigger. Become.

Here, it can be said that the game under the above-mentioned probability change state or time-saving state is a privilege game in which the transition to the special game state is easier than the normal game state.
That is, the main control unit 50 has a function of giving the player a privileged game such as a probability change or a time reduction.

[About hit]
In the pachinko gaming machine 1 of the present embodiment, the types of hits drawn in the special symbol variation display game, that is, the hit types targeted for the big hit lottery, are "15R low base non-probable change big hit" and "15R low base probable change α big hit". , "15R low base probability variation β jackpot", "15R high base probability variation jackpot", "2R low base probability variation jackpot", and "small hit" are provided.

<5. Main control processing>

Hereinafter, the control process of this embodiment will be described. First, the main processing by the main control unit (main control board) 50 will be described here.
FIG. 8 is a flowchart showing the main processing of the main control unit 50. The main process is started when the power is turned on without operating the initialization switch (not shown) as in the case of recovery from a power failure, and when the initialization switch is turned on and the power is turned on. May be turned on. In either case, when the power is turned on to the pachinko gaming machine 1, a voltage is supplied to each control board by the power supply board 58. In this case, the main control unit 50 (main control CPU 100) starts the main process shown in FIG.

In this main control side main process, the main control CPU 100 first executes necessary initial setting processes before the start of the game operation in step S11. For example, it first sets itself to the interrupt disabled state, sets it to a predetermined interrupt mode (interrupt mode 2), and initially sets the register value inside the CPU including each part of the microcomputer.
Next, in step S12, the main control CPU 100 determines the state (ON, OFF) of the RAM clear signal, which is the output signal of the RAM clear switch input via the input port (not shown). The RAM clear signal is a signal that determines whether or not to initialize the entire area of the RAM. The RAM clear signal usually has a value corresponding to the ON / OFF state of the initialization switch operated by the clerk of the pachinko parlor.

When the RAM clear signal is in the ON state, the main control CPU 100 advances the processing from steps S12 to S16, and zero-clears the entire area of the RAM. Therefore, the value of the backup flag set when the power is turned off becomes zero together with other checksum values.
Subsequently, in step S17, the main control CPU 100 transmits a "RAM clear display command" for notifying that the RAM area has been zero-cleared to each control board as an initialization command. Then, in step S18, for example, 30 seconds is stored in the RAM clear notification timer as the time for notifying that the RAM has been cleared.

Next, in step S19, the main control CPU 100 initially sets the CTC that outputs the interrupt signal that activates the timer interrupt operation, and sets the CPU to the interrupt enable state.
After that, as the processing of steps S20, S21, and S22, the interrupt prohibition state and the interrupt enable state are repeated until an interrupt occurs, and various random number update processes are executed during that time. In the various random number update processes in step S21, the random numbers used for changing the initial value (start value) of various random numbers used for the special symbol fluctuation display and the normal symbol fluctuation display, and the fluctuations used for selecting the fluctuation pattern. Update the random number for the pattern.
The various random numbers used for the special symbol variation display and the normal symbol variation display are, for example, random numbers related to the jackpot lottery circulating in a predetermined numerical range by increment processing (random numbers for special symbol determination used for the symbol lottery). Or, a random number related to the auxiliary hit lottery (a random number for determining the auxiliary hit used for the winning lottery per auxiliary). Further, the random numbers used for changing the initial value are an initial value random number for special symbol determination, an initial value random number for auxiliary hit determination, and the like.

In the main control RAM 102, as various random number counters used for symbol lottery related to big hit lottery, auxiliary hit lottery, variable pattern lottery, etc., a random number counter for special symbol determination, a counter for generating initial values, and a random number counter for special symbol determination. , Auxiliary hit determination random number counter Initial value generation counter, auxiliary hit determination random number counter, fluctuation pattern random number 1 counter, fluctuation pattern random number 2 counter, and the like are provided. These counters serve as random number generation means for generating random numbers by software.
In the various random number update processes in step S21, two initial value generation counters that generate initial values of the above-mentioned special symbol determination random number counter and auxiliary hit determination random number counter, a random number 1 counter for a variation pattern, and a random number 2 for a variation pattern Update the counter etc. to generate the above various soft random numbers. For example, assuming that the numerical range that can be taken as the random number 1 counter for the fluctuation pattern is 0 to 238, a value is acquired from the count value storage area for generating the value of the random number 1 for the fluctuation pattern of the main control RAM 102, and the acquired value is set to 1. Is added and then stored in the original count value storage area. At this time, if the result of adding 1 to the acquired value is 239, 0 is stored in the original random number counter storage area. The other random number counters for generating initial values are updated in the same way. The main control CPU 100 is adapted to repeatedly execute various random number update processes except during the timer interrupt process that is intermittently executed.

The above has described the case where it is determined in step S12 that the RAM clear switch is ON. The case where the RAM clear switch is OFF will be described subsequently. For example, when recovering from a power failure state, the initialization switch (RAM clear signal) is in the OFF state. In such a case, the main control CPU 100 proceeds from step S12 to S13 to determine the backup flag value. The backup flag is set to the ON state when the power is cut off, and is reset to the OFF state at the first timer interrupt process after the power is restored.
Therefore, when the power is turned on or when the power is restored from the power failure state, the backup flag should normally be in the ON state. However, if the predetermined process is not completed by the time the power is turned off for some reason, the backup flag is reset (OFF). Therefore, when the backup flag is in the OFF state, the main control CPU 100 advances the process from steps S13 to S16, and returns the operation of the gaming machine to the initial state.

On the other hand, if the backup flag is in the ON state, the main control CPU 100 advances the process from steps S13 to S14 and executes a checksum operation for calculating the checksum value. Here, the checksum operation is an 8-bit addition operation targeting the work area of the main control RAM 102.
Then, when the checksum value is calculated, this calculation result is compared with the stored value of the SUM address of the main control RAM 102. The checksum value obtained by the same checksum operation is stored in this SUM address when the power is cut off. Then, the stored calculation result is maintained by the backup power supply together with other data of the main control RAM 102. Therefore, originally, both should match by the determination in step S14.
However, there are cases where the checksum operation cannot be executed when the power is turned off, or even if the checksum operation can be executed, the data in the work area is damaged before the checksum operation of the main process is executed. In such a case, the determination result in step S14 will be inconsistent.
When data corruption is detected due to a discrepancy in the determination results, the main control CPU 100 proceeds to the processes of steps S14 to S16 to execute the RAM clear process, and returns the operating state of the gaming machine to the initial state.

If the checksum value obtained by the checksum calculation in step S14 and the stored value at the SUM address match, the main control CPU 100 proceeds to step S15, returns the stack pointer before the power is cut off based on the backup data, and returns the stack pointer. Executes the game recovery process required to start the game from the process state when the power is cut off.
When the game recovery process of step S15 is completed, the process proceeds to step S19, the CTC is initially set and the CPU is set to the interrupt enabled state, and then the interrupt prohibited state and the interrupt permitted state are set until an interrupt occurs. In the meantime, various random number update processes described above are executed (steps S20 to S22).

Next, the timer interrupt process of the main control CPU 100 will be described. FIG. 9 shows the timer interrupt processing of the main control CPU 100. This main control timer interrupt process is started by an interrupt from the CTC at regular time intervals (about 4 ms), and is interrupted and executed during the above-mentioned main process execution.

When a timer interrupt occurs, the main control CPU 100 saves the contents of the register to the stack area, and then performs a power supply abnormality check process for monitoring the power supply state from the power supply board 58 as step S51 in FIG. This power supply abnormality check process mainly monitors whether power is supplied normally. Here, in the event of an abnormality such as a power failure, a backup process is performed in which predetermined game information at the time of power failure is stored in the RAM so that the game can be restored without any trouble when the power is restored.

Next, in step S52, the main control CPU 100 performs a timer management process for managing the timer used for the game operation control. The timer values of various timers (for example, special symbol accessory operation timers) used for controlling the game operation of the pachinko gaming machine 1 are managed (updated) by this process.

In step S53, the main control CPU 100 performs an input management process. In this input management process, the detection information by various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. The detection information by the various sensors here includes, for example, an upper start port sensor 71, a lower start port sensor 72, a gate sensor (ordinary symbol start port sensor) 73, a first large winning opening sensor 75, and a second large winning opening sensor 76. , ON / OFF information (winning detection information) of the switch signal output from the winning detection switch such as the general winning opening sensor 74.
By the process of this step S53, it is monitored for each interrupt whether or not the winning is detected (the winning is generated) in each winning opening. Further, the above-mentioned "winning counter" is a counter provided corresponding to each winning opening and counting the number of winning game balls (number of winning balls). In the present embodiment, in a predetermined area of the main control RAM 102, an upper start opening winning counter for the upper starting opening 41, a lower starting opening winning counter for the lower starting opening 42a, a normal symbol starting opening winning counter for the gate 44, and a first A first large winning opening winning counter for the large winning opening 45a, a second large winning opening winning counter for the second large winning opening 46a, a winning counter for the general winning opening for the general winning opening 43, and the like are provided.
Further, in this input management process, it is also monitored whether or not there is an illegal prize based on whether or not the detection information from the prize detection switch has won a prize during the period in which the prize should be allowed. For example, if the first and second big prize opening sensors 75 and 76 detect a game ball even though the big hit game is not in progress, this is regarded as an illegal prize and the prize detection information is invalidated and invalidated. A predetermined error process is performed in the error management process of step S55 described later in order to notify the outside to that effect.

In step S54, the main control CPU 100 performs a random number management process in the timer interrupt that periodically updates the random numbers related to each variation display. In this periodic random number update process, the random number for special symbol determination and the random number for auxiliary hit determination are updated (+1 addition for each interrupt), and the start value of the random number counter is changed every time the random number counter goes around. For example, the value of the random number counter for special symbol determination is updated (+1 addition) within a predetermined range, and the value of the counter for generating the initial value of the random number counter for special symbol determination is read out every time the random number counter for special symbol determination makes one round. The value of the generation counter is stored in the special symbol determination random number counter. As a result, the start value of the special symbol determination random number counter is changed according to the value of the above generation counter, so that the count value of the special symbol determination random number counter becomes random even though the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process for monitoring the presence or absence of an abnormality in the game operation state. In this error management process, as abnormalities in the game operation state, for example, monitoring whether or not a disconnection has occurred between the boards and monitoring whether or not there has been an illegal prize have been performed, and these operation abnormalities (errors) have occurred. In that case, predetermined error processing corresponding to the error is performed.
As error processing, for example, the progress of a predetermined game operation (for example, a game ball payout operation, a game ball launch operation, etc.) is stopped, or an error notification command is transmitted to the effect control unit 51, and an error is generated by the effect means. Is notified that an error has occurred.

In step S56, the main control CPU 100 performs the prize ball management process. In this prize ball management process, the data stored in the input management process of step S53 is grasped, the above-mentioned winning counter is confirmed, and if there is a winning, a payout control command for specifying the number of prize balls is paid out. It is transmitted to the board 53.
Upon receiving this payout control command, the payout control board 53 controls the game ball payout device 55 to perform a payout operation of a designated number of prize balls. As a result, the number of prize balls corresponding to each winning opening is paid out. The number of prize balls corresponding to the winning openings is a predetermined number of winning balls per winning opening set for each winning opening x the number of prize balls corresponding to the value of the winning counter.

In step S57, the main control CPU 100 normally performs a symbol management process. In this normal symbol management process, a lottery is performed for each auxiliary in the normal symbol variation display, and based on the lottery result, the fluctuation pattern of the normal symbol and the stop display mode of the normal symbol are determined, and blinking is repeated at predetermined time intervals. Create symbol data (LED blinking display data during normal symbol fluctuation), or create stop display data (LED blinking display data during normal symbol stop display) if the normal symbol is not changing. Or something.

In step S58, the main control CPU 100 performs a normal electric accessory management process. In this ordinary electric accessory management process, the generation of an excitation signal for solenoid control for the ordinary electric accessory solenoid 77 and its data (solenoid control data) are generated based on the lottery result of the auxiliary hit lottery of the ordinary symbol management process in step S57. Make settings. Based on the data set here, an excitation signal is output to the normal electric accessory solenoid 77 in the solenoid management process of step S64 described later, whereby the operation of the movable wing piece 42b is controlled.
In step S59, the main control CPU 100 performs a special symbol management process. In this special symbol management process, a big hit lottery is mainly performed in the special symbol variation display, and based on the lottery result, the variation pattern of the special symbol (look-ahead variation pattern, variation pattern at the start of variation), special stop symbol, etc. are selected. decide.
In step S60, the main control CPU 100 performs a special electric accessory management process. In this special electric accessory management process, mainly, when the big hit lottery result is "big hit" or "small hit", the setting process necessary for executing and controlling the winning game corresponding to the hit is performed.

In step S61, the main control CPU 100 performs right-handed notification information management processing. In this right-handed notification information management process, right-handed instruction is given in situations where right-handedness is advantageous, such as an opportunity to open the first and second prize openings 45a and 46a and an electric support state in which the movable wing piece 42b is driven. Performs processing for displaying the "launch position guidance effect (right-handed notification effect)" for notifying. The right-handed instruction is, specifically, an effect operation instructing the player to aim at the right game area 3c. For example, the main liquid crystal display device 32M may display an image prompting the player to "right-handed". , A right-handed message voice is generated from the speaker 25.
When a right-handed notification effect is performed, in this right-handed notification information management process, a "right-handed instruction command" for instructing execution of the right-handed notification effect is transmitted to the effect control unit 51 as an effect control command, and this command is received. The staging control unit 51 controls the execution of right-handed notification by image or voice.
In step S62, the main control CPU 100 performs LED management processing. This LED management process is a process of outputting display data for normal symbol display and first and second special symbol display to the symbol display unit 33. By this process, the variable display and the stop display of the normal symbol and the special symbol are performed. The display data of the normal symbol created by the normal symbol management process in step S57 and the display data of the special symbol created by the special symbol display data update process during the special symbol management process in step S59 are the LED management process. It is output with.

In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management process, the operating state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. As the operation state information, the fact that the big hit game has occurred (the condition device has been activated), the fact that the small hit game has occurred, and the fact that the symbol variation display has been executed (the fact that the special symbol variation display game has started or ended). , Information such as winning information (information on the fact that a prize has been won in the starting opening or the big winning opening and the number of prize balls) is included.
In step S64, the main control CPU 100 performs a solenoid management process. In this solenoid management process, the excitation signal output process for the normal electric accessory solenoid 77 based on the solenoid control data created in the normal electric accessory management process in step S58 and the special electric accessory management process in step S60 are created. The excitation signal is output to the first and second winning opening solenoids 78 and 79 based on the solenoid control data. As a result, the movable wing pieces 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower starting port 42a and the large winning openings 45a and 46b are opened and closed.

After completing the above steps S51 to S64, the main control CPU 100 restores the contents of the saved register and sets the interrupt enabled state in step S65. As a result, the timer interrupt process is terminated, the process returns to the main control side main process of FIG. 8 before the interrupt, and the main control main process is performed until the next timer interrupt occurs.

In the above processing, the main control unit 50 (main control CPU 100) sequentially transmits necessary commands to the staging control unit 51.
As an example of the command, a part of the fluctuation pattern command and the winning command related to the winning lottery of the special symbol variation display game are shown in FIG. 10A, and a part of the symbol designation command is shown in FIG. 10B.
In the fluctuation pattern command and the winning command, the type of fluctuation pattern is defined by the upper byte and the lower byte, and the upper byte is configured to be different depending on the loss / hit.
The symbol specification command has a configuration in which the first and second special symbols are indicated by the upper byte and the hit type is specified by the lower byte.

<6. Processing of the staging control unit>

Next, the processing of the staging control unit 51 will be described. First, a structural example of scenario data for staging control will be described.
The structure of the scenario registration information will be described with reference to FIGS. 11 and 12. FIG. 11A shows the structure of scenario registration information as a main scenario and a sub-scenario. This scenario registration information is set using the work area provided in the staging control RAM 202 (for example, the built-in CPU work memory 202b).
In the present embodiment, the scenario registration information has 64 channels of scenario channels sCH0 to SCH63. The scenarios registered in each scenario channel SCH can be executed at the same time.

As shown in the figure, the information that can be registered in each scenario channel sCH includes the sub-scenario timer (scTm) used in the sub-scenario update process, the previous time (scPrevTm), and the sub-scenario execution line showing the execution line of the sound / motor sub-scenario table. (ScIx), sub-scenario execution line lmp (lmpIx) indicating the execution line of the ramp sub-scenario table, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating the execution line of the main scenario table, There are a main scenario number (mcNo), a main scenario option (mcOpt), a user option (userFn), a waiting time (delay), and a checksum (checkSum), which are optional data that can be added to the main scenario.

When starting the production by the sound output by the speaker 25, the light emission by the lamp units 63 and 64, and the driving of the movable body accessory by the movable body accessory motor 65, the standby time (delay) and the main scenario number (mcNo) are set as the scenario channels. Register to a free scenario channel from sch0 to sch63.
The wait time (delay) indicates the time from registration to the scenario channel sCH to the start of the scenario. The waiting time (delay) is subtracted by 1 at a predetermined processing timing (for example, step S104 in FIG. 15 described later). When the waiting time (delay) is 0, the process corresponding to the registered data is executed.

FIG. 13 shows an example of scenario numbers 1, 2, and 3 as a part of the main scenario table. As the scenario of each scenario number, the value of the main scenario timer (msTm) can be described as time data in each line (row) of the scenario, and the sub-scenario number (scNo) and option (OPT) can be described. .. That is, in the main scenario table, the sub-scenario (and option in some cases) to be executed is specified as the time by the main scenario timer (msTm). The scenario data end code D_SEEND or the scenario data loop code D_SELOP is described in the last line of the scenario.
The value of the main scenario timer (msTm) is incremented by 1 at a predetermined processing timing (for example, step S104 in FIG. 15 described later) from the start of the main scenario.
The scenario table of each scenario number advances to the next row after the time of the main scenario timer (msTm) in one row elapses. The time data for each row indicates when that row ends.
For example, in the case of scenario number 2, the operation of sub-scenario number 2 is specified as the time of the timer value "1500", the operation of sub-scenario number 20 is specified as the time of the next timer value "500", and the next timer value " The operation of sub-scenario number 21 is specified as the time of "2000". The next line is the scenario data exit code D_SEEND. If the scenario data end code is D_SEEND, this scenario is deleted from the scenario registration information (work).

Next, the structure of the lamp data registration information will be described with reference to FIG. 11B. As the lamp data registration information, information indicating a scenario selected from the lamp sub-scenario table, that is, an effect operation (lighting pattern) by the lamp units 63 and 64 is registered. This lamp data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the lamp data registration information has 16 channels of the lamp channels dwCH0 to dwCH15. Priority is set for each lamp channel dwCH0 to dwCH15, and the priority increases in order from the lamp channel dwCH0 to dwCH15. Therefore, the scenario (ramp sub-scenario) registered in the ramp channel dwCH15 is executed with the highest priority. Further, for example, if a scenario is registered in the lamp channels dwCH3 and dwCH10, the scenario registered in the lamp channel dwCH10 is preferentially executed.
The lamp channel dwCH0 is mainly used for a lamp effect associated with BGM (Back Ground Music), the lamp channel dwCH15 is used for an error-related lamp effect, and the lamp channels dwCH1 to dwCH14 are used for a normal effect.

As shown in the figure, the information that can be registered in each lamp channel dwCH includes a registered lighting number (lmpNew) indicating the registered lighting pattern number, an execution lighting number (lmpNo) indicating the execution lighting pattern number, and a lamp subscenario. There is an offset (offset), an execution time (time), and a checksum (checkSum) that indicate the execution line.

FIG. 14A shows an example of lamp subscenario numbers 1, 2, and 3 as a part of the ramp subscenario table. As the lamp sub-scenario of each number, the value of the time data (time) is described in each line (row) of the scenario, and the lamp channel and the lamp number indicating various lighting patterns are described. In addition, the ramp scenario data end code D_LSEND is described in the last line.

In this ramp subscenario table, the time data (time) of each line indicates the time when the line is started after the subscenario is started.
The time data in the table is compared with the main scenario timer (msTm) described above, and if they match, the lamp number of the line is registered in the lamp data registration information of FIG. 11B. The registered ramp channel dwCH is the channel indicated by the line.
For example, it is assumed that the scenario number 2 shown in FIG. 13 is registered and the sub-scenario number 2 is referred to in the above-mentioned scenario channel SCH. In the lamp sub-scenario number 2 shown in FIG. 14A, the lamp channel 5 (dwCH5) and the lamp number 5 are described with the time data (time) = 0 in the first line. In this case, when the main scenario timer (msTm) = 0, the information of the first line is first registered in the lamp channel dwCH5 of the lamp data registration information of FIG. 11B as the registration lighting number (lmpNew) = 5. The value of the sub-scenario execution line lmp (lmpIx) of the scenario registration information is updated to the value of the next line (second line). This is a registration for executing the lighting pattern operation of the lighting number 5 with a relatively low priority of the lamp channel dwCH5.
For the second line, the same processing is performed when the main scenario timer (msTm) reaches "500". That is, the registered lighting number (lmpNew) = 6 (that is, the instruction of the lighting pattern of the lighting number 6) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) is the same value in two consecutive lines, the processing for each line will be started at the same time.
In the lamp drive data creation process described later, the lamp drive data is created based on the lamp data registration information updated in this way.

Next, the structure of the motor data registration information will be described with reference to FIG. 11C. As the motor data registration information, information indicating a scenario selected from the motor sub-scenario table is registered. This motor data registration information is also set using the work area of the staging control RAM 202.
In the present embodiment, the motor data registration information is assumed to have eight channels of motor channels mCH0 to mCH7 corresponding to, for example, eight motors.
As shown in the figure, the information that can be registered in each motor channel mCH includes the execution operation number (no), the registration operation number (noNew), the operation count (lcnt), the excitation counter (tcnt), the execution step (step), and the operation line. (Offset), parent (migration source) / child (migration destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) ), Current input information (currentSw), switch information on the software (softSw), count on the software (softCnt).

FIG. 14C shows an example of the motor sub-scenario No. 1 as a part of the motor sub-scenario table. As the motor sub-scenario of each number, the time data (time) value (ms) is described in each line (row) of the scenario, and the motor and solenoid / user option information is described. The scenario data end code D_MSEND is described in the last line.

Regarding this motor sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (it is 0 at the beginning), the time data (time) value of this motor sub-scenario table is set in the sub-scenario timer (scTm). do. The time data (time) of each line indicates the timing at which the line ends. The absolute time is described in the sub-scenario timer (scTm), and therefore, the time data value to be set is the value of (time data of the relevant line)-(time data of the previous line).
The motor data (motors 0 to 3, 4 to 7) is configured to indicate the motor operation pattern number (the number of the motor operation table of FIG. 20 to be described later) in 1 byte for each motor. The operation pattern number is set in the registration operation number (noNew) and the execution operation number (no) of the motor channel corresponding to the motor number.
In step S202 of FIG. 19, which will be described later, the motor data registration information is updated, and in step S203, motor drive data is created based on the update of the motor data registration information.

FIG. 12 shows sound data registration information. As the sound data registration information, information indicating a scenario selected from the sound sub-scenario table is registered. This sound data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the sound data registration information has 16 channels of sound channels aCH0 to aCH15.
As shown in the figure, the information that can be registered in each sound channel aCH includes volume transition amount (frzVq), volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0), and stereo (frzSt). ), Loop (frzLp), phrase number hi (frzHi), phrase number low (frzLo).

FIG. 14B shows an example of sound subscenario numbers 1 and 2 as a part of the sound subscenario table. As the sound / motor sub-scenario of each number, the time data (time) value (ms) is described in each line (line) of the scenario, and BGM, warning sound, error sound, and sound control information are described. To. The scenario data end code D_SEEND is described in the last line.
Regarding this sound sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (it is 0 at the beginning), the time data (time) value of this sound sub-scenario table is set in the sub-scenario timer (scTm). do. The time data (time) of each line indicates the timing at which the line ends. The absolute time is described in the sub-scenario timer (scTm), and therefore, the time data value to be set is the value of (time data of the relevant line)-(time data of the previous line).
The BGM data of the line is composed of information registered in the sound data registration information such as the phrase number and volume value of the BGM, and is set in the sound channel aCH0 (in the case of stereo, aCH1 in addition) in the sound data registration information. ..
The warning sound data of the line is composed of information registered in the sound data registration information such as the phrase number and the volume value of the warning sound, and is set in a vacant place of the sound channels aCH2 to aCH14.
The error sound data of the line is composed of information registered in the sound data registration information such as the phrase number and the volume value of the error sound, and is set in the sound channel aCH15.
The sound control data has the lower 6 bytes as channel information and the upper 2 bytes as control information.
In step S133 of FIG. 15, which will be described later, playback output control is performed based on the scenario update process and the updated sound data registration information.

The sound sub-scenario table and the motor sub-scenario table may have a table structure integrated for each time line.

An example of the processing of the staging control unit 51 that performs the staging control using the scenario data structure as described above, particularly the processing of the staging control CPU 200, will be described with reference to FIG.
The effect control CPU 200 starts the process of FIG. 15 when the power is turned on to the gaming machine main body.

First, in step S100, the effect control CPU 200 performs necessary initial setting processing before the start of the game operation. For example, as initial setting processing, interface system initialization, interrupt setting, external memory initialization, WDT initialization, starting point return processing and control initialization of a movable body accessory, sound source control initialization, serial output controller 240 Initializes, initializes the scheduler (scenario scheduler, device scheduler, lamp scheduler, sound scheduler), initializes the system timer, initializes the liquid crystal control, and so on.
Each scheduler refers to the above-mentioned scenario registration information, motor data registration information, lamp data registration information, sound data registration information, or the progress of scenario control based on these. As the initialization process, the work area for storing the scenario registration information and the like is initialized.

When the initial setting process of step S100 is completed, the staging control CPU 200 repeats the processes after step S101.
In particular, in the present embodiment, the staging control CPU 200 executes the processes after step S101 while monitoring the frame timing of the display data in order to also perform the liquid crystal control at the same time. In this example, control is performed based on a V blank signal, which is a synchronization signal used for display control. The synchronization signal of the display data such as the V blank signal is generated in the portion of the 1-chip microcomputer 250 that realizes the VDP function. For example, it is generated by the synchronization signal generation unit 265. In this embodiment, the V blank signal is generated twice during 1/30 second (33.3 ms), which is one frame period of the displayed image.
Since the effect control CPU 200 counts up the V blank interrupt counter in response to the V blank signal, the V blank interrupt counter is counted up every 1/60 second (16.6 ms).
As a matter of course, the individual processing of the staging control CPU 200 is performed based on the processing clock having a frequency extremely higher than the frequency of the V blank signal. Each process of FIG. 15 is performed while grasping the period from the start to the end of the frame according to the V blank signal. At the start time of the frame, the processes are performed once in steps S103 to S106, and then the V blank. Steps S121 to S143 are repeated until the end of one frame period is confirmed by the value of the interrupt counter. Steps S150 to S151 are performed when the end of one frame period is detected.

In step S101, the staging control CPU 200 performs clear control on the WDT circuit 210. Therefore, the WDT circuit 210 is reset every frame if the staging control CPU 200 is in a normal processing state.
In step S102, the effect control CPU 200 confirms the frame update flag. The frame update flag is a flag for managing scheduler updates and the like in the frame period.
The frame update flag is turned off at the start of a certain frame of the display data (because it is turned off in step S151 described later at the end of the frame).
Therefore, at the frame start timing, the staging control CPU 200 proceeds from step S102 to S103.

In step S103, the effect control CPU 200 updates the drawing. For example, as described above, a display list, which is a group of drawing commands described in the order of drawing, is created, and preload execution start control is performed.
In this example, since the main liquid crystal display device 32M and the sub liquid crystal display device 32S are provided as the liquid crystal display device 32, the image data to be displayed on these liquid crystal display devices in the drawing update process in step S103. Display list is created and preloaded for each. The point of performing the processing for each of the main liquid crystal display device 32M and the sub liquid crystal display device 32S in this way is that each processing in the frame end processing in step S150 (waiting for drawing completion, switching of display screen, waiting for preload completion, start of drawing). The same applies to.

In step S104, the staging control CPU 200 updates the frame of the scenario scheduler. Specifically, this is a process of updating the waiting time (delay), the main scenario timer (msTm), and the sub-scenario timer (scTm) of the scenario registration information of FIG. 11A. That is, it can be said that the timer of the effect scenario is advanced by one timing at the start of the frame.
Then, the staging control CPU 200 turns on the frame update flag in step S105. This is information indicating that the timer of the scenario has progressed in the current frame.
Further, the staging control CPU 200 turns off the scheduler update flag in step S106. This is information indicating that the scheduler update, that is, the update of the scenario contents (scenario registration information, lamp data registration information, sound data registration information) accompanying the progress of the timer has not been performed yet.
Then, the process returns to step S101. After the effect control CPU 200 clears the WDT circuit 210, the frame update flag is ON in step S102, so that the process proceeds to step S120.

As described above, steps S103 to S106 are performed only once after the frame start timing, and in step S104, the timer of the scenario registration information is updated. As will be described later, content update and control are executed according to the progress of the timer of the scenario, and for this reason, the scenario for the effect progresses every 33.3 ms, which is one frame period. For example, the main scenario timer (msTm) advances every 33.3 ms. The time of the main scenario timer (msTm) in one row in the main scenario table of FIG. 13 corresponds to the time of the indicated value × 33.3 ms. Further, the time in one line indicated by the time in the sub-scenario table of FIG. 14 also corresponds to the time of the indicated value × 33.3 ms.

In step S120, the effect control CPU 200 branches the process according to the value of the V blank interrupt counter. If the V-blank interrupt counter has not reached "2" (that is, "0" or "1"), the process proceeds to step S121.
The V-blank interrupt counter is cleared at the end of the frame in step S150 and is incremented twice in one frame. Therefore, the V blank interrupt counter = 0 indicates the first half period of the frame, and the V blank interrupt counter = 1 indicates the second half period of the frame. The V blank interrupt counter = 2 at the V blank signal at the end of the frame.
The effect control CPU 200 advances from step S120 to S121 so as to repeat steps S121 to S143 as many times as possible during the frame period when the V blank interrupt counter is “0” or “1”.

In step S121, the effect control CPU 200 branches the process depending on whether the V blank interrupt counter is “0” or “1”. That is, whether the present is the first half or the second half of a certain frame period.
Currently, if the V blank interrupt counter = 0, that is, the first half of the frame, the process proceeds to step S122 to confirm the reception command from the main control unit 50. That is, it is confirmed whether or not one or more received commands are stored in the command reception buffer. If there is no receive command, the process proceeds to step S130.
If there is one or a plurality of received commands, the staging control CPU 200 performs command analysis processing in step S123.

Then, the staging control CPU 200 turns off the scheduler update flag in step S124. Note that turning off the scheduler update flag in step S124 means that if a command is received during the current frame period, even after the scheduler update flag has been turned off in step S131 before. It has the meaning of turning it off.

An example of the command analysis process in step S123 will be described with reference to FIGS. 17 and 18.
As described above, in step S122 of FIG. 15, the effect control CPU 200 confirms whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer, and if the effect control command is stored. The command will be read by the process shown in FIG.

In the staging control unit 51, a command reception buffer for taking in the staging control command transmitted from the main control unit 50 is prepared in the staging control RAM 202 (for example, D-RAM 202a).
First, in step S301 of FIG. 17, the effect control CPU 200 confirms the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address.
The light pointer is updated in response to command reception, and the received effect control command is stored at the address indicated by the light pointer accordingly. The read pointer is updated (step S302) when reading from the command reception buffer. Therefore, if the read pointer = the write pointer, the effect control command that has not been read yet is stored in the command reception buffer. Therefore, if the read pointer is not a write pointer, the process proceeds to step S302, and the effect control CPU 200 loads 1 byte of command data from the address indicated by the read pointer in the command reception buffer. In this case, the read pointer is incremented for the next read (load).

Actually, the presence / absence of the receive command in step S122 of FIG. 15 can also be determined by whether or not the read pointer = the write pointer. As an actual program, if the read pointer = the write pointer at the time when the command check process is first performed, it may be determined in step S122 of FIG. 15 that there is no receive command.

As described above, one effect control command is composed of two bytes, one byte as a mode and one byte as an event. In step S303 of FIG. 17, the effect control CPU 200 confirms whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit7 out of 8 bits (Bit0 to Bit7).
If the mode is set, the process proceeds to step S304 as a process of receiving higher-level data of the command, and the read command data is saved in the register "command HI byte". It also clears the "command LO byte" register. Then, the process returns to step S301.
Even if the read pointer is not equal to the write pointer, the effect control command that has not been read is stored in the command reception buffer. Therefore, the process proceeds to step S302, and the effect control CPU 200 uses the read pointer in the command reception buffer. Load 1 byte of command data from the indicated address. It also increments the read pointer.
If the read command is an event, the process proceeds from step S303 to S305 as a process of receiving lower-level data of the command, and the read command data is saved in the register "command LO byte".

By saving the command data of the mode and the event in the registers "command HI byte" and "command LO byte", the effect control CPU 200 has taken in one command.
Therefore, in step S306, the staging control CPU 200 performs processing according to the captured command. A specific example will be described later with reference to FIG.

The read pointer = write pointer is a case where the effect control command that the effect control CPU 200 has not yet captured does not exist in the command reception buffer. By confirming the read pointer = write pointer in step S301, the command analysis process as step S123 in FIG. 15 is terminated.

An example of the command correspondence process in step S306 will be described with reference to FIG.
FIG. 18A shows a basic process as a command corresponding process. In response to the reception of the 2-byte effect control command, the effect control CPU 200 first confirms in step S321 of FIG. 18A whether or not the test mode is currently in progress. If the test mode is in progress, step S322 clears all the production scenarios, stops the sound output, and turns off the LEDs in the lamp units 63 and 64. Then, the test mode is terminated in step S323.
If you are not in test mode, do not perform these processes.
Then, the staging control CPU 200 performs processing for the captured staging control command as step S330.

As the effect control command, for example, a special symbol fluctuation pattern designation command, a special symbol designation command, a hold ball subtraction command, a hold ball addition command, an error display designation command, a jackpot start designation command, and the like are set in various ways. In step S330, the staging control CPU 200 performs the process specified by the program in response to the received command. Here, four effect control commands are listed in FIGS. 18B to 18E to illustrate specific processing.

FIG. 18B shows the process S330a when the variation pattern command is taken in as the command process in the step S330.
In this case, the effect control CPU 200 performs a process of setting the symbol command waiting state in step S331. This is because the effect control CPU 200 controls the variation display of the symbol by sequentially receiving the variation pattern command and the symbol command.

FIG. 18C shows the process S330b when the symbol designation command is taken in as the command process in the step S330.
In this case, the staging control CPU 200 first confirms in step S332 whether or not the variation pattern command has been received. If it has not been received, the process ends as it is.
If the variation pattern command has already been received when the symbol designation command is received, the process proceeds to step S333, and first, the scenario registration for the operation of the accessory origin correction is performed. Then, in step S334, the symbol fluctuation flag is set. The symbol fluctuation flag is provided corresponding to each of the first special symbol, the second special symbol, and the normal symbol, and each flag represents the fluctuation state. For example, a 2-bit first special symbol fluctuation flag FZ1, a second special symbol fluctuation flag FZ2, and a normal symbol fluctuation flag FZ3 are prepared, and each of them indicates that it is changing, stopped (hit), or stopped (off). Here, with the start of fluctuation, the corresponding symbol fluctuation flag (one of FZ1, FZ2, FZ3) is set to a value indicating "changing".
If the symbol change flag is a hit, it is set to a value indicating "stopped (hit)" for a predetermined time at the end of the symbol change, and then a value indicating "stopped (off)" until the symbol change starts. Is set to.
In step S335, the staging control CPU 200 performs the fluctuation start process. After that, the fluctuation pattern command is deleted in step S336 according to the start of fluctuation.

FIG. 18D shows the process S330c when the power-on command is taken in as the command process in step S330.
In this case, the staging control CPU 200 clears the staging control RAM 202 in step S337. For example, the contents of the command reception / transmission buffer and the input information buffer for the operation unit 60 and the checksum storage area are cleared.
Then, in step S338, an error release command is transmitted, in step S339, the accessory error information is cleared, in step S340, the accessory operation is stopped, in step S341, the power-on scenario is registered, and in step S342, the power is turned on to be transmitted to the liquid crystal control board 52. Set commands in sequence.

FIG. 18E shows the process S330d when the RAM clear command is taken in as the command process in step S330.
In this case, the staging control CPU 200 clears the staging control RAM 202 in step S343. For example, the contents of the command reception / transmission buffer and the input information buffer for the operation unit 60 and the checksum storage area are cleared.
Then, in step S344, an error release command is transmitted, and in step S345, a RAM clear error set and an error notification timer are set. Further, in step S346, the information related to the lottery process in the effect control RAM 202 is cleared, and in step S347, the information related to the scenario is cleared. Then, in step S348, a power initial on display (RAM clear) command to be transmitted to the liquid crystal control board 52 is set.

The processing corresponding to the command reception has been described above.
The process of steps S122 to S124 of FIG. 15 as the process corresponding to the above command reception is started to be executed only during the period of V blank interrupt counter = 0.

Subsequently, the effect control CPU 200 confirms the scheduler update flag in step S130 of FIG. 15 and branches the process. Here, the processing of steps S131 to S134 is performed only when the scheduler update flag is off.
Then, in step S131, the frame update flag is turned on.
Since the scheduler update flag is turned off in step S106 immediately after the start of the frame, the processes of steps S131 to S134 are performed when the process of step S130 is first performed in the current frame period. Further, since the scheduler update flag is turned off in step S124, the processes of steps S131 to S134 are performed even when a command is received.

The staging control CPU 200 performs processing as a scenario scheduler execution in step S132. This is the process of updating the scenario registration information. For example, among the information registered in the scenario channel SCH, the processing corresponding to the registered data is executed for the information whose waiting time (delay) is 0. That is, processing is performed according to the specified scenario number in the main scenario table. The main scenario execution line (mcIx), sub-scenario execution line (scIx), sub-scenario execution line lmp (lmpIx), etc. are also updated.
In step S133, the staging control CPU 200 executes the sound scheduler and processes the output. This is the update processing of the sound data registration information according to the sound sub-scenario specified in the scenario table, and the output processing of the sound control signal based on the sound data registration information. The staging control CPU 200 causes the sound controller 230 to execute sound output according to the progress of the current scenario.

In step S134, the effect control CPU 200 performs the lamp scheduler execution process.
This is the process of updating the lamp data registration information according to the lamp sub-scenario specified in the scenario table.
For example, the staging control CPU 200 performs the following processing for each of the lamp channels dwCH0 to dwCH15. First, the main scenario timer (msTm) and the time data (time) of the ramp sub-scenario table are compared. The time data (time) in the ramp subscenario table indicates the time (ms) at which the line (the line indicated by the subscenario execution line lmp (lmpIx)) is started. Therefore, if the time of the main scenario timer is equal to or longer than the time data (time), the process for that line is performed.
For example, first, it is determined whether or not the current line is the line in which the ramp scenario data end code D_LSEND is described. If the line is not the line in which the lamp scenario data end code D_LSEND is described, the effect control CPU 200 acquires the lamp channel dwCH and the lamp number described in the line, and registers the lighting pattern number in the acquired lamp channel dwCH. ..
Further, the registered lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH. That is, the lamp number acquired from the line in the lamp sub-scenario table is set in the registered lighting number (lmpNew), and "0" is set in the execution lighting number (lmpNo). Also, the value of the subscenario execution line lmp (lmpIx) is incremented by 1. As described above, the lamp data registration information is updated to the state in which the lamp effect operation to be executed is registered.

In step S134, the lamp data registration information is updated as described above, and the lamp drive data creation and the lamp drive data output based on the updated lamp data registration information are performed in the later steps S141 and S142.

In step S140, the staging control CPU 200 branches the process according to the value of the V blank interrupt counter. If the V-blank interrupt counter is "0", the processes of steps S141 to S143 are executed, and if it is "1", these processes are not executed.
In step S141, the staging control CPU 200 creates lamp drive data. That is, lamp drive data that is actually output from the serial output controller 240 to the frame driver unit 61 and the panel driver unit 62 is generated based on the information registered in each lamp channel dwCH of the lamp data registration information.
Then, in step S142, the generated lamp drive data is transferred to the serial output controller 240 and controlled to be output as serial data.
In step S143, the effect control CPU 200 performs key event processing. Then, the process returns to step S101.
The process of creating and outputting the lamp drive data in steps S141 and S142 is started only when the V blank interrupt counter = 0. That is, these processes are started only during the first half of the frame.

After the V blank interrupt counter = 2, that is, when the end of the frame period is detected, the staging control CPU 200 performs the frame end processing in steps S120 to S150.
Here, the staging control CPU 200 performs processing such as waiting for drawing completion, clearing the V blank interrupt counter, switching the display screen, waiting for preload completion, and starting drawing.

FIG. 16 shows a specific example of the frame end processing.
In step S171, the staging control CPU 200 waits for the completion of drawing. This waits for the drawing of the image to be displayed in the next frame period to be completed.
As described above, the VRAM 209 is provided with frame buffers 209A and 209B, and during the frame period in which the display circuit 221 or the like reads out and displays the display data of one of them, the display data of the next frame is stored in the other frame buffer. Drawing is done. It is confirmed in step S171 that this drawing is completed.

Normally, at the end of this frame period, the drawing of the display data of the next frame is designed to be completed. If the drawing is not completed at this point, it is assumed that there is something wrong with the drawing process.
Therefore, when a drawing completion wait occurs, the waiting time may be counted and changes such as reducing the number of drawings accessed in one frame period may be made depending on the waiting time.
Further, if the wait is a little (about 1 ms), the processing of the next frame is only slightly delayed, so that there may be no particular problem.
If the drawing is not completed even after waiting for a long time, the WDT circuit 210 resets the processing of the staging control CPU 200.

After confirming the completion of drawing, the staging control CPU 200 clears the V blank interrupt counter in step S172.
Then, in step S173, the display screen is swapped. That is, the VRAM 209 switches the frame buffer for reading the display data for the frame buffers 209A and 209B.
It is conceivable that the frame buffer is switched unconditionally because the V blank interrupt counter = 2, but in the case of this embodiment, the frame buffer is switched after confirming the drawing completion in step S171. .. Therefore, the display data transferred to the display circuit 221 or the like is the display data for which drawing is completed correctly. That is, if the drawing is not completed by the second time of the vertical synchronization signal, the display data of the frame buffer being drawn will not be displayed.

In step S174, the staging control CPU 200 confirms the completion of the preload.
The preload is usually designed to finish within one frame period, but this is confirmed in step S174.
Even if the preload is delayed to some extent, the output of the display data of the next frame has already started in step S173, so that it does not cause a big problem.
After that, the display list preloaded in step S175 is written to the frame buffer opposite to the frame buffer switched to the display data read target in step S173.

After performing the above frame end processing, the frame update flag is turned off in step S151 of FIG. 15, and the process returns to step S101. Then, as explained, the processing for the new frame period is performed.

In addition to the above processing of FIG. 15, the staging control CPU 200 executes the processing of FIG. 19 as, for example, an interrupt processing every 1 ms. That is, the process of FIG. 19 is a process executed every 1 ms regardless of the frame timing of the display data.
The staging control CPU 200 performs the WDT pulse generation process in step S200. The WDT circuit 210 counts every 1 ms by this WDT pulse.
In step S201, the staging control CPU 200 performs sensor update processing for the motor and solenoid. This is a process of detecting the information of each sensor 68S as the origin switch 68 described above.

In step S202, the effect control CPU 200 performs device scheduler execution processing. Specifically, the motor data registration information is updated. Further, in step S203, the motor drive data is output to the motor driver 70 as the device scheduler output process.
That is, the staging control CPU 200 controls the motor operation every 1 ms, which is a time interval of about 1/30 of the frame period.

In the following step S204, the staging control CPU 200 performs a key input process. That is, the signals corresponding to the operations of various controls (effect buttons 11, 12, cross keys 13, etc.) in the operation unit 60 are confirmed.
As shown in FIG. 4, the detection information of the origin switch 68 and the operation information of the operation unit 60 can be detected as serial input data. Therefore, the key input process may be confirmed at the same time as the detection information of the origin switch 68 in step S201. This makes the detection process more efficient.

Although the processing example of the staging control CPU 200 has been described so far, in the above processing example, the staging control CPU 200 performs various processes according to the frame of the display data.
FIG. 20 shows various timings for each frame period of the display data.
Each frame of the display data is frame FR0, FR1, FR2, and so on. For example, the frame FR0 is displayed at the time points T0 to T1, and the frame FR1 is displayed at the time points T1 to T2.
Since the value of the V blank interrupt counter is cleared in step S150 of FIG. 15 (S172 of FIG. 16), it is "0" at the start of the frame and at the middle of the frame (time T0m, T1m, etc.) as shown in the figure. It becomes "1" and is cleared immediately after it becomes "2".

The drawing process by the drawing circuit 225 is executed for the display data of the next frame within the frame period. For example, the drawing of the display data of the frame FR1 is executed within the time points T0 to T1 during the display period of the frame FR0. Specifically, since drawing is started in step S150, drawing for the next frame is started at the beginning of the frame. This drawing is usually completed within the frame period.
If, for example, the drawing started at the time point T0 is not completed at the time point T1, the completion is awaited in step S171 of FIG.

The preload by the preloader 220 is executed one frame before in preparation for drawing. For example, the preload for drawing the display data of the frame FR2 is executed within the time points T0 to T1 during the display period of the frame FR0. Specifically, since it is started in step S103, preloading for the next frame is started at the beginning of the frame. Preloading is usually completed within the frame period.
If, for example, the preload started at the time point T0 is not completed at the time point T1, the completion is awaited in step S174 of FIG. If the preload is delayed a little, it will delay the start of drawing a little.

As the processing of the staging control CPU 200, steps S150, S151, S101, and S103 are performed at each frame start timing SLs. As shown in FIG. 20, the main processing is control of switching between frame buffers 209A and 209B, starting drawing, creating a display list, and starting preloading.
Here, during the frame period indicated by the arrow SL, the processes of the steps S121 to S143 are repeated.
However, the reception command processing (S122 to S124) is executed only during the first half of the frame indicated by the arrow CA. This is because these are executed only when the V blank interrupt counter = 0.
The analysis process of the received command is as shown in FIGS. 17 and 18, but this is a process with a relatively heavy processing load and the number of processes increases depending on the number of received commands. Depending on the type of command, it may be necessary to perform a lottery for directing. In the present embodiment, such processing is performed only in the first half of the frame.
Therefore, for the command signal, for example, for the command signal received in the period indicated by the broken line as the time points T0m to T1m, the command analysis is performed in the period from the time points T1 to T1m.

Further, the lamp data creation / output processing (S141 to S143) is also executed only during the first half of the frame, which is indicated by the arrow CA. This is because these are also executed only when the V blank interrupt counter = 0.
This prevents the frame end process (S150) from being delayed with respect to the frame end timing due to the creation and output of the lamp drive data.
If the lamp drive data output in step S142 is not performed in the latter half of the frame, it is assumed that the lamp drive data is not output from the serial output controller 240. In that case, the LED driver 90 Since the lamp drive data immediately before is maintained, the light emission operation immediately before is executed.

<7. Display of the number of grants of the embodiment>
[7-1. First example]

The pachinko gaming machine 1 of the present embodiment is given to the player according to the winning of the winning openings as the first major winning opening 45a and the second major winning opening 46a, for example, in the privileged gaming state as a probable change state or a time saving state. The cumulative value of the game balls to be played is displayed on the image display means as "cumulative grant number display"("cumulative acquisition number display" for the player).
The "cumulative value" here is the cumulative value of the number of game balls granted from the start of the special game that triggered the start of the privilege game to the end of the privilege game (hereinafter, also referred to as "the cumulative value of the privilege game unit"). Means. That is, it means the cumulative value while the special game is in the consecutive villas with the privilege game, and is reset to 0 for each privilege game.

In this example, the cumulative number of grants is displayed in a part of the display area 32Ma in the display screen of the main liquid crystal display device 32M, for example, in the form shown in FIG. In the display of the cumulative number of grants in this example, a 5-digit numerical value is displayed, and the cumulative value of the number of game balls granted can be displayed from "0000" to "99999".
The position of the display area 32Ma may be fixed or variable. In addition, the cumulative number of grants displayed in the display area 32Ma may be temporarily hidden due to the establishment of predetermined conditions in the progress of the game.

Here, regarding the cumulative number of grants displayed as described above, it is conceivable to increase the display value by the number of grants (“15” in this example) according to the prize each time a prize is awarded. In the embodiment, a method of increasing the display value by a predetermined value is adopted in order to improve the effect of the effect (hereinafter, also referred to as "first display update"). Specifically, in this example, the display value is incremented by a numerical value smaller than the number given according to the prize (for example, "1"), and the update cycle of the display value matches the frame cycle of the display image (that is,). The display value is incremented by "1" in the frame cycle).
At this time, the cumulative value (actual cumulative value) of the number of game balls granted according to the winning and the cumulative number of game balls currently displayed so that the displayed value does not exceed the actual cumulative value. The displayed value is sequentially compared with the value (cumulative value during display), and the displayed value is increased by "1" under the condition that the cumulative value during display is smaller than the actual cumulative value.
By such a method, the frequency of updating the display value of the acquired number is increased, the player can be given a stronger sense of acquisition of the game ball, and the effect of the effect can be improved.

However, the shortest period in which the displayed value can be updated is the frame period, which is limited. For this reason, in situations where the actual cumulative value suddenly increases, such as when a large number of prizes are won at one time, it takes time for the cumulative value being displayed to catch up with the actual cumulative value, and there is a risk that the inaccurate display state will continue. There is.

Therefore, in the present embodiment, while updating the display value as the first display update described above, the following display value is also updated as the second display update. That is, the display of the cumulative number of grants is updated by an update method capable of increasing the increase range of the display value of the cumulative number of grants as compared with the time of update by the first display update according to the satisfaction of the predetermined condition.

Hereinafter, a method of displaying the number of grants as a first example will be specifically described with reference to FIGS. 22 to 25.
FIG. 22 is a functional block diagram schematically showing a function related to a granting number display method as a first example among the functions of the staging control unit 51.
As shown in the figure, the effect control unit 51 serves as a command reception buffer F1, a cumulative value calculation unit F2, a first counter F3, a storage value update unit F4, a second counter F5, a display numerical conversion unit F6, and a display update unit F7. Has the function of.

As described above, the command reception buffer F1 is a buffer for storing the reception command for the effect control command transmitted by the main control unit 50, and is provided as a storage area of a part of the effect control RAM 202 (for example, D-RAM202a), for example. Has been done.
The cumulative value calculation unit F2 calculates the cumulative value of the number of game balls granted based on the effect control command from the main control unit 50 received in the command reception buffer F1.
The first counter F3 is a storage means for storing the cumulative value (actual cumulative value) calculated by the cumulative value calculation unit F2, and is prepared as a part area of the staging control RAM 202 (for example, D-RAM202a) in this example. There is.

Here, as the effect control command, there is a command indicating that the game ball has won a prize in the first prize opening 45a and the second prize opening 46a (hereinafter referred to as "winning notification command"). The cumulative value calculation unit F2 adds the number of game balls given according to the prize (“15” in this example) to the stored value of the first counter F3 each time the prize notification command from the main control unit 50 is received. , The value after addition is stored in the first counter F3.
In this example, in order to be able to identify "0000" to "99999" as the actual cumulative value, the first counter F3 can store information of at least 131072 (2 to the 17th power) bits.

The above-mentioned processing by the cumulative value calculation unit F2 is executed as a kind of each command processing (S330: see FIG. 18) in the above-mentioned command analysis processing (S123).

The storage value update unit F4 updates the storage value of the second counter F5.
The second counter F5 is a storage area for storing a value to be displayed as a cumulative grant number display in the display area 32Ma, and is prepared as, for example, a part of the staging control RAM 202 (for example, D-RAM 202a).
The storage value update unit F4 updates the storage value of the second counter F5 so that the above-mentioned first display update and second display update can be realized, which will be described later.

The display numerical conversion unit F6 converts the stored value of the second counter F5 into numerical information for display, that is, numerical information of each digit. Specifically, each numerical value of the myriad, thousands, hundreds, tens, and ones digits of the stored value of the second counter F5 is obtained as follows.
Myriad ... The quotient of the memory value of the second counter F5 divided by 10000 ... The quotient of the remainder divided by 10000 above divided by 1000. The quotient divided by 100 ... The quotient divided by 100 above and the quotient divided by 10 ... The remainder divided by 10 above

The display update unit F7 updates the value of each digit in the cumulative grant number display of the display area 32Ma according to the value of each digit obtained by the display numerical conversion unit F6. The process by the display update unit F7 is realized by steps S103 and S150 shown in FIG.

FIG. 23 is a flowchart showing a process corresponding to the first display update by the storage value update unit F4. The staging control CPU 200 executes the processes of FIG. 23 and FIG. 24 described below.
The process shown in FIG. 23 is executed so that the cycle of the determination process in step S301 coincides with the frame cycle.

In step S301, the effect control command CPU 200 determines whether or not the value of the first counter F3 is larger than the value of the second counter F5. This corresponds to determining whether or not the displayed cumulative value is smaller than the actual cumulative value with respect to the cumulative value of the number of game balls granted.

If the value of the first counter F3 is larger than the value of the second counter F5, the effect control CPU 200 increments the value of the second counter F5 by 1 in step S302, and returns to step S301. As a result, as long as it is determined in step S301 that "the value of the first counter F3> the value of the second counter F5" (that is, as long as the cumulative value being displayed is smaller than the actual cumulative value), the value of the cumulative number of grants is displayed. Will increase by one.
Such an increase in the value of the cumulative number of grants is not determined in step S301 as "value of the first counter F3> value of the second counter F5", that is, the cumulative value being displayed catches up with the actual cumulative value. It will continue until it arrives. In other words, when the cumulative value being displayed catches up with the actual cumulative value, the increase in the cumulative grant number display value is stopped until "value of the first counter F3> value of the second counter F5" again. ..

If the effect control CPU 200 determines in step S301 that the value of the first counter F3 is not larger than the value of the second counter F5, the process proceeds to step S303 and the value of the first counter F3 becomes the second counter F5. It is determined whether or not it is less than the value of (whether the cumulative value being displayed is larger than the actual cumulative value).
When it is determined that the value of the first counter F3 is not less than the value of the second counter F5 (that is, when "the value of the first counter F3 = the value of the second counter F5"), the effect control CPU 200 returns to step S301. That is, in this case, the value of the cumulative number of grants is not increased, and the increase of the value of the cumulative number of grants is stopped until "the value of the first counter F3> the value of the second counter F5" again as described above. ..

In step S303, it is determined that "the value of the first counter F3 <the value of the second counter F5" is determined when some abnormality occurs. In this case, the staging control CPU 200 proceeds to step S304, updates the value of the second counter F5 to the value of the first counter F3, and returns to step S301.
As a result, for the occurrence of an abnormality in which the value of the second counter F5, that is, the value to be displayed as the cumulative number of grants is larger than the actual cumulative value, the value larger than the actual cumulative value continues to be displayed. It is designed so that there is no such thing. That is, it is possible to ensure the display accuracy of the number of acquired game media even when an abnormality occurs.

It is also possible to perform error notification according to the number of times and frequency determined in step S303 that "the value of the first counter F3 <the value of the second counter F5".
Further, in the above, it is assumed that the value of the second counter F5 is always the cumulative value being displayed, that is, the value of the second counter F5 is unconditionally displayed as the value of the cumulative number of grants. According to this premise, the behavior during the abnormality response processing in steps S303 and S304 is that after a value larger than the actual cumulative value (only one frame) is displayed as the display value of the cumulative number of grants, the display value of the cumulative number of grants is displayed. It will be corrected to a value that matches the actual cumulative value. At this time, it is also possible to prevent a value larger than the actual cumulative value from being displayed for even one frame as the cumulative number of grants. Specifically, every time the display value of the cumulative number of grants is updated to the value of the second counter F5, it is determined whether or not "the value of the first counter F3 <the value of the second counter F5", and "the first The value of the second counter F5 may be displayed as the display value of the cumulative number of grants on condition that the value of the first counter F3 is not equal to the value of the second counter F5.
As can be understood from the above description, the value of the second counter F5 does not necessarily match the cumulative value being displayed, but can be rephrased as representing a “value to be displayed as the cumulative number of grants”.

FIG. 24 is a flowchart showing the process corresponding to the second display update.
In step S401, the effect control CPU 200 waits until a predetermined condition related to the progress of the game is satisfied. The "predetermined condition relating to the progress of the game" will be described later, but for example, it is possible to exemplify that the privileged game state as a probable change state or a time saving state ends, or that one big hit game ends. ..

When the predetermined condition relating to the game progress is satisfied in step S401, the effect control CPU 200 updates the value of the second counter F5 to the value of the first counter F3 in step S402, and ends the process shown in FIG. 24.

By the above processing, it is possible to match the display value of the cumulative number of grants with the actual cumulative value at the timing of the turning point related to the progress of the game. That is, it is possible to sequentially guarantee the accuracy of the displayed value at the timing of the turning point.

It should be noted that the display of the cumulative number of grants does not match the actual cumulative value only when the predetermined condition related to the progress of the game is satisfied, but whether or not the actual cumulative value matches the displayed cumulative value when the predetermined condition is satisfied. It is also possible to update the display of the cumulative number of grants on the condition that they do not match. This makes it possible to prevent unnecessary display updates from being performed.

With reference to FIG. 25, an example of a “predetermined condition” for monitoring the establishment in step S401 will be described.
As the timing for matching the displayed value of the cumulative number of grants with the actual cumulative value, the timing indicated by the arrow P in FIGS. 25A and 25B can be mentioned.
Specifically, the end timing or start timing of each round game during the jackpot game (during special game) as indicated by the arrow P1 in FIG. 25A, the start timing of the jackpot end interval as indicated by the arrow P2, or the arrow P3. The start timing of the jackpot start interval as represented by can be mentioned.

Further, the timing related to the end of the privileged gaming state as indicated by the arrows P4 and P5 in FIG. 25B can be mentioned. In FIG. 25B, the main liquid crystal display device 32M displays a result screen indicating that the privilege game ends with 100 jackpot consecutive villas, the deviation is derived due to the final symbol change in the privilege game, and the privilege game ends. Represents an example of being done.
The timing of the arrow P4 is the start timing of the final symbol variation, and the timing of the arrow P5 is the display start timing of the result screen. Matching the display value of the cumulative number of grants with the actual cumulative value on the result screen is display accuracy when the cumulative number of grants represents the cumulative number of grants during one award game as in this example. It is especially important for collateral.

When the display value of the cumulative number of grants matches the actual cumulative value at the timing of the arrow P1, in step S401, the main control unit 50 waits for the reception of the effect control command to be transmitted at the end of each round game. Similarly, when the display value of the cumulative number of grants matches the actual cumulative value at the timing of the arrows P2, P3, and P4, in step S401, the main control unit 50 waits for the reception of the effect control command to be transmitted at those timings. It should be done.
Regarding the timing of the arrow P5, the corresponding command transmission from the main control unit 50 may not be performed. In that case, in step S401, the staging control unit 51 waits for the occurrence of an event that occurs internally in response to the arrival of the “result screen display start timing”. For example, it waits for the occurrence of a predetermined event such as the start of drawing the result screen.

The timing of matching the displayed value of the cumulative number of grants with the actual cumulative value does not necessarily match the timing of matching the value of the second counter F5 with the value of the first counter F3. For example, in the example shown in FIG. 25A, the cumulative number of grants is displayed on condition that the first jackpot game shown in the first stage is completed and the first round of the second jackpot game shown in the second stage is started (P1). Consider the case where the value matches the actual cumulative value. In this case, there is a somewhat long period between the timing of matching the displayed value of the cumulative number of grants with the actual cumulative value and the timing of the end of the round game immediately before that (the timing of the end of the 15th round game in the first jackpot game). It is possible to intervene and match the value of the second counter F5 with the value of the first counter F3 in advance according to the satisfaction of some condition within this period. For example, at the timing of arrow P2 (start timing of the first jackpot end interval) and the timing of arrow P3 (start timing of the second jackpot start interval) in the figure, the value of the second counter F5 is set to the value of the first counter F3 in advance. For example, make them match. It is conceivable that the timing at which the value of the second counter F5 matches the value of the first counter F3 in advance is the timing at which a predetermined condition related to the progress of the game is satisfied, as shown by the arrows P2 and P3.
In order to match the displayed value of the cumulative number of grants with the actual cumulative value as described above, the value of the second counter F5 is previously set to the first counter at the prior timing (for example, the timing at which the predetermined condition relating to the game progress in advance is satisfied). By matching the value of F3, it is possible to smoothly display the cumulative number of grants when the display value of the cumulative number of grants matches the actual cumulative value.
At this time, it is desirable that the round game does not intervene between the timing of matching the displayed value of the cumulative number of grants with the actual cumulative value and the timing of matching the value of the second counter F5 with the value of the first counter F3. This is because the value of the second counter F5 is incremented by a predetermined value by updating the first display according to the winning of the game ball to the large winning opening during the round game.

Here, as described above, when the second display update as the first example of matching the display value of the cumulative number of grants with the actual cumulative value according to the fulfillment of the predetermined condition related to the progress of the game is performed, an example is shown in FIG. As such, the predetermined image Gs can be displayed in an area that at least partially overlaps with the display area (32Ma) of the cumulative number of grants.
In the example of FIG. 26A, a predetermined image Gs is inserted and displayed between the display of the cumulative number of grants before the update and the display of the cumulative number of grants after the update.
Further, in the example of FIG. 26B, the predetermined image Gs is covered and displayed on the cumulative number of grants before the update, and the cumulative number of grants after the update is displayed after the cover display. In this covering display, the predetermined image Gs has a certain transparency, and the cumulative number of grants before the update can be seen through. Further, the transparency of the predetermined image Gs at this time may be changed with time, for example, the transparency may be gradually lowered. Further, in the process of changing the transparency of the predetermined image Gs covered and displayed, the display value of the cumulative number of grants can be switched from the value before the update to the value after the update. Specifically, a state in which a semi-transparent predetermined image Gs is covered and displayed on the value of the cumulative number of grants before the update → the value of the cumulative number of grants is switched to the value after the update while making the predetermined image Gs non-transparent → the predetermined image is displayed. The display is changed in the order of translucently displaying the value of the cumulative number of grants after updating so that it can be seen through → the state of hiding the predetermined image Gs (only the value of the cumulative number of grants after updating is displayed). ..
Further, as the predetermined image Gs, as shown in FIG. 26C, not all the numerical values displayed in the display area 32Ma but only a part of the numerical values (particularly the numerical values on the lower digit side) can be overlapped and displayed. As a result, it is possible to selectively cover only the numerical value portion to be updated, and the player can easily grasp the numerical value portion that has been updated.
It is desirable that the predetermined images Gs are displayed over at least a plurality of frames so that the player can visually recognize them. For example, it is conceivable that the display period is about 0.5 to 2 seconds.

By displaying the predetermined image Gs as described above, when the display update mode of the cumulative grant number is switched from the first display update to the second display update, the predetermined image Gs is superimposed and displayed on the display area of the cumulative grant number. It is possible to do. Therefore, it is possible to alleviate the discomfort of the player due to the change of the display update mode of the cumulative number of grants from the first display update to the second display update.

[7-2. Second example]

Subsequently, a method of displaying the number of grants as a second example will be described with reference to the flowchart of FIG. 27.
In the method of displaying the number of grants as the second example, the second display update is different from the first example. That is, in the second example, the process shown in FIG. 24 is not performed.
In FIG. 27, the same step numbers are assigned to the processes that are the same as the processes already described in the first example, and the description thereof will be omitted. Also in the process of FIG. 27, the cycle of the determination process in step S301 is executed so as to coincide with the frame cycle.

In this case, when the effect control CPU 200 determines in step S301 that "the value of the first counter F3> the value of the second counter F5", the value of the first counter F3 and the value of the second counter F5 are determined in step S305. It is determined whether or not the difference value (for example, the absolute value) of is less than the first threshold value a.
If the difference value is less than the first threshold value a, the effect control CPU 200 proceeds to step S306, increments (+1) the value of the second counter F5 by 1, and returns to step S301. This is the same behavior as the first display update described in the first example.

On the other hand, when it is determined in step S305 that the difference value is not less than the first threshold value a, the staging control CPU 200 proceeds to step S307 and the difference value is equal to or more than the first threshold value a and less than the second threshold value b (a ≦ difference value). It is determined whether or not it is <b). The second threshold value b> the first threshold value a.
If “a ≦ difference value <b”, the staging control CPU 200 proceeds to step S308, increments (+2) the value of the second counter F5 by 2, and returns to step S301.

On the other hand, if “a ≦ difference value <b”, that is, “difference value ≧ b”, the staging control CPU 200 proceeds to step S309, increments (+3) the value of the second counter F2 by 3, and returns to step S301. ..

The process when it is determined in step S301 that "the value of the first counter F3> the value of the second counter F5" is the same as in the case of the first example (steps S303 and S304). That is, in this case as well, the same abnormality handling processing as in the case of the first example is performed.

As described above, in the second example, as the second display update, when the value of the first counter F3 is larger than the value of the second counter F5 and the difference value between those values is equal to or larger than the predetermined threshold value, The value of the second counter F5 is updated with a value larger than the value to be added in the first display update (“1” in this example).
As a result, when the actual cumulative value is larger than the cumulative value being displayed, the cumulative number of grants is displayed so that the increase in the display value of the cumulative number of grants increases according to the size of the difference value. Will be updated.
Therefore, the effect of suppressing the display delay with respect to the actual cumulative value can be enhanced, and the accuracy of displaying the acquired number can be improved.
In particular, in this example, the value to be added to the second counter F5 is changed in three or more stages according to the magnitude of the difference value. This makes it possible to enhance the effect of suppressing the display delay with respect to the actual cumulative value.

In the above, an example is given in which the value to be added to the second counter F5 is changed by 1 at each stage according to the magnitude of the difference value, but the added value at each stage can be arbitrarily set. Further, the stage for changing the addition value is not limited to three stages, and may be four or more stages.

Further, also in the second example, it is also possible to perform a process of updating the display of the cumulative number of grants with a value that matches the actual cumulative value according to the establishment of the predetermined condition relating to the game progress, as in the process of FIG. 24. ..

Here, in the above, in the case of updating the display as the first example and the second example, the example in which the cumulative value of the update target is only one type (only the "privilege game unit cumulative value") is given. In addition to the cumulative value of the bonus game unit, the cumulative value of the number of media grants includes, for example, the cumulative value of the number of game balls granted during one big hit game (during a special game) (“big hit unit cumulative value”) and one time. It is also possible to display the cumulative value in other units such as the cumulative value of the number of game balls granted during the round game (“round unit cumulative value”), and in that case, the cumulative value in the other units is also the first. It is also possible to update the display in the same manner as in the first example and the second example. In this case, the first counter F3 and the second counter F5 may be provided for each cumulative value to be updated.

[7-3. Third example]

The third example is a modification related to the hardware configuration and the program module configuration.
In the following description, the same parts as those already explained will be designated by the same reference numerals and the description thereof will be omitted.

In the above, as the pachinko gaming machine 1, an example in which the staging control unit 51 that comprehensively controls various staging operations also has display control functions such as drawing and display data generation for the display image of the liquid crystal display device 32 is given. However, as in the pachinko gaming machine 1A shown in FIG. 28, a liquid crystal control board 52 that has a display control function of the staging control unit 50 may be separately provided.

Compared to the pachinko gaming machine 1, the pachinko gaming machine 1A shown in FIG. 28 is provided with a staging control unit (effect control board) 51A in place of the staging control unit 50, and has a liquid crystal interface board 66, a liquid crystal control board 52, and a sound source. The difference is that the IC59 and the sound data ROM 69 have been added.
Note that FIG. 28 illustrates a configuration including a single liquid crystal display device 32 for convenience of explanation, but of course, the main liquid crystal display device 32M and the sub liquid crystal display device 32S are provided as in the case of FIG. It can also be configured.

The sound source IC 59 and the sound data ROM 69 have a function corresponding to the sound controller 230 shown in FIG. That is, the sound source IC 59 decodes the compressed audio data stored in the sound data ROM 69 based on the control of the effect control unit 51A (effect control CPU 200) to generate an output audio signal, and outputs the output audio signal to the external amplifier unit 67. ..

In this case, the main roles of the staging control unit 51A are receiving the staging control command from the main control unit 50, determining the selection of the staging based on the staging control command, transmitting the liquid crystal control command to the liquid crystal control board 52 side, and the sound source IC 59. Control, light emission control of the light emitting units 20w and 20b (LED), operation control of the movable body accessory, and the like.

The staging control unit 51A transmits a liquid crystal control command to the liquid crystal control board 52 side, and the liquid crystal control command is sent to the liquid crystal control board 52 via the liquid crystal interface board 66.
Although not shown, the liquid crystal control board 52 includes a VDP (Video Display Processor), an image ROM, a VRAM (Video RAM), a liquid crystal control CPU, a liquid crystal control ROM, and a liquid crystal control RAM.
The VDP controls overall video output processing such as image development processing and image drawing. The image ROM stores image data (effect image data) for which VDP performs image development processing. The VRAM is an image memory area that temporarily stores the image data developed by the VDP.
The liquid crystal control CPU outputs control data necessary for the VDP to perform display control.
The liquid crystal control ROM stores a program that describes the display control operation procedure of the liquid crystal control CPU and various data necessary for the display control.
The liquid crystal control RAM functions as a work area or a buffer memory.

With these configurations, the liquid crystal control board 52 generates various image data based on the liquid crystal control command from the staging control unit 51A and outputs the various image data to the liquid crystal display device 32. As a result, various effects images are displayed on the liquid crystal display device 32. Specifically, the liquid crystal control CPU of the liquid crystal control board 52 acquires the liquid crystal control command obtained by the effect control unit 51A analyzing the reception command from the main control unit 50, and analyzes the liquid crystal control command. Image data is generated based on the analysis result and output to the liquid crystal display device 32.

As described above, in the pachinko gaming machine 1A, the computer device (effect control unit 51A) having a function of comprehensively controlling various effect operations is separately a computer device having a function of performing image display control of the liquid crystal display device 32. (Liquid crystal control board 52) is provided. Hereinafter, such a configuration is also referred to as a “2 CPU configuration”. On the other hand, a configuration in which both of these functions are integrated into a single computer device, such as the staging control unit 51, is also referred to as a “1 CPU configuration”.

FIG. 29 is a functional block diagram showing a functional configuration for realizing display update as the first example and the second example described above in the case of the above-mentioned two CPU configuration.
As shown in the figure, the effect control unit 51A has a command reception buffer F11, a cumulative value calculation unit F2, an effect control side first counter F31, and a transmission numerical conversion unit F8, and the liquid crystal control board 52 has a command reception buffer. It has an F12, an inverse conversion unit F9, a liquid crystal control side first counter F32, a storage value update unit F4, a second counter F5, a display numerical conversion unit F6, and a display update unit F7.

On the effect control unit 51A side, the command reception buffer F11 is the same as the command reception buffer F1. Further, the first counter F31 on the effect control side is a buffer for storing the actual cumulative value calculated by the cumulative value calculation unit F2.

Here, in the case of a two-CPU configuration, the liquid crystal control board 52 generates display data for performing various displays including the cumulative number of grants, but the liquid crystal control board 52 is based on the liquid crystal control command transmitted by the staging control unit 51A. It works. Therefore, the effect control unit 51A also transmits the numerical information necessary for displaying the cumulative number of grants to the liquid crystal control board 52 side by the liquid crystal control command.

At this time, the data length of the liquid crystal control command is defined as a predetermined length, as in the staging control command. Specifically, in this example, the liquid crystal control command has a 2-byte configuration consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT) as well as the staging control command.
As described above, since the cumulative grant number display corresponds to 5 digits, at least 17 bits are required for the cumulative value information, which is a bit length that cannot be transmitted by a single liquid crystal control command.

Therefore, in this example, the cumulative value to be transmitted to the liquid crystal control board 52 side is divided into the values of each digit and transmitted by a plurality of liquid crystal control commands.
The transmission numerical conversion unit F8 is responsible for this function. Specifically, the value of the first counter F31 on the effect control side is processed in the same manner as the display numerical conversion unit F6 described above to obtain the value of each digit. Get (eg 4 bits). Then, the value of each digit is transmitted to the liquid crystal control board 52 side by a plurality of liquid crystal control commands.

On the liquid crystal control board 52 side, the command reception buffer F12 is used as a buffer for receiving the liquid crystal control command.
When the liquid crystal control command including the information of the value of each of the above digits is stored in the command reception buffer F12, the inverse conversion unit F9 obtains the value of each digit according to the liquid crystal control command and converts it into the original numerical information. (Reverse conversion). Specifically, "0000" to "99999" are converted into numerical information having at least 17 bits that can be identified.

The first counter F32 on the liquid crystal control side stores numerical information (actual cumulative value information) obtained by the inverse conversion unit F9.
In this case, the storage value update unit F4 performs the update processing of the value of the second counter F5 described in the first example and the second example above, using the storage value of the first counter F32 on the liquid crystal control side as the above-mentioned actual cumulative value. (See FIGS. 23, 24, 27).
The processing of the display numerical conversion unit F6 and the display update unit F7 is the same as that described above.

By providing the numerical value conversion unit F8 for transmission and the inverse conversion unit F9 as described above, in the case where the effect control unit 51A should transmit the numerical value information used for displaying the cumulative number of grants by the liquid crystal control command in the two CPU configuration, the numerical value is said. Information can be transmitted properly.

Here, in the one CPU configuration shown in FIG. 22, there is an advantage that it is not necessary to perform the processing of the transmission numerical conversion unit F8 and the inverse conversion unit F9 as described above. There is also an advantage that the number of counters can be reduced.

In the above, an example in which the storage value update unit F4 for performing the update process as the first example and the second example is provided on the liquid crystal control board 52 side is shown, but the storage value update unit F4 is on the staging control unit 51A side. It can also be installed in. In that case, the effect control side second counter is provided on the effect control unit 51A side, and the storage value update unit F4 updates the value of the effect control side second counter. In this case, the transmission numerical conversion unit F8 converts the value of the second counter on the effect control side and transmits it to the liquid crystal control board 52 side by the liquid crystal control command. On the liquid crystal control board 52 side, the first counter F32 on the liquid crystal control side is omitted, and the value inversely converted by the inverse conversion unit F9 is stored in the second counter F5.

Here, the processing of the transmission numerical conversion unit F8 and the inverse conversion unit F9 as described above can be performed even in the case of one CPU configuration.
Specifically, for example, as shown in FIG. 30, the staging control function unit F51A that functions as the staging control unit 51A and the liquid crystal control function unit F52 that functions as the liquid crystal control board 52 are combined by one computer device. This is a case where the staging control unit 51B, which is designed to be realized by processing, is used.

As can be seen in comparison with FIG. 29, the functions of the staging control function unit F51A are the same as the functions of the staging control unit 51A (F11, F2, F31, F8). Further, the functions of the liquid crystal control function unit F52 are the same as the functions of the liquid crystal control board 52 (F12, F9, F32, F4, F5, F6, F7).

According to the 1 CPU configuration shown in FIG. 30, the program for realizing the function as the staging control function unit F51A is almost the same as the program for realizing the function by the staging control unit 51A, and similarly, the liquid crystal control function unit. The program for realizing the function as F52 is almost the same as the program for realizing the function by the liquid crystal control board 52.
That is, in realizing the one-CPU configuration shown in FIG. 30, the program of the staging control unit 51A and the program of the liquid crystal control board 52 in the existing two-CPU configuration can be used almost as they are, and the one-CPU configuration can be used. It is possible to reduce the work load related to program creation for realization.
Here, according to the one-CPU configuration, the number of computer devices to be used for the gaming machine can be reduced, and the cost can be reduced by reducing the number of parts.

In the one CPU configuration shown in FIG. 30, the program for realizing the staging control function unit F51A and the liquid crystal control function unit F52 can be configured as independent program modules.

<8. Summary of Embodiments and Modifications>

According to the gaming machine (pachinko gaming machines 1, 1A) as the above embodiment, the processing for the effect control can be made more efficient, and the appropriate effect control can be realized.
In addition, the staging control processing load can be reduced.

Further, the gaming machine as an embodiment includes a display means (main liquid crystal display device 32M, liquid crystal display device 32) capable of displaying an image related to the game, and a main control means (main control unit 50) for controlling the progress of the game operation. The main control means is provided with sub-control means (effect control unit 51 or effect control unit 51A and liquid crystal control board 52 or effect control unit 51B) that controls the display means based on instructions from the main control means. However, it has a special game granting means capable of granting a special game advantageous to the player for a predetermined period of time as compared with a normal gaming state according to the establishment of a specific condition, and a predetermined granting condition during the special game. Is a gaming machine in which a predetermined number of game media are given to the player according to the establishment of the above, and the cumulative number of the game media is displayed in the display means. Cumulative value counting means (cumulative value calculation unit F2) that counts the cumulative value of the number of grants of the game medium based on the instruction information transmitted according to the display means, and the cumulative number of cumulative grants displayed on the display means during display. The value is compared with the actual cumulative value, which is the cumulative value counted by the cumulative value counting means, and if the actual cumulative value is larger than the displayed cumulative value, the value obtained by adding the predetermined value to the displayed cumulative value is used. It has a first display updating means (for example, see FIG. 23) for updating the display of the cumulative number of grants.

As a result, it is possible to increase the frequency of updating the value of the cumulative number of grants, and it is possible to give the player a stronger sense of acquisition of the game medium.
Therefore, it is possible to improve the staging effect by increasing the acquisition feeling of the game medium.

Further, in the gaming machine as the embodiment, the sub-control means can increase the increase range of the display value of the cumulative number of grants larger than that at the time of the update by the first display update means, depending on the establishment of the predetermined condition. It has a second display updating means (see, for example, FIG. 24 or FIG. 27) for updating the display of the cumulative number of grants by the updating method.
As a result, while the effect of enhancing the acquisition feeling of the game medium is realized by the first display updating means, the second display is updated even if the difference between the actual cumulative value and the displayed cumulative value becomes large due to, for example, a large number of prizes. It is possible to update the display so as to further increase the increase range of the display value of the cumulative number of grants by means.
Therefore, it is possible to achieve both an improvement in the effect of the effect by enhancing the acquisition feeling of the game medium and a guarantee of accuracy in displaying the number of acquisitions of the game medium.

Further, in the gaming machine as an embodiment, the first display updating means performs comparison in the frame period of the display image by the display means.
This makes it possible to update the display of the cumulative number of grants at the maximum frequency.
Therefore, the possibility of display delay with respect to the actual cumulative value can be minimized.

Furthermore, in the gaming machine as the embodiment, the second display updating means updates the display of the cumulative number of grants by a value that matches the actual cumulative value according to the establishment of the predetermined condition relating to the progress of the game.
This makes it possible to match the displayed value of the cumulative number of grants with the actual value at the timing of the turning point related to the progress of the game, such as the timing when the special game ends or the timing when the round game ends. That is, it is possible to sequentially guarantee the accuracy of the displayed value at the timing of the turning point.
Therefore, it is possible to improve the accuracy of the acquisition number display while improving the effect of the effect by enhancing the acquisition feeling of the game medium.
Further, in this case, in order to ensure the accuracy of the acquired number display, it is not necessary to sequentially compare the actual cumulative value and the displayed value as in the first display updating means. Therefore, the processing load can be reduced.

Further, in the gaming machine as the embodiment, in the first display updating means, the actual cumulative value is larger than the displayed cumulative value, and the difference value between the actual cumulative value and the displayed cumulative value is less than a predetermined threshold value. In the case, the display of the cumulative number of grants is updated by the value obtained by adding the predetermined value to the cumulative value being displayed, and the second display updating means is displayed as the actual cumulative value because the actual cumulative value is larger than the cumulative value being displayed. When the condition that the difference value from the medium cumulative value is equal to or higher than the predetermined threshold value is satisfied, the display of the cumulative number of grants is updated by adding a value larger than the predetermined value to the displayed cumulative value.
As a result, when the actual cumulative value is larger than the cumulative value being displayed, the cumulative number of grants is displayed so that the increase in the display value of the cumulative number of grants increases according to the size of the difference value. Will be updated.
Therefore, it is possible to enhance the effect of suppressing the display delay with respect to the actual cumulative value, and it is possible to improve the accuracy of the acquisition number display while improving the staging effect by enhancing the acquisition feeling of the game medium.

Furthermore, in the gaming machine as an embodiment, when the value to be displayed as the cumulative grant number is larger than the actual cumulative value, the sub-control means displays the cumulative grant number by a value that matches the actual cumulative value. Has a third display updating means (see steps S301, S303, S304 in FIGS. 23 and 27) for updating.
As a result, control is performed so that a value larger than the actual cumulative value will not continue to be displayed in response to the occurrence of an abnormality in which the value to be displayed as the cumulative number of grants is larger than the actual cumulative value. Will be.
Therefore, it is possible to improve the accuracy of the acquisition number display.

Further, in the gaming machine as an embodiment, the sub-control means includes a first storage means (first counter F3, or an effect control side first counter F31 and a liquid crystal control side first counter F32) for storing actual cumulative values. , The first storage means has a second storage means (second counter F5) capable of storing numerical information separately, and the first display update means is the storage value of the first storage means and the second storage means. A comparison with the storage value is performed, and if the storage value of the first storage means is larger than the storage value of the second storage means, a predetermined value is added to the storage value of the second storage means, and the second storage means after the addition is added. The display of the cumulative number of grants is updated based on the stored value of.
As a result, both the storage means for storing the value to be compared with the actual cumulative value and the storage means for storing the value to be displayed as the cumulative number of grants are used.
Therefore, it is possible to make effective use of storage resources.

Further, in the gaming machine as the embodiment, the sub-control means can increase the increase range of the display value of the cumulative number of grants larger than that at the time of the update by the first display update means, depending on the establishment of the predetermined condition. A second display updating means for updating the display of the cumulative number of grants by the updating method, and a first storage means for storing the actual cumulative value (first counter F3, or the first counter F31 on the effect control side and the first counter F32 on the liquid crystal control side). ) And a second storage means (second counter F5) capable of storing numerical information separately from the first storage means, and the first display update means is the storage value and the second storage of the first storage means. A comparison is made with the storage value of the means, and if the storage value of the first storage means is larger than the storage value of the second storage means, a predetermined value is added to the storage value of the second storage means, and the second after the addition. The display of the cumulative number of grants is updated based on the storage value of the storage means, and the second display update means increases the storage value of the second storage means as compared with the time of updating by the first display update means, depending on the satisfaction of the predetermined condition. The storage value of the second storage means is updated by an update method capable of increasing the width, and the display of the cumulative number of grants is updated based on the storage value of the second storage means after the update.
As a result, the storage means for storing the value to be compared with the actual cumulative value and the storage means for storing the value to be displayed as the cumulative number of grants can be shared, and the storage resource can be effectively used.

Further, in the gaming machine as the embodiment, when the second display updating means updates the display of the cumulative grant number with a value that matches the actual cumulative value, at least a part of the display area overlaps with the display area of the cumulative grant number. Is displaying a predetermined image (see FIG. 26).
As a result, when the display update mode of the cumulative grant number is switched from the first display update to the second display update, it is possible to superimpose the predetermined image on the display area of the cumulative grant number.
Therefore, it is possible to alleviate the discomfort of the player due to the change of the display update mode of the cumulative number of grants from the first display update to the second display update.

It should be noted that the present invention is not limited to the examples given in the embodiments, and various modified examples and application examples can be considered.
In the above, an example of managing the timing based on the V blank signal as a signal synchronized with the frame of the display data is given, but a vertical synchronization signal other than the V blank signal may be used, or the horizontal synchronization signal may be counted within the frame period. Timing management may be performed.

Further, in the above, an example of using a liquid crystal display device as an image display means has been given, but other image display means such as an organic EL (Electro Luminescence) display device can also be used.

Further, in the above, the display update cycle of the cumulative number of grants given by the first display update means is matched with the frame cycle, but the display update cycle must be matched with the frame cycle, for example, by setting the cycle to be twice the frame cycle. There is no.

Further, in the above, although the example in which the present invention is applied to a ball game machine such as the pachinko game machine 1 or 1A is shown, it can also be applied to a rotating cylinder type game machine (so-called slot machine).
In a revolving gaming machine, normally, a predetermined number of game media (game medals) are consumed for each game, so the cumulative value of the number of game media granted is calculated by reflecting the consumption of the bets. I do. At this time, the behavior of reducing the value of the first counter F3 is included, but it can be assumed that the medal insertion command indicating the medal insertion is received more than the predetermined number of bets in one game due to an error. , The value update process of the first counter F3 is performed so that the reduction amount in one game does not exceed the predetermined bet number.

1,1A Pachinko game machine 20w, 20b Light emitting unit 32 Liquid crystal display device 32M Main liquid crystal display device 32S Sub liquid crystal display device 50 Main control board (main control unit)
51, 51A, 51B Staging control board (staging control unit)
52 LCD control board 200 Staging control CPU
201 Staging control ROM
202 Staging control RAM
250 Microcomputer 32Ma Display area Gs Predetermined image F1, F11, F12 Command reception buffer F2 Cumulative value calculation unit F3 First counter F4 Storage value update unit F5 Second counter F6 Display numerical conversion unit F7 Display update unit F8 Numerical conversion for transmission Part F9 Inverse conversion part F31 Direction control side first counter F32 Liquid crystal control side first counter

Claims (1)

Multiple staging means, including display means for displaying staging images,
A control means for controlling the operation of the plurality of effect means according to a received command is provided.
The control means is
The image control process for displaying the effect image is performed based on the frame synchronization signal used for transferring the display data to the display means, and at the same time.
It is configured to analyze the received command within one frame period of the image displayed by the display means specified by the frame synchronization signal.
The analysis process is started only in the frame front end side period from the frame start timing to the elapse of a predetermined time within one frame period of the image displayed by the display means, and is started a plurality of times within the one frame period. Made feasible,
The staging means include sound staging means for producing a sound-related staging.
The control means is
A gaming machine that outputs sound control information based on the command after the analysis process is performed and before the next frame period starts.

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