JP6902647B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine such as a ball-and-ball gaming machine and a rotating body gaming machine, and more particularly to a production control in the gaming machine.

Japanese Patent No. 461391

In ball game machines (so-called pachinko game machines) and rotating body game machines (so-called slot game machines), for production using a liquid crystal display unit that displays various images such as production images, LEDs (Light Emitting Diodes), etc. It is equipped with production means for executing production operations, such as a light emitting unit that lights and blinks, a voice output unit that produces sound effects such as music, sound effects, and dialogue, and a movable body accessory driven by a motor. By controlling each of these production means in cooperation with each other, a game production that enhances the interest is realized.

The above-mentioned Patent Document 1 discloses a technique in which an effect control unit outputs and controls drive data for light emission drive as serial data to an LED driver for light emission effect.

In such a gaming machine, in addition to the original control of the game operation, various effects and display operations using a liquid crystal display, a light emitting unit, a sound output unit, a movable body accessory, etc. are performed. Therefore, the effect operation is performed. The control load of the microcomputer that controls the above tends to increase.
Therefore, an object of the present invention is to improve the efficiency of control processing of a microcomputer or the like for effect control so that appropriate effect control can be executed.

The gaming machine of the present invention controls a display means for displaying an effect image, a light emitting means for performing a light emitting operation as an effect emission different from the effect image, and at least the display of the display means and the light emission of the light emitting means. A control means is provided, and the control means can execute analysis processing of a received command a plurality of times within one frame cycle of an image displayed by the display means, and the analysis processing is described in the above-mentioned analysis processing. It starts only in the frame front end side period from the frame start timing to the detection of the lapse of a predetermined time within one frame period of the image displayed by the display means.
The gaming machine includes a plurality of effect means including a display means for displaying an effect image and a light emitting means, and a control means for controlling the operation of the effect means in response to a received command. The drive control related to the light emitting means and the image control process for displaying the effect image in the display means are performed based on the frame synchronization signal used for transferring the display data to the display means and controlling the display operation, and a plurality of frames are performed. The buffer area is sequentially switched between the first area for reading the display data of the image displayed by the display means and the second area for drawing the display data of the next frame, and is defined by the frame synchronization signal. At the end of one frame period of the image displayed by the display means, confirmation and drawing of the display data of the image of the next frame in the frame buffer area which is the second area are confirmed and drawn. An image stored in the image material data storage means for switching the allocation as the first area and the second area after the completion confirmation and for the next frame of the frame for which the drawing completion is confirmed after the switching. Confirmation of completion of the preload process for storing data in a predetermined storage area, start of drawing using the frame buffer area switched to the second area after the completion of the preload process, and further next to the frame in which drawing is started. The preload process for the frame is started, and the preload process is a process of transferring an image data material whose storage position is indicated as being in the ROM area in the setting information for setting the image content to a predetermined storage area. Therefore, the setting information may be rewritten so that the storage position of the image data material becomes the storage position after transfer according to the preload processing.
Further, the gaming machine includes a plurality of effect means including a display means for displaying an effect image and a light emitting means for performing a light emitting operation, and a control means for controlling the operation of the effect means in response to a received command. Is to perform all or part of the processing for controlling the light emission of the light emitting means and the analysis processing of the received command in a predetermined time from the frame start timing within one frame period of the image displayed by the display means. It may be started if it is the frame front end side period until the detection, and may not be started in the frame end side period that is the period after the predetermined time elapse is detected.
The frame end side period is a period detected as a period after a predetermined time elapses from the frame start time within the frame period until the timing at which the frame ends. For example, it is the latter half period when one frame period is divided into the first half and the second half. In this frame end side period, all or part of the processing for light emission control is skipped. Furthermore, the command analysis process is not started.
Further, in the above-mentioned gaming machine, the control means may detect the start timing of the frame end side period by a counter that counts based on the frame synchronization signal of the image displayed by the display means. ..
For example, a counter that counts based on a signal synchronized with an image frame such as a vertical blanking signal recognizes the start timing of the frame end period. This makes it possible to facilitate timing management.

According to the present invention, it is possible to improve the efficiency of control processing of a microcomputer or the like for effect control and realize appropriate effect control.

It is a perspective view of the pachinko gaming machine of embodiment of this invention. It is a front view of the board surface of the pachinko gaming machine of the embodiment. It is a block diagram of the control structure of the pachinko gaming machine of embodiment. It is a block diagram of the effect control part of embodiment. It is a block diagram of the display control system of the effect control part of embodiment. It is explanatory drawing of the driver configuration of embodiment. It is explanatory drawing of the LED driver of embodiment. It is explanatory drawing of the motor controller and the motor driver of embodiment. It is a flowchart of the main control main process of embodiment. It is a flowchart of the main control timer interrupt processing of embodiment. It is explanatory drawing of the command of embodiment. It is explanatory drawing of the scenario registration information, the lamp data registration information, and the motor data registration information of an embodiment. It is explanatory drawing of the sound data registration information of embodiment. It is explanatory drawing of the main scenario table of embodiment. It is explanatory drawing of the sub-scenario table of embodiment. It is the flowchart of the effect control main processing of 1st Embodiment. It is a flowchart of the frame end processing of embodiment. It is a flowchart of the command analysis processing in the effect control of embodiment. It is a flowchart of the command correspondence processing in the effect control of embodiment. It is a flowchart of the effect control timer interrupt process of embodiment. It is explanatory drawing of the motor operation table of embodiment. It is explanatory drawing of the display control timing of 1st Embodiment. It is the flowchart of the effect control main processing of 2nd Embodiment. It is a flowchart of the effect control main process of 3rd Embodiment. It is explanatory drawing of the display control timing of the 3rd Embodiment.

Hereinafter, a pachinko gaming machine will be taken as an example of an embodiment of the gaming machine according to the present invention, and will be described in the following order.
<1. Structure of pachinko machine>
<2. Control configuration of pachinko machine>
<3. Composition of production control unit>
<4. Outline of operation>
<5. Main control processing>
<6. Processing of the production control unit of the first embodiment>
<7. Processing of the production control unit of the second embodiment>
<8. Processing of the production control unit of the third embodiment>
<9. Summary and modification examples>

<1. Structure of pachinko machine>
First, the configuration of the pachinko gaming machine 1 as the embodiment of the present invention will be schematically described with reference to FIGS. 1 and 2.
FIG. 1 is a front perspective view showing the appearance of the pachinko gaming machine 1 of the embodiment, and FIG. 2 is a front view of the gaming board.
The pachinko gaming machine 1 shown in FIGS. 1 and 2 is mainly composed of a “frame portion” and a “game board portion”.
The "frame portion" includes a front frame 2, an outer frame 4, a glass door 5, and an operation panel 7, which will be described below. The "game board section" is composed of the game board 3 of FIG. In the following description, the "frame portion" or "frame side" is a general term for the front frame 2, the outer frame 4, the glass door 5, and the operation panel 7. Further, the “board portion” or “board side” refers to the game board 3.

As shown in FIG. 1, in the pachinko gaming machine 1, a frame-shaped front frame 2 is attached to the front surface of a wooden outer frame 4 so as to be openable and closable. Although not shown, a game board storage frame is formed on the back surface of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the game area 3a formed on the surface of the game board 3 faces the front side of the game machine of FIG. 1 from the opening 2a of the front frame 2.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the player side on the front side via the transparent glass.

The glass door 5 is attached to the front frame 2 so as to be openable and closable by a shaft support mechanism 6. Then, by operating a door unlocking key cylinder (not shown) provided at a predetermined position of the glass door 5, the locked state of the glass door 5 with respect to the front frame 2 can be released, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can be released by operating the door lock release key cylinder.
Further, on the front side of the glass door 5, light emitting portions 20w are provided in various places as light emitting means on the frame side. For example, the light emitting unit 20w performs a light emitting operation for directing, a light emitting operation for error notification, a light emitting operation according to an operating state, and the like as a light emitting operation by the LED.

An operation panel 7 is provided on the lower side of the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a shaft support mechanism (not shown).
The operation panel 7 is provided with an upper saucer unit 8, a lower saucer unit 9, and a firing operation handle 10.

The upper saucer unit 8 is formed with an upper saucer 8a for storing a game ball to be used as a bullet. The lower saucer unit 9 is formed with a lower saucer 9a for storing game balls that cannot be stored in the upper saucer 8a.
Further, the upper saucer unit 8 is provided with a ball removal button 16 for pulling out the game ball stored in the upper saucer 8a toward the lower saucer 9a. The lower tray unit 9 is provided with a ball pulling lever 17 for pulling out the game ball stored in the lower tray 9a below the gaming machine.
Further, the upper tray unit 8 has a ball lending button 14 for requesting the payout of the game ball to the game ball lending device (not shown), and a card for requesting the return of the valuable value medium inserted in the game ball lending device. A return button 15 is provided.
Further, the upper saucer unit 8 is provided with effect buttons 11 and 12, and a cross key 13. The effect buttons 11 and 12 are push buttons that can be operated by turning on the built-in lamp during a predetermined input acceptance period, and can bring about a change in the effect by pressing the effect buttons when the built-in lamp is lit. Further, the cross key 13 is an operator for the player to perform an operation according to the effect situation, an operation for setting the effect, and the like.

The launch operation handle 10 is provided on the right end side of the operation panel 7, and is an operator for the player to operate the launch device 32 shown in FIG. 3 for the ball.
Further, speakers 25 for acoustically outputting the effect sound are provided on both sides of the upper portion of the front frame 2 and in the vicinity of the firing operation handle 10.

Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or resin board. A ball guide rail 31 for guiding the launched game ball is annularly mounted on the game board 3 as a board surface partition member, and a substantially circular region surrounded by the ball guide rail 31 is referred to as a game area 3a. It has become.

A main liquid crystal display device 32M (LCD: Liquid Crystal Display) is provided in a substantially central portion of the game area 3a, and a sub liquid crystal display device 32S is provided on the right side of the main liquid crystal display device 32M.
In the main liquid crystal display device 32M, under the control of the effect control unit 51, which will be described later,, for example, three decorative symbols, left, middle, and right, are variablely displayed on the background image. In addition, various production images such as normal production, reach production, and super reach production are also displayed. Similarly, the sub-liquid crystal display device 32S also displays according to various effects.

Further, in the game area 3a, a center decoration 35C is provided so as to surround the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The center decoration 35C not only exerts a decorative effect due to its design, but also has a function of protecting the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S from surrounding game balls. Further, the center decoration 35C also functions as a member that enables the left and right strikes of the flow path of the game ball according to the launch strength or the stroke length of the game ball. That is, the flow path of the game ball launched to the upper part of the game area 3a via the ball guide rail 31 flows down either the left game area 3b or the right game area 3c divided by the center decoration 35C. In the case of so-called left-handed, the game ball flows down the left game area 3b, and in the case of right-handed, the game ball flows down the right game area 3c.

Further, a lower left decoration 35L is provided below the left game area 3b to exert a decorative effect and define a range as the left game area 3b.
Similarly, a lower right decoration 35R is provided below the right game area 3c to exert a decorative effect and define the range as the left game area 3b.
In the game area 3a (left game area 3b and right game area 3c), nails 49 and windmills 47 are provided at required locations to form various flow paths of the game ball.
Further, a center stage 35S is provided below the main liquid crystal display device 32M, which exerts a decorative effect and functions as a floating area of a game ball.
Although not shown, the center decoration 35C is provided with a movable body accessory that exerts a visual effect at an appropriate position.

A symbol display unit 33 using a dot display formed by arranging a plurality of LEDs is provided near the upper right edge of the game area 3a.
In the symbol display unit 33, a first special symbol display unit, a second special symbol display unit, and a normal symbol display unit are formed by a predetermined dot area, and the first special symbol, the second special symbol, and the ordinary symbol are formed. Each fluctuation display operation (variation display operation that sets fluctuation start and fluctuation stop) is performed.
The main liquid crystal display device 32M changes and displays the decorative symbol by the image in time with the variable display of the first and second special symbols by the symbol display unit 33.

A winning device having an upper starting port 41 (first special symbol starting port) is provided below the center decoration 35C, and a lower starting port 42a (second special symbol starting port) is provided below the winning device. A variable winning device 42 is provided.
Inside the upper start port 41 and the lower start port 42a, detection sensors (upper start port sensor 71 and lower start port sensor 72 shown in FIG. 3) for detecting the passage of the game ball are formed.

The upper starting port 41 is a winning opening related to the starting condition of the variable display operation of the first special symbol on the symbol display unit 33, and has a fixed winning rate that does not have a starting opening opening / closing means (means for opening or expanding the starting port). It is a type winning device.

The ordinary variable winning device 42 having the lower starting port 42a is configured as a winning rate variable winning device in which the winning rate of the game ball at the starting port can be changed by the starting port opening / closing means. That is, it is a so-called electric tulip-type winning device provided with a pair of left and right movable wing pieces (movable members) 42b that allow the lower starting port 42a to be opened or expanded.
The lower starting port 42a of the normal variable winning device 42 is a winning opening related to the starting condition of the variable display operation of the second special symbol in the symbol display unit 33. The winning rate of the lower starting port 42a varies depending on the operating state of the movable wing piece 42b. That is, when the movable wing piece 42b is open, winning is easy, and when the movable wing piece 42b is closed, winning is difficult or impossible.

Further, a plurality of general winning openings 43 are provided on the left and right sides of the ordinary variable winning device 42. Inside each general winning opening 42, a detection sensor (general winning opening sensor 74 shown in FIG. 3) for detecting the passage of a game ball is formed.
Further, on the lower side of the right game area 3c, a normal symbol start port 44 formed of a gate (specific passage area) through which the game ball can pass is provided. The normal symbol start port 44 is a winning opening related to a variable display operation of the normal symbol in the symbol display unit 33, and a sensor (gate sensor 73 shown in FIG. 3) for detecting a passing game ball is formed inside the winning opening. Has been done.

A first special variable winning device 45 (special electric accessory) is provided in the middle of the flow path from the normal symbol starting port 44 in the right game area 3c to the normal variable winning device 42.
The first special variable winning device 45 has a structure in which the first large winning opening 45a is closed / opened by a recessed opening door 45b. Further, a sensor (first grand prize opening sensor 75 in FIG. 3) for detecting the passage of the game ball through the first grand winning opening 45a is formed inside the sensor.
Around the first prize opening 45a, the lower right decoration 35R is in a state of bulging from the surface of the game board 3, and the upper side of the bulging portion and the upper surface of the open door 45b guide the downstream of the right flow path 3c. Forming a part. Therefore, when the open door 45b is pulled into the inside of the board, the game ball that has reached the downstream guide portion easily enters the first large winning opening 45a.

A second special variable winning device 46 (special electric accessory) is provided below the normal variable winning device 42. The second special variable winning device 46 has a structure in which the second large winning opening 46a inside is closed / opened by an open door 46b whose lower portion is pivotally supported and can be opened and closed. Further, a sensor for detecting the passage of the game ball through the second special winning opening 46a (second special winning opening sensor 76 in FIG. 3) is formed inside the sensor.
When the opening door 46b is opened, the second large winning opening 46a is opened. In this state, the game ball that has flowed down the left game area 3b or the right game area 3c has a high probability of entering the second large winning opening 50.

As described above, the upper start opening 41, the lower start opening 42a, the normal symbol start opening 44, the first major winning opening 45a, the second major winning opening 46a, and the general winning opening 43 are formed in the game area of the board surface. Has been done.
In the pachinko gaming machine 1 of the present embodiment, when there is a prize in a prize opening other than the normal symbol start opening 44 among these winning openings, one winning ball set for each winning opening is used. The number of prize balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the number of prize balls is set such that the upper start opening 41 and the lower start opening 42a are 3, the first big winning opening 45a, the second big winning opening 46a is 13, and the general winning opening 43 is 10.
The game balls that do not win in each of these winning openings are discharged from the gaming area 3a via the out opening 48.
Here, "winning" means that the winning opening takes in the game ball inside the winning opening, or the game ball passes through the gate. Actually, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated as if a "winning" has occurred in the winning opening. The game ball related to this winning is also referred to as a "winning ball".

On the board as described above, the center decoration 35C, the lower left decoration 35L, the lower right decoration 35R, the center stage 35S, the first special variable winning device 45, the second special variable winning device 46, and the movable body accessory (not shown). Although not shown in detail, for example, LED light emitting units 20b, 20Z, 20H, and 20J are provided as light emitting means on the panel side.
The light emitting unit 20b performs a light emitting operation for producing and a light emitting operation for error notification.
The light emitting units 20Z, 20H, and 20J are light emitting units for presenting various situations.
The light emitting unit 20Z performs a light emitting operation for identifying variable symbols. Three light emitting units 20Z are provided, for example, corresponding to each of the first special symbol, the second special symbol, and the normal symbol, and for each of the corresponding symbols, for example, the symbol change is stopped, changed, or hit. Performs a light emitting operation to identify.
The light emitting unit 20H performs a light emitting operation for displaying the number of holds. The light emitting unit 20H is provided, for example, with a total of eight light emitting units 20H, for example, displaying up to four hold numbers for the first special symbol variation and up to four hold numbers for the second special symbol change. The number of holds is displayed in the light emitting state.
The light emitting unit 20J performs a light emitting operation for notifying the game state. The required number of light emitting units 20J is provided (three in this example), and in each light emitting state, the jackpot, the probability change, the time saving, and the like are notified.
In this example, the light emitting units 20Z, 20H, 20J are provided on the panel side, but all or part of the light emitting units 20Z, 20H, 20J may be provided on the frame side.

In the following description, the light emitting unit 20w on the board side and the light emitting unit 20b on the frame side may be referred to as "directing light emitting unit".
Further, the light emitting unit 20Z may be referred to as a “variable symbol identification light emitting unit”, the light emitting unit 20H may be referred to as a “holding number display light emitting unit”, and the light emitting unit 20J may be referred to as a “game state notification light emitting unit”.
Further, the light emitting units 20Z, 20H, and 20J may be collectively referred to as "situation presenting light emitting unit".

<2. Control configuration of pachinko machine>
Next, the configuration of the control system of the pachinko gaming machine 1 of the present embodiment will be described. FIG. 3 is a schematic block diagram of the internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 of the present embodiment is mainly provided with a main control board 50, an effect control board 51, a payout control board 53, a launch control board 54, and a power supply board 58 as boards forming the control configuration thereof. ..

The main control board 50 is equipped with a microcomputer or the like, and performs comprehensive control related to the overall gaming operation of the pachinko gaming machine 1. In the following, the components of the main control board 50 including the microcomputer mounted on the main control board 50 will be referred to as “main control unit 50”.
The effect control board 51 is equipped with a microcomputer or the like, and receives an effect control command from the main control unit 50 to perform control for executing various effect operations using an image display, light emission, acoustic output, and a movable body accessory. I do. In the following, the structure of the effect control board 51 including the microcomputer mounted on the effect control board 51 will be referred to as “effect control unit 51”.

The payout control board 53 controls the payout of prize balls by the game ball payout device 55 connected to the pachinko game machine 1.
The launch control board 54 controls the launch operation of the game ball by the launch device 56 provided in the pachinko gaming machine 1 of the player.
The power supply board 58 performs AC / DC conversion and further DC / DC conversion from an external power supply (for example, AC24V), and supplies an operating power supply voltage Vcc to each part. The power supply path is not shown.

First, the main control unit 50 and its peripheral circuits will be described.
The main control unit 50 is equipped with a microprocessor incorporating a CPU 100 (hereinafter referred to as "main control CPU 100"), a ROM 101 (hereinafter referred to as "main control ROM 101"), a RAM 102 (hereinafter referred to as "main control RAM 102"), and the like. ing.
The main control CPU 100 executes various calculations and control processes according to the progress of the game based on the control program.
The main control ROM 101 stores a game operation control program by the main control CPU 100 and various data necessary for game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processing, and as a buffer area for various input / output data and processing data.
Although not shown, the main controller 50 includes an interface circuit with each unit, a random number generation circuit for generating lottery random numbers related to special symbol variation display, a CTC (Counter Timer Circuit) for counting various times, and a main controller. It also includes an interrupt controller circuit that gives an interrupt signal to the control CPU 100.

As described above, the main control unit 50 includes each winning means (upper starting port 41, lower starting port 42a, normal symbol starting port 44, first large winning opening 45a, second large winning opening 46a, general) in the game area of the board surface. It is configured to receive the detection signal of the sensor provided in the winning opening 43).
That is, the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first winning opening sensor 75, and the second major winning opening sensor 76 are sent to the main control unit 50. Be supplied.
These sensors (71 to 76) are composed of detection switches that detect the game ball that has entered, but specifically, non-contact switches such as photo switches and proximity switches, and contacts such as micro switches. It can be configured with a switch.

The main control unit 50 receives the detection signals of the upper start port sensor 71, the lower start port sensor 72, the gate sensor 73, the general winning port sensor 74, the first special winning opening sensor 75, and the second major winning opening sensor 76, respectively. Processing is performed according to. For example, lottery processing, symbol variation control, prize ball payout control, effect control command transmission control, external data transmission processing, and the like are performed.

Further, a normal electric accessory solenoid 77 for opening and closing the movable wing piece 42b of the lower starting port 42 is connected to the main control unit 50, and the main control unit 50 transmits a control signal according to the progress of the game and is normally electric. The driving operation of the accessory solenoid 77 is executed, and the opening / closing operation of the movable wing piece 42b is executed.
Further, the main control unit 50 includes a first large winning opening solenoid 78 that opens and closes and drives the opening door 45b of the first large winning opening 45, and a second large winning opening that opens and closes and drives the open door 46b of the second large winning opening 46. The mouth solenoid 79 is connected. The main control unit 50 drives and controls the first special winning opening solenoid 78 or the second special winning opening solenoid 79 according to the so-called jackpot situation, and opens the first special winning opening 45 or the second major winning opening 46. To execute.

Further, a symbol display unit 33 is connected to the main control unit 50, and a control signal is transmitted to the symbol display unit 33 to execute various symbol displays (LEDs are turned off / on / blinking). As a result, the display operation on the first special symbol display unit 80, the second special symbol display unit 81, and the normal symbol display unit 82 on the symbol display unit 33 is executed.

Further, a frame external terminal board 57 is connected to the main control unit 50. The main control unit 50 can transmit information regarding the progress of the game to a hall computer (not shown) via the frame external terminal board 57. The game progress information is, for example, information such as jackpot winning information, prize ball number information, and symbol variation display execution count information. The hall computer is a management computer that comprehensively manages the pachinko hall gaming machines, and is installed outside the gaming machines.

A payout control board 53 is connected to the main control unit 50. The payout control board 53 is connected to a launch control board 54 that controls the launch device 56 and a game ball payout device 55 that pays out the game balls.
The main control unit 50 transmits a control command related to payout (payout control command for specifying the number of prize balls) to the payout control board 53. The payout control board 53 controls the game ball payout device 55 in response to the control command to execute the payout of the game ball.
Further, the payout control board 53 can transmit information (payout state signal) regarding the payout operation state to the main control unit 50. The main control unit 50 side monitors whether or not the game ball payout device 55 is functioning normally by the payout status signal. Specifically, it monitors whether or not a problem such as jamming or insufficient payout of prize balls has occurred during the payout operation of the prize balls.

Further, the main control unit 50 transmits an effect control command including information on the special symbol variation display to the effect control unit 51. The transmission of the effect control command from the main control unit 50 to the effect control unit 51 is executed by one-way communication. This is to prevent an illegal signal due to an illegal act from the outside from being input to the main control unit 50 via the effect control unit 51.

Subsequently, the effect control unit 51 and its peripheral circuits will be described.
The effect control unit 51 is equipped with a microprocessor incorporating a CPU 200 (hereinafter referred to as "effect control CPU 200"), ROM 201 (hereinafter referred to as "effect control ROM 201"), and RAM 202 (hereinafter referred to as "effect control RAM 202"). It constitutes a microcomputer.

The effect control CPU 200 performs arithmetic processing for various effect operations and controls of each effect means based on the effect control program and the effect control command received from the main control unit 50. In the case of the pachinko gaming machine 1 of the present embodiment, the effect means are a main liquid crystal display device 32M, a sub liquid crystal display device 32S, light emitting units 20w and 20b, a speaker 25, and a movable body accessory (not shown).
The effect control CPU 200 also performs control for presenting various situations. Specifically, it is the light emission control of the light emitting units 20Z, 20H, and 20J.
The effect control ROM 201 stores a control program for the effect operation by the effect control CPU 200 and various data necessary for the effect operation control.
The effect control RAM 202 (D-RAM 202a in FIG. 4, work memory 202b for built-in CPU) is used as a work area used by the effect control CPU 200 for various arithmetic processes, a table data area, a buffer area for various input / output data and processing data, and the like. Used.
As will be described later, the arithmetic control unit 51 shows an example in which the one-chip microprocessor and its peripheral circuits are mounted, but various configurations of the effect control unit 51 can be considered. For example, in addition to a microcomputer, an interface circuit with each part, a random number generation circuit for generating lottery random numbers for production, a CTC for various time counting, a watchdog timer (WDT) circuit, and an interrupt signal to the production control CPU 200. In some cases, an interrupt controller circuit for giving a sound effect, a sound source IC for sound production, and the like are provided.

The main roles of the effect control unit 51 are to receive the effect control command from the main control unit 50, determine the selection of the effect based on the effect control command, and control the display (display data) of the main liquid crystal display device 32M and the sub liquid crystal display device 32S. Supply), audio output control of the speaker 45, light emission control of the light emitting units 20w, 20b, 20Z, 20H, 20J (LED), operation control of the movable body accessory (drive control of the movable body accessory motor 65), and the like.

Since the effect control unit 51 also has a function as a control device for the main liquid crystal display device 32M and the sub liquid crystal display device 32S, the effect control unit 51 includes a so-called VDP (Video Display Processor), an image ROM, and a VRAM ( It also has a function as Video RAM), and the effect control CPU 200 also functions as a liquid crystal control unit.
VDP refers to a function that controls overall video output processing such as image development processing and image drawing.
The image ROM refers to a memory in which image data (effect image data) for which VDP performs image development processing is stored.
The VRAM is an image memory area that temporarily stores the image data developed by the VDP.

With these configurations, the effect control unit 51 generates various image data based on the command from the main control unit 50 and outputs the various image data to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. As a result, various effects images are displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

Further, a frame driver unit 61 and a board driver unit 62 are connected to the effect control unit 51.
The frame driver unit 61 drives the LED of the lamp unit 63 on the frame side to emit light. The lamp unit 63 is a general representation of the light emitting unit 20w provided on the frame side as shown in FIG.
The panel driver unit 62 drives the LED of the lamp unit 64 on the panel side to emit light. The lamp unit 64 is a general representation of the light emitting units 20b, 20Z, 20H, and 20J provided on the panel side as shown in FIG.

A motor driver unit 70 is connected to the effect control unit 51.
The motor driver unit 70 drives the movable body accessory motor 65 to execute the operation of the movable body accessory provided on the panel side.
As the movable body accessory motor 65, for example, a stepping motor is used.
The origin position is defined for each movable accessory motor 65. The origin position is, for example, a position where the accessory does not normally appear on the board surface of FIG.
An origin switch 68 is provided on each movable accessory motor 65 so that the effect control unit 51 can confirm whether or not each movable accessory motor 65 is at the origin position. For example, a photo interrupter is used. The information of the origin switch 68 is detected by the effect control CPU 200.

Further, details will be described later with reference to FIGS. 6, 7, and 8. However, in the case of the present embodiment, the effect control unit 51 uses the light emission drive data and the motor drive data as serial data, and the frame driver unit 61 and the panel driver. Output to unit 62 and motor driver unit 70.

Further, the effect control unit 51 executes audio output control from the speaker 25. The production control unit 51 outputs music for production and audio signals as audio to the amplifier unit 67 as stereo output signals of, for example, two channels of Lch and Rch. This audio signal is amplified by the amplifier unit 67 and then given to the speaker 25.
Although only one system of the amplifier unit 67 and the speaker 25 is shown in FIG. 3 for convenience of illustration, the amplifier unit 67 and the speaker 25 are actually provided with output channels corresponding to, for example, Lch and Rch, respectively. , Stereo sound reproduction is possible.

Further, an operation unit 60 that can be operated by the player is connected to the effect control unit 51, and an operation detection signal from the operation unit 60 can be received. The operation unit 60 is the effect buttons 11 and 12 and the cross key 13 described with reference to FIG. 1, and their operation detection mechanisms.
The effect control unit 51 can perform various effect controls in response to the operation detection signal from the operation unit 60.

The effect control unit 51 determines the effect pattern by lottery or uniquely from a plurality of types of effect patterns prepared in advance based on the effect control command sent from the main control unit 50, and various effects are performed at the required timing. Control the means. As a result, the main liquid crystal display device 32M and the sub liquid crystal display device 32S corresponding to the effect pattern display the effect image, reproduce the sound from the speaker 25, and the lamp units 63 and 64 (light emitting units 20w, 20b, 20Z, 20H, 20J). ), The lighting and blinking drive of the LED and the operation of the movable body accessory motor 65 are realized, and various production patterns are developed in chronological order. As a result, the production according to the "production scenario" is realized.

The function of the effect control command is defined by a 2-byte configuration consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish between MODE and EVENT, Bit7 of MODE is ON and Bit7 of EVENT is OFF.
The effect control command from the main control unit 50 is taken into the reception buffer by the effect control unit 51. The effect control CPU 200 confirms the reception buffer at a predetermined timing, analyzes the received effect control command, and determines the effect control to be executed.

<3. Composition of production control unit>
FIG. 4 shows a specific configuration example of the effect control unit 51.
The effect control unit 51 of the example of FIG. 4 is configured by externally connecting, for example, the effect control ROM 201, D-RAM 202a, CG-ROM 206, WDT (watchdog timer) circuit 210, etc. to the one-chip microcomputer 250. There is.

The one-chip microcomputer 250 includes an effect control CPU 200, and has functions such as the above-mentioned VDP and VRAM, as well as a function of performing light emission control, motor control, and sound control by each of the illustrated parts.
Each component will be explained.

The one-chip microcomputer 250 is equipped with an effect control CPU 200. The effect control CPU 200 performs various control processes as described above.
The effect control CPU 200 uses an internal device or an external device of the microprocessor 250 via the CPU interface 203.
That is, the effect control CPU 200 is connected to the host interface 204 via the CPU interface 203, receives commands from the main control unit 50, reads access to the effect control ROM 201, and transmits / receives signals to / from the WDT circuit 210 via the host interface 204. , And communicate with each part inside via the bus 251.

The effect control CPU 200 uses the D-RAM 202a and the built-in CPU work memory 202b as the effect control RAM 202 described above.
The D-RAM 202a is connected to the RAM interface 208, and the effect control CPU 200 writes or reads from the D-RAM 202a via the RAM interface 208.

The system control register 205 is a register for initializing the system.
The transfer circuit 212 performs transfer using the internal resources of the microprocessor 250 and external peripherals as input and output.

The CG-ROM 206 is an image ROM and stores character image data to be displayed.
The CG-ROM 206 is connected to the CG bus interface 207 provided in the microcomputer 250. As a result, the required part in the microcomputer 250 can access the CG-ROM 206 via the CG bus interface 207.

The microcomputer 250 includes, for example, a VRAM 209 having a capacity of 48 Mbytes. The VRAM 209 stores drawing material and frame data.
The usage mode of the VRAM 209 can be various depending on the setting, but in this example, two frame buffers 209A and 209B are set as storage areas for frame data for display, and the frame buffers 209A and 209B are alternately used for each frame. To draw and output display data.

In this embodiment, since two display devices (main liquid crystal display device 32M and sub liquid crystal display device 32S) are used, the frame buffers 209A and 209B are the main liquid crystal display device 32M and the sub liquid crystal display device 32S, respectively. It is prepared corresponding to.
That is, the illustrated frame buffer 209A includes a frame buffer area for the main liquid crystal display device 32 and a frame buffer area for the sub liquid crystal display device 32S, and the frame buffer 209B includes a frame buffer area and the sub for the main liquid crystal display device 32. Includes a frame buffer area for the liquid crystal display device 32S.
Image data for one frame for the main liquid crystal display device 32M and the sub liquid crystal display device 32S is generated in the frame buffers 209A and 209B of the VRAM 209, respectively, and the frame buffers 209A and 209B are drawn by a predetermined drawing command. The position is specified.

The index table 211 manages the VRAM 209, such as setting the storage area of the VRAM 209.

The preloader 220, the display circuits 221, 222, 223, the GDEC (graphic decoder) 223, and the drawing circuit 225 perform various processes as a video processor (VDP).
The effect control CPU 200 creates a display list for setting the image contents to be displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S in response to the effect control command. This display list is a collection of drawing commands.
The display list consists of a group of drawing commands listed in the order in which they are drawn. The drawing command also includes a command that defines what kind of image is drawn at which position in one frame, and a storage position (source address) such as CG-ROM206 of the image to be drawn is also specified.

The drawing circuit 225 draws a figure in the frame buffer (209A or 209B) on the VRAM 209.
The GDEC 223 decodes the compressed image data used for drawing and develops it in the VRAM 209.

The preloader 220 analyzes the display list transmitted by the data transfer circuit 72, and transfers the image material referred to therein, that is, the image data on the CG-ROM 206, to the designated area of either DRAM 202a or VRAM 209. To do.
At this time, the preloader 220 outputs a display list in which the reference destination of the image data is rewritten to the address after the transfer. The rewritten display list is transmitted to the drawing circuit 225 by the data transfer circuit 212.

Since random access to the image data occurs during drawing by the drawing circuit 225, if the image data is directly referred to from the CG-ROM 206, which is vulnerable to random access such as a NAND flash memory, the drawing performance is greatly deteriorated. Therefore, by using the preloader 220 to transfer the image data and the display list to the D-RAM 202a or the built-in VRAM 209 in advance, it is possible to execute moving image decoding and drawing at high speed.

As described above, in the present embodiment, since the preloader 220 is functioning, the reference destination of the image data (CG data as the image material) of the display list is set to D-RAM 202a or VRAM 209 instead of CG-ROM 206. This is the preload area. Therefore, random access to the image data generated during the execution of drawing by the drawing circuit 225 can be quickly executed, which is advantageous for the drawing process even for a high-resolution moving image with a lot of movement.

The display circuits 221, 222, and 223 display and output the display data of the frame buffer (209A or 209B) of the VRAM 209 to the outside.
Here, the microcomputer 250 is provided with three display circuits 221, 222, and 223, which are compatible with three screen outputs that enable one system of digital RGB output and two systems of LVDS (Low voltage differential signaling) output. This is because it has a structure. In the case of this example, for example, the digital RGB output is used as the display data output to the main liquid crystal display device 32M, and one LVDS output is used as the display data output to the sub liquid crystal display device 32S.
The display data from the display circuits 221, 222, 223 are selected by the LCD interface 226 and output to external devices, that is, the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

The display circuits 221, 222, and 223 output display data as non-interlaced output. Further, the display data is provided with a scaling processing function for enlarging / reducing from 2 times to 1/2 times, a dithering function, and a color correction function.
FIG. 5 shows a block diagram of the display circuits 221, 222, 223 and the LCD interface 226.

Each display circuit 221, 222, 223 has a synchronization signal generation unit 265, and performs processing in synchronization with the frame of the image, respectively. The synchronization signal generation unit 265 generates, for example, a V blank signal indicating a vertical blank period (ineffective line scanning period), a horizontal synchronization signal, and a vertical synchronization signal as synchronization signals. These synchronization signals can be used for internal control processing of the microcomputer 250, and are also used for display data transfer and display control operation to the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The synchronization signals used in the display circuits 221, 222, and 223 can be synchronized with each other. For example, the display circuits 221, 222, and 223 can be forcibly synchronized by using the falling edge of the vertical synchronization signal of an external display such as the main liquid crystal display device 32M as a trigger.

Each display circuit 221, 222, 223 acquires the frame data read from the frame buffer 209A or 209B of the VRAM 210 by the VRAM reading unit 261.
Regarding the display circuits 221,222, it is possible to perform scaling processing by the scaler 262, color correction processing by the color correction unit 263, and dithering processing by the ditherer 264 on the acquired frame data. Then, digital RGB output and LVDS output are performed as outputs after processing by the ditherer 264. The same applies to the display circuit 223, but in the example shown in this figure, the display circuit 223 does not have the function of the scaler 262.

The LCD interface 226 has a digital RGB output unit 226a and an LVDS output unit 226b.
Display data as digital RGB output from the display circuits 221, 222, 223 is supplied to the digital RGB output unit 226a. The digital RGB output unit 226a selects one digital RGB output of the display circuits 221, 222, 223 and supplies it to the main liquid crystal display device 32M.
Further, the LVDS output unit 226b is supplied with display data as LVDS output from the display circuits 221, 222, 223. The LVDS output unit 226b can select and output two LVDS outputs from the display circuits 221, 222, and 223. In the case of the pachinko gaming machine 1 of the present embodiment, the LVDS output of one of the display circuits 221, 222, 223 is supplied to the sub liquid crystal display device 32S.
Of course, this is an example, and it is conceivable to supply one LVDS output to the main liquid crystal display device 32M, or to supply the digital RGB output to the sub liquid crystal display device 32S.

The microcomputer 250 of FIG. 4 has a sound controller 230.
The sound controller 230 has, for example, a sound source control unit and a sound data storage unit that stores compressed audio data. Based on the control of the effect control CPU 200, the sound controller 230 decodes the compressed audio data to generate an output audio signal, and an external amplifier Output to unit 67.
Regardless of whether or not the sound controller 230 is mounted, the effect control CPU 200 may control the sound source IC outside the microcomputer 250 to output the audio signal to the amplifier unit 67.

The microcomputer 250 has a general-purpose port 231. For example, it is an 8-bit input / output port. The general-purpose port 231 enables input / output with various external devices.

The serial output controller 240 outputs the control signal as serial data to the outside. In the case of the present embodiment, the serial output controller 240 is provided with the lamp controller 241 and the motor controller 242, and outputs the light emission drive data of the lamp units 63 and 64 and the motor drive data of the movable accessory motor 65. Will be.
FIG. 6 shows an output system of light emission drive data from the serial output controller 240 (lamp controller 241 and motor controller 242) to the frame driver unit 61 and the panel driver unit 62, and an output system of motor drive data to the motor driver unit 70. ..

In the frame driver unit 61, n LED drivers 90 are connected in parallel to the serial data output channel ch1 of the serial output controller 240.
As the signal line of the serial data output channel ch1, a clock line for supplying the clock signal CLK and a data line for supplying serial data DATA as light emission drive data (also referred to as “LED drive data” or “ramp drive data”) are provided. Has been done. Each of these signal lines is connected so as to supply each signal in parallel to the n LED drivers 90 constituting the frame driver unit 61.
A device ID used by the effect control CPU 200 as a slave address is set in each LED driver 90 of the frame driver unit 61. That is, it is an identifier of each LED driver 90. For the sake of explanation, the device IDs (slave addresses) of each LED driver 90 are tentatively expressed as w1, w2, ... As shown in the figure.

Further, in the board driver unit 62, m LED drivers 90 are connected in parallel to the serial data output channel ch2 of the effect control CPU 200.
Similar to channel ch1, the signal line of the serial data output channel ch2 is also provided with a clock line for supplying the clock signal CLK and a data line for supplying the serial data DATA as the light emission drive data. Each of these signal lines is connected so as to supply each signal in parallel to the m LED drivers 90 constituting the panel driver unit 62.
A device ID (identifier of each LED driver 90) used by the effect control CPU 200 as a slave address is set in each LED driver 90 of the board driver unit 62. For the sake of explanation, the device IDs (slave addresses) of the LED drivers 90 are tentatively referred to as b1, b2, ... As shown in the figure.

The LED driver 90 in the frame driver unit 61 and the panel driver unit 62 is, for example, a 24-channel LED driver and includes 24 current terminals. Therefore, one LED driver 90 can supply the LED drive current to a maximum of 24 series. Specifically, for example, 8 series of R (red) LED drive current supply, 8 series of G (green) LED drive current supply, and 8 series of B (blue) LED drive current supply are performed, and 8 full-color LEDs emit light. It can be driven. Here, one "series" refers to one LED connected to one current terminal, or a group of a plurality of LEDs connected in series or in parallel to one current terminal. There is.
The number n of the LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of the light emitting unit 20w). Therefore, n may be 1 or 2 or more. The frame driver unit 61 has one or more LED drivers 90.
The number m of the LED driver 90 in the board driver unit 62 is determined by the number of LED series (the number of series of the light emitting units 20b, 20Z, 20H, 20J) arranged on the board side. Therefore, m may be 1 or 2 or more. The board driver unit 62 has one or more LED drivers 90.

FIG. 7 shows a schematic configuration example of a main part of the LED driver 90.
The LED driver 90 includes a serial bus interface 191, an address setting unit 192, a data buffer / PWM controller 193, a D / A converter 194, and a drive current source circuit 195-1 to 195-24.
The drive current source circuits 195-1 to 195-24 are current sources that output the above-mentioned 24 series of drive currents from the current terminals 196-1 to 196-24, respectively.

The clock signal CLK and serial data DATA from the serial output controller 240 are input to the serial bus interface 191 in the LED driver 90. The serial bus interface 191 takes in the serial data DATA at the timing of the clock signal CLK. The serial bus interface 191 converts the captured serial data into parallel data and transfers it to the data buffer / PWM controller 193.
The serial output controller 240 specifies a slave address and transmits LED drive data.
The data buffer / PWM controller 193 confirms the slave address of the parallel data transferred from the serial bus interface 191. When it is confirmed that the slave address included in the parallel data matches the own slave address (either w1 to w (n) or b1 to b (m)) set in the address setting unit 192. , The LED drive data included in the parallel data is stored in the designated register as valid data.

When the data buffer / PWM controller 193 captures the LED drive data of each series, the data buffer / PWM controller 193 uses a value corresponding to the luminance information (gradation value) indicated by the LED drive data as each drive control value of the 24 series, D / A. Output to converter 194.
The D / A converter 194 converts a value corresponding to the luminance information into an analog signal and uses it as a control signal for each current source circuit 195 to 195-24.

A 24-series LED 120 is connected to all (or a part) of the current terminals 196 (196-1 to 196-24). The figure shows a state in which one LED 120 is connected to one series of current terminals 196 for simplification, but a configuration in which a plurality of LEDs are connected to one series of current terminals 196 (for example, series connection) is also possible. Of course it is possible.
In each series (current terminals 196-1 to 196-24), a power supply voltage Vcc is applied to the series connection of the LED 120 and the resistor R. A current is passed through the LED 120 of each series by the current source circuits 195-1 to 195-24, and light is emitted.
That is, each current source circuit 195-1 to 195-24 operates so as to pass a drive current of a current amount corresponding to the signal supplied from the D / A converter 194 to the corresponding series of LEDs 120.

To specifically describe such LED drive control for one series, the data buffer / PWM controller 193 converts a digital data string corresponding to a pulse duty according to the gradation value of the series into a D / A converter 194. The D / A converter 194 converts the digital data string into a pulse signal as an analog signal and supplies the digital data string to the current source circuit 195 of the series. The current source circuit 195 is output-controlled by the H / L of the pulse signal, and outputs currents of, for example, 0 mA and 5 mA. For example, in such an operation, a drive current having an average current value corresponding to the gradation value flows through the LED 120 as a result.
In the present embodiment, the current values are set to, for example, 0 mA and 5 mA by the PWM drive method, and the gradation control is performed (integrally) in the time axis direction. Needless to say, the current value may actually be changed according to the gradation. Regardless of whether it is duty control or level control, appropriate gradation expression is possible by setting the average current value per unit time to a level according to the gradation.

The number n of the LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of the light emitting unit 20w). Therefore, n may be 1 or 2 or more. The frame driver unit 61 has one or more LED drivers 90.
The number m of the LED driver 90 in the board driver unit 62 is determined by the number of LED series (the number of series of the light emitting units 20b, 20Z, 20H, 20J) arranged on the board side. Therefore, m may be 1 or 2 or more. The board driver unit 62 has one or more LED drivers 90.

As examples of the lamp units 63 and 64 using LEDs or the like, one system (one serial data output channel) on the frame side and one system on the panel side are given, but of course, the present invention is not limited to this. A plurality of systems may be provided for the lamp portion 63 on the frame side, or a plurality of systems may be provided for the lamp portion 64 on the panel side.

Next, the output of the motor drive data will be described. As shown in FIG. 5, serial data DATA as motor drive data is output from the serial output controller 240 to the motor driver unit 70.
In the motor driver unit 70, p motor drivers 91 are connected in parallel to the serial data output channel ch3 of the serial output controller 240.
Similarly, the signal line of the serial data output channel ch3 is provided with a clock line for supplying the clock signal CLK and a data line for supplying the serial data DATA as the motor drive data. Each of these signal lines is connected so as to supply each signal in parallel to the p motor drivers 91 constituting the motor driver unit 70.
A device ID (identifier of each motor driver 91) used by the effect control CPU 200 as a slave address is set in each motor driver 91 of the motor driver unit 70. For the sake of explanation, the device IDs (slave addresses) of each motor driver 91 are tentatively expressed as mt1, mt2, ... As shown in the figure.

Each motor driver 91 in the motor driver unit 70 may have the configuration shown in FIG. 7 in the same manner as the LED driver 90. That is, the same driver can be used.
The number p of the motor driver 91 in the motor driver unit 70 is determined by the number of motors used for the movable body accessory 65 and the like. Therefore, p may be 1 or 2 or more. The motor driver unit 70 has one or more motor drivers 91.

A movable body accessory motor 65 for driving a movable body accessory is connected to the motor driver 91.
FIG. 8 shows an example in which, for example, a stepping motor 121 is connected as a movable accessory motor 65 to all (or a part of) the current terminals 196-1 to 196-24 of the motor driver 91.
Here, the drive current is supplied to the four-phase stepping motor 121 by current terminals 96-1 to 96-4, current terminals 96-5 to 96-8, ... Current terminals 96-21 to 96-24, respectively. An example of the configuration to be used is shown.
Since the driver having the above-described configuration in FIG. 7 is a circuit that outputs the current indicated by the given command (serial data) from the current terminals 196-1 to 196-24, the stepping motor and the stepping motor are as shown in FIG. It can also be used as a motor driver 91 for a physically movable body driving device such as a solenoid.
The operation of the movable body accessory is finely set according to the effect scenario, and the effect control unit 51 controls the drive direction, the drive amount, and the like accordingly. The movable body uses the motor driver 91 in the motor driver unit 70. By driving the accessory, it is possible to control the movable object by serial data together with the light emitting units (LEDs 20w, 20b) of the lamp units 63 and 64, and the control process and the configuration can be made more efficient.

In one LED driver 90, a method may be adopted in which some current terminals are used for driving the LED and some other current terminals are used for driving a stepping motor, a solenoid, or the like.

Further, for each of the movable body accessory motors 65 (stepping motor 121), the sensors 68s described as the origin switch 68 in FIG. 3 are arranged correspondingly. The signal from each sensor 68s is input to the parallel / serial conversion unit 260.
Further, an example is shown in which the user's operation information from the operation unit 60 is also input to the parallel / serial conversion unit 92. The user's operation information is a signal corresponding to the operation of the effect buttons 11, 12, the cross key 13, and the like.
The parallel / serial conversion unit 260 is mounted on the effect control unit (effect control board) 51 as an IC separate from the one-chip microcomputer 250, for example, but may be built in the one-chip microcomputer 250.

The parallel / serial conversion unit 260 inputs, for example, 32 systems of signals, converts the input data into serial data Is, and supplies the input data to the motor controller 242.
The operation of the parallel / serial conversion unit 260 is controlled by the control signal CNT from the motor controller 242. The parallel / serial conversion unit 260 transfers serial data using the clock signal CLK.
With this configuration, the serial output controller 240 collects the origin detection state of each movable body accessory motor 65 and the user operations for the operation units 60 such as the effect switches 11 and 12, that is, the inputs required for the effect control are collectively efficient. Can be detected. Therefore, the effect control CPU 200 can efficiently grasp the effect state.

<4. Outline of operation>
The outline of the operation of the pachinko gaming machine 1 will be described.
[Design variation display game]
In the pachinko gaming machine 1, a jackpot lottery by a random number lottery is performed in the main control unit 50 on the condition that a predetermined starting condition, specifically, a game ball wins a prize in the upper starting port 41 or the lower starting port 42. Based on this lottery result, the special symbol (identification symbol for notifying the jackpot lottery result) is variablely displayed on the first special symbol display unit 80 or the second special symbol display unit 81 to start the special symbol variable display game. After a certain period of time has elapsed, the result is displayed on the special symbol display unit (80 or 81).

In the present embodiment, the big hit lottery based on the winning of the upper starting port 41 and the big hit lottery based on the winning of the lower starting port 42 are performed independently. Therefore, the jackpot lottery result for the upper start opening 41 is derived and displayed on the first special symbol display unit 80 side, and the jackpot lottery result for the lower start opening 42 is derived and displayed on the second special symbol display unit 81 side.
For the sake of explanation, the special symbol variation display game on the first special symbol display unit 80 side is referred to as the "first special symbol variation display game", and the special symbol variation display game on the second special symbol display unit 81 side is referred to as the "second special symbol variation display game". It is called a "display game". However, the first and second special symbols are collectively referred to as "special symbol", and the first and second special symbol variation display games are collectively referred to as "special symbol variation display game".

When the special symbol variation display game is started, a decorative symbol variation display game in which the decorative symbol (game symbol) is variablely displayed on the main liquid crystal display device 32M is started, and various effects are displayed accordingly. It will be issued. Then, when the lottery result is displayed on the first and second special symbol display units (80, 81), the result is also displayed on the main liquid crystal display device 32M by the decorative symbol. That is, in this decorative symbol variation display game, an effect display that reflects the lottery result in the special symbol variation display game, that is, an effect that reflects the jackpot lottery result appears.

For example, when the result of the special symbol variation display game is "big hit", the result of the decorative symbol variation display game also reflects the "big hit". Further, the special symbol indicating the big hit is stopped and displayed on the special symbol display unit (80, 81) in a predetermined display mode, and the "left", "middle", and "right" display areas are displayed on the main liquid crystal display device 32M. In a predetermined display mode in which the decorative symbols reflect the big hit lottery result on the winning effective line (for example, in each display area of "left", "middle", and "right", the three decorative symbols are "7" and "7". It is stopped and displayed at the display state of "7").

In the case of this "big hit", for example, the first big winning opening solenoid 78 or the second big winning opening solenoid 79 is driven, and the opening operation of the first big winning opening 45 or the second big winning opening 46 in a predetermined pattern is performed. It is executed, and a special gaming state (big hit game) that is more advantageous to the player than the normal gaming state occurs. In this big hit game, the big winning opening is opened until a predetermined time elapses, or until a predetermined number of game balls are won in the big winning opening, and the big winning opening is determined on condition that either of them is satisfied. Round games such as time closure are repeated a predetermined number of times.
When the big hit game is started, an opening effect for notifying that the big hit has been started is performed first, and after the opening effect is completed, the above-mentioned round game is performed for a predetermined number of rounds. In addition, during the round game, a round effect corresponding to each round is performed. Then, after the specified number of rounds is completed, an ending effect is performed to notify that the jackpot is finished, and the jackpot game is finished.

In this way, the special symbol variation display game and the decorative symbol variation display game have almost the same symbol game time (from the start timing of the variation display to the stop display timing), and reflect the result of the special symbol variation display game. Since things are to be expressed in the decorative symbol variation display game, these two symbol variation display games can be regarded as equivalent symbol games. For the sake of explanation, the above two symbol variation display games may be simply referred to as a "symbol variation display game".

Further, based on the fact that the game ball has passed through the gate 44 (normal symbol start port), the main control unit 50 performs an auxiliary hit lottery by a random number lottery. According to the lottery result, the normal symbol represented by the LED of the normal symbol display unit 82 is variablely displayed to start the normal symbol variable display game, and after a predetermined time elapses, the result is specified as whether the LED is lit or not lit. Stop display by combination.

Then, in the case of "auxiliary hit", the normal electric accessory solenoid 77 is activated, the movable wing piece 42b is opened, the lower starting port 42 is opened or expanded, and the game ball is easily flowed in (starting port opened). State), and an auxiliary game state (hereinafter referred to as "solenoid open game") that is more advantageous to the player than the normal game state occurs. In this general electric opening game, the movable wing pieces 42b are released for a predetermined time (for example, 0.2 seconds) or until a predetermined number (for example, 4) of game balls are won, and then for a predetermined time (for example, 4 seconds). (0.5 seconds) The operation of closing the movable wing piece 42b is repeated a predetermined number of times. In addition, when the game ball wins a prize in the lower start opening 42 during the Fuden opening game, the special symbol variation display game is similarly played, and the decorative symbol variation display game is played accordingly.

Here, during a special symbol variation display game, a normal symbol variation display game, a big hit game, a normal electric opening game, etc., further from the upper start port sensor 71, the lower start port sensor 72, or the gate sensor 73. When there is an input of a detection signal and the start condition is satisfied, the game information used for the winning lottery is acquired based on this detection signal, and this is the data related to the start right for playing each variable display game. As (holding data), the maximum number of holding storages (for example, up to 4), which is a predetermined upper limit, can be held and stored, except for those related to the variable display. In order to clarify the number of holds to the player, the hold display provided as an icon image is lit and displayed on the screen by the hold number display unit 20H or the main liquid crystal display device 32M.
Normally, a variable display game is executed for each reserved ball in the order in which the reserved balls are generated. In the present embodiment, 4 pieces, which is the same number as the maximum number of reserved symbols, is treated as the upper limit predetermined number, and up to 4 pieces of reserved data related to the 1st special symbol and the 2nd special symbol are stored respectively, and the special symbol or the normal symbol is changed. Hold as the fixed number of times.

[Game state]
The pachinko gaming machine 1 of the present embodiment is configured to be capable of generating a plurality of types of gaming states.
First, the pachinko gaming machine 1 of the present embodiment has a "probability variation (hereinafter referred to as" probability variation ") function" in which the main control unit 50 (CPU100) is responsible for the functional unit. There are two types of this, a probabilistic function related to a special symbol (hereinafter referred to as "special symbol probabilistic function") and a probabilistic function related to a normal symbol (hereinafter referred to as "ordinary symbol probabilistic function").

The special symbol probability change function changes the lottery probability of the jackpot from a low probability (for example, 1/399) of a predetermined probability (normal probability) to a high probability (for example, 1 / 39.9), which is more advantageous than the normal gaming state. It is a function to generate a "high probability state". Under this high probability state, the jackpot lottery probability is high, so that jackpots are likely to occur.
The normal symbol probability change function is more advantageous than the normal gaming state by changing the lottery probability per auxiliary from a low probability (for example, 1/256), which is a predetermined probability (normal probability), to a high probability (for example, 255/256). It is a function to generate a "probability change state per auxiliary". Under this auxiliary hit probability variation state, the auxiliary hit lottery probability becomes a high probability state, so that auxiliary hits are likely to occur, and the general electric open game occurs more frequently, and the movable wing per unit time is higher than the normal game state. The operation rate is improved, in which the operation rate of the piece 42b is improved.

Further, the pachinko gaming machine 1 of the present embodiment has a "variable time shortening (hereinafter referred to as" time saving ") function" in which the main control unit 50 takes charge of the functional unit. There are two types of this: a time saving function related to a special symbol (hereinafter referred to as a "special symbol time saving function") and a time saving function related to a normal symbol (hereinafter referred to as a "normal symbol time saving function").

The special symbol time reduction function shortens the average time required for one special symbol fluctuation display game (the time from when the special symbol starts to fluctuate until it is confirmed and displayed, that is, the fluctuation time of the special symbol). It is a function to generate a "time saving state". Under the special symbol time reduction state, the average fluctuation time of the special symbol in one special symbol variation display game is shortened, and the number of big hit lottery per unit time is improved as compared with the normal game state.
In the pachinko gaming machine 1, the variation display time of the special symbol may be shortened due to the difference in the number of holdings, but in this case, the special symbol time reduction state does not occur, and it depends on other control processing. It is a thing.

The normal symbol time reduction function shortens the average time required for one normal symbol fluctuation display game (the time from when the normal symbol starts to fluctuate until it is confirmed and displayed, that is, the fluctuation time of the normal symbol). It is a function to generate a "time saving state". Under the normal symbol time reduction state, the average fluctuation time of the normal symbol in one normal symbol variation display game is shortened, and the number of lottery times per auxiliary per unit time is improved as compared with the normal game state. ..

Further, the pachinko gaming machine 1 of the present embodiment has an "open extension function" in which the main control unit 50 is responsible for its functional unit.
The open extension function is a function of generating an "open extension state" in which the period for opening the movable wing piece 42b and the number of times the movable wing piece 42b is opened are extended. This open extension state is a so-called "electric chew support state". Under the open extension state, the open operation period (starting port open state time) of the movable wing piece 42b is extended from, for example, 0.2 seconds to 1.7 seconds, and the number of times of opening and closing thereof is changed from, for example, 1 to 2 times. It is extended, and the operating rate is improved, in which the operating rate of the movable wing piece 42b per unit time is improved as compared with the normal gaming state.

By operating one or a plurality of types of each of the above functions, it is possible to bring about a change in the internal gaming state of the gaming machine.
Here, in the present embodiment, the operation start conditions of the normal symbol probability change function, the normal symbol time reduction function, and the open extension function are the same as the operation start conditions of the special symbol time reduction function, and each function operates at the same opportunity. Will be done.

[About hit]
In the pachinko gaming machine 1 of the present embodiment, the types of hits drawn in the special symbol variation display game, that is, the types of hits subject to the big hit lottery, are "15R low base non-probable big hit" and "15R low base probable change α". A plurality of types of hits such as "big hit", "15R low base probability variation β jackpot", "15R high base probability variation jackpot", "2R low base probability variation jackpot", and "small hit" are provided.

<5. Main control processing>
Hereinafter, the control process of the present embodiment will be described. First, the main processing by the main control unit (main control board) 50 will be described here.
FIG. 9 is a flowchart showing the main processing of the main control unit 50. The main process is started when the power is turned on without operating the initialization switch (not shown) as in the case of recovery from a power failure, and when the initialization switch is turned on and the power is turned on. May be turned on. In any case, when the power is turned on to the pachinko gaming machine 1, the power supply board 58 supplies a voltage to each control board. In this case, the main control unit 50 (main control CPU 100) starts the main process shown in FIG.

In this main control side main process, the main control CPU 100 first executes the necessary initial setting process before the start of the game operation in step S11. For example, it first sets itself to the interrupt disabled state, sets it to a predetermined interrupt mode (interrupt mode 2), and initially sets the register value inside the CPU including each part of the microcomputer.
Next, in step S12, the main control CPU 100 determines the state (ON, OFF) of the RAM clear signal, which is the output signal of the RAM clear switch input via the input port (not shown). The RAM clear signal is a signal that determines whether or not to initialize the entire area of the RAM. The RAM clear signal usually has a value corresponding to the ON / OFF state of the initialization switch operated by the pachinko parlor clerk.

When the RAM clear signal is in the ON state, the main control CPU 100 advances the process from steps S12 to S16 to zero-clear the entire area of the RAM. Therefore, the value of the backup flag set when the power is turned off becomes zero together with other checksum values.
Subsequently, in step S17, the main control CPU 100 transmits a "RAM clear display command" for notifying that the RAM area has been zero-cleared to each control board as an initialization command. Then, in step S18, for example, 30 seconds is stored in the RAM clear notification timer as the time for notifying that the RAM has been cleared.

Next, in step S19, the main control CPU 100 initially sets the CTC that outputs the interrupt signal that activates the timer interrupt operation, and sets the CPU to the interrupt enable state.
After that, as the processing of steps S20, S21, and S22, the interrupt prohibition state and the interrupt enable state are repeated until an interrupt occurs, and various random number update processes are executed during that time. In the various random number update processes in step S21, the random numbers used for changing the initial value (start value) of various random numbers used for the special symbol variation display and the normal symbol variation display, and the variation used for selecting the variation pattern. Update the random number for the pattern.
The various random numbers used for the special symbol variation display and the normal symbol variation display are, for example, random numbers related to the jackpot lottery circulating in a predetermined numerical range by increment processing (random numbers for special symbol determination used for the symbol lottery). Or, a random number related to the lottery for the auxiliary hit (a random number for determining the auxiliary hit used for the winning lottery for the auxiliary hit). Further, the random numbers used for changing the initial value are an initial value random number for special symbol determination, an initial value random number for auxiliary hit determination, and the like.

In the main control RAM 102, as various random number counters used for symbol lottery related to big hit lottery, auxiliary hit lottery, variable pattern lottery, etc., a random number counter for special symbol determination, a counter for generating initial values, and a random number counter for special symbol determination. , Auxiliary hit determination random number counter Initial value generation counter, auxiliary hit determination random number counter, fluctuation pattern random number 1 counter, fluctuation pattern random number 2 counter, and the like are provided. These counters serve as random number generating means for generating random numbers by software.
In the various random number update processes in step S21, two initial value generation counters for generating the initial values of the above-mentioned special symbol determination random number counter and auxiliary hit determination random number counter, a variation pattern random number 1 counter, and a variation pattern random number 2 The counters and the like are updated to generate the above-mentioned various soft random numbers. For example, assuming that the numerical range that can be taken as the random number 1 counter for the fluctuation pattern is 0 to 238, a value is acquired from the count value storage area for generating the value of the random number 1 for the fluctuation pattern of the main control RAM 102, and the acquired value is set to 1. Is added and then stored in the original count value storage area. At this time, if the result of adding 1 to the acquired value is 239, 0 is stored in the original random number counter storage area. The other random number counters for generating initial values are updated in the same manner. The main control CPU 100 repeatedly executes various random number update processes except during the timer interrupt process that is intermittently executed.

The above has described the case where it is determined that the RAM clear switch is ON in step S12. The case where the RAM clear switch is OFF will be described subsequently. For example, when recovering from a power failure state, the initialization switch (RAM clear signal) is in the OFF state. In such a case, the main control CPU 100 proceeds from step S12 to S13 to determine the backup flag value. The backup flag is set to the ON state when the power is cut off, and is reset to the OFF state at the first timer interrupt process after the power is restored.
Therefore, when the power is turned on or when the power is restored from the power failure state, the backup flag should normally be in the ON state. However, if for some reason the predetermined process is not completed before the power is turned off, the backup flag is reset (OFF). Therefore, when the backup flag is in the OFF state, the main control CPU 100 advances the process from steps S13 to S16, and returns the operation of the gaming machine to the initial state.

On the other hand, if the backup flag is in the ON state, the main control CPU 100 advances the process from steps S13 to S14 and executes a checksum operation for calculating the checksum value. Here, the checksum operation is an 8-bit addition operation for the work area of the main control RAM 102.
Then, when the checksum value is calculated, this calculation result is compared with the stored value of the SUM address of the main control RAM 102. The checksum value obtained by the same checksum calculation is stored in this SUM address when the power is turned off. Then, the stored calculation result is maintained by the backup power supply together with other data of the main control RAM 102. Therefore, originally, both should match by the determination in step S14.
However, the checksum calculation may not be executed when the power is turned off, or even if the checksum calculation can be executed, the data in the work area may be damaged before the checksum calculation of the main process is executed. In such a case, the determination result in step S14 will be inconsistent.
When data corruption is detected due to a discrepancy in the determination results, the main control CPU 100 proceeds to the processes of steps S14 to S16 to execute the RAM clear process, and returns the operating state of the gaming machine to the initial state.

When the checksum value obtained by the checksum calculation in step S14 and the stored value of the SUM address match, the main control CPU 100 proceeds to step S15, returns the stack pointer before the power is cut off based on the backup data, and returns the stack pointer. Executes the game recovery process required to start the game from the process state when the power is cut off.
When the game recovery process of step S15 is completed, the process proceeds to step S19, the CTC is initially set and the CPU is set to the interrupt enabled state, and then the interrupt prohibited state and the interrupt enabled state are set until an interrupt occurs. In the meantime, various random number update processes described above are executed (steps S20 to S22).

Next, the timer interrupt process of the main control CPU 100 will be described. FIG. 10 shows the timer interrupt process of the main control CPU 100. This main control timer interrupt process is started by an interrupt from the CTC at regular time intervals (about 4 ms), and is interrupted and executed during the above-mentioned main process execution.

When a timer interrupt occurs, the main control CPU 100 saves the contents of the register in the stack area, and then first performs a power supply abnormality check process for monitoring the power supply state from the power supply board 58 as step S51 in FIG. In this power supply abnormality check process, it mainly monitors whether or not the power supply is normally supplied. Here, in the event of an abnormality such as a power failure, a backup process is performed in which predetermined game information at the time of power failure is stored in the RAM so that the game can be returned without any trouble when the power is restored.

Next, in step S52, the main control CPU 100 performs a timer management process for managing the timer used for the game operation control. The timer values of various timers (for example, special symbol accessory operation timers) used for controlling the game operation of the pachinko gaming machine 1 are managed (updated) by this process.

In step S53, the main control CPU 100 performs an input management process. In this input management process, the detection information by various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. The detection information by the various sensors here includes, for example, an upper start port sensor 71, a lower start port sensor 72, a gate sensor (ordinary symbol start port sensor) 73, a first large winning opening sensor 75, and a second large winning opening sensor 76. , ON / OFF information (winning detection information) of the switch signal output from the winning detection switch such as the general winning opening sensor 74.
By the process of step S53, whether or not a prize is detected (a prize is generated) at each prize opening is monitored for each interrupt. Further, the above-mentioned "winning counter" is a counter provided corresponding to each winning opening and counting the number of winning game balls (number of winning balls). In the present embodiment, in a predetermined area of the main control RAM 102, an upper start opening winning counter for the upper starting port 41, a lower starting opening winning counter for the lower starting port 42a, a normal symbol starting opening winning counter for the gate 44, and the like. A first large winning opening winning counter for one large winning opening 45a, a second large winning opening winning counter for the second large winning opening 46a, a winning counter for the general winning opening for the general winning opening 43, and the like are provided. ..
Further, in this input management process, it is also monitored whether or not there is an illegal prize based on whether or not the detection information from the prize detection switch has won a prize during the period in which the prize should be allowed. For example, if the first and second big prize opening sensors 75 and 76 detect a game ball even though the big hit game is not in progress, this is regarded as an illegal prize and the prize detection information is invalidated and invalidated. A predetermined error process is performed in the error management process in step S55, which will be described later, in order to notify the outside to that effect.

In step S54, the main control CPU 100 performs a random number management process in the timer interrupt that periodically updates the random numbers related to each variation display. In this periodic random number update process, the random number for special symbol determination and the random number for auxiliary hit determination are updated (+1 addition for each interrupt), and the start value of the random number counter is changed every time the random number counter goes around. For example, the value of the special symbol determination random number counter is updated within a predetermined range (+1 addition), and each time the special symbol determination random number counter makes one round, the value of the special symbol determination random number counter initial value generation counter is read out. The value of the generation counter is stored in the special symbol determination random number counter. As a result, the start value of the special symbol determination random number counter is changed according to the value of the above generation counter, so that the count value of the special symbol determination random number counter becomes random even though the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process for monitoring the presence or absence of an abnormality in the game operation state. In this error management process, as abnormalities in the game operation state, for example, monitoring whether or not a disconnection has occurred between the boards, monitoring whether or not there has been an illegal winning, or the like, and these operation abnormalities (errors) have occurred. In that case, predetermined error processing corresponding to the error is performed.
As error processing, for example, the progress of a predetermined game operation (for example, a game ball payout operation, a game ball launch operation, etc.) is stopped, an error notification command is transmitted to the effect control unit 51, and an error is generated by the effect means. Is notified that an error has occurred.

In step S56, the main control CPU 100 performs the prize ball management process. In this prize ball management process, the data stored in the input management process of step S53 is grasped, the above-mentioned winning counter is confirmed, and if there is a winning, a payout control command for specifying the number of winning balls is paid out. It is transmitted to the board 53.
Upon receiving this payout control command, the payout control board 53 controls the game ball payout device 55 to perform a payout operation for a designated number of prize balls. As a result, the number of prize balls corresponding to each winning opening is paid out. The number of prize balls corresponding to the winning openings is the predetermined number of winning balls per winning opening set for each winning opening x the number of prize balls corresponding to the value of the winning counter.

In step S57, the main control CPU 100 performs a normal symbol management process. In this normal symbol management process, a lottery is performed for each auxiliary in the normal symbol variation display, and based on the lottery result, the fluctuation pattern of the normal symbol and the stop display mode of the normal symbol are determined, and blinking is repeated at predetermined time intervals. Create symbol data (LED blinking display data during normal symbol fluctuation), or create stop display data (LED blinking display data during normal symbol stop display) if the normal symbol is not fluctuating. Or something.

In step S58, the main control CPU 100 performs a normal electric accessory management process. In this ordinary electric accessory management process, an excitation signal for solenoid control for the ordinary electric accessory solenoid 77 and its data (solenoid control data) are generated based on the lottery result of the auxiliary hit lottery of the ordinary symbol management process in step S57. Make settings. Based on the data set here, an excitation signal is output to the normal electric accessory solenoid 77 in the solenoid management process in step S64 described later, whereby the operation of the movable wing piece 42b is controlled.
In step S59, the main control CPU 100 performs a special symbol management process. In this special symbol management process, a big hit lottery is mainly performed in the special symbol fluctuation display, and based on the lottery result, the fluctuation pattern of the special symbol (look-ahead fluctuation pattern, fluctuation pattern at the start of fluctuation), special stop symbol, etc. are selected. decide.
In step S60, the main control CPU 100 performs a special electric accessory management process. In this special electric accessory management process, mainly, when the big hit lottery result is "big hit" or "small hit", the setting process necessary for executing and controlling the winning game corresponding to the hit is performed.

In step S61, the main control CPU 100 performs right-handed notification information management processing. In this right-handed notification information management process, right-handed instruction is given in situations where right-handedness is advantageous, such as an opportunity to open the first and second prize openings 45a and 46a and an electric support state in which the movable wing piece 42b is driven. Performs processing for displaying the "launch position guidance effect (right-handed notification effect)" for notifying. The right-handed instruction is, specifically, an effect operation instructing the player to aim at the right-handed game area 3c. For example, the main liquid crystal display device 32M is made to display an image prompting the player to "right-handed". Or, a right-handed message voice is generated from the speaker 25.
When the right-handed notification effect is performed, in this right-handed notification information management process, a "right-handed instruction command" for instructing the execution of the right-handed notification effect is transmitted to the effect control unit 51 as an effect control command, and this command is received. Then, the effect control unit 51 controls the execution of the right-handed notification by the image or the sound.
In step S62, the main control CPU 100 performs the LED management process. This LED management process is a process of outputting display data for normal symbol display and first and second special symbol display to the symbol display unit 33. By this process, the variable display and the stop display of the normal symbol and the special symbol are performed. The display data of the normal symbol created by the normal symbol management process in step S57 and the display data of the special symbol created by the special symbol display data update process during the special symbol management process in step S59 are the LED management process. Is output.

In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management process, the operating state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. The operation state information includes the fact that the big hit game has occurred (the condition device has been activated), the fact that the small hit game has occurred, and the fact that the symbol variation display has been executed (the fact that the special symbol variation display game has started or ended). , Information such as prize information (information on the fact that a prize has been won in the starting opening or the big winning opening and the number of prize balls) is included.
In step S64, the main control CPU 100 performs a solenoid management process. In this solenoid management process, the excitation signal output process for the normal electric accessory solenoid 77 based on the solenoid control data created in the ordinary electric accessory management process in step S58 and the special electric accessory management process in step S60 are created. The excitation signal is output to the first and second winning opening solenoids 78 and 79 based on the solenoid control data. As a result, the movable wing pieces 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower start opening 42a and the large winning openings 45a and 46b are opened and closed.

After completing the processes of steps S51 to S64, the main control CPU 100 restores the saved register contents and sets the interrupt enabled state in step S65. As a result, the timer interrupt process is terminated, the process returns to the main control side main process of FIG. 9 before the interrupt, and the main control main process is performed until the next timer interrupt occurs.

In the above processing, the main control unit 50 (main control CPU 100) sequentially transmits necessary commands to the effect control unit 51.
As an example of the command, a part of the variation pattern command and the winning command related to the winning lottery of the special symbol variation display game is shown in FIG. 11A, and a part of the symbol designation command is shown in FIG. 11B.
The fluctuation pattern command and the winning command are configured so that the type of fluctuation pattern is defined by the upper byte and the lower byte, and the upper byte differs depending on the loss / hit.
The symbol specification command has a configuration in which the first and second special symbols are indicated by the upper byte and the hit type is specified by the lower byte.

<6. Processing of the production control unit of the first embodiment>
Next, the processing of the effect control unit 51 will be described. First, a structural example of scenario data for effect control will be described.
The structure of the scenario registration information will be described with reference to FIGS. 12 and 13. FIG. 12A shows the structure of scenario registration information as a main scenario and a sub-scenario. This scenario registration information is set using the work area provided in the effect control RAM 202 (for example, the built-in CPU work memory 202b).
In the present embodiment, the scenario registration information has 64 channels of scenario channels sCH0 to SCH63. The scenarios registered in each scenario channel SCH can be executed at the same time.

As shown in the figure, the information that can be registered in each scenario channel SCH includes the sub-scenario timer (scTm) used in the sub-scenario update process, the previous time (scPrevTm), and the sub-scenario execution line indicating the execution line of the sound / motor sub-scenario table. (ScIx), sub-scenario execution line lmp (lmpIx) indicating the execution line of the ramp sub-scenario table, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating the execution line of the main scenario table, There are a main scenario number (mcNo), a main scenario option (mcOpt), a user option (userFn), a waiting time (delay), and a checksum (checkSum), which are optional data that can be added to the main scenario.

When starting the production by the sound output by the speaker unit 59, the light emission by the lamp units 63 and 64, and the driving of the movable object accessory by the movable object accessory motor 65, the standby time (delay) and the main scenario number (mcNo) are set as scenarios. Register with a vacant scenario channel among channels SCH0 to SCH63.
The delay time indicates the time from registration to the scenario channel SCH until the scenario is started. The waiting time (delay) is subtracted by 1 at a predetermined processing timing (for example, step S104 in FIG. 16 described later). When the waiting time (delay) is 0, the process corresponding to the registered data is executed.

FIG. 14 shows an example of scenario numbers 1, 2, and 3 as a part of the main scenario table. As the scenario of each scenario number, the value of the main scenario timer (msTm) can be described as time data in each line (row) of the scenario, and the sub-scenario number (scNo) and option (OPT) can be described. .. That is, in the main scenario table, the sub-scenario (and option in some cases) to be executed is specified as the time by the main scenario timer (msTm). The scenario data end code D_SEEND or the scenario data loop code D_SELOP is described in the last line of the scenario.
The value of the main scenario timer (msTm) is incremented by 1 at a predetermined processing timing (for example, step S104 in FIG. 16 described later) from the start of the main scenario.
The scenario table of each scenario number advances to the next row after the time of the main scenario timer (msTm) in one row elapses. The time data for each row indicates when that row ends.
For example, in the case of scenario number 2, the operation of sub-scenario number 2 is specified as the time of the timer value "1500", the operation of sub-scenario number 20 is specified as the time of the next timer value "500", and the next timer value " The operation of sub-scenario number 21 is specified as the time of "2000". The next line is the scenario data exit code D_SEEND. In the case of the scenario data end code D_SEEND, this scenario is deleted from the scenario registration information (work).

Next, the structure of the lamp data registration information will be described with reference to FIG. 12B. As the lamp data registration information, information indicating a scenario selected from the lamp sub-scenario table, that is, an effect operation (lighting pattern) by the lamp units 63 and 64 is registered. This lamp data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the lamp data registration information has 16 channels of the lamp channels dwCH0 to dwCH15. Priority is set for each of the lamp channels dwCH0 to dwCH15, and the priority increases in order from the lamp channels dwCH0 to dwCH15. Therefore, the scenario (ramp sub-scenario) registered in the ramp channel dwCH15 is executed with the highest priority. Further, for example, if a scenario is registered in the lamp channels dwCH3 and dwCH10, the scenario registered in the lamp channel dwCH10 is preferentially executed.
The lamp channel dwCH0 is mainly used for a lamp effect associated with BGM (Back Ground Music), the lamp channel dwCH15 is used for an error-related lamp effect, and the lamp channels dwCH1 to dwCH14 are used for a normal effect.

As shown in the figure, the information that can be registered in each lamp channel dwCH includes a registered lighting number (lmpNew) indicating the registered lighting pattern number, an execution lighting number (lmpNo) indicating the execution lighting pattern number, and a lamp subscenario. There is an offset indicating the execution line, an execution time (time), and a checksum (checkSum).

FIG. 15A shows an example of lamp subscenario numbers 1, 2 and 3 as a part of the lamp subscenario table. As the lamp sub-scenario of each number, the value of the time data (time) is described in each line of the scenario, and the lamp channel and the lamp number indicating various lighting patterns are described. In addition, the ramp scenario data end code D_LSEND is described in the last line.

In this ramp sub-scenario table, the time data (time) of each line indicates the time when the line is started after the sub-scenario is started.
The above-mentioned main scenario timer (msTm) is compared with the time data of the table, and if they match, the lamp number of the line is registered in the lamp data registration information of FIG. 12B. The registered lamp channel dwCH is the channel indicated by the line.
For example, suppose that the scenario number 2 shown in FIG. 14 is registered and the sub-scenario number 2 is referred to in the above-mentioned certain scenario channel SCH. In the lamp sub-scenario number 2 shown in FIG. 15A, the lamp channel 5 (dwCH5) and the lamp number 5 are described with the time data (time) = 0 in the first line. In this case, when the main scenario timer (msTm) = 0, the information of the first line is first registered in the lamp channel dwCH5 of the lamp data registration information of FIG. 12B as the registration lighting number (lmpNew) = 5. The value of the sub-scenario execution line lmp (lmpIx) of the scenario registration information is updated to the value of the next line (second line). This is a registration for executing the lighting pattern operation of the lighting number 5 with a relatively low priority of the lamp channel dwCH5.
For the second line, the same processing is performed when the main scenario timer (msTm) reaches "500". That is, the registered lighting number (lmpNew) = 6 (that is, the indication of the lighting pattern of the lighting number 6) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) is the same value in two consecutive lines, the processing for each line will be started at the same time.
In the lamp drive data creation process described later, the lamp drive data is created based on the lamp data registration information updated in this way.

Next, the structure of the motor data registration information will be described with reference to FIG. 12C. As the motor data registration information, information indicating a scenario selected from the motor sub-scenario table is registered. This motor data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the motor data registration information is assumed to have eight channels of motor channels mCH0 to mCH7 corresponding to, for example, eight motors.
As shown in the figure, the information that can be registered in each motor channel mCH includes the execution operation number (no), the registration operation number (noNew), the operation count (lcnt), the excitation counter (tcnt), the execution step (step), and the operation line. (Offset), parent (migration source) / child (migration destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) ), Current input information (currentSw), switch information on software (softSw), count on software (softCnt).

FIG. 15C shows an example of the motor sub-scenario number 1 as a part of the motor sub-scenario table. As the motor sub-scenario of each number, the time data (time) value (ms) is described in each line of the scenario, and the motor and solenoid / user option information is described. In addition, the scenario data end code D_MSEND is described in the last line.

Regarding this motor sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (it is 0 at the beginning), the time data (time) value of this motor sub-scenario table is set in the sub-scenario timer (scTm). To do. The time data (time) of each line indicates the timing at which the line ends. The absolute time is described in the sub-scenario timer (scTm). Therefore, the time data value to be set is the value of (time data of the line concerned)-(time data of the previous line).
The motor data (motors 0 to 3, 4 to 7) is configured to indicate the motor operation pattern number (the number of the motor operation table of FIG. 21 to be described later) in 1 byte for each motor. The operation pattern number is set in the registration operation number (noNew) and the execution operation number (no) of the motor channel corresponding to the motor number.
In step S202 of FIG. 20, which will be described later, the motor data registration information is updated, and in step S203, motor drive data is created based on the update of the motor data registration information.

FIG. 13 shows sound data registration information. As the sound data registration information, information indicating a scenario selected from the sound sub-scenario table is registered. This sound data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the sound data registration information has 16 channels of sound channels aCH0 to aCH15.
As shown in the figure, the information that can be registered in each sound channel aCH includes volume transition amount (frzVq), volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0), and stereo (frzSt). ), Loop (frzLp), phrase number hi (frzHi), phrase number low (frzLo).

FIG. 15B shows an example of sound subscenario numbers 1 and 2 as a part of the sound subscenario table. As the sound / motor sub-scenario of each number, the time data (time) value (ms) is described in each line (line) of the scenario, and BGM, warning sound, error sound, and sound control information are described. To. In addition, the scenario data end code D_SEEND is described in the last line.
Regarding this sound sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (it is 0 at the beginning), the time data (time) value of this sound sub-scenario table is set in the sub-scenario timer (scTm). To do. The time data (time) of each line indicates the timing at which the line ends. The absolute time is described in the sub-scenario timer (scTm). Therefore, the time data value to be set is the value of (time data of the line concerned)-(time data of the previous line).
The BGM data of the line is composed of information registered in the sound data registration information such as the phrase number and volume value of the BGM, and is set in the sound channel aCH0 (additionally aCH1 in the case of stereo) in the sound data registration information. ..
The warning sound data of the line is composed of information to be registered in the sound data registration information such as the phrase number and the volume value of the warning sound, and is set in a vacant place of the sound channels aCH2 to aCH14.
The error sound data of the line is composed of information registered in the sound data registration information such as the phrase number and the volume value of the error sound, and is set in the sound channel aCH15.
The sound control data has the lower 6 bytes as channel information and the upper 2 bytes as control information.
In step S133 of FIG. 16, which will be described later, playback output control is performed based on the scenario update process and the updated sound data registration information.

The sound sub-scenario table and the motor sub-scenario table may have a table structure integrated for each time line.

An example of the processing of the effect control unit 51 that performs the effect control using the scenario data structure as described above, particularly the process of the effect control CPU 200, will be described with reference to FIG.
The effect control CPU 200 starts the process of FIG. 16 when the power is turned on to the gaming machine main body. The effect control CPU 200 first performs necessary initial setting processing before the start of the game operation in step S100. For example, as initial setting processing, interface system initialization, interruption setting, external memory initialization, WDT initialization, starting point return processing and control initialization of a movable body accessory, sound source control initialization, serial output controller 240 Initializes, initializes the scheduler (scenario scheduler, device scheduler, lamp scheduler, sound scheduler), initializes the system timer, initializes the liquid crystal control, and so on.
Each scheduler refers to the above-mentioned scenario registration information, motor data registration information, lamp data registration information, sound data registration information, or the progress of scenario control based on these. As the initialization process, the work area for storing the scenario registration information and the like is initialized.

When the initial setting process of step S100 is completed, the effect control CPU 200 repeats the processes after step S101.
In particular, in the present embodiment, the effect control CPU 200 executes the processes after step S101 while monitoring the frame timing of the display data in order to perform the liquid crystal control at the same time. In this example, control is performed based on a V blank signal, which is a synchronization signal used for display control. A synchronization signal of display data such as a V blank signal is generated at a portion of the one-chip microcomputer 250 that realizes the VDP function. For example, it is generated by the synchronization signal generation unit 265. In the present embodiment, the V blank signal is generated twice during 1/30 second (33.3 ms), which is one frame period of the displayed image.
Since the effect control CPU 200 counts up the V blank interrupt counter in response to the V blank signal, the V blank interrupt counter counts up every 1/60 second (16.6 ms).
As a matter of course, the individual processing of the effect control CPU 200 is performed based on the processing clock having a frequency extremely higher than the frequency of the V blank signal. Each process of FIG. 16 is performed while grasping the period from the start to the end of the frame according to the V blank signal. At the start of the frame, the processes are performed once in steps S103 to S106, and then the V blank. Steps S121 to S143 are repeated until the end of the one-frame period is confirmed by the value of the interrupt counter. Steps S150 to S151 are performed when the end of one frame period is detected.

In step S101, the effect control CPU 200 performs clear control on the WDT circuit 210. Therefore, the WDT circuit 210 is reset every frame if the effect control CPU 200 is in a normal processing state.
In step S102, the effect control CPU 200 confirms the frame update flag. The frame update flag is a flag for managing scheduler updates and the like in a frame period.
The frame update flag is turned off at the start of a certain frame of the display data (because it is turned off in step S151 described later at the end of the frame).
Therefore, at the frame start timing, the effect control CPU 200 proceeds from step S102 to S103.

In step S103, the effect control CPU 200 updates the drawing. For example, it creates a display list, which is a group of drawing commands described in the order of drawing as described above, and controls the execution start of preload.

In step S104, the effect control CPU 200 updates the frame of the scenario scheduler. Specifically, this is a process of updating the waiting time (delay) and the sub-scenario timer (scTm) of the scenario registration information of FIG. 12A. That is, it can be said that the timer of the effect scenario is advanced by one timing at the start of the frame.
Then, the effect control CPU 200 turns on the frame update flag in step S105. This is information indicating that the timer of the scenario has progressed in the current frame.
Further, the effect control CPU 200 turns off the scheduler update flag in step S106. This is information indicating that the scheduler update, that is, the update of the scenario contents (scenario registration information, lamp data registration information, sound data registration information) accompanying the progress of the timer has not been performed yet.
Then, the process returns to step S101. After the effect control CPU 200 clears the WDT circuit 210, the frame update flag is turned ON in step S102, so that the process proceeds to step S120.

As described above, steps S103 to S106 are performed only once after the frame start timing, and in step S104, the timer of the scenario registration information is updated. As will be described later, content update and control are executed according to the progress of the timer of the scenario. Therefore, the scenario for the production progresses every 33.3 ms, which is one frame period. For example, the main scenario timer (msTm) advances every 33.3 ms. The time of the main scenario timer (msTm) in one row in the main scenario table of FIG. 14 corresponds to the time of the indicated value × 33.3 ms. Further, the time of one line indicated by the time in the sub-scenario table of FIG. 15 also corresponds to the time of the indicated value × 33.3 ms.

In step S120, the effect control CPU 200 branches the process according to the value of the V blank interrupt counter. If the V-blank interrupt counter has not reached “2” (that is, if it is “0” or “1”), the process proceeds to step S121.
The V-blank interrupt counter is cleared at the end of the frame in step S150 and is incremented twice in one frame. Therefore, the V blank interrupt counter = 0 indicates the first half period of the frame, and the V blank interrupt counter = 1 indicates the second half period of the frame. The V blank interrupt counter = 2 at the V blank signal at the end of the frame.
The effect control CPU 200 proceeds from steps S120 to S121 so as to repeat steps S121 to S143 as many times as possible during the frame period in which the V-blank interrupt counter is “0” or “1”.

In step S121, the effect control CPU 200 branches the process depending on whether the V blank interrupt counter is “0” or “1”. That is, whether the present is the first half or the second half of a certain frame period.
Currently, if the V blank interrupt counter = 0, that is, the first half of the frame, the process proceeds to step S122 to confirm the received command from the main control unit 50. That is, it is confirmed whether or not one or more received commands are stored in the receive buffer for commands. If there is no receive command, the process proceeds to step S130.
If there is one or a plurality of received commands, the effect control CPU 200 performs command analysis processing in step S123.
Then, the effect control CPU 200 turns off the scheduler update flag in step S124. Note that turning off the scheduler update flag in step S124 means that if a command is received during the current frame period, even after the scheduler update flag has been turned off in step S131 before. It has the meaning of turning it off.

An example of the command analysis process in step S123 will be described with reference to FIGS. 18 and 19.
As described above, in step S122 of FIG. 16, the effect control CPU 200 confirms whether or not the effect control command supplied from the main control unit 50 is stored in the command reception buffer, and if the effect control command is stored. The command will be read by the process shown in FIG.

In the effect control unit 51, a command reception buffer for taking in the effect control command transmitted from the main control unit 50 is prepared in the effect control RAM 202 (for example, D-RAM 202a).
First, in step S301 of FIG. 18, the effect control CPU 200 confirms the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address.
The light pointer is updated in response to command reception, and the received effect control command is stored at the address indicated by the light pointer accordingly. The read pointer is updated (step S302) when reading from the command reception buffer. Therefore, if the read pointer = the write pointer, the effect control command that has not been read yet is stored in the command reception buffer. Therefore, if the read pointer is not a write pointer, the process proceeds to step S302, and the effect control CPU 200 loads 1 byte of command data from the address indicated by the read pointer in the command reception buffer. In this case, the read pointer is incremented for the next read (load).

Actually, the presence or absence of the reception command in step S122 of FIG. 16 can also be determined by whether or not the read pointer = the write pointer. As an actual program, if the read pointer = the write pointer at the time when the command check process is first performed, it may be determined in step S122 of FIG. 16 that there is no receive command.

As described above, one effect control command is formed by two bytes, one byte as a mode and one byte as an event. In step S303 of FIG. 18, the effect control CPU 200 confirms whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit7 out of 8 bits (Bit0 to Bit7).
If the mode is set, the process proceeds to step S304 as a process of receiving higher-level data of the command, and the read command data is saved in the register "command HI byte". It also clears the "command LO byte" register. Then, the process returns to step S301.
Even after that, if the read pointer = the write pointer, the effect control command that has not been read yet is stored in the command reception buffer. Therefore, the process proceeds to step S302, and the effect control CPU 200 uses the read pointer in the command reception buffer. Load 1 byte of command data from the indicated address. It also increments the read pointer.
If the read command is an event, the process proceeds from step S303 to S305 as a process of receiving lower-level data of the command, and the read command data is saved in the register "command LO byte".

By saving the command data of the mode and the event in the registers "command HI byte" and "command LO byte", the effect control CPU 200 has taken in one command.
Therefore, in step S306, the effect control CPU 200 performs processing according to the captured command. A specific example will be described later in FIG.

The read pointer = write pointer is when there is no effect control command in the command reception buffer that has not yet been captured by the effect control CPU 200. By confirming the read pointer = write pointer in step S301, the command analysis process as step S123 in FIG. 16 ends.

An example of the command correspondence process in step S306 will be described with reference to FIG.
FIG. 19A shows a basic process as a command corresponding process. In response to the reception of the 2-byte effect control command, the effect control CPU 200 first confirms in step S321 of FIG. 19A whether or not the test mode is currently in progress. If the test mode is in progress, step S322 clears all the production scenarios, stops the sound output, and turns off the LEDs in the lamp units 63 and 64. Then, the test mode is terminated in step S323.
If you are not in test mode, do not perform these processes.
Then, as step S330, the effect control CPU 200 performs processing on the captured effect control command.

As the effect control command, for example, a special symbol fluctuation pattern designation command, a special symbol designation command, a hold ball subtraction command, a hold ball addition command, an error display designation command, a jackpot start designation command, and the like are set in various ways. In step S330, the effect control CPU 200 performs the process specified by the program in response to the received command. Here, specific processing is illustrated by listing four effect control commands in FIGS. 19B to 19E.

FIG. 19B shows the process S330a when the variation pattern command is taken in as the command process in the step S330.
In this case, the effect control CPU 200 performs a process of setting the symbol command waiting state in step S331. This is because the effect control CPU 200 controls the variation display of the symbol by sequentially receiving the variation pattern command and the symbol command.

FIG. 19C shows the process S330b when the symbol designation command is incorporated as the command process in step S330.
In this case, the effect control CPU 200 first confirms in step S332 whether or not the variation pattern command has been received. If it has not been received, the process ends as it is.
If the variation pattern command has already been received when the symbol designation command is received, the process proceeds to step S333, and first, the scenario registration for the operation of the accessory origin correction is performed. Then, in step S334, the symbol variation flag is set. The symbol fluctuation flag is provided corresponding to each of the first special symbol, the second special symbol, and the normal symbol, and each flag represents the fluctuation state. For example, a 2-bit first special symbol fluctuation flag FZ1, a second special symbol fluctuation flag FZ2, and a normal symbol fluctuation flag FZ3 are prepared, and each of them indicates changing, stopping (hit), and stopping (missing). Here, with the start of fluctuation, the corresponding symbol fluctuation flag (one of FZ1, FZ2, FZ3) is set to a value indicating "changing".
In the case of a hit, the symbol variation flag is set to a value indicating "stopped (hit)" for a predetermined time at the end of the symbol variation, and then a value indicating "stopped (off)" until the symbol variation is started. Is set to.
In step S335, the effect control CPU 200 performs the fluctuation start process. After that, the fluctuation pattern command is deleted in step S336 according to the start of fluctuation.

FIG. 19D shows the process S330c when the power-on command is taken in as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S337. For example, the contents of the command reception / transmission buffer and the input information buffer for the operation unit 60 and the checksum storage area are cleared.
Then, in step S338, an error release command is transmitted, in step S339, the accessory error information is cleared, in step S340, the accessory operation is stopped, in step S341, the power-on scenario is registered, and in step S342, the power is turned on to be transmitted to the liquid crystal control board 52. Set commands in sequence.

FIG. 19E shows the process S330d when the RAM clear command is taken in as the command process in step S330.
In this case, the effect control CPU 200 clears the effect control RAM 202 in step S343. For example, the contents of the command reception / transmission buffer and the input information buffer for the operation unit 60 and the checksum storage area are cleared.
Then, in step S344, an error release command is transmitted, and in step S345, a RAM clear error set and an error notification timer are set. Further, in step S346, the information related to the lottery process in the effect control RAM 202 is cleared, and in step S347, the information related to the scenario is cleared. Then, in step S348, the power initial on display (RAM clear) command to be transmitted to the liquid crystal control board 52 is set.

The processing corresponding to the command reception has been described above.
The processing of steps S122 to S124 of FIG. 16 as the processing corresponding to the above command reception is started only during the period of V blank interrupt counter = 0.

Subsequently, the effect control CPU 200 confirms the scheduler update flag in step S130 of FIG. 16 and branches the process. Here, the processing of steps S131 to S134 is performed only when the scheduler update flag is off.
Then, in step S131, the frame update flag is turned on.
Since the scheduler update flag is turned off in step S106 immediately after the start of the frame, the processes of steps S131 to S134 are performed when the process of step S130 is first performed in the current frame period. Further, since the scheduler update flag is turned off in step S124, the processes of steps S131 to S134 are performed even when a command is received.

The effect control CPU 200 performs a process as a scenario scheduler execution in step S132. This is the process of updating the scenario registration information. For example, among the information registered in the scenario channel SCH, the processing corresponding to the registered data is executed for the information whose waiting time (delay) is 0. That is, processing is performed according to the scenario number specified in the main scenario table. The main scenario execution line (mcIx), sub-scenario execution line (scIx), sub-scenario execution line lmp (lmpIx), etc. are also updated.
In step S133, the effect control CPU 200 executes the sound scheduler and processes the output. This is the update processing of the sound data registration information according to the sound sub-scenario specified in the scenario table, and the output processing of the sound control signal based on the sound data registration information. The effect control CPU 200 causes the sound controller 230 to execute sound output according to the progress of the current scenario.

In step S134, the effect control CPU 200 performs the lamp scheduler execution process.
This is a process of updating the lamp data registration information according to the lamp sub-scenario specified in the scenario table.
For example, the effect control CPU 200 performs the following processing for each of the lamp channels dwCH0 to dwCH15. First, the main scenario timer (msTm) and the time data (time) of the lamp sub-scenario table are compared. The time data (time) in the ramp sub-scenario table indicates the time (ms) at which the line (the line indicated by the sub-scenario execution line lmp (lmpIx)) is started. Therefore, if the time of the main scenario timer is equal to or longer than the time data (time), the processing for that line is performed.
For example, first, it is determined whether or not the current line is the line in which the ramp scenario data end code D_LSEND is described. If the line is not the line in which the lamp scenario data end code D_LSEND is described, the effect control CPU 200 acquires the lamp channel dwCH and the lamp number described in the line, and registers the lighting pattern number in the acquired lamp channel dwCH. ..
Further, the registered lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH. That is, the lamp number acquired from the line in the lamp sub-scenario table is set to the registered lighting number (lmpNew), and "0" is set to the execution lighting number (lmpNo). Also, the value of the sub-scenario execution line lmp (lmpIx) is incremented by 1. As described above, the lamp data registration information is updated to the state in which the lamp effect operation to be executed is registered.

In step S134, the lamp data registration information is updated as described above, and the lamp drive data creation and the lamp drive data output based on the updated lamp data registration information are performed in the later steps S141 and S142.

In step S140, the effect control CPU 200 branches the process according to the value of the V blank interrupt counter. If the V-blank interrupt counter is "0", the processes of steps S141 to S143 are executed, and if it is "1", these processes are not executed.
In step S141, the effect control CPU 200 creates lamp drive data. That is, the lamp drive data that is actually output from the serial output controller 240 to the frame driver unit 61 and the panel driver unit 62 is generated based on the information registered in each lamp channel dwCH of the lamp data registration information.
Then, in step S142, the generated lamp drive data is transferred to the serial output controller 240 and controlled so as to be output as serial data.
In step S143, the effect control CPU 200 performs key event processing. Then, the process returns to step S101.
The process of creating and outputting the lamp drive data in steps S141 and S142 is started only when the V blank interrupt counter = 0. That is, these processes are started only during the first half of the frame.

After the V-blank interrupt counter = 2, that is, when the end of the frame period is detected, the effect control CPU 200 performs the frame end processing of steps S120 to S150.
Here, the effect control CPU 200 performs processing such as waiting for drawing completion, clearing the V blank interrupt counter, switching the display screen, waiting for preload completion, and starting drawing.

A specific example of the frame end processing is shown in FIG.
In step S171, the effect control CPU 200 waits for the completion of drawing. This waits for the completion of drawing the image to be displayed in the next frame period.
As described above, the VRAM 209 is provided with frame buffers 209A and 209B, and during the frame period in which the display circuit 221 or the like reads and displays one display data, the display data of the next frame is stored in the other frame buffer. Drawing is done. It is confirmed in step S171 that this drawing is completed.

Normally, at the end of this frame period, the drawing of the display data of the next frame is designed to be completed. If the drawing is not completed at this point, it is assumed that there is some problem in the drawing process.
Therefore, when a drawing completion wait occurs, the waiting time may be counted, and depending on the waiting time, changes such as reducing the number of drawings accessed in one frame period may be made.
Further, if the wait is a little (about 1 ms), the processing of the next frame is only slightly delayed, so that there may be no particular problem.
If the drawing is not completed even after waiting for a long time, the processing of the effect control CPU 200 is reset by the WDT circuit 210.

After confirming the completion of drawing, the effect control CPU 200 clears the V blank interrupt counter in step S172.
Then, in step S173, the display screen is swapped. That is, the VRAM 209 switches the frame buffers for reading the display data for the frame buffers 209A and 209B.
It is conceivable that the frame buffer is switched unconditionally because the V blank interrupt counter = 2, but in the case of this embodiment, the frame buffer is switched after confirming the drawing completion in step S171. It is said. Therefore, the display data transferred to the display circuit 221 or the like is the display data for which drawing is completed correctly. That is, if the drawing is not completed by the second time of the vertical synchronization signal, the display data of the frame buffer being drawn will not be displayed.

In step S174, the effect control CPU 200 confirms the completion of preloading.
The preload is usually designed to finish within one frame period, but this is confirmed in step S174.
Even if the preload is delayed to some extent, the output of the display data of the next frame has already started in step S173, so that it does not pose a big problem.
After that, the process of writing the preloaded display list in step S175 to the frame buffer opposite to the frame buffer switched to the display data read target in step S173 is performed.

After performing the above processing at the end of the frame, the frame update flag is turned off in step S151 of FIG. 16, and the process returns to step S101. Then, as explained, the processing for the new frame period is performed.

In addition to the above processing of FIG. 16, the effect control CPU 200 executes the processing of FIG. 20 as, for example, an interrupt processing every 1 ms. That is, the process of FIG. 20 is a process executed every 1 ms regardless of the frame timing of the display data.
The effect control CPU 200 performs the WDT pulse generation process in step S200. The WDT circuit 210 counts every 1 ms by this WDT pulse.
In step S201, the effect control CPU 200 performs the sensor update process of the motor and the solenoid. This is a process of detecting the information of each sensor 68S as the origin switch 68 described above.

In step S202, the effect control CPU 200 performs the device scheduler execution process. Specifically, the motor data registration information is updated. Further, in step S203, the motor drive data is output to the motor driver 70 as the device scheduler output process.
That is, the effect control CPU 200 controls the motor operation every 1 ms, which is a time interval of about 1/30 of the frame period.

Here, the motor operation table used for the motor operation control according to the motor data registration information will be described. 21A to 21D illustrate four motor operation tables. Each motor operation table is numbered, for example, these are motor operation tables 1, 71, 72, x.

The motor operation table is a table in which one row (one control item) is composed of three contents of option (OPT), speed (SPEED), and step (STEP). Option (OPT) indicates the control type, and Speed (SPEED) and Step (STEP) indicate the indicated value for the control content indicated by the control type.
With this structure, one line (one control item) is information that defines one control process, and in principle, a series of operation patterns are specified in the form that the processes of each line are sequentially performed.

As options (OPT) indicating the control type, in this example, various operation types are defined as an operation system option indicating the control content of the motor operation and a non-operation system option indicating the control content not accompanied by the operation of the motor. ..
In the case of the operation system option, the speed (SPEED) is an indicated value indicating the motor drive speed, and the step (STEP) is an indicated value indicating the motor operating range (the number of steps of the stepping motor).
On the other hand, in the case of the non-operation type option, the speed (SPEED) is set as an instruction value for specifying the next processing such as the next transition line (number of progress lines), link destination, and number of loops. Steps are usually not used.
In this way, the indicated value, speed (SPEED), is shared by the operating system option and the non-operating system option, but the meanings of the instruction contents are different.

It should be noted that the execution step (step) of the motor data registration information in FIG. 12C and the step (STEP) of the above motor operation table are different. The execution step (step) is a variable updated in the motor operation update process in step S202, and the step (STEP) in the motor operation table is information for designating the number of driving steps of the motor operation.

The operating options are as follows. The "origin SW" is an origin switch 68 for detecting the position of a movable body accessory operated by each motor.
cw_all ・ ・ ・ Forward rotation operation: Operates when the origin SW is on / off
cw_on ・ ・ ・ Forward rotation operation: Stop when the origin SW is on, operate when the origin SW is off
cw_off ・ ・ ・ Forward rotation operation: Operation when the origin SW is on, stop when the origin SW is off
ccw_all ・ ・ ・ Reverse operation: Operates when the origin SW is on / off
ccw_on ・ ・ ・ Reverse operation: Stop when the origin SW is on, operate when the origin SW is off
ccw_off ・ ・ ・ Reverse operation: Operation when the origin SW is on, stop when the origin SW is off
stop ・ ・ ・ Stop operation (without excitation)
keep ・ ・ ・ Stop operation (with excitation)
cw_on2 ・ ・ ・ Forward rotation operation: Stop when the origin SW is on, operate when the origin SW is off
cw_off2 ・ ・ ・ Forward rotation operation: Operation when the origin SW is on, stop when the origin SW is off
ccw_on2 ・ ・ ・ Reverse operation: Stop when the origin SW is on, operate when the origin SW is off
ccw_off2 ・ ・ ・ Reverse operation: Operation when the origin SW is on, stop when the origin SW is off
cw_btn ・ ・ ・ Forward rotation operation: operation when the button is pressed, stop when the button is not pressed
ccw_btn ・ ・ ・ Reverse operation: Operation when the button is pressed, stop when the button is not pressed

The non-operating options are as follows.
sys_ck1 ・ ・ ・ Origin SW off: Move to next line, Origin SW on: Move specified number of lines (SPEED value)
sys_ck2 ・ ・ ・ Origin SW off: Move the specified number of lines (SPEED value), Origin SW on: Move to the next line
sys_ck3 ・ ・ ・ Origin SW off: Move to next line, Origin SW on: Move specified number of lines (SPEED value)
sys_ck4 ・ ・ ・ Origin SW off: Move the specified number of lines (SPEED value), Origin SW on: Move to the next line
roop_s ・ ・ ・ Loop start point: Number of loops = SPEED value
roop_e ・ ・ ・ Loop end point
link ・ ・ ・ Link command: The link destination is the motor operation table with the number shown in the SPEED value.
err_cnt ・ ・ ・ Error counter +1
sys_err ・ ・ ・ No error command
sys_erc ・ ・ ・ There is an error command
nor_end ・ ・ ・ Normal end: No origin check
chk_end ・ ・ ・ Check end: Check the origin, and if it is not the origin, an error occurs.

Each motor operation table as shown in FIG. 21 defines an operation pattern.
For example, in the motor operation table 1 of FIG. 21A, an operation pattern as an initial operation process is defined. This operation pattern is as follows.
The first line, sys_ck1 (system check 1), checks whether it is within the origin.
If it is within the origin, it shifts to the link (link instruction) of the "7" destination specified by the speed (SPEED: in this case, the number of traveling lines).
If it is outside the origin, it shifts to the second line, which is the next line. In the second line, it is moved toward the origin by ccw_on (reverse operation). Here, according to "6" specified by the speed (SPEED), one-step driving is performed at intervals of 6 counts of the operation count (lcnt) (see FIG. 16C) "8" times indicated by the step (STEP). Since the operation count (lcnt) is updated every 1 ms, the operation of this second line drives the stepping motor to return to the origin for 8 steps at a speed of 1 step in 6 ms. Become.
Therefore, in the case of the operation system option, the time required for processing one line is SPEED × STEP × 1 ms.

Next, in the third line, it is continuously moved toward the origin by ccw_on (reverse operation). In the operation of the third line, the stepping motor is driven at a speed of one step every 3 ms for twice the total number of steps. That is, the operation of returning to the origin is performed at a speed higher than that of the second line. Since ccw_on is stopped when the origin switch is turned on, the processing of the third line ends when the origin switch is reached.

Since the origin should have been returned by the processing of the second and third lines above, sys_ck1 (system check 1) on the fourth line checks whether or not the origin is within the origin.
If it is within the origin, it shifts to ccw_all (reverse operation) of the 6th line of the "2" destination specified by the speed (SPEED: in this case, the number of traveling lines).
If it is outside the origin, it shifts to the next line, the link (link command) on the fifth line. Since the motor operation table 71 (FIG. 21B) is specified in the link (link instruction) on the fifth line, the retry operation of the motor operation table 71 is executed. When the retry operation of the motor operation table 71 is normally completed (nor_end), the link (link instruction) on the fifth line is completed, and the process proceeds to the next sixth line.

In the sixth line, ccw_all (reverse operation) is used to drive the stepping motor so as to return it toward the origin for 58 steps at a speed (high speed) of 1 step in 3 ms.
Further, in the next 7th line, the stepping motor is driven to return to the origin for 8 steps at a speed (low speed) of 1 step in 6 ms, also as ckW_all (reverse operation).
The 6th and 7th lines are further pushed in after confirming that they are within the origin, and this pushing operation is performed in two stages of high speed → low speed.

When the inside of the origin is confirmed in the 1st line, or after the 6th and 7th lines are pushed in, the process proceeds to the link (link command) in the 8th line, and the speed (SPEED: in this case, the link destination). ) Will be transferred to the motor operation table 72 (FIG. 21C).
The motor operation table 72 defines an operation pattern as a reciprocating operation, and when this is normally terminated (nor_end), the link (link command) on the 8th row of the motor operation table 1 is terminated, and the next 9 rows. Go to the eyes. The ninth line is nor_end (normal end), and the initial operation process as the motor operation table 1 ends here.

Here, the initial operation processing as the motor operation table 1 has been described, but as in this example, each motor operation table specifies the required operation for each row, and the number of rows to be skipped and the link destination depending on the case. The operation pattern is defined as a structure in which the motor operation table number, the number of loops, etc. can be specified.
Although not described, the motor operating tables of FIGS. 21B, 21C, 21D and many other motor operating tables (not shown) are also based on options (OPT), speed (SPEED), and steps (STEP) in each row. The operation is specified, and a series of operation patterns are specified.
FIG. 21B shows the operation pattern of the motor for the retry operation, FIG. 21C shows the operation pattern of the motor for the reciprocating operation, and FIG. 21D shows the operation of the motor for making the accessory "appear → swing 10 times → return". This is an example of a motor operation table showing operation patterns.

With respect to motor control, such a motor operation table defines fine motor operation. In steps S202 and S203 of FIG. 20, registration of the sub-scenario in the motor data registration information of FIG. 12C and control according to the motor operation table designated in this sub-scenario are executed.

For example, the effect control CPU 200 sets the number of the motor operation table described in the motor sub-scenario table in the motor registration information (work) with respect to the motor data registration information shown in FIG. 12C. That is, in the motor data registration information, the execution operation number (no) and the registration operation number (noNew) are set in the motor channel mCHn corresponding to the motor MT (n) currently to be registered.
In this case, the motor operation table number described in the motor sub-scenario table is written in the registration operation number (noNew). The execution operation number (no) is updated to the motor operation table number (operation pattern number) when it is actually executed, and is set to "0" at this point.
As a result, the number of the motor operation table is registered in each motor channel mCH of the motor data registration information (work) according to the contents of the motor sub-scenario table.

After the motor operation table number is registered, the operation shown in each row of the motor operation table of that number is sequentially designated as the operation to be controlled.
For example, the following processing is roughly performed for each of the motors MT (n) (n = 0 to 7) corresponding to the motor channels mCH0 to mCH7 of the motor data registration information.
In the following description, the data described in the option (OPT) of the motor operation table is "D_OPT", the data described in the speed (SPEED) is "D_SPEED", and the data described in the step (STEP) is "". Notated as "D_STEP".

The effect control CPU 200 first confirms whether or not the execution operation number (no) and the registration operation number (noNew) in the target motor channel mCHn match, and if they do not match, the operation is started and the motor channel mCHn is set to the operation start. Clear the corresponding excitation output data and substitute the value of the registered operation number (noNew) for the execution operation number (no).
Further, the effect control CPU 200 has an operation count (lcnt), an operation line (ofset), an execution step (step), a loop start point (roopAddr), a loop count (roopCnt), a parent number (retNo), and a return address of the motor channel mCHn. (RetAddr) and error counter (errCnt) are set to 0 respectively. In addition, the value of "5A" indicating the parent is set in the attribute of the parent (migration source) / child (migration destination).
The above is the process when the control based on the registered motor operation table is started.

After that, the following processing is performed.
The effect control CPU 200 acquires data of the motor operation table corresponding to the motor MT (n), the execution operation number (no), and the operation line (ofset).
That is, the data "D_OPT", "D_SPEED", and "D_STEP" of the row indicated by the operation line (ofset) in the motor operation table indicated by the execution operation number (no) are acquired. Since the operation line (ofset) is initially set to 0, the data "D_OPT", "D_SPEED", and "D_STEP" of the first row of the specified motor operation table are acquired. For example, if the execution operation number (no) is 72, the first rows of the motor operation table 72 in FIG. 21C, "cw_off", "6", and "8", are acquired as "D_OPT", "D_SPEED", and "D_STEP". become.

Then, the effect control CPU 200 confirms whether the data "D_OPT" is the data of the operating system option or the data of the non-operating system option.
If it is the data of the non-operating system option, the processing is performed according to the non-operating system option. For example, the process specified by the above "sys_ck1", "roop_s", etc. is performed.

If it is the data of the operation system option, the process accompanied by the drive control is performed. For example, the value of the operation count (lcnt) and the value of "D_SPEED" are compared to determine whether or not it is the update timing of the excitation output data.
In the case of the operation system option, the value of "D_SPEED" indicates the interval of one-step drive of the stepping motor. If "D_SPEED" = 6, the one-step drive is performed once every six times. The operation count (lcnt) is a value that is first set to "0" in step S1604 and then incremented, that is, is incremented by 1 for each 1 ms timer interrupt process.
Therefore, when the operation count (lcnt) = "D_SPEED" -1, it is the update timing of the excitation output data.

If it is not the update timing of the excitation output data, the operation count (lcnt) is incremented, the processing of the current motor channel mCHn is completed, and the process proceeds to the processing of the next motor channel mCH.
When it is the update timing of the excitation output data, the effect control CPU 200 increments the execution step (step) on the motor data registration information. The execution step is a variable that counts whether or not the number of steps indicated by "D_STEP" acquired from the motor operation table has been reached. Then, processing according to the operation system option indicated by "D_OPT", for example, processing for the operation indicated as "cw_all", "cw_on", etc. is performed.

The above is an outline of the process, but as the device scheduler execution process in step S202 of FIG. 20, the motor data registration information is updated so that the contents to be executed sequentially are shown as described above. That is, the content of the line (operation line) to be executed every 1 ms is specified for the motor operation table registered in the motor data registration information.
Then, in step S203, the effect control CPU 200 generates motor drive data corresponding to the contents of the rows of the designated motor operation table for each motor channel mCHn, and controls the motor channels to be output from the serial output controller 240.

In step S204 of FIG. 20, the effect control CPU 200 performs a key input process. That is, the signals corresponding to the operations of the effect buttons 11, 12, the cross key 13, and the like are confirmed.
As shown in FIGS. 4 and 8, the detection information of the sensor 68s and the operation information of the effect buttons 11 and 12 and the cross key 13 can be detected as serial input data. Therefore, the key input process may be confirmed at the same time as the detection information of the sensor 68s in step S201. This makes the detection process more efficient.

Although the processing example of the effect control CPU 200 has been described so far, in the above processing example, the effect control CPU 200 performs various processes according to the frame of the display data.
FIG. 22 shows various timings for each frame period of the display data.
Let each frame of the display data be frames FR0, FR1, FR2, and so on. For example, the frame FR0 is displayed at the time points T0 to T1, and the frame FR1 is displayed at the time points T1 to T2.
Since the value of the V blank interrupt counter is cleared in step S150 of FIG. 16 (S172 of FIG. 17), it is "0" at the start of the frame and at the middle of the frame (time T0m, T1m, etc.) as shown in the figure. It becomes "1" and is cleared immediately after it becomes "2".

The drawing process by the drawing circuit 225 is executed for the display data of the next frame within the frame period. For example, the drawing of the display data of the frame FR1 is executed within the time points T0 to T1 which is the display period of the frame FR0. Specifically, since drawing is started in step S150, drawing for the next frame is started at the beginning of the frame. This drawing is usually completed within the frame period.
If, for example, the drawing started at the time point T0 is not completed at the time point T1, the completion is awaited in step S171 of FIG.

The preload by the preloader 220 is executed one frame before in preparation for drawing. For example, the preload for drawing the display data of the frame FR2 is executed within the time points T0 to T1 which is the display period of the frame FR0. Specifically, since it is started in step S103, preloading for the next frame is started at the beginning of the frame. Preloading is usually completed within the frame period.
If, for example, the preload started at the time point T0 is not completed at the time point T1, the completion is awaited in step S174 of FIG. If the preload is delayed a little, it will delay the start of drawing a little.

As the processing of the effect control CPU 200, steps S150, S151, S101, and S103 are performed at each frame start timing SLs. As shown in FIG. 22, the main processing is control of switching between frame buffers 209A and 209B, starting drawing, creating a display list, and starting preloading.
Here, during the frame period indicated by the arrow SL, the processes of the steps S121 to S143 are repeated.
However, the reception command processing (S122 to S124) is executed only during the first half of the frame indicated by the arrow CA. This is because these are executed only when the V blank interrupt counter = 0.
The analysis process of the received command is as shown in FIGS. 18 and 19, but this is a process with a relatively heavy processing load, and the number of processes increases depending on the number of received commands. Depending on the type of command, it may be necessary to perform a lottery for the production. In the present embodiment, such processing is performed only in the first half of the frame.
Therefore, regarding the command signal, for example, for the command signal received in the period indicated by the broken line as the time points T0m to T1m, the command analysis is performed in the period of the time points T1 to T1m.

The lamp data creation / output processing (S141 to S143) is also executed only during the first half of the frame, which is indicated by the arrow CA. This is because these are also executed only when the V blank interrupt counter = 0.
This prevents the frame end process (S150) from being delayed with respect to the frame end timing due to the creation and output of the lamp drive data.
If the lamp drive data output in step S142 is not performed in the latter half of the frame, it is assumed that the lamp drive data is not output from the serial output controller 240. In that case, the LED driver 90 Since the lamp drive data immediately before is maintained, the light emission operation immediately before is executed.

<7. Processing of the production control unit of the second embodiment>
FIG. 23 shows the processing of the effect control CPU 200 of the second embodiment. This is an example in which the lamp drive data output control in step S142 of FIG. 16 is changed so as to be performed at the timing shown as step S144. That is, regardless of the first half / second half of the frame, the output of the lamp drive data is an example of processing to be executed.
However, since the lamp drive data in step S141 is not created in the latter half of the frame, the lamp drive data created in the first half of the immediately preceding frame is repeatedly output in the latter half of the frame.
The other processing of the second embodiment is the same as that described with reference to FIGS. 16 to 20.

<8. Processing of the production control unit of the third embodiment>
FIG. 24 shows the processing of the effect control CPU 200 of the third embodiment.
After the power is turned on, the effect control CPU 200 performs various initial settings in step S300, and then repeats the processes after step S301.

In step S302, the effect control CPU 200 initializes the image processing relationship. This initialization refers to the initialization processing of various variables at the frame start timing.
In step S302, the effect control CPU 200 performs command analysis processing. For example, specifically, it is the process described with reference to FIGS. 18 and 19.
In step S303, the effect control CPU 200 performs a scenario management process. This scenario management process refers to the process of steps S104 and S132 of FIG.
In step S304, the effect control CPU 200 performs drawing update processing. This is the control of creating the display list and starting the preload execution in step S103 of FIG.

In step S305, the effect control CPU 200 performs sound management processing. This sound management process is the same as the process of step S133 of FIG.
In step S306, the drawing completion wait and the preload completion wait are performed. The waiting for the completion of drawing is the waiting for the completion of drawing the display data of the next frame, which was started in the immediately preceding step S312. The preload completion wait is the preload completion wait for drawing the next frame, which was started in the immediately preceding step S304.

The effect control CPU 200 proceeds from step S307 to step S312 only for the first power-on, and starts drawing the first frame. After that, the process proceeds from step S307 to S308.

In step S308, the effect control CPU 200 branches the process according to the value of the V blank interrupt counter. If the V-blank interrupt counter is "0", the lamp drive data is created and output control is performed in step S149. That is, the lamp drive data that is actually output from the serial output controller 240 to the frame driver unit 61 and the panel driver unit 62 is generated based on the information registered in each lamp channel dwCH of the lamp data registration information.
Then, the generated lamp drive data is transferred to the serial output controller 240 and controlled so as to be output as serial data.

When the V blank interrupt counter = 1, step S309 is not performed. That is, the lamp drive data creation and output processing in step S309 is performed only during the first half of the frame when the V blank interrupt counter = 0.

In step S310, it waits for the V blank interrupt counter = 2. Then, when the V blank interrupt counter = 2, the frame buffer is switched and the V blank interrupt counter is cleared in step S311, and the drawing start control is performed in step S312. Then, the process returns to step S301.

The above process of FIG. 24 is different from the process of FIG. 16 in the following points.
-The command analysis process is performed once immediately after the start of the frame (S302).
-Sound management (S305) is performed immediately after scenario management.
-As scenario management, the scheduler frame update of FIG. 16 and the scenario scheduler execution process are collectively performed once.
-After waiting for the completion of drawing and preloading (S306), lamp data creation / output (S309) is performed.
-Since it waits until the end of the frame period (S310), steps S301 to S312 are performed once in one frame period. Therefore, the sound data output (S305) and the lamp data creation / output (S309) are performed once per frame.

As described above, the processing becomes simpler than that of the first and second embodiments, and the processing load of the effect control CPU 200 is reduced.
Note that the motor control is performed by, for example, an interrupt process every 1 ms as shown in FIG.

FIG. 25 shows various timings for each frame period of the third embodiment. The format of the notation is the same as that shown in FIG.
The timings of the display frame, the value of the V blank interrupt counter, the drawing of the drawing circuit, and the preload processing of the preloader are the same as those in FIG.

As the processing of the effect control CPU 200, steps S311 and S312 and S301 to S310 are sequentially performed from immediately after each frame start timing SLs during the frame period indicated by the arrow SL. As shown in FIG. 22, the main processes include switching between frame buffers 209A and 209B, drawing start, command analysis processing, scenario management, display list creation, preload start, sound management, and lamp data creation / output control. It is done once within the frame period.

However, the lamp data creation / output is not executed unless it is started within the first half period of the frame indicated by the arrow CA.
This prevents the frame end processing (S311 and S312) from being delayed with respect to the frame end timing due to the creation and output of the lamp drive data.
If the lamp drive data output in step S309 is not performed in the latter half of the frame, it is assumed that the lamp drive data is not output from the serial output controller 240. In that case, the LED driver 90 Since the lamp drive data of the immediately preceding frame is maintained, the immediately preceding light emitting operation will continue to be executed.

In this case, the command analysis process (S302) is executed only once immediately after the start of the frame. The analysis process of the received command is a process with a relatively heavy processing load as described above. In the present embodiment, this process is performed once immediately after the start of the frame so that the series of processes shown in FIG. 24 can be completed by the end of the frame period unless a special abnormality occurs. ..
Therefore, regarding the command signal, for example, for the command signal received in the period indicated by the broken line as the time points T1 to T2, the command analysis is performed immediately after the time point T2.

<9. Summary and modification examples>
According to the pachinko gaming machine 1 of the above-described embodiment, the processing for effect control can be made more efficient, and appropriate effect control can be realized.
In addition, the effect control processing load can be reduced.

Further, the pachinko gaming machine 1 of the embodiment includes a display means for displaying an effect image (for example, a main liquid crystal display device 32M or a sub liquid crystal display device 32S) and a light emitting means for performing a light emitting operation (for example, lamp units 63, 64). At least, a control means (for example, an effect control unit 51) for controlling the light emission of the light emitting means is provided. Then, the control means performs all or part of the processing for controlling the light emission of the light emitting means on the front end side of the frame from the frame start timing to the detection of the lapse of a predetermined time within one frame period of the image displayed by the display means. If it is a period, it starts, and it does not start in the frame end side period, which is the period after the elapse of a predetermined time is detected.
The frame end-side period is a period from the start time of the frame to the end of the frame after a predetermined time has elapsed within the frame period. For example, it is the latter half period when one frame period is divided into the first half and the second half. In the present embodiment, all or part of the processing for controlling light emission is skipped during the period on the end side of the frame.
For example, in the case of the first embodiment, the lamp drive data creation and lamp drive data output processing of steps S141 and S142 of FIG. 16 are not started during the frame end side period.
In the case of the second embodiment, the process of creating the lamp drive data in step S141 of FIG. 23 is not started during the frame end side period.
In the case of the third embodiment, the processing of the lamp drive data creation and the lamp drive data output in step S309 of FIG. 24 is not started during the frame end side period.
As a result, it is possible to prevent the control for various effects and the like performed together with the image display of the display means from being missed in time for the next frame. Therefore, when the frame start timing is detected and various effect controls are performed according to the frame period, it is possible to provide a processing procedure that does not increase the processing load of the effect control unit 51 (particularly, the 1-chip microcomputer 250).
Then, it is possible to avoid a delay in the effect control according to the frame timing of the display image and realize an appropriate effect operation.
In particular, in the embodiment, the control means (effect control unit 51) also controls the display means. In this case, by matching the processing for the light emission effect to the display control (that is, the frame period), the processing efficiency can be improved, the timing control and the register configuration for that purpose can be simplified, but in some cases, immediately before the end of the frame. The processing such as the light emission effect performed in the above may not be completed within the frame period, and it is expected that the processing will be delayed accordingly. Therefore, by not performing light emission control during the frame end side period, it is possible to eliminate such a situation.
It should be noted that the reason why all the part of the light emitting effect is skipped in the latter half of the frame is that even if the LED light emitting operation remains the same as the immediately preceding light emitting operation in the period of 16.6 ms, there is no great influence. It is also meaningful to realize an appropriate effect that the sound effect and the movable accessory effect are not skipped even in the latter half of the frame with respect to the control of the light emission effect. In other words, skipping all part of the light emission effect in the latter half of the frame and not skipping the sound effect process in step S133 and the motor control (movable body accessory effect process) in steps S202 and S203 means that the frame maintains the effect. This is effective in that the delay in processing until the end timing can be eliminated.

Further, in the first, second, and third embodiments, the light emission drive data creation process (S141, S309) is performed as a part of the light emission control process in which the effect control unit 51 does not start in the frame end side period. Including.
Controls for the light emission effect include production scenario management, progress (update) of the effect content according to the effect scenario, acquisition of control data according to the effect content to be executed, generation of drive data for the control, and drive data. There is output of. Of these, at least the generation of light emission drive data (lamp drive data) is not executed during the frame end side period.
By not creating the light emission drive data, the processing load in the latter half of the frame is reduced, and it is possible to prevent the frame switching timing from being missed. As a result, it is possible to prevent the effect control at the frame timing from being hindered.
It should be noted that the light emission drive data may be output, and in that case, the lighting is performed according to the immediately preceding drive data, but as described above, no problem occurs in the actual operation.

Further, in the first and third embodiments, the effect control unit 51 includes serial transmission processing (S142, S309) of light emission drive data as a part of the processing for light emission control that does not start in the frame end side period. That is, among the controls for the light emission effect, at least the light emission drive data output, particularly the serial output, is not executed during the frame end side period.
The serial transmission output of the light emission drive data is a relatively time-consuming process, and if it is executed in the latter half of the frame, there is a high possibility that it will not be completed by the frame switching timing. Therefore, by not executing this in the frame end side period, it is possible to prevent the next frame from being missed.

Further, in the first, second, and third embodiments, the effect control unit 51 starts (ends) a frame by a V blank interrupt counter that counts based on a V blank signal which is a frame synchronization signal of the displayed image. ) Timing and the start timing of the frame end side period are detected (S120, S140). This makes it possible to facilitate timing management.

By the way, as a modification of the first and second embodiments, step S134 may be performed only when the V blank interrupt counter = 0 in step S140. In other words, scenario update (update of lamp data registration information) should not be performed during the latter half of the frame. That is, all the processes for controlling light emission (S134, S141, S142) are not performed in the latter half of the frame. Note that "all" means all the processes related only to lamp control.
By doing so, the effect of reducing the processing load in the latter half of the frame can be further exerted. In particular, in the case of the embodiment, the timer of the scenario is advanced as the scenario scheduler frame update in step S104. In other words, the scenario always progresses by one timing for each frame. Therefore, the progress of the scenario of the lamp effect is secured, and even if the step S134 is not executed, the progress of the scenario is not delayed and the appropriate effect cannot be performed.
Further, even during the period in which steps S134, S141, and S142 are not performed, the LED driver 90 drives the LED 120 based on the immediately preceding light emission drive data, so that the light emission state does not give a sense of discomfort to the player.
Of course, also in the first and second embodiments, since the scenario timer progresses in step S104, the scenario always progresses by one timing for each frame, and the progress of the ramp effect scenario is ensured. Therefore, the progress of the scenario is not delayed.

The pachinko gaming machine 1 of the embodiment includes a plurality of effect means including display means (main liquid crystal display device 32M and sub liquid crystal display device 32S) for displaying the effect image. That is, there are also directing means such as lamp units 63 and 64, a movable body accessory, and a sound output system. The control means (effect control unit 51) detects the frame start timing of the image displayed by the display means, and the analysis process (S123) of the received command sets a predetermined time from the frame start timing within one frame period. It starts only in the front end period of the frame until it elapses.
The frame front end period is a period within the frame period from the start time of the frame to the elapse of a predetermined time. For example, it is the first half period when one frame period is divided into the first half and the second half.
The received command is analyzed and the content of the effect is determined based on the analysis result. However, the analysis process of this command is started only in the period on the front end side of the frame, and after a predetermined time has passed from the start of the frame. , The analysis process is not started.
As a result, it is possible to prevent the control for various effects and the like performed together with the image display of the display means from being missed in time for the next frame. The analysis process is a relatively burdensome process, such as grasping the received command content and including a corresponding process according to the command content. Therefore, in order to be in time for the next frame start timing, this command analysis is started only during the frame front end side period.
Therefore, when the frame start timing is detected and various effect controls are performed in frame synchronization, it is possible to provide a processing procedure that does not increase the processing load.
In particular, when the effect control unit 51 also controls the display means, it is possible to improve the efficiency of the process, simplify the timing control, and simplify the register configuration for that purpose by performing display control, that is, frame synchronization, for the process for the light emission effect. However, the received command analysis process may not be completed within the frame period, which may delay the process. Therefore, by limiting the period for starting the command analysis process to the period on the front end side of the frame, it is possible to avoid a situation in which the process is delayed.

Further, in the first and second embodiments, the effect control unit 51 uses a V-blank interrupt counter that counts based on a V-blank signal, which is a frame synchronization signal of an image displayed by the display means, to start a frame. And the end timing of the frame front end side period is detected (S121). This makes it possible to facilitate timing management.

Further, in the third embodiment, the control means (effect control unit 51) detects the frame start timing of the image displayed by the display means, and the analysis processing of the received command is performed within one frame period. It is executed once according to the detection of the start timing (S302).
As a result, the command analysis process is started immediately after the frame start timing. Since it is performed only once, it usually does not occur that the command analysis process starts in the latter half of the frame period. Therefore, it is possible to prevent the processing from being missed at the frame end timing due to the heavy command analysis processing.

Further, as can be understood from the above, in the processing and modification of FIGS. 16 and 23 of the first and second embodiments, the analysis processing (S123) of the received command is started in the frame end side period. In addition, all or part of the processing for controlling light emission will not be started.
As a result, the processing amount of the effect control unit 51 in the period on the rear end side of the frame is further reduced, and the effect of preventing the control for various effects performed together with the image display of the display means from being in time for the next frame is further improved. Can be enhanced.

Further, the pachinko gaming machine 1 of the embodiment includes a plurality of effect means including a display means for displaying an effect image, a movable body driven by a motor, and a light emitting means. Further, the control means (effect control unit 51 or effect control CPU 200) for controlling the operation of the effect means according to the received command is provided.
The effect control CPU 200 executes the drive control related to the light emitting means as one of the first processes performed according to the frame timing of the display data to be displayed by the display means. The process performed according to the frame timing is a process of progressing the process corresponding to the frame period, for example, a process of monitoring the frame timing and defining various processing timings. That is, the first process in the embodiment is the main process of FIG. 16 in which the execution timing is defined by the frame timing.
On the other hand, the drive control of the motor related to the movable body is executed as one of the second processes executed at predetermined intervals shorter than the frame period regardless of the frame timing. The second process is the timer interrupt process shown in FIG.
As a result, the light emission effect can be realized according to the frame of the display data, while the motor control of the movable body accessory can be finely operated by being controlled at shorter time intervals regardless of the frame timing. It becomes.
The lamp control (and sound control) is output for each frame timing, so that the processing load is not excessive. On the other hand, by processing the motor at a cycle shorter than the frame timing, it is possible to avoid delaying the motor operation.

Further, in the embodiment, a display control means (functional part as VDP) that controls the display means based on a drawing instruction from the control means (effect control CPU 200) is provided. The frame timing is a timing based on the frame synchronization signal output from the display control means.
By confirming the frame timing based on the frame synchronization signal, timing control becomes easy.

Further, the effect control unit 51 also executes the detection of the information of the origin switch of the motor in step S201 of FIG. 20 as one of the second processes. That is, the detection of the origin switch information is also combined with the motor drive control so that the motor control of the movable body accessory can be appropriately executed. In this case, the control of the movement of the movable body accessory (progress of the scenario, etc.) can be facilitated by performing the origin sensing at the same 1 ms cycle as the device scheduler execution process in step S202.

Further, the effect control unit 51 also executes the detection of the operation information of the user operation means for the effect in step S204 of FIG. 20 as one of the second processes. As a result, the operation information detection operation can be performed in detail.
As described above, the one-chip microcomputer 250 can collectively detect the detection of the user operation information and the origin sensing as the input from the parallel / serial conversion unit 260 of FIG. Therefore, by simultaneously performing the process of step S204 and the process of step S201, more efficient external information detection becomes possible.

Further, in the first and second embodiments, the control means (effect control unit 51) has the first region for reading out the display data of the image displayed by the display means for the plurality of frame buffers 209A and 209B, and the next The allocation as the second area for drawing the display data of the frame of is sequentially switched. At this time, in the embodiment, at the end of one frame period of the image displayed by the display means (S150), the drawing of the display data of the image of the next frame in the frame buffer area, which is the second area, is completed. (Step S171 in FIG. 17), after confirming the completion of drawing, switching between the first area and the second area (S173) is performed, and drawing using the frame buffer area switched to the second area is started (S175). ).
By confirming the completion of drawing and switching the frame buffer area of the VRAM 209 in this way, the influence on the displayed image can be minimized. That is, the display data transferred to the display circuit 221 or the like becomes the display data in which the drawing is completed correctly, and if the drawing is not completed by the second time of the vertical synchronization signal, the display data of the frame buffer being drawn is displayed. That doesn't happen.
Then, it is possible to realize an image display effect based on an appropriate display data output even in a situation where the processing load is relatively high, such as controlling a plurality of effect means including the display means for displaying the effect image.

Further, in the first and second embodiments, the control means (effect control unit 51) allocates the plurality of frame buffers 209A and 209B as the first region and the second region according to the end of the one frame period. While switching (S173), it is confirmed whether or not the predetermined storage area (D-RAM202a or VRAM209) preloading of the image data material for drawing stored in the CG-ROM206 is completed (S174), and the preloading is performed. After the completion is confirmed, drawing using the frame buffer area designated as the second area by switching is started (S175).
As described above, the reference destination of the image data (CG data as the image material) of the display list is not the CG-ROM206 but the preload area set in the D-RAM 202a or the VRAM 209, so that the drawing by the drawing circuit 225 is performed. Random access to image data generated during execution can be speeded up, and drawing processing can be performed even for high-resolution moving images with a lot of movement. That is, by confirming the completion of preloading and then starting drawing, it is possible to maintain a state in which drawing with such an advantage can be reliably executed. Therefore, the drawing process using the preloaded image material is appropriately executed. In particular, it is effective to wait for the completion of preload before drawing as the processing of the 1-chip microcomputer 250, which tends to increase the processing load.

The gaming machine of the embodiment has a first effect means which is a display means (main liquid crystal display device 32M and a sub liquid crystal display device 32S) for displaying an effect image, and a movable body role driven by a movable body accessory motor 65. It is provided with a second effect means and a third effect means, which are objects. The third effect means are a sound output system (amplifier unit 67, speaker 25) and lamp units 63 and 64.
Then, in the first and second embodiments, the control means (effect control unit 51) controls the third effect means (S133 in FIGS. 16 and 23) at the frame period of the display data to be displayed by the display means. Running. That is, basically, it is performed once per frame.
On the other hand, the drive control of the movable body accessory motor 65 relating to the movable body of the second effect means is executed at 1 ms intervals shorter than the frame period regardless of the frame timing (S202, S203 in FIG. 20).
As a result, the control of the third effect means can be realized according to the frame of the display data, while the operation control of the movable body accessory motor can be finer.
For example, in the sound control, the processing load is not excessive by setting the output for each frame timing. On the other hand, by processing the motor at a cycle shorter than the frame timing, it is possible to avoid delaying the motor operation. Therefore, fine movement of the movable body accessory becomes possible.

Further, when the reception command is acquired, the effect control unit 51 further executes the control related to the third effect means regardless of the frame period. That is, in FIGS. 16 and 23, when there is a receive command, steps S132, S133, and S134 are performed by turning off the scheduler update flag in step S124.
As a result, it is possible to quickly execute the effect according to the command acquisition.

In the first and second embodiments, the scenario is not updated (frame update flag is OFF) at the timing when the display frame of the image is changed, which is detected by the display synchronization signal (V blank signal or the like) (S151). , At least the timer of the scenario is updated according to the unupdated state (S102 → S103 → S104).
Therefore, in the processing of the effect control CPU 200, the scenario progress management can be performed at the optimum timing in relation to the timing of the frame of the display data.

Further, in the first and second embodiments, the scenario scheduler frame update / non-update is managed by the first information (frame update flag), and the execution / non-execution of the scenario update (scheduler execution) is performed by the second information (scheduler). It is managed by the update flag) (S105, S106, S130, S151).
Then, the frame update flag is turned OFF (not updated) based on the frame synchronization signal (V blank signal). After the scheduler update flag is turned OFF (not executed) according to the scheduler frame update, the status is confirmed according to the frame synchronization signal, and if it is OFF (not executed), the scenario update is executed.
As a result, the timer progress of the scenario and the scenario update are managed so as to be performed at different timings, and the execution once per frame can be managed by a simple process.

Further, in the first and second embodiments, the scenario update information (scheduler update flag) is turned ON together with the scenario update execution (S132) (S131). After turning it on, the scenario update (S131 to S134) is not performed even during the frame period (regardless of the value of the V blank interrupt counter). The scheduler update flag is returned to OFF at the beginning of the next frame period (S106).
However, when a command is received, it is immediately turned off (S124) so that the scenario update is executed.
Depending on such processing, in the main processing of the effect control CPU 200, the scenario can be appropriately updated once per frame without unnecessarily updating the scenario, and the synchronization between the display and other effects can be easily ensured. it can.
On the other hand, by executing the scenario update immediately according to the command analysis, it is possible to quickly respond to the command regardless of the progress of the display frame.

Although the embodiments have been described above, the present invention is not limited to the examples given in the embodiments, and various modified examples and application examples can be considered.
An example of managing the timing based on the V blank signal as a signal synchronized with the frame of the display data was given, but the timing management within the frame period by using a vertical synchronization signal other than the V blank signal or by counting the horizontal synchronization signal. May be done. For example, it is conceivable to use a vertical synchronization signal or a horizontal synchronization signal for timing management as the above-mentioned frame front end side period and frame rear end side period.
Further, the period on the front end side of the frame is not necessarily the period of 16.6 ms in the first half of the frame. It may be a period from the frame start timing to a certain point in the middle of the frame period.
Similarly, the rear end period of the frame is not necessarily the period of 16.6 ms in the latter half of the frame. It may be a period from a certain point in the middle of the frame to the end of the frame.

Further, although the present invention has shown an example of application to a ball game machine such as the pachinko game machine 1, it can also be applied to a rotating cylinder type game machine (so-called slot machine).

1 Pachinko game machine 20w, 20b Light emitting unit 32M Main liquid crystal display device 32S Sub liquid crystal display device 50 Main control board (main control unit)
51 Production control board (Production control unit)
61 Frame driver part 62 Board driver part 63, 64 Light emitting part 65 Movable body accessory motor 90 LED driver 200 Production control CPU
201 Production control ROM
202 Production control RAM
250 microcomputer

Claims (1)

Display means for displaying the production image and
A light emitting means that performs a light emitting operation as a directing light emission different from the effect image,
At least a control means for controlling the display of the display means and the light emission of the light emitting means, and
With
The control means
The analysis process of the received command can be executed a plurality of times within one frame cycle of the image displayed by the display means, and the analysis process is performed within one frame period of the image displayed by the display means. A gaming machine that starts only in the frame front end side period from the frame start timing to the detection of the lapse of a predetermined time.

Images