JP2020099796A - Game machine - Google Patents

Abstract

To achieve proper processing of performance control synchronized with frames.SOLUTION: A game machine includes: display means for displaying a performance image; light emitting means for performing a light emitting operation; and control means for controlling light emission of at least the light emitting means. The control means is capable of executing analysis processing of a received command a plurality of times within one frame period of the image displayed on the display means, and the analysis processing is started only in the frame front end side period until passage of a predetermined time is detected from a frame start timing, in one frame period of the image displayed on the display means.SELECTED DRAWING: Figure 16

Description

The present invention relates to a game machine such as a ball game machine and a rotating body game machine, and more particularly, to performance control in the game machine.

Japanese Patent No. 4613191

In a ball game machine (so-called pachinko game machine), a rotating body game machine (so-called slot game machine), etc., for production using a liquid crystal display unit for displaying various images such as effect images, LED (Light Emitting Diode), etc. A light emitting unit that lights up and blinks, a sound output unit that produces a sound such as music, a sound effect, and a dialogue, a movable body accessory that is driven by a motor, and the like, and a production unit that performs a production operation are installed. By controlling these effect means in cooperation with each other, a game effect that improves the interest is realized.

Patent Document 1 discloses a technique in which the effect control unit outputs drive data for light emission drive as serial data to an LED driver for light emission effect control and controls it.

In such a gaming machine, in addition to the original control of the game operation, various effects and display operations using a liquid crystal display, a light emitting unit, a sound output unit, a movable body accessory, etc. are performed. There is a tendency that the control load of the microcomputer that controls the CPU increases.
Therefore, an object of the present invention is to improve the efficiency of control processing of a microcomputer for effect control so that appropriate effect control is executed.

A gaming machine of the present invention includes display means for displaying an effect image, light emitting means for performing a light emitting operation, and control means for controlling light emission of at least the light emitting means, and the control means is the display means. The analysis process of the received command can be executed a plurality of times within one frame period of the image to be displayed, and the analysis process starts the frame within the one frame period of the image displayed by the display means. It starts only in the frame front end side period from the timing until the passage of a predetermined time is detected.
It should be noted that the gaming machine includes a plurality of rendering means including a display means for displaying a rendering image and a light emitting means, and a control means for controlling the operation of the rendering means according to the received command, and the control means is the above-mentioned. The drive control relating to the light emitting means and the image control processing for displaying the effect image on the display means are performed based on the frame synchronization signal used for the transfer of the display data to the display means and the display operation control, and a plurality of frames Regarding the buffer area, the allocation as the first area for reading the display data of the image displayed by the display means and the allocation for the second area for drawing the display data of the next frame are sequentially switched, and are defined by the frame synchronization signal. At the end of one frame period of the image displayed by the display means, confirmation of the completion of drawing the display data of the image of the next frame in the frame buffer area, which is the second area, and drawing An image stored in the image material data storage unit for the switching of the allocation as the first area and the second area after confirmation of completion, and the frame subsequent to the frame for which the completion of drawing has been confirmed after switching. Confirmation of completion of preload processing for storing data in a predetermined storage area, start of drawing using the frame buffer area switched to the second area after completion of preload processing, and further processing of the frame where drawing is started The preload process is started for the frame of, and the preload process is a process of transferring the image data material whose storage position is shown in the ROM area in the setting information for setting the image content to a predetermined storage area. Therefore, in accordance with the preload process, the setting information may be rewritten so that the storage position of the image data material becomes the storage position after the transfer.
Further, the gaming machine includes a plurality of rendering means including a display means for displaying a rendering image and a light emitting means for performing a light emitting operation, and a control means for controlling the operation of the rendering means according to the received command. For all or a part of the processing for controlling the light emission of the light emitting means and the analysis processing of the received command after a predetermined time has elapsed from the frame start timing within one frame period of the image displayed on the display means. The frame front end side period before detection may be started, and may not be started in the frame end side period which is a period after the elapse of the predetermined time.
The frame end side period is a period that is detected after a predetermined time has elapsed from the frame start point within the frame period and before the timing when the frame ends. For example, it is a second half period when one frame period is divided into a first half and a second half. In this frame end side period, all or part of the processing for light emission control is skipped. Furthermore, the command analysis process is not started.
Further, in the above-mentioned gaming machine, the control means may detect the start timing of the frame end side period by a counter that counts based on a frame synchronization signal of an image displayed on the display means. ..
For example, the start timing of the frame end side period is recognized by a counter that counts based on a signal such as a vertical blanking signal synchronized with the frame of the image. As a result, timing management can be facilitated.

According to the present invention, it is possible to improve the efficiency of control processing by a microcomputer or the like for effect control and realize appropriate effect control.

It is a perspective view of a pachinko gaming machine of an embodiment of the present invention. It is a front view of the board surface of the pachinko gaming machine of the embodiment. It is a block diagram of a control configuration of the pachinko gaming machine of the embodiment. It is the block diagram of the production control section of form of execution. It is a block diagram of a display control system of the effect control unit of the embodiment. It is an explanatory view of a driver configuration of an embodiment. It is explanatory drawing of the LED driver of embodiment. It is an explanatory view of a motor controller and a motor driver of an embodiment. 5 is a flowchart of main control main processing according to the embodiment. It is a flow chart of main control timer interruption processing of an embodiment. It is explanatory drawing of the command of embodiment. It is an explanatory view of scenario registration information, lamp data registration information, and motor data registration information of an embodiment. It is an explanatory view of sound data registration information of an embodiment. It is explanatory drawing of the main scenario table of embodiment. It is explanatory drawing of the sub-scenario table of embodiment. It is the flowchart of production control main processing of form of 1st execution. 9 is a flowchart of a process at the end of a frame according to the embodiment. It is the flowchart of the command analysis processing in the production control of form of execution. It is the flowchart of the command correspondence processing in the production control of form of execution. It is the flowchart of production control timer interruption processing of form of execution. It is explanatory drawing of the motor operation table of embodiment. It is explanatory drawing of the display control timing of 1st Embodiment. It is a flow chart of production control main processing of a 2nd embodiment. It is the flowchart of the production control main processing of 3rd execution form. It is explanatory drawing of the display control timing of 3rd Embodiment.

Hereinafter, a pachinko game machine will be described as an example of an embodiment of a game machine according to the present invention, and will be described in the following order.
<1. Structure of pachinko machine>
<2. Control configuration of pachinko machine>
<3. Structure of production control section>
<4. Overview of operation>
<5. Processing of main controller>
<6. Process of production control unit of first embodiment>
<7. Process of production control unit of second embodiment>
<8. Process of production control unit of third embodiment>
<9. Summary and Modifications>

<1. Structure of pachinko machine>
First, with reference to FIG. 1 and FIG. 2, a configuration of a pachinko gaming machine 1 as an embodiment of the present invention will be schematically described.
FIG. 1 is a front perspective view showing an external appearance of a pachinko gaming machine 1 of an embodiment, and FIG. 2 is a front view of a gaming board.
The pachinko gaming machine 1 shown in FIGS. 1 and 2 mainly includes a “frame portion” and a “game board portion”.
The “frame portion” is configured to have a front frame 2, an outer frame 4, a glass door 5, and an operation panel 7, which will be described below. The "gaming board section" comprises the gaming board 3 of FIG. In the following description, “frame portion” or “frame side” is a general term for the front frame 2, the outer frame 4, the glass door 5, and the operation panel 7. Further, the "board portion" or "board side" indicates the game board 3.

As shown in FIG. 1, in a pachinko gaming machine 1, a frame-shaped front frame 2 is attached to a front surface of a wooden outer frame 4 so as to be openable and closable. Although not shown, a game board storage frame is formed on the back surface of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the game area 3a formed on the surface of the game board 3 faces the front side of the game machine of FIG. 1 through the opening 2a of the front frame 2.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the front player side through the transparent glass.

The glass door 5 is attached to the front frame 2 by a shaft support mechanism 6 so as to be openable and closable. By operating a door lock releasing key cylinder (not shown) provided at a predetermined position of the glass door 5, the locked state of the glass door 5 with respect to the front frame 2 is released, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can be released by operating the door lock releasing key cylinder.
Further, on the front surface side of the glass door 5, light emitting portions 20w are provided at various places as light emitting means on the frame side. The light emitting unit 20w performs, for example, a light emitting operation for performance, a light emitting operation for notifying an error, a light emitting operation according to an operation state, and the like as a light emitting operation by an LED.

An operation panel 7 is provided below the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a shaft support mechanism (not shown).
The operation panel 7 is provided with an upper pan unit 8, a lower pan unit 9, and a firing operation handle 10.

The upper tray unit 8 is formed with an upper tray 8a for storing game balls used for bullets. The lower tray unit 9 is formed with a lower tray 9a that stores game balls that cannot be stored in the upper tray 8a.
Further, the upper tray unit 8 is provided with a ball removing button 16 for pulling out the game balls stored in the upper tray 8a toward the lower tray 9a. The lower tray unit 9 is provided with a ball pulling lever 17 for pulling down the game balls stored in the lower tray 9a below the gaming machine.
In the upper tray unit 8, a ball lending button 14 for requesting the payout of game balls to a game ball lending device (not shown), and a card for requesting the return of the valuable medium inserted in the game ball lending device. A return button 15 is provided.
Further, the upper tray unit 8 is provided with effect buttons 11 and 12 and a cross key 13. The effect buttons 11 and 12 are push buttons that can be operated by turning on the built-in lamp during a predetermined input reception period, and can be changed by pressing when the built-in lamp is lit. The cross key 13 is a manipulator for the player to perform an operation according to the effect situation or an operation for effect setting.

The firing operation handle 10 is an operator provided on the right end side of the operation panel 7 and operated by the player to activate the firing device 32 shown in FIG. 3 for a ball.
Speakers 25 that acoustically output the effect sound are provided on both sides of the upper portion of the front frame 2 and near the firing operation handle 10.

Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or resin plate. On this game board 3, a ball guide rail 31 for guiding the launched game balls is annularly mounted as a board surface partition member, and a substantially circular area surrounded by the ball guide rail 31 is a game area 3a. Has become.

A main liquid crystal display device 32M (LCD: Liquid Crystal Display) is provided substantially in the center of the game area 3a, and a sub liquid crystal display device 32S is provided on the right side of the main liquid crystal display device 32M.
In the main liquid crystal display device 32M, under the control of the effect control unit 51 to be described later, three decorative symbols, for example, left, middle, and right, are variably displayed on the background image. Further, various effect images such as normal effect, reach effect, and super reach effect are also displayed. Similarly, the sub liquid crystal display device 32S also performs display according to various effects.

Further, in the game area 3a, a center decoration 35C is provided so as to surround the periphery of the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The center decoration 35C not only exerts a decorative effect due to its design, but also has a function of protecting the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S from surrounding game balls. Further, the center decoration 35C also functions as a member that allows the left and right of the flow path of the game ball to be separately divided depending on the strength of the game ball being launched or the stroke length. That is, the flow path of the game ball that has been hit on the upper part of the game area 3a via the ball guide rail 31 flows down either the left game area 3b or the right game area 3c divided by the center ornament 35C. In the case of so-called left hitting, the game ball flows down the left game area 3b, and in the case of right hitting, the game ball flows down the right game area 3c.

Further, below the left game area 3b, a lower left decoration 35L is provided, which exerts a decorative effect and defines the range as the left game area 3b.
Similarly, a lower right decoration 35R is provided below the right game area 3c to exert a decorative effect and define a range as the left game area 3b.
In the game area 3a (left game area 3b and right game area 3c), nails 49 and windmills 47 are provided at various places to form various downflow paths of the game ball.
Further, a center stage 35S is provided below the main liquid crystal display device 32M, which exerts a decorative effect and also functions as a floating area for a game ball.
Although not shown, the center ornament 35C is provided with a movable body accessory that has a visual effect in place.

In the vicinity of the upper right edge of the game area 3a, a symbol display section 33 formed of a dot display formed by arranging a plurality of LEDs is provided.
In this symbol display unit 33, the first special symbol display unit, the second special symbol display unit, and the normal symbol display unit are formed by the predetermined dot areas, and the first special symbol, the second special symbol, and the normal symbol Each variation display operation (variation display operation that sets variation start and variation stop) is performed.
The main liquid crystal display device 32M temporally synchronizes with the variable display of the first and second special symbols by the symbol display unit 33, and variably displays the decorative symbol by the image.

Below the center ornament 35C, a winning device having an upper starting port 41 (first special symbol starting port) is provided, and further below it is provided with a lower starting port 42a (second special symbol starting port). A variable winning device 42 is provided.
Inside the upper starting opening 41 and the lower starting opening 42a, detection sensors (upper starting opening sensor 71, lower starting opening sensor 72 shown in FIG. 3) for detecting passage of a game ball are formed.

The upper starting opening 41 is a winning opening relating to the starting condition of the variable display operation of the first special symbol in the symbol display section 33, and has no starting opening opening/closing means (means for opening or expanding the starting opening) It is a type of winning device.

The normal variation winning device 42 having the lower starting opening 42a is configured as a winning rate varying type winning device in which the winning rate of the game ball at the starting opening can be changed by the starting opening opening/closing means. That is, this is a so-called electric tulip type winning device, which is provided with a pair of left and right movable blades (movable members) 42b that can open or expand the lower start opening 42a.
The lower starting opening 42a of this normal variation winning device 42 is a winning opening relating to the starting condition of the variable display operation of the second special symbol in the symbol display section 33. Then, the winning rate of the lower starting opening 42a changes according to the operating state of the movable wing piece 42b. That is, when the movable wing piece 42b is open, winning is easy, and when the movable wing piece 42b is closed, winning is difficult or impossible.

Further, a plurality of general winning openings 43 are provided on the left and right of the normal variable winning device 42. A detection sensor (general winning hole sensor 74 shown in FIG. 3) for detecting passage of a game ball is formed inside each general winning hole 42.
Further, on the lower side of the right game area 3c, a normal symbol starting port 44 formed of a gate (specific passage area) through which a game ball can pass is provided. This normal symbol starting port 44 is a winning port related to the variable display operation of the normal symbol in the symbol display portion 33, and inside thereof, a sensor (gate sensor 73 shown in FIG. 3) for detecting a passing game ball is formed. Has been done.

A first special variation winning device 45 (special electric auditors) is provided in the flow path from the normal symbol starting port 44 to the normal variation winning device 42 in the right game area 3c.
The first special variation winning device 45 has a structure in which the first big winning opening 45a is closed/opened by a retractable opening door 45b. Further, a sensor (first special winning opening sensor 75 in FIG. 3) that detects passage of a game ball to the first special winning opening 45a is formed inside thereof.
Around the first big winning opening 45a, the lower right decoration 35R is in a state of bulging from the surface of the game board 3, and the upper side of the bulging portion and the upper surface of the open door 45b guide downstream of the right downflow route 3c. Forming a part. Therefore, by opening the open door 45b to the inside of the board, the game ball that has reached the downstream guide portion easily enters the first special winning opening 45a.

A second special variable winning device 46 (special electric winning device) is provided below the normal variable winning device 42. The second special variation winning device 46 has a structure in which a lower portion is pivotally supported and an opening/closing door 46b that can be opened/closed closes/opens the second special winning opening 46a therein. In addition, a sensor (second special winning opening sensor 76 in FIG. 3) that detects passage of a game ball to the second special winning opening 46a is formed inside thereof.
When the opening door 46b is opened, the second special winning opening 46a is opened. In this state, the game ball flowing down the left game area 3b or the right game area 3c will enter the second big winning opening 50 with a high probability.

As described above, in the game area of the board, the upper starting opening 41, the lower starting opening 42a, the normal symbol starting opening 44, the first big winning opening 45a, the second big winning opening 46a, and the general winning opening 43 are formed as winning openings. Has been done.
In the pachinko gaming machine 1 of the present embodiment, among these winning openings, if there is a winning in a winning opening other than the normal symbol starting opening 44, per winning ball set for each winning opening The number of prize balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the number of prize balls is set such that the upper starting opening 41 and the lower starting opening 42a are three, the first big winning opening 45a, the second big winning opening 46a are 13, the general winning opening 43 is 10, and the like.
The game balls that have not won a prize in each of these winning openings are discharged from the game area 3a through the outlet 48.
Here, the "winning prize" means that the winning opening takes in the game ball inside it or the game ball passes through the gate. Actually, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated as if a "winning" has occurred at that winning opening. The game ball related to this winning is also called a "winning ball".

On the board as described above, the center decoration 35C, the lower left decoration 35L, the lower right decoration 35R, the center stage 35S, the first special variation winning device 45, the second special variation winning device 46, and a movable body accessory not shown. Although not shown in detail in the figure, light emitting units 20b, 20Z, 20H, and 20J formed of, for example, LEDs are provided at various places as light emitting means on the board side.
The light emitting unit 20b performs a light emitting operation for performance and a light emitting operation for error notification.
The light emitting units 20Z, 20H, and 20J are light emitting units for presenting various situations.
The light emitting unit 20Z performs a light emitting operation for identifying variable symbols. The light emitting unit 20Z is provided, for example, three corresponding to each of the first special symbol, the second special symbol, and the ordinary symbol. For the respective corresponding symbols, for example, during stop of fluctuation of the symbol, during fluctuation, and hitting. A light emitting operation for identifying is performed.
The light emitting unit 20H performs a light emitting operation for displaying the number of holdings. The light emitting unit 20H displays, for example, the maximum number of reservations for the first special symbol fluctuation up to 4, and also displays the maximum number of reservations for the second special symbol fluctuation up to 4, for example, a total of eight are provided. And the number of holdings is displayed in the light emitting state.
The light emitting unit 20J performs a light emitting operation for informing the gaming state. The light emitting units 20J are provided in a required number (three in this example), and each of the light emitting states informs that the jackpot is in progress, the probability is changing, the time is shortening, or the like.
Although the light emitting units 20Z, 20H, and 20J are provided on the board side in this example, all or a part of the light emitting units 20Z, 20H, and 20J may be provided on the frame side.

Hereinafter, for the sake of explanation, the board-side light emitting unit 20w and the frame-side light emitting unit 20b may be referred to as “effect light emitting unit”.
Further, the light emitting unit 20Z may be referred to as a “variable symbol identifying light emitting unit”, the light emitting unit 20H may be referred to as a “holding number display light emitting unit”, and the light emitting unit 20J may be referred to as a “game state notification light emitting unit”.
Further, the light emitting units 20Z, 20H, and 20J may be collectively referred to as “situation presenting light emitting unit”.

<2. Control configuration of pachinko machine>
Next, the configuration of the control system of the pachinko gaming machine 1 of the present embodiment will be described. FIG. 3 is a schematic block diagram of the internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 of the present embodiment is mainly provided with a main control board 50, a production control board 51, a payout control board 53, a launch control board 54, and a power supply board 58 as boards for forming the control configuration thereof. ..

A microcomputer or the like is mounted on the main control board 50, and performs overall control of overall gaming operations of the pachinko gaming machine 1. In the following, the structure of the main control board 50 including the microcomputer mounted on the main control board 50 will be referred to as the “main control section 50”.
The effect control board 51 is equipped with a microcomputer or the like, receives an effect control command from the main controller 50, and performs control for executing various effect operations using image display, light emission, sound output, and movable body accessory. I do. In the following, the structure of the effect control board 51 including the microcomputer and the like mounted on the effect control board 51 will be referred to as “effect control unit 51”.

The payout control board 53 performs payout control of prize balls by the game ball payout device 55 connected to the pachinko gaming machine 1.
The launch control board 54 controls the launching operation of the game ball by the launching device 56 provided in the pachinko gaming machine 1 of the player.
The power supply board 58 performs AC/DC conversion and further DC/DC conversion from an external power supply (for example, AC 24V), and supplies the operating power supply voltage Vcc to each unit. The illustration of the power supply path is omitted.

First, the main controller 50 and its peripheral circuits will be described.
The main control unit 50 includes a microprocessor including a CPU 100 (hereinafter referred to as “main control CPU 100”), a ROM 101 (hereinafter referred to as “main control ROM 101”), a RAM 102 (hereinafter referred to as “main control RAM 102”), and the like. ing.
The main control CPU 100 executes various calculations and control processes according to the progress of the game based on the control program.
The main control ROM 101 stores a control program for game operation by the main control CPU 100 and various data necessary for game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processes and a buffer area for various input/output data and process data.
Although illustration is omitted, the main control unit 50 is an interface circuit with each unit, a random number generation circuit that generates random numbers for lottery related to special symbol variation display, a CTC (Counter Timer Circuit) for various time counting, a main An interrupt controller circuit for giving an interrupt signal to the control CPU 100 is also provided.

The main control unit 50, as described above, each winning means in the game area of the board surface (upper starting opening 41, lower starting opening 42a, normal symbol starting opening 44, first big winning opening 45a, second big winning opening 46a, general It is configured to receive a detection signal of a sensor provided at the winning opening 43).
That is, the detection signals of the upper starting opening sensor 71, the lower starting opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first big winning opening sensor 75, and the second big winning opening sensor 76 are sent to the main controller 50. Supplied.
Note that these sensors (71 to 76) are composed of detection switches that detect the game balls that have entered, but specifically, contactless switches such as photo switches and proximity switches, and contact switches such as micro switches. It can be configured with a switch.

The main control unit 50 receives the detection signals of the upper starting opening sensor 71, the lower starting opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first big winning opening sensor 75, and the second big winning opening sensor 76. Processing is performed according to. For example, lottery processing, symbol variation control, prize ball payout control, effect control command transmission control, external data transmission processing, etc. are performed.

Further, the main control unit 50 is connected to an ordinary electric accessory solenoid 77 that opens and closes the movable wing piece 42b of the lower starting port 42, and the main control unit 50 transmits a control signal in accordance with the progress of the game to be ordinary electric. A driving operation of the accessory solenoid 77 is performed, and an opening/closing operation of the movable blade 42b is performed.
Further, in the main control unit 50, a first special winning opening solenoid 78 that opens and closes the opening door 45b of the first special winning opening 45 and a second big winning opening that opens and closes the opening door 46b of the second special winning opening 46. The mouth solenoid 79 is connected. The main controller 50 drives and controls the first big winning opening solenoid 78 or the second big winning opening solenoid 79 in accordance with the so-called big hit situation to open the first big winning opening 45 or the second big winning opening 46. To run.

In addition, the symbol display unit 33 is connected to the main control unit 50, and a control signal is transmitted to the symbol display unit 33 to execute various symbol displays (LED extinguishing/lighting/blinking). Thereby, the display operation in the first special symbol display unit 80, the second special symbol display unit 81, the normal symbol display unit 82 in the symbol display unit 33 is executed.

An external terminal board 57 for a frame is connected to the main controller 50. The main control unit 50 is capable of transmitting information regarding the progress of the game to a hall computer (not shown) via the frame external terminal board 57. The information on the progress of the game is, for example, information such as jackpot winning information, prize ball number information, and symbol variation display execution number information. The hall computer is a management computer that comprehensively manages the gaming machine in the pachinko hall, and is installed outside the gaming machine.

A payout control board 53 is connected to the main controller 50. To the payout control board 53, a launch control board 54 that controls the launching device 56 and a game ball payout device 55 that pays out the game balls are connected.
The main control unit 50 transmits a control command (payout control command for designating the number of prize balls) related to payout, to the payout control board 53. The payout control board 53 controls the game ball payout device 55 according to the control command to execute the payout of the game balls.
Further, the payout control board 53 can transmit information (payout state signal) regarding the payout operation state to the main control unit 50. On the main control unit 50 side, this payout state signal monitors whether or not the game ball payout device 55 is functioning normally. Specifically, during the prize ball payout operation, it is monitored whether or not a problem such as a ball jam or insufficient prize ball payout has occurred.

In addition, the main control unit 50 transmits an effect control command including information on the special symbol variation display to the effect control unit 51. In addition, the transmission of the production control command from the main control unit 50 to the production control unit 51 is executed by one-way communication. This is to prevent an unauthorized signal due to an unauthorized act from the outside from being input to the main control unit 50 via the effect control unit 51.

Next, the effect control unit 51 and its peripheral circuits will be described.
The effect control unit 51 is equipped with a microprocessor incorporating a CPU 200 (hereinafter referred to as “effect control CPU 200”), a ROM 201 (hereinafter referred to as “effect control ROM 201”), and a RAM 202 (hereinafter referred to as “effect control RAM 202”). It constitutes a microcomputer.

Based on the effect control program and the effect control command received from the main control unit 50, the effect control CPU 200 performs arithmetic processing for various effect operations and control of each effect means. In the case of the pachinko gaming machine 1 of the present embodiment, the rendering means is the main liquid crystal display device 32M, the sub liquid crystal display device 32S, the light emitting units 20w and 20b, the speaker 25, and a movable body accessory (not shown).
The effect control CPU 200 also performs control for presenting various situations. Specifically, it is the light emission control of the light emitting units 20Z, 20H, and 20J.
The effect control ROM 201 stores a control program for effect operation by the effect control CPU 200 and various data necessary for effect operation control.
The effect control RAM 202 (D-RAM 202a in FIG. 4, work memory 202b for built-in CPU) is used as a work area used by the effect control CPU 200 for various arithmetic processes, a table data area, a buffer area for various input/output data and processing data, and the like. Used.
As will be described later, the arithmetic control unit 51 shows an example in which a 1-chip microcomputer and its peripheral circuits are mounted, but various configurations of the effect control unit 51 are conceivable. For example, in addition to a microcomputer, an interface circuit with each unit, a random number generation circuit that generates random numbers for lottery for performance, a CTC for various time counting, a watchdog timer (WDT) circuit, an interrupt signal to the performance control CPU 200. In some cases, an interrupt controller circuit for giving a sound, a sound source IC for sound production, and the like are provided.

The main role of the effect control unit 51 is to receive an effect control command from the main control unit 50, select and determine an effect based on the effect control command, display control of the main liquid crystal display device 32M and the sub liquid crystal display device 32S (display data). Supply), audio output control of the speaker 45, light emission control of the light emitting units 20w, 20b, 20Z, 20H, and 20J (LED), operation control of the movable body accessory (drive control of the movable body accessory motor 65), and the like.

Since the effect control unit 51 also has a function as a control device for the main liquid crystal display device 32M and the sub liquid crystal display device 32S, the effect control unit 51 includes so-called VDP (Video Display Processor), image ROM, VRAM ( The function control CPU 200 also functions as a liquid crystal control unit.
VDP refers to a function that controls overall video output processing such as image development processing and image drawing.
The image ROM refers to a memory that stores image data (effect image data) for which the VDP performs image expansion processing.
The VRAM is an image memory area for temporarily storing the image data expanded by the VDP.

With these configurations, the effect control unit 51 generates various image data based on the command from the main control unit 50 and outputs the image data to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. As a result, various effect images are displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

Further, a frame driver unit 61 and a board driver unit 62 are connected to the effect control unit 51.
The frame driver unit 61 drives the LEDs of the lamp unit 63 on the frame side to emit light. The lamp section 63 is a general term for the light emitting section 20w provided on the frame side as shown in FIG.
The board driver unit 62 drives the LEDs of the lamp unit 64 on the board side to emit light. The lamp section 64 is a general term for the light emitting sections 20b, 20Z, 20H, and 20J provided on the board side as shown in FIG.

Further, a motor driver unit 70 is connected to the effect control unit 51.
The motor driver unit 70 drives the movable body accessory motor 65 to execute the operation of the movable body accessory object provided on the board side.
As the movable body accessory motor 65, for example, a stepping motor is used.
The origin position is defined for each movable body accessory motor 65. The origin position is, for example, a position where the accessory does not normally appear on the board surface of FIG.
An origin switch 68 is provided on each movable body accessory motor 65 so that the effect control unit 51 can confirm whether or not each movable body accessory motor 65 is at the origin position. For example, a photo interrupter is used. Information on the origin switch 68 is detected by the effect control CPU 200.

Further, details will be described later with reference to FIGS. 6, 7, and 8, but in the case of the present embodiment, the effect control unit 51 uses the light emission drive data and the motor drive data as serial data, and the frame driver unit 61 and the board driver. It is output to the unit 62 and the motor driver unit 70.

In addition, the production control unit 51 causes voice output control from the speaker 25 to be executed. The effect control unit 51 outputs the music for the effect and the sound signal as the sound to the amplifier unit 67 as a stereo output signal of two channels of Lch and Rch, for example. This audio signal is amplified by the amplifier section 67 and then given to the speaker 25.
Although only one system of the amplifier 67 and the speaker 25 is shown in FIG. 3 for convenience of illustration, actually, the amplifier 67 and the speaker 25 are provided with output channels corresponding to Lch and Rch, respectively. , Sound reproduction by stereo is enabled.

Further, the effect control unit 51 is connected to an operation unit 60 that can be operated by the player, and can receive an operation detection signal from the operation unit 60. The operation unit 60 is the effect buttons 11 and 12 and the cross key 13 described in FIG. 1, and their operation detection mechanism.
The effect control unit 51 can perform various effect controls according to the operation detection signal from the operation unit 60.

Based on the production control command sent from the main control unit 50, the production control unit 51 determines a production pattern from a plurality of types of production patterns prepared in advance by a lottery or uniquely, and produces various productions at necessary timings. Control means. Thereby, the effect image is displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S corresponding to the effect pattern, the sound is reproduced from the speaker 25, and the lamp units 63 and 64 (light emitting units 20w, 20b, 20Z, 20H, and 20J). ), the LED blinking drive and the operation of the movable body accessory by the movable body motor 65 are realized, and various effect patterns are developed in time series. As a result, the production according to the "production scenario" is realized.

The effect control command defines a function by a 2-byte configuration including a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish MODE and EVENT, Bit7 of MODE is ON and Bit7 of EVENT is OFF.
The effect control command from the main control unit 50 is taken into the reception buffer in the effect control unit 51. The effect control CPU 200 confirms the reception buffer at a predetermined timing, analyzes the received effect control command, and determines the effect control to be executed.

<3. Structure of production control section>
FIG. 4 shows a specific configuration example of the effect control unit 51.
The production control unit 51 in the example of FIG. 4 is configured by externally connecting a production control ROM 201, a D-RAM 202a, a CG-ROM 206, a WDT (watchdog timer) circuit 210, and the like to the 1-chip microcomputer 250, for example. There is.

The one-chip microcomputer 250 includes the effect control CPU 200, and has the functions of the above-described VDP, VRAM, etc., and further the function of performing light emission control, motor control, and sound control by the respective units illustrated.
Each component will be described.

The 1-chip microcomputer 250 is equipped with a performance control CPU 200. The effect control CPU 200 performs various control processes as described above.
The effect control CPU 200 uses an internal device or an external device of the microcomputer 250 via the CPU interface 203.
That is, the effect control CPU 200 is connected to the host interface 204 via the CPU interface 203, receives commands from the main control unit 50, reads access to the effect control ROM 201, and transmits/receives signals to/from the WDT circuit 210 via the host interface 204. , And communicates with the internal units via the bus 251.

The effect control CPU 200 uses the D-RAM 202a and the built-in CPU work memory 202b as the effect control RAM 202 described above.
The D-RAM 202a is connected to the RAM interface 208, and the effect control CPU 200 writes to and reads from the D-RAM 202a via the RAM interface 208.

The system control register 205 is a register for initializing the system.
The transfer circuit 212 performs transfer using the internal resources of the microcomputer 250 and external peripherals as inputs and outputs.

The CG-ROM 206 is an image ROM and stores character image data to be displayed.
The CG-ROM 206 is connected to the CG bus interface 207 provided in the microcomputer 250. As a result, a required part in the microcomputer 250 can access the CG-ROM 206 via the CG bus interface 207.

The microcomputer 250 has a built-in VRAM 209 having a capacity of 48 Mbytes, for example. The VRAM 209 stores drawing materials and frame data.
Although various usage modes of the VRAM 209 are possible by setting, in this example, two frame buffers 209A and 209B are set as storage areas of the frame data for display, and the frame buffers 209A and 209B are alternately used for each frame. To draw and output display data.

Since two display devices (a main liquid crystal display device 32M and a sub liquid crystal display device 32S) are used in this embodiment, the frame buffers 209A and 209B are respectively the main liquid crystal display device 32M and the sub liquid crystal display device 32S. Will be prepared according to.
That is, the illustrated frame buffer 209A includes a frame buffer area for the main liquid crystal display device 32 and a frame buffer area for the sub liquid crystal display device 32S, and a frame buffer 209B includes a frame buffer area for the main liquid crystal display device 32 and a sub buffer area. It includes a frame buffer area for the liquid crystal display device 32S.
Image data for one frame for the main liquid crystal display device 32M and one frame for the sub liquid crystal display device 32S are generated in the frame buffers 209A and 209B of the VRAM 209, respectively. The position is specified.

The index table 211 manages the VRAM 209 such as setting a storage area of the VRAM 209.

The preloader 220, the display circuits 221, 222, 223, the GDEC (graphic decoder) 223, and the drawing circuit 225 perform various processes as a video processor (VDP).
The effect control CPU 200 creates a display list for setting image contents to be displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S according to the effect control command. The display list is a group of drawing commands.
The display list is composed of a group of drawing commands described in the drawing order. The drawing command includes a command that defines what kind of image is drawn at which position in one frame, and the storage position (source address) of the image to be drawn such as the CG-ROM 206 is also specified.

The drawing circuit 225 draws a figure in the frame buffer (209A or 209B) on the VRAM 209.
The GDEC 223 decodes the compressed image data used for drawing and expands it in the VRAM 209.

The preloader 220 analyzes the display list transmitted by the data transfer circuit 72, and transfers the image material referred to therein, that is, the image data on the CG-ROM 206 to a designated area of either the DRAM 202a or the VRAM 209. To do.
Further, at this time, the preloader 220 outputs a display list in which the reference destination of the image data is rewritten to the transferred address. The rewritten display list is transmitted to the drawing circuit 225 by the data transfer circuit 212.

Since random access to the image data occurs during execution of the drawing by the drawing circuit 225, if the image data is directly referenced from the CG-ROM 206 which is weak in random access such as a NAND flash memory, the drawing performance is significantly deteriorated. Therefore, by using the preloader 220 to transfer the image data and the display list to the D-RAM 202a or the built-in VRAM 209 in advance, the moving image decoding and the drawing can be executed at high speed.

As described above, in the present embodiment, the preloader 220 is made to function, so the reference destination of the image data (CG data as image material) in the display list is set in the D-RAM 202a or VRAM 209, not in the CG-ROM 206. It is a preload area. Therefore, the random access to the image data that occurs during the drawing by the drawing circuit 225 can be performed quickly, which is advantageous for the drawing process even for a high-resolution moving image with a lot of movement.

The display circuits 221, 222, 223 display-output the display data of the frame buffer (209A or 209B) of the VRAM 209 to the outside.
Here, the microcomputer 250 is provided with three display circuits 221, 222, and 223, which are compatible with three screen outputs that enable one system of digital RGB output and two systems of LVDS (Low voltage differential signaling) output. This is because the configuration is adopted. In the case of this example, for example, the digital RGB output is used as the display data output to the main liquid crystal display device 32M, and one LVDS output is used as the display data output to the sub liquid crystal display device 32S.
The display data from the display circuits 221, 222, 223 is selected by the LCD interface 226 and output to an external device, that is, the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

The display circuits 221, 222, and 223 output display data as non-interlaced output. Further, the display data is provided with a scaling processing function for enlarging/reducing from 2 times to 1/2 times, a dithering function, and a color correction function.
FIG. 5 shows a block diagram of the display circuits 221, 222, 223 and the LCD interface 226.

Each of the display circuits 221, 222, and 223 has a synchronization signal generation unit 265, and performs processing in synchronization with each frame of an image. The synchronization signal generation unit 265 generates, as the synchronization signal, for example, a V blank signal indicating a vertical blank period (ineffective line scanning period), a horizontal synchronization signal, and a vertical synchronization signal. These synchronization signals can be used for control processing inside the microcomputer 250, and also used for display data transfer to the main liquid crystal display device 32M and sub liquid crystal display device 32S and display control operation.
The synchronization signals used in the display circuits 221, 222, and 223 can be synchronized with each other. For example, the display circuits 221, 222, and 223 can be forcibly synchronized with each other by using the fall of the vertical synchronizing signal of the external display such as the main liquid crystal display device 32M as a trigger.

Each display circuit 221, 222, 223 acquires the frame data read from the frame buffer 209A or 209B of the VRAM 210 by the VRAM reading unit 261.
With respect to the display circuits 221, 222, it is possible to perform scaling processing by the scaler 262, color correction processing by the color correction unit 263, and dithering processing by the dither 264 on the acquired frame data. Then, digital RGB output and LVDS output are performed as outputs after the processing by the ditherer 264. The same applies to the display circuit 223, but in the example of this figure, the display circuit 223 does not include the function of the scaler 262.

The LCD interface 226 has a digital RGB output section 226a and an LVDS output section 226b.
Display data as digital RGB outputs from the display circuits 221, 222, and 223 is supplied to the digital RGB output unit 226a. The digital RGB output section 226a selects one digital RGB output of the display circuits 221, 222, 223 and supplies it to the main liquid crystal display device 32M.
Further, the LVDS output unit 226b is supplied with the display data as the LVDS output from the display circuits 221, 222, and 223. The LVDS output unit 226b can select and output two LVDS outputs from the display circuits 221, 222, and 223. In the case of the pachinko gaming machine 1 of the present embodiment, the LVDS output of one of the display circuits 221, 222, 223 is supplied to the sub liquid crystal display device 32S.
Of course, this is an example, and it is conceivable that one LVDS output is supplied to the main liquid crystal display device 32M, and that digital RGB output is supplied to the sub liquid crystal display device 32S.

The microcomputer 250 of FIG. 4 has a sound controller 230.
The sound controller 230 has, for example, a sound source control unit and a sound data storage unit that stores compressed sound data. Under the control of the effect control CPU 200, the sound controller 230 decodes the compressed sound data to generate an output sound signal, and an external amplifier. Output to the unit 67.
Note that the effect control CPU 200 may control the sound source IC outside the microcomputer 250 to output a sound signal to the amplifier section 67 regardless of whether the sound controller 230 is installed or not.

The microcomputer 250 has a general-purpose port 231. For example, it is an 8-bit input/output port. The general-purpose port 231 enables input/output with various external devices.

The serial output controller 240 outputs the control signal as serial data to the outside. In the case of the present embodiment, the serial output controller 240 is provided with the lamp controller 241 and the motor controller 242, and outputs the light emission drive data of the lamp units 63 and 64 and the motor drive data of the movable body accessory motor 65. Be seen.
FIG. 6 shows an output system of emission drive data from the serial output controller 240 (the lamp controller 241 and the motor controller 242) to the frame driver unit 61 and the board driver unit 62, and an output system of the motor drive data to the motor driver unit 70. ..

In the frame driver unit 61, n LED drivers 90 are connected in parallel to the serial data output channel ch1 of the serial output controller 240.
As the signal line of the serial data output channel ch1, a clock line for supplying a clock signal CLK and a data line for supplying serial data DATA as light emission drive data (also referred to as “LED drive data” or “lamp drive data”) are provided. Has been. Each of these signal lines is connected so as to supply each signal in parallel to the n LED drivers 90 forming the frame driver unit 61.
A device ID used as a slave address by the effect control CPU 200 is set in each LED driver 90 of the frame driver unit 61. That is, it is an identifier of each LED driver 90. For the sake of explanation, the device IDs (slave addresses) of the LED drivers 90 are written as w1, w2,...

In the board driver unit 62, m LED drivers 90 are connected in parallel to the serial data output channel ch2 of the effect control CPU 200.
Similarly to the channel ch1, the signal line of the serial data output channel ch2 is also provided with a clock line for supplying the clock signal CLK and a data line for supplying the serial data DATA as the light emission drive data. Each of these signal lines is connected so as to supply each signal in parallel to the m LED drivers 90 that form the panel driver unit 62.
A device ID (identifier of each LED driver 90) used as a slave address by the effect control CPU 200 is set in each LED driver 90 of the board driver unit 62. For the sake of explanation, the device IDs (slave addresses) of the respective LED drivers 90 are described as b1, b2,...

Each of the LED drivers 90 in the frame driver unit 61 and the board driver unit 62 is, for example, a 24-channel LED driver and has 24 current terminals. Therefore, one LED driver 90 can supply the LED drive current to up to 24 series. Specifically, for example, 8 series of R (red) LED drive currents are supplied, 8 series of G (green) LED drive currents are supplied, and 8 series of B (blue) LED drive currents are supplied to emit 8 full-color LEDs. It can be driven. Here, one "series" refers to one LED connected to one current terminal or a group of a plurality of LEDs connected in series or in parallel to one current terminal. There is.
The number n of the LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of the light emitting units 20w). Therefore, n may be 1 or may be 2 or more. The frame driver unit 61 has one or a plurality of LED drivers 90.
The number m of the LED drivers 90 in the board driver unit 62 is determined by the number of LED series (the number of light emitting sections 20b, 20Z, 20H, and 20J) arranged on the board side. Therefore, m may be 1 or may be 2 or more. The board driver unit 62 has one or a plurality of LED drivers 90.

FIG. 7 shows a schematic configuration example of a main part of the LED driver 90.
The LED driver 90 includes a serial bus interface 191, an address setting unit 192, a data buffer/PWM controller 193, a D/A converter 194, and drive current source circuits 195-1 to 195-24.
The drive current source circuits 195-1 to 195-24 are current sources that perform the above-mentioned 24 series of drive current outputs from the current terminals 196-1 to 196-24, respectively.

To the LED driver 90, the clock signal CLK and the serial data DATA from the serial output controller 240 are input to the serial bus interface 191. The serial bus interface 191 takes in the serial data DATA at the timing of the clock signal CLK. The serial bus interface 191 converts the captured serial data into parallel data and transfers it to the data buffer/PWM controller 193.
The serial output controller 240 specifies the slave address and transmits the LED drive data.
The data buffer/PWM controller 193 confirms the slave address of the parallel data transferred from the serial bus interface 191. When it is confirmed that the slave address included in the parallel data matches with its own slave address (either w1 to w(n) or b1 to b(m)) set in the address setting unit 192. The LED drive data included in the parallel data is stored in the designated register as valid data.

The data buffer/PWM controller 193, after taking in the LED drive data of each series, sets the value corresponding to the brightness information (gradation value) indicated by the LED drive data as D/A as each drive control value of 24 series. Output to the converter 194.
The D/A converter 194 converts a value corresponding to the luminance information into an analog signal, which is used as a control signal to each of the current source circuits 195-1 to 195-24.

The LEDs 120 of 24 series are connected to all (or part) of the current terminals 196 (196-1 to 196-24). It should be noted that the figure shows a state in which one LED 120 is connected to one series of current terminals 196 for simplification, but a configuration in which a plurality of LEDs are connected to one series of current terminals 196 (for example, serial connection) is also possible. Naturally possible.
In each series (current terminals 196-1 to 196-24), the power supply voltage Vcc is applied to the series connection of the LED 120 and the resistor R. A current is caused to flow through the LEDs 120 of each series by the current source circuits 195-1 to 195-24 to emit light.
That is, each of the current source circuits 195-1 to 195-24 operates so that a drive current having a current amount corresponding to the signal supplied from the D/A converter 194 is supplied to the LEDs 120 of the corresponding series.

To be more specific about such LED drive control for one series, the data buffer/PWM controller 193 uses the D/A converter 194 to convert the digital data string corresponding to the pulse duty corresponding to the gradation value of the series. Then, the D/A converter 194 converts the digital data string into a pulse signal as an analog signal and supplies the pulse signal to the current source circuit 195 of the relevant series. The output of the current source circuit 195 is controlled by H/L of the pulse signal, and outputs a current of 0 mA and 5 mA, for example. For example, with such an operation, a drive current having an average current value corresponding to the gradation value eventually flows through the LED 120.
In this embodiment, the current value is set to 0 mA and 5 mA by the PWM driving method, and the gradation control is performed (integrally) in the time axis direction. Of course, it goes without saying that the current value may actually be changed according to the gradation. Regardless of whether it is duty control or level control, an appropriate current level can be expressed by setting the average current value per unit time to a level corresponding to the gray level.

The number n of the LED drivers 90 in the frame driver unit 61 is determined by the number of LED series arranged on the frame side (the number of series of the light emitting units 20w). Therefore, n may be 1 or may be 2 or more. The frame driver unit 61 has one or a plurality of LED drivers 90.
The number m of the LED drivers 90 in the board driver unit 62 is determined by the number of LED series (the number of light emitting sections 20b, 20Z, 20H, and 20J) arranged on the board side. Therefore, m may be 1 or may be 2 or more. The board driver unit 62 has one or a plurality of LED drivers 90.

As the lamp units 63 and 64 using LEDs and the like, an example in which one system (one serial data output channel) is provided on the frame side and one system is provided on the board side is not limited to this. A plurality of systems may be provided for the frame side lamp section 63, or a plurality of systems may be provided for the board side lamp section 64.

Next, the output of motor drive data will be described. As shown in FIG. 5, serial data DATA as motor drive data is output from the serial output controller 240 to the motor driver unit 70.
In the motor driver unit 70, p motor drivers 91 are connected in parallel to the serial data output channel ch3 of the serial output controller 240.
Similarly, the signal line of the serial data output channel ch3 is also provided with a clock line for supplying the clock signal CLK and a data line for supplying the serial data DATA as motor drive data. Each of these signal lines is connected so as to supply each signal in parallel to the p motor drivers 91 constituting the motor driver unit 70.
A device ID (identifier of each motor driver 91) used by the production control CPU 200 as a slave address is set in each motor driver 91 of the motor driver unit 70. For the sake of explanation, the device IDs (slave addresses) of the respective motor drivers 91 are described as mt1, mt2,...

Each motor driver 91 in the motor driver unit 70 may have the configuration of FIG. 7 similarly to the LED driver 90. That is, the same driver can be used.
The number p of the motor drivers 91 in the motor driver unit 70 is determined by the number of motors used for the movable body accessory 65 and the like. Therefore, p may be 1 or may be 2 or more. The motor driver unit 70 has one or a plurality of motor drivers 91.

A movable body accessory motor 65 that drives the movable body accessory is connected to the motor driver 91.
FIG. 8 shows an example in which a stepping motor 121, for example, is connected as the movable body accessory motor 65 to all (or part) of the current terminals 196-1 to 196-24 of the motor driver 91.
Here, drive currents are supplied to the four-phase stepping motor 121 from current terminals 96-1 to 96-4, current terminals 96-5 to 96-8,... Current terminals 96-21 to 96-24, respectively. An example of the configuration is shown.
The driver configured as described above with reference to FIG. 7 is a circuit that outputs a current instructed by a given command (serial data) from the current terminals 196-1 to 196-24. It can also be used as a motor driver 91 for a physical movable body driving device such as a solenoid.
The operation of the movable body accessory is finely set according to the production scenario, and the production control unit 51 controls the drive direction, the drive amount, and the like according to the scenario. By driving the accessory, it becomes possible to control the movable accessory by serial data together with the light emitting units (LEDs 20w, 20b) of the lamp units 63, 64, and the control processing and configuration can be made efficient.

Note that, in one LED driver 90, a method may be adopted in which some current terminals are used for driving the LEDs and other some current terminals are used for driving the stepping motor, the solenoid, and the like.

Further, a sensor 68s described as the origin switch 68 in FIG. 3 is arranged corresponding to each of the movable body accessory motors 65 (stepping motors 121). The signal from each sensor 68s is input to the parallel/serial conversion unit 260.
Also, an example is shown in which user operation information from the operation unit 60 is also input to the parallel/serial conversion unit 92. The user operation information is a signal corresponding to the operation of the effect buttons 11 and 12, the cross key 13, and the like.
The parallel/serial conversion unit 260 is mounted on the effect control unit (effect control board) 51 as an IC separate from the 1-chip microcomputer 250, for example, but may be built in the 1-chip microcomputer 250.

The parallel/serial conversion unit 260 inputs signals of, for example, 32 systems, converts the input data into serial data Is, and supplies the serial data Is to the motor controller 242.
The operation of the parallel/serial conversion unit 260 is controlled by the control signal CNT from the motor controller 242. The parallel/serial conversion unit 260 performs serial data transfer using the clock signal CLK.
With this configuration, the serial output controller 240 collects the origin detection state of each movable body accessory motor 65 and the user operation on the operation unit 60 such as the effect switches 11 and 12, that is, collects the input necessary for the effect control, and improves the efficiency. Can be detected. Therefore, the effect control CPU 200 can efficiently grasp the effect state.

<4. Overview of operation>
The outline of the operation of the pachinko gaming machine 1 will be described.
[Variable pattern display game]
In the pachinko gaming machine 1, a jackpot lottery is carried out by a random number lottery in the main controller 50 on condition that a predetermined starting condition, specifically, a game ball has been won in the upper starting opening 41 or the lower starting opening 42. Based on this lottery result, the special symbol (identification symbol for notifying the jackpot lottery result) is variably displayed on the first special symbol display portion 80 or the second special symbol display portion 81 to start the special symbol variable display game, After a certain period of time, the result is displayed on the special symbol display portion (80 or 81).

In the present embodiment, the jackpot lottery based on the winning of the upper starting opening 41 and the jackpot lottery based on the winning of the lower starting opening 42 are performed independently. Therefore, the jackpot lottery result regarding the upper starting opening 41 is arranged to be displayed on the first special symbol display portion 80 side, and the jackpot lottery result regarding the lower starting opening 42 is displayed on the second special symbol display portion 81 side.
In the description, the special symbol variation display game on the side of the first special symbol display unit 80 is the “first special symbol variation display game”, and the special symbol variation display game on the side of the second special symbol display unit 81 is the “second special symbol variation”. Display game". However, the first and second special symbols are collectively referred to as "special symbol", and the first and second special symbol variable display games are collectively referred to as "special symbol variable display game".

When the special symbol variable display game is started, along with this, a decorative symbol variable display game in which the decorative symbol (game symbol) is variably displayed on the main liquid crystal display device 32M is started, and various effects are accompanied by this. Will be issued. When the lottery result is displayed on the first and second special symbol display portions (80, 81), the result is also displayed on the main liquid crystal display device 32M by the decorative symbol. That is, in this decorative symbol variable display game, an effect display that reflects the lottery result in the special symbol variable display game, that is, an effect that reflects the jackpot lottery result appears.

For example, when the result of the special symbol variable display game is "big hit", the result of the decorative symbol variable display game is also an effect in which "big hit" is reflected. Further, the special symbol display portion (80, 81), the special symbol indicating a big hit is stopped and displayed in a predetermined display mode, and the main liquid crystal display device 32M has each display area of "left", "middle", and "right". In a predetermined display mode in which the decorative design reflects the big hit lottery result on the winning effective line (for example, in each display area of “left”, “middle” and “right”, three decorative designs are “7” and “7”). It is stopped and displayed in the display state of "7".

In the case of this "big hit", for example, the first big winning opening solenoid 78 or the second big winning opening solenoid 79 is driven to open the first big winning opening 45 or the second big winning opening 46 in a predetermined pattern. The special game state (big hit game) that is executed and is more advantageous to the player than the normal game state occurs. In this big hit game, until the opening time of the special winning opening elapses a predetermined time or until a predetermined number of game balls are won in the special winning opening, the special winning opening is predetermined on the condition that either of them is satisfied. The round game, which is closed for a certain time, is repeated a predetermined number of times.
When the big hit game is started, an opening effect is first notified to the effect that the big hit is started, and after the opening effect is finished, the round game is performed for a specified number of rounds. Also, during the round game, a round effect corresponding to each round is performed. Then, after the specified number of rounds, an ending effect for notifying that the big hit is ended is performed, whereby the big hit game is ended.

In this way, the special symbol variable display game and the decorative symbol variable display game have substantially the same symbol game time (variable display start timing to stop display timing), and reflect the result of the special symbol variable display game. Since the thing is expressed in the decorative symbol variable display game, these two symbol variable display games can be regarded as an equivalent symbol game. For the sake of explanation, the above two symbol variable display games may be simply referred to as "symbol variable display game".

Further, based on that the game ball has passed through the gate 44 (normal symbol starting port), the main control unit 50 performs an auxiliary winning lottery by a random number lottery. According to this lottery result, the normal symbol represented by the LED of the normal symbol display portion 82 is variably displayed to start the normal symbol variable display game, and after a lapse of a predetermined time, the result is specified whether the LED is turned on or off. Stop display by combination.

When the "auxiliary hit" is reached, the normal electric accessory solenoid 77 is actuated, the movable wing piece 42b is opened, and the lower starting opening 42 is opened or enlarged to allow a game ball to easily flow in (starting opening is opened). State), and an auxiliary game state (hereinafter, referred to as "normal electric open game") that is more advantageous to the player than the normal game state occurs. In this normal electric open game, the movable wing piece 42b is opened for a predetermined time (for example, 0.2 seconds) or until a predetermined number (for example, 4) of game balls are won, and then for a predetermined time (for example, for example). (0.5 seconds) The operation of closing the movable blade 42b is repeated a predetermined number of times. Even when the game ball wins the lower start opening 42 during the normal electric opening game, the special symbol variable display game is similarly performed, and the decorative symbol variable display game is also performed.

Here, during the special symbol variation display game, during the normal symbol variation display game, during the big hit game, or during the normal electric open game, etc., from the upper starting mouth sensor 71 or the lower starting mouth sensor 72 or the gate sensor 73. When a detection signal is input and the starting condition is satisfied, the game information used in the winning lottery is acquired based on the detection signal, and the data related to the starting right for executing each variable display game is acquired. As the (holding data), it is possible to hold and store up to the maximum number of held storages (for example, up to 4) which is a predetermined upper limit value, excluding those relating to variable display. In order to make the number of holdings clear to the player, a holding display provided as an icon image is lit on the screen of the holding number display unit 20H and the main liquid crystal display device 32M.
Normally, the variable display game is executed for each of the reserved balls in the order of occurrence of the reserved balls. In the present embodiment, the same number as the maximum reserved storage number of 4 is treated as a predetermined upper limit number, and the first special symbol and the reserved data relating to the second special symbol are stored up to 4 respectively, and the variation of the special symbol or the normal symbol Hold as a fixed number.

[Game state]
In the pachinko gaming machine 1 of the present embodiment, a plurality of types of gaming states can be generated.
First, the pachinko gaming machine 1 of the present embodiment has a "probability variation (hereinafter referred to as "probable variation") function" in which the main control unit 50 (CPU 100) plays a functional part. There are two types of probability variation function related to special symbols (hereinafter referred to as "special symbol probability variation function") and probability variation function related to normal symbols (hereinafter referred to as "normal symbol probability variation function").

The special symbol probability variation function changes the lottery probability of the big hit from a low probability (for example, 1/399) of a predetermined probability (normal probability) to a high probability (for example, 39.9/1), which is more advantageous than a normal game state. It is a function to generate a "high probability state". Under this high-probability state, the jackpot lottery probability becomes a high probability, so that the jackpot is likely to occur.
The normal symbol probability variation function is advantageous over the normal game state by changing the probability of lottery per auxiliary from a low probability (for example, 1/256) which is a predetermined probability (normal probability) to a high probability (for example, 255/256). This is a function to generate the "auxiliary contact probability change state". Under this probability change condition of the auxiliary hit, the auxiliary hit lottery probability becomes a high probability state, so the auxiliary hit is likely to occur, the regular electric open game frequently occurs, and the movable blade per unit time is higher than that in the normal game state. The operating rate improving state is achieved in which the operating rate of the piece 42b is improved.

Further, the pachinko gaming machine 1 of the present embodiment has a "variable time shortening (hereinafter referred to as "time saving") function" in which the main controller 50 plays a functional part thereof. There are two types of time saving functions related to special symbols (hereinafter referred to as "special symbol time saving functions") and time saving functions related to ordinary symbols (hereinafter referred to as "normal symbol time saving functions").

Special symbol time saving function, shortened the average time required for one special symbol variable display game (the time from the start of fluctuation of the special symbol to the fixed display. In other words, the variation time of the special symbol) This is a function to generate a "time saving state". Under the special symbol time saving state, the average variation time of the special symbols in one special symbol variation display game is shortened, and the lottery number improving state is achieved in which the number of jackpot lottery per unit time is improved as compared with the normal gaming state.
In the pachinko gaming machine 1, the variable display time of the special symbol may be shortened due to the difference in the number of holdings, but in this case, the special symbol time saving state does not occur, and it is caused by another control process. It is a thing.

Normal symbol time saving function, "normal symbol" that shortens the average time required for one normal symbol variable display game (the time from the start of variation of the regular symbol to the fixed display. That is, the variation time of the regular symbol) This is a function to generate a "time saving state". Under the normal symbol time saving state, the average variation time of the normal symbol in one ordinary symbol variable display game is shortened, and the lottery number improvement state in which the number of lots per assist per unit time is improved compared to the normal game state ..

In addition, the pachinko gaming machine 1 of the present embodiment has an "open extension function" in which the main controller 50 plays a functional part.
The open extension function is a function of generating a "open extension state" in which the period during which the movable wing piece 42b is opened and the number of times of opening thereof are extended. This open extended state is called a so-called "electricity support state". In the open extension state, the opening operation period (starting port open state time) of the movable wing piece 42b is extended, for example, from 0.2 seconds to 1.7 seconds, and the number of times of opening and closing thereof is changed from once to twice, for example. The operating ratio is extended and the operating ratio of the movable wing piece 42b per unit time is improved as compared with the normal game condition.

By operating one or more kinds of each function as described above, it is possible to change the internal gaming state of the gaming machine.
Here, in the present embodiment, the normal symbol probability changing function, the normal symbol time saving function, and the operation start condition of the opening extension function are the same as the operation starting condition of the special symbol time saving function, and each function operates at the same trigger. Will be done.

[About]
In the pachinko gaming machine 1 of the present embodiment, the types of hits drawn in the special symbol variable display game, that is, the types of hits targeted for the big hit lottery, are “15R low base non-probable variation big hit” and “15R low base probable variation α”. Multiple types of hits are provided, such as "big hit", "15R low base probability variation big hit", "15R high base probability variation big hit", "2R low base probability variation big hit", and "small hit".

<5. Processing of main controller>
The control process of this embodiment will be described below. First, main processing by the main control unit (main control board) 50 will be described.
FIG. 9 is a flowchart showing the main processing of the main controller 50. The main process is started when the power is turned on without operating the initialization switch (not shown) as in the case of recovery from a power failure, and when the initialization switch is turned on and the power is turned on. May be turned on. In any case, when the pachinko gaming machine 1 is powered on, the power supply board 58 supplies a voltage to each control board. In this case, the main control unit 50 (main control CPU 100) starts the main processing shown in FIG.

In this main control side main process, the main control CPU 100 first executes a necessary initial setting process before starting the game operation in step S11. For example, it first sets itself in the interrupt disabled state, sets a predetermined interrupt mode (interrupt mode 2), and initializes the register value inside the CPU including each part of the microcomputer.
Next, in step S12, the main control CPU 100 determines the state (ON, OFF) of the RAM clear signal, which is the output signal of the RAM clear switch input via an input port (not shown). The RAM clear signal is a signal that determines whether or not to initialize the entire area of the RAM. The RAM clear signal normally has a value corresponding to the ON/OFF state of the initialization switch operated by the pachinko parlor staff.

When the RAM clear signal is in the ON state, the main control CPU 100 advances the processing from step S12 to S16, and zero-clears all the areas of the RAM. Therefore, the value of the backup flag set when the power is cut off becomes zero together with other checksum values.
Subsequently, in step S17, the main control CPU 100 transmits a "RAM clear display command" for notifying that the RAM area has been zero-cleared to each control board as an initialization command. Then, in step S18, for example, 30 seconds is stored in the RAM clear notification timer as a time for notifying that the RAM has been cleared.

Next, in step S19, the main control CPU 100 initializes the CTC that outputs an interrupt signal that activates the timer interrupt operation, and sets the CPU to the interrupt enable state.
After that, as the processing of steps S20, S21, and S22, the interrupt-disabled state and the interrupt-enabled state are repeated until an interrupt occurs, and various random number update processes are executed during that period. In the random number updating process of this step S21, random numbers used to change the initial value (start value) of various random numbers used for special symbol variation display and normal symbol variation display, and variation used for selection of variation patterns Update the random number for the pattern.
The various random numbers used for the special symbol fluctuation display and the normal symbol fluctuation display are, for example, random numbers related to the jackpot lottery that circulates within a predetermined numerical range by an increment process (random numbers for special symbol determination used in the symbol lottery). Or a random number related to the auxiliary winning lottery (a random number for auxiliary winning determination used in the winning lottery per auxiliary). Further, the random numbers used for changing the initial values include special symbol determination initial value random numbers, auxiliary hit determination initial value random numbers, and the like.

In the main control RAM 102, as various random number counters used in the symbol lottery related to the big hit lottery, the auxiliary hit lottery, or the variation pattern lottery, a special symbol determination random number counter initial value generation counter, a special symbol determination random number counter A random number counter for generating auxiliary hit determination initial value counter, a random number counter for auxiliary hit determination, a random number 1 counter for variation pattern, a random number 2 counter for variation pattern, and the like are provided. These counters serve as random number generating means for generating random numbers by software.
In the various random number update processing of step S21, two initial value generation counters for generating initial values of the special symbol determination random number counter and the auxiliary winning determination random number counter, the variation pattern random number 1 counter, the variation pattern random number 2 A counter or the like is updated to generate the above various soft random numbers. For example, if the numerical value range that can be taken as the fluctuation pattern random number 1 counter is 0 to 238, a value is acquired from the count value storage area for generating the value of the fluctuation pattern random number 1 of the main control RAM 102, and the acquired value is set to 1 Is stored in the original count value storage area. At this time, if the result of adding 1 to the acquired value is 239, 0 is stored in the original random number counter storage area. The other initial value generating random number counters are similarly updated. The main control CPU 100 is configured to repeatedly execute various random number updating processes except during the time of performing the timer interrupt process which is intermittently executed.

The case where it is determined in step S12 that the RAM clear switch is ON has been described above. The case where the RAM clear switch is OFF will be described subsequently. For example, at the time of recovery from the power failure state, the initialization switch (RAM clear signal) is in the OFF state. In such a case, the main control CPU 100 advances the processing from step S12 to S13 and determines the backup flag value. The backup flag is set to the ON state when the power is shut off, and is reset to the OFF state in the first timer interrupt process after the power is restored.
Therefore, the backup flag should normally be in the ON state when the power is turned on or when the power is restored from the power failure. However, if the predetermined process is not completed before the power is cut off for some reason, the backup flag is reset (OFF). Therefore, when the backup flag is in the OFF state, the main control CPU 100 advances the process from step S13 to S16 and returns the operation of the gaming machine to the initial state.

On the other hand, if the backup flag is in the ON state, the main control CPU 100 advances the process from step S13 to S14, and executes the checksum calculation for calculating the checksum value. Here, the checksum operation is an 8-bit addition operation for the work area of the main control RAM 102.
Then, when the checksum value is calculated, this calculation result is compared with the stored value of the SUM address of the main control RAM 102. This SUM address stores the checksum value obtained by the same checksum calculation when the power is cut off. The stored calculation result is maintained by the backup power supply together with other data in the main control RAM 102. Therefore, originally, the two should match according to the determination in step S14.
However, there is a case where the checksum calculation cannot be executed when the power is shut off, or even if the checksum calculation can be executed, the data in the work area may be damaged before the checksum calculation is executed in the main process. In such a case, the determination result of step S14 does not match.
When data corruption is detected due to the mismatch of the determination results, the main control CPU 100 proceeds to the processing of steps S14 to S16 to execute the RAM clear processing, and returns the operating state of the gaming machine to the initial state.

If the checksum value calculated by the checksum operation in step S14 and the stored value of the SUM address match, the main control CPU 100 proceeds to step S15 and restores the stack pointer before power-off based on the backup data, The game recovery process necessary to start the game from the processing state when the power is cut off is executed.
Then, when the game recovery process of step S15 is completed, the process proceeds to step S19, CTC is initialized and the CPU is set to the interrupt enabled state, and thereafter, the interrupt disabled state and the interrupt enabled state are generated until an interrupt occurs. While repeating the above, the above-described various random number updating processing is executed during that time (steps S20 to S22).

Next, the timer interrupt process of the main control CPU 100 will be described. FIG. 10 shows the timer interrupt processing of the main control CPU 100. The main control timer interrupt process is activated by an interrupt from the CTC at regular intervals (about 4 ms), and is interrupted and executed during execution of the main process.

When a timer interrupt occurs, the main control CPU 100 saves the contents of the register in the stack area, and then first performs a power supply abnormality check process for monitoring the power supply state from the power supply board 58 in step S51 of FIG. In this power supply abnormality check process, it is mainly monitored whether or not the power is normally supplied. Here, for example, when an abnormality such as power failure occurs, a backup process of storing predetermined game information at the time of power failure in the RAM is performed so that the game can be restored without trouble when the power is restored.

Next, in step S52, the main control CPU 100 performs timer management processing for managing the timer used for game operation control. Timer values of various timers (for example, special symbol auditors product operation timer) used for game operation control of the pachinko gaming machine 1 are managed (updated) by this processing.

In step S53, the main control CPU 100 performs an input management process. In this input management process, detection information from various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. The detection information by the various sensors here includes, for example, an upper starting opening sensor 71, a lower starting opening sensor 72, a gate sensor (normal symbol starting opening sensor) 73, a first big winning opening sensor 75, a second big winning opening sensor 76. It is ON/OFF information (winning detection information) of a switch signal output from a winning detection switch such as the general winning opening sensor 74.
By the processing of this step S53, whether or not a winning is detected (a winning occurs) at each winning opening is monitored for each interruption. The "winning counter" is a counter that is provided for each winning opening and counts the number of game balls that have won (the number of winning balls). In the present embodiment, in a predetermined area of the main control RAM 102, the upper starting opening prize counter for the upper starting opening 41, the lower starting opening winning counter for the lower starting opening 42a, the normal symbol starting opening winning counter for the gate 44, the first A first special winning opening winning counter for the first big winning opening 45a, a second big winning opening winning counter for the second big winning opening 46a, a general winning opening winning counter for the general winning opening 43, etc. are provided. ..
Further, in this input management processing, it is also monitored whether or not there is an illegal prize, based on whether or not the detection information from the prize detection switch has won during the period in which the prize should be allowed. For example, when the first and second special winning opening sensors 75 and 76 detect a game ball even though the big hit game is not being performed, this is regarded as an illegal winning and the winning detection information is invalidated and invalidated. A predetermined error process is performed in the error management process of step S55, which will be described later, in order to notify the effect to the outside.

In step S54, the main control CPU 100 performs a timer interrupt random number management process that regularly updates the random numbers associated with each variable display. In this regular random number update process, the special symbol determination random number and the auxiliary winning determination random number are updated (+1 is added for each interrupt), and the start value of the random number counter is changed each time the random number counter makes one round. For example, the value of the special symbol determination random number counter is updated within a predetermined range (+1 addition), and each time the special symbol determination random number counter makes one round, the value of the special symbol determination random number counter initial value generation counter is read, The value of the generation counter is stored in the special symbol determination random number counter. As a result, the start value of the special symbol determination random number counter is changed according to the value of the generation counter, so that the count value of the special symbol determination random number counter becomes random even though the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process for monitoring whether there is an abnormality in the game operation state. In this error management processing, as an abnormality of the game operation state, for example, whether or not there is a disconnection between the boards, or whether or not there is an illegal prize, and these operation abnormalities (errors) have occurred. In that case, a predetermined error process corresponding to the error is performed.
As the error processing, for example, the progress of a predetermined game operation (for example, a payout operation of a game ball or a launching operation of a game ball) is stopped, or an error notification command is transmitted to the effect control unit 51, and an error is caused by the effect means. Is notified that the event has occurred.

In step S56, the main control CPU 100 performs prize ball management processing. In this prize ball management process, the data stored in the input management process of step S53 is grasped, the above-mentioned prize counter is confirmed, and if a prize is won, a payout control command for designating the number of prize balls is paid out. Transmit to the substrate 53.
The payout control board 53, which has received the payout control command, controls the game ball payout device 55 to perform the payout operation for the designated number of prize balls. As a result, the number of prize balls corresponding to each winning opening is paid out. The number of prize balls corresponding to the prize holes is a predetermined number of prize balls per prize ball set for each prize hole×the number of prize balls corresponding to the value of the prize counter.

In step S57, the main control CPU 100 performs normal symbol management processing. In this normal symbol management process, the auxiliary winning lottery in the normal symbol variation display is performed, and based on the result of the lottery, the variation pattern of the ordinary symbol and the stop display mode of the ordinary symbol are determined, or the blinking is repeated every predetermined time. Create symbol data (data for LED blinking display during normal symbol change), or if normal symbol is not changing, create data for stop display (LED blink display data during normal symbol stop display) Or

In step S58, the main control CPU 100 performs normal electric accessory management processing. In this ordinary electric auditors product management process, based on the lottery result of the auxiliary winning lottery in the ordinary symbol management process in step S57, the excitation signal for solenoid control of the ordinary electric auditors product solenoid 77 is generated and its data (solenoid control data). Make settings. Based on the data set here, an excitation signal is output to the ordinary electric accessory solenoid 77 in the solenoid management process in step S64 described later, and thereby the operation of the movable wing piece 42b is controlled.
In step S59, the main control CPU 100 performs a special symbol management process. In this special symbol management process, mainly, a big hit lottery in the special symbol variation display, based on the lottery result, the variation pattern of the special symbol (prefetch variation pattern, variation pattern at the start of variation), special stop symbol, etc. decide.
In step S60, the main control CPU 100 performs a special electric auditors product management process. In this special electric auditors product management process, mainly when the big hit lottery result is "big hit" or "small hit", the setting processing necessary for executing and controlling the hit game corresponding to the hit is performed.

In step S61, the main control CPU 100 performs right-handed notification information management processing. In this right-handing notification information management process, for example, a right-handing instruction is given in a situation where right-handing is advantageous, such as an opportunity to open the first and second special winning openings 45a and 46a and an electric support state in which the movable wing piece 42b is driven. Processing for causing the "launch position guidance effect (right-handed notification effect)" to be notified is displayed. Specifically, the right-handing instruction is a directing operation for instructing a player to aim at the right game area 3c, and for example, causes the main liquid crystal display device 32M to display an image prompting the player to “right-hand”. Alternatively, a right-handed message voice is generated from the speaker 25.
When the right-handing notification effect is performed, in this right-handing notification information management process, a "right-handing instruction command" for instructing execution of the right-handing notification effect is transmitted to the effect control unit 51 as an effect control command, and the command is received. Then, the effect control unit 51 controls the execution of the right-handed notification by image or sound.
In step S62, the main control CPU 100 performs LED management processing. This LED management process is a process of outputting display data for the normal symbol display and the first and second special symbols display to the symbol display unit 33. By this process, the variable display and the stop display of the normal symbol and the special symbol are performed. The display data of the normal symbol created in the normal symbol management process of step S57 and the display data of the special symbol created in the special symbol display data update process during the special symbol management process of step S59 are the LED management process. Is output with.

In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management processing, the operating state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. As the operation state information, the fact that the big hit game has occurred (the condition device has been activated), the fact that the small hit game has occurred, that the symbol variation display has been executed (the fact that the special symbol variation display game has started or ended) , Winning information (information that the player has won the starting opening or the big winning opening and the number of prize balls).
In step S64, the main control CPU 100 performs solenoid management processing. In this solenoid management process, an excitation signal is output to the normal electric auditors product solenoid 77 based on the solenoid control data created in the normal electric Auditor product management process in step S58, and is created in the special electric auditors product management process in step S60. The excitation signal output processing for the first and second special winning opening solenoids 78 and 79 is performed based on the solenoid control data. As a result, the movable wing pieces 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower start opening 42a and the special winning openings 45a and 46b are opened and closed.

After completing the processing in steps S51 to S64, the main control CPU 100 restores the saved contents of the register and sets the interrupt enabled state in step S65. As a result, the timer interrupt process is terminated, the process returns to the main process main process before the interrupt shown in FIG. 9, and the main control main process is performed until the next timer interrupt occurs.

In the above processing, the main control unit 50 (main control CPU 100) sequentially transmits necessary commands to the effect control unit 51.
As an example of the command, the variation pattern command related to the winning lottery of the special symbol variation display game, part of the winning command is shown in FIG. 11A, and part of the symbol designating command is shown in FIG.
In the variation pattern command and the winning command, the type of the variation pattern is defined by the upper byte and the lower byte, and the upper byte is different depending on the deviation/win.
The symbol designating command is configured such that the upper byte shows the first and second special symbols and the lower byte designates the winning type.

<6. Process of production control unit of first embodiment>
Next, the processing of the effect control unit 51 will be described. First, an example of the structure of scenario data for effect control will be described.
The structure of the scenario registration information will be described with reference to FIGS. FIG. 12A shows the structure of scenario registration information as a main scenario and a sub-scenario. The scenario registration information is set using a work area provided in the effect control RAM 202 (for example, the work memory 202b for built-in CPU).
In this embodiment, the scenario registration information has 64 channels of scenario channels sCH0 to sCH63. The scenarios registered in each scenario channel sCH can be executed simultaneously.

As shown in the figure, the information that can be registered in each scenario channel sCH includes the sub-scenario timer (scTm) used in the sub-scenario update process, the previous time (scPrevTm), and the sub-scenario execution line indicating the execution line of the sound/motor sub-scenario table. (ScIx), sub-scenario execution line lmp (lmpIx) indicating the ramp sub-scenario table execution line, main scenario timer (msTm) used for scenario update processing, main scenario execution line (mcIx) indicating the main scenario table execution line, There is a main scenario number (mcNo), a main scenario option (mcOpt) that is optional data that can be added to the main scenario, a user option (userFn), a waiting time (delay), and a checksum (checkSum).

When the sound output from the speaker unit 59, the light emission from the lamp units 63 and 64, and the production by driving the movable body accessory by the movable body accessory motor 65 are started, the standby time (delay) and the main scenario number (mcNo) are set as a scenario. Register to a vacant scenario channel of channels sCH0 to sCH63.
The waiting time (delay) indicates the time from the registration to the scenario channel sCH to the start of the scenario. The waiting time (delay) is decremented by 1 at a predetermined processing timing (for example, step S104 in FIG. 16 described later). When the waiting time (delay) is 0, the process corresponding to the registered data is executed.

FIG. 14 shows an example of scenario numbers 1, 2, and 3 as a part of the main scenario table. As the scenario of each scenario number, the value of the main scenario timer (msTm) is described as time data in each line of the scenario, and the sub-scenario number (scNo) and option (OPT) can be described. .. That is, in the main scenario table, the sub-scenario (and optionally the option) to be executed is designated as the time by the main scenario timer (msTm). In the last line of the scenario, the scenario data end code D_SEEND or the scenario data loop code D_SELOP is described.
The value of the main scenario timer (msTm) is incremented by 1 at a predetermined processing timing (for example, step S104 in FIG. 16 described later) from the start of the main scenario.
The scenario table for each scenario number advances to the next row when the time of the main scenario timer (msTm) in a certain row has elapsed. The time data of each row indicates the timing when the row ends.
For example, in the case of scenario number 2, the operation of sub-scenario number 2 is designated as the time of timer value “1500”, the operation of sub-scenario number 20 is designated as the time of the next timer value “500”, and the next timer value “ The operation of sub-scenario number 21 is designated as the time of 2000". The next line is the scenario data end code D_SEEND. When the scenario data end code is D_SEEND, this scenario is deleted from the scenario registration information (work).

Next, the structure of the lamp data registration information will be described with reference to FIG. 12B. As the lamp data registration information, the scenario selected from the lamp sub-scenario table, that is, the information indicating the effect operation (lighting pattern) by the lamp units 63 and 64 is registered. This lamp data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the lamp data registration information has 16 channels of the ramp channels dwCH0 to dwCH15. A priority is set for each of the lamp channels dwCH0 to dwCH15, and the priority increases in order from the lamp channels dwCH0 to dwCH15. Therefore, the scenario (ramp sub-scenario) registered in the ramp channel dwCH15 is executed with the highest priority. Further, for example, if a scenario is registered in the lamp channels dwCH3 and dwCH10, the scenario registered in the lamp channel dwCH10 is preferentially executed.
The ramp channel dwCH0 is mainly used for a lamp effect associated with BGM (Back Ground Music), the ramp channel dwCH15 is used for an error-related lamp effect, and the ramp channels dwCH1 to dwCH14 are used for a normal effect.

The information that can be registered in each lamp channel dwCH is, as shown in the figure, a registered lighting number (lmpNew) indicating the registered lighting pattern number, an execution lighting number (lmpNo) indicating the number of the lighting pattern to be executed, and a lamp sub-scenario of the lamp sub-scenario. There are an offset (offset) indicating an execution line, an execution time (time), and a checksum (checkSum).

FIG. 15A shows an example of lamp sub-scenario numbers 1, 2, and 3 as a part of the lamp sub-scenario table. As the lamp sub-scenario of each number, a value of time data (time) is described in each line of the scenario, and a lamp channel and a lamp number indicating various lighting patterns are described. Further, the lamp scenario data end code D_LSEND is described in the last line.

In the ramp sub-scenario table, the time data (time) of each line indicates the time when the line is started after the sub-scenario is started.
The main scenario timer (msTm) described above is compared with the time data in the table, and if they match, the lamp number of that line is registered in the lamp data registration information in FIG. 12B. The registered ramp channel dwCH is the channel shown on the line.
For example, suppose that scenario number 2 shown in FIG. 14 is registered and sub-scenario number 2 is referred to in the above-mentioned certain scenario channel sCH. In the ramp sub-scenario number 2 shown in FIG. 15A, the ramp channel 5 (dwCH5) and the ramp number 5 are described with the time data (time)=0 on the first line. In this case, when the main scenario timer (msTm)=0, the information of the first line is first registered in the lamp channel dwCH5 of the lamp data registration information of FIG. 12B as the registered lighting number (lmpNew)=5. The value of the sub-scenario execution line lmp (lmpIx) of the scenario registration information is updated to the value of the next line (second line). This is a registration for performing the lighting pattern operation of the lighting number 5 with a relatively low priority of the lamp channel dwCH5.
For the second line, similar processing is performed when the main scenario timer (msTm) becomes "500". That is, the registered lighting number (lmpNew)=6 (that is, the lighting pattern instruction of the lighting number 6) is registered in the lamp channel dwCH5 of the lamp data registration information.
If the time data (time) has the same value in two consecutive lines, the processing for each line is started at the same time.
In the lamp drive data creation process described below, the lamp drive data is created based on the lamp data registration information updated in this way.

Next, the structure of the motor data registration information will be described with reference to FIG. 12C. As the motor data registration information, information indicating a scenario selected from the motor sub-scenario table is registered. This motor data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the motor data registration information has eight channels, for example, motor channels mCH0 to mCH7 corresponding to eight motors.
As the information that can be registered in each motor channel mCH, as shown in the figure, execution operation number (no), registration operation number (noNew), operation count (lcnt), excitation counter (tcnt), execution step (step), operation line. (Offset), parent (migration source)/child (migration destination) attribute (attribute), parent number (retNo), return address (retAddr), loop start point (roopAddr), loop count (roopCnt), error counter (errCnt) ), current input information (currentSw), software switch information (softSw), and software count (softCnt).

FIG. 15C shows an example of the motor sub-scenario number 1 as a part of the motor sub-scenario table. As the motor sub-scenario of each number, the value (ms) of time data (time) is described in each line of the scenario, and the information of the motor and solenoid/user option is described. The scenario data end code D_MSEND is described in the last line.

Regarding this motor sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (it is 0 at the beginning), the value of the time data (time) of this motor sub-scenario table is set in the sub-scenario timer (scTm). To do. The time data (time) of each line indicates the timing when the line ends. The absolute time is described in the sub-scenario timer (scTm). Therefore, the time data value to be set is the value of (time data of the relevant line)-(time data of the previous line).
The motor data (motors 0 to 3 and 4 to 7) is configured to indicate the number of the motor operation pattern (the number of the motor operation table in FIG. 21, which will be described later) with 1 byte for each motor. The operation pattern number is set in the registration operation number (noNew) and execution operation number (no) of the motor channel corresponding to the motor number.
This motor data registration information is updated in step S202 of FIG. 20 described later, and in step S203, motor drive data is created based on the update of the motor data registration information.

FIG. 13 shows sound data registration information. As the sound data registration information, information indicating the scenario selected from the sound sub-scenario table is registered. This sound data registration information is also set using the work area of the effect control RAM 202.
In the present embodiment, the sound data registration information has 16 sound channels aCH0 to aCH15.
As information that can be registered in each sound channel aCH, as shown in the figure, volume transition amount (frzVq), volume (frzVl), transition amount change (rsv2), volume change (rsv1), phrase change (rsv0), stereo (frzSt). ), a loop (frzLp), a phrase number hi (frzHi), and a phrase number low (frzLo).

FIG. 15B shows an example of sound sub-scenario numbers 1 and 2 as a part of the sound sub-scenario table. As the sound/motor sub-scenario of each number, the value (ms) of time data (time) is described in each line of the scenario, and BGM, warning sound, error sound, and sound control information are described. It The scenario data end code D_SEEND is written in the last line.
Regarding this sound sub-scenario table, when the sub-scenario timer (scTm) becomes 0 (it is 0 at the beginning), the value of the time data (time) of this sound sub-scenario table is set in the sub-scenario timer (scTm). To do. The time data (time) of each line indicates the timing when the line ends. The absolute time is described in the sub-scenario timer (scTm). Therefore, the time data value to be set is the value of (time data of the relevant line)-(time data of the previous line).
The BGM data of the line is composed of information to be registered in the sound data registration information such as the BGM phrase number and volume value, and is set to the sound channel aCH0 (additionally aCH1 in the case of stereo) in the sound data registration information. ..
The data of the warning sound of the line is composed of information registered in the sound data registration information such as the phrase number of the warning sound and the volume value, and is set in a vacant place of the sound channels aCH2 to aCH14.
The error sound data of the line is composed of information registered in the sound data registration information such as the phrase number and volume value of the error sound, and is set in the sound channel aCH15.
The sound control data consists of channel information in the lower 6 bytes and control information in the upper 2 bytes.
In step S133 of FIG. 16 described later, reproduction output control is performed based on the scenario update process and the updated sound data registration information.

The sound sub-scenario table and the motor sub-scenario table may be integrated into a table structure for each line of time.

An example of the process of the effect control unit 51 that performs the effect control using the scenario data structure as described above, particularly the process of the effect control CPU 200 will be described with reference to FIG. 16.
The effect control CPU 200 starts the processing of FIG. 16 when the power of the gaming machine main body is turned on. First, in step S100, effect control CPU 200 performs necessary initial setting processing before starting the game operation. For example, as the initialization processing, interface system initialization, interrupt setting, external memory initialization, WDT initialization, movable body accessory starting point return processing and control initialization, sound source control initialization, serial output controller 240 Initialization, initialization of scheduler (scenario scheduler, device scheduler, lamp scheduler, sound scheduler), initialization of system timer, initialization of liquid crystal control, etc. are performed.
Each scheduler refers to the above-mentioned scenario registration information, motor data registration information, lamp data registration information, sound data registration information, or progress of scenario control based on these. As the initialization processing, a work area for storing the scenario registration information and the like is initialized.

When the initial setting process of step S100 ends, the effect control CPU 200 repeats the process of step S101 and subsequent steps.
In particular, in the present embodiment, the effect control CPU 200 executes the processing from step S101 while monitoring the frame timing of the display data in order to perform the liquid crystal control at the same time. In this example, control is performed based on the V blank signal which is a synchronizing signal used for display control. A display data synchronizing signal such as a V blank signal is generated in a portion of the 1-chip microcomputer 250 that realizes the VDP function. For example, it is generated by the synchronization signal generation unit 265. In this embodiment, the V blank signal is generated twice during 1/30 seconds (33.3 ms) which is one frame period of the display image.
The effect control CPU 200 counts up the V blank interrupt counter in response to the V blank signal, so the V blank interrupt counter is counted up every 1/60 seconds (16.6 ms).
Naturally, each process of the effect control CPU 200 is performed based on the processing clock having a frequency extremely higher than the frequency of the V blank signal. Each process of FIG. 16 is performed while grasping the period from the frame start to the end in accordance with the V blank signal. At the frame start point, the process is performed once in steps S103 to S106, and then V blank is performed. Steps S121 to S143 are repeated until the end of one frame period is confirmed by the value of the interrupt counter. When the end of one frame period is detected, steps S150 to S151 are performed.

In step S101, the effect control CPU 200 performs clear control for the WDT circuit 210. Therefore, the WDT circuit 210 is reset every frame when the effect control CPU 200 is in a normal processing state.
In step S102, the effect control CPU 200 confirms the frame update flag. The frame update flag is a flag for managing scheduler update and the like in a frame period.
The frame update flag is turned off at the start of a certain frame of the display data (because it is turned off in step S151 described later at the end of the frame).
Therefore, at the frame start timing, the effect control CPU 200 proceeds from step S102 to step S103.

In step S103, the effect control CPU 200 updates the drawing. For example, a display list, which is a group of drawing commands described in the drawing order as described above, is created, and execution start control of preload is performed.

In step S104, the effect control CPU 200 updates the frame of the scenario scheduler. Specifically, this is a process of updating the waiting time (delay) and the sub-scenario timer (scTm) of the scenario registration information of FIG. 12A. That is, it can be said that the process of advancing the timer of the production scenario by one timing at the start of the frame.
Then, the effect control CPU 200 turns on the frame update flag in step S105. This is information indicating that the scenario timer has been advanced in the current frame.
In addition, the production control CPU 200 turns off the scheduler update flag in step S106. This is information indicating that the scheduler has been updated, that is, the scenario content (scenario registration information, lamp data registration information, sound data registration information) has not been updated as the timer progresses.
Then, the process returns to step S101. After the production control CPU 200 clears the WDT circuit 210, since the frame update flag is ON in step S102, the process proceeds to step S120.

As described above, steps S103 to S106 are performed only once after the frame start timing, and the scenario registration information is updated in the timer in step S104. As will be described below, content update and control are executed according to the progress of the scenario timer, but for this reason, the scenario for effecting progresses every 33.3 ms which is one frame period. For example, the main scenario timer (msTm) advances every 33.3 ms. The time of the main scenario timer (msTm) in one line in the main scenario table of FIG. 14 corresponds to the value expressed by 33.3 ms. Further, the time of one line indicated by the time (time) in the sub-scenario table of FIG. 15 also corresponds to the expressed value×33.3 ms.

At step S120, effect control CPU 200 branches the process depending on the value of the V blank interrupt counter. If the V blank interrupt counter has not reached “2” (that is, “0” or “1”), the process proceeds to step S121.
The V blank interrupt counter is cleared at the end of the frame in step S150 and is incremented twice for one frame. Therefore, V blank interrupt counter=0 indicates the first half period of the frame, and V blank interrupt counter=1 indicates the second half period of the frame. The V blank signal at the end of the frame sets the V blank interrupt counter=2.
The effect control CPU 200 proceeds from step S120 to step S121 so as to repeat steps S121 to S143 as many times as possible during the frame period in which the V blank interrupt counter is “0” or “1”.

In step S121, the effect control CPU 200 branches the process depending on whether the V blank interrupt counter is "0" or "1". That is, the present is the first half or the second half of a certain frame period.
If the V blank interrupt counter is currently 0, that is, if it is the first half of the frame, the process proceeds to step S122, and the received command from the main control unit 50 is confirmed. That is, it is confirmed whether or not one or more reception commands are stored in the reception buffer for commands. If there is no received command, the process proceeds to step S130.
If there is one or a plurality of received commands, the effect control CPU 200 performs command analysis processing in step S123.
And production control CPU200 turns off the scheduler update flag in step S124. Note that turning off the scheduler update flag in step S124 means that the command is received again in the current frame period even if the scheduler update flag is turned off once in step S131. Meaning to turn off.

An example of the command analysis processing in step S123 will be described with reference to FIGS.
As described above, the effect control CPU 200 confirms in step S122 of FIG. 16 whether the effect control command supplied from the main control unit 50 is stored in the command reception buffer, and if the effect control command is stored. The command will be read in the process of FIG.

In the effect control unit 51, a command reception buffer that captures the effect control command transmitted from the main control unit 50 is prepared in the effect control RAM 202 (for example, D-RAM 202a).
The effect control CPU 200 first confirms the read pointer indicating the read address of the command reception buffer and the write pointer indicating the write address in step S301 of FIG.
The light pointer is updated in response to the command reception, and the received effect control command is stored in the address indicated by the light pointer accordingly. The read pointer is updated when reading from the command reception buffer (step S302). Therefore, if the read pointer is not the write pointer, it means that the effect control command that has not been read is stored in the command reception buffer. Therefore, if the read pointer is not the write pointer, the process proceeds to step S302, and the effect control CPU 200 loads 1-byte command data from the address indicated by the read pointer in the command receiving buffer. In this case, the read pointer is incremented for the next read (load).

It should be noted that the actual presence/absence of the received command in step S122 of FIG. 16 can also be determined by whether or not the read pointer=write pointer. As an actual program, if the read pointer=write pointer at the time when the command check processing is first performed, it may be determined that there is no received command in step S122 of FIG.

As described above, one effect control command is formed by 2 bytes, 1 byte as a mode and 1 byte as an event. The production control CPU 200 confirms in step S303 in FIG. 18 whether the loaded 1-byte command data is a mode or an event. This confirmation is performed by the value of Bit7 of 8 bits (Bit0 to Bit7).
If it is the mode, the process proceeds to step S304 as the process of receiving the upper data of the command, and the read command data is saved in the register "command HI byte". It also clears the "command LO byte" register. Then, the process returns to step S301.
Even if the read pointer is not equal to the write pointer, the effect control command that has not been read is stored in the command reception buffer. Load 1 byte of command data from the indicated address. Also, the read pointer is incremented.
If the read command is an event, the process proceeds from step S303 to S305 as the process of receiving the lower data of the command, and the read command data is saved in the register "command LO byte".

By saving the command data of the mode and the event in the register "command HI byte" and "command LO byte", the effect control CPU 200 has fetched one command.
Then, production control CPU200 does the processing which responds to the command which is taken in step S306. A specific example will be described later with reference to FIG.

The read pointer=write pointer is the case where the effect control command that the effect control CPU 200 has not yet fetched does not exist in the command reception buffer. When the read pointer=write pointer is confirmed in step S301, the command analysis process in step S123 of FIG. 16 is completed.

An example of the command handling process in step S306 will be described with reference to FIG.
FIG. 19A shows a basic process as a command corresponding process. In response to the reception of the 2-byte effect control command, effect control CPU 200 first confirms in step S321 of FIG. 19A whether or not the test mode is currently in progress. If in the test mode, in step S322 all effect scenarios are cleared, sound output is stopped, and the LEDs of the lamp units 63 and 64 are turned off. Then, in step S323, the test mode ends.
Unless in the test mode, these processes are not performed.
Then, the effect control CPU 200 performs the process for the imported effect control command in step S330.

As the production control command, for example, a special symbol variation pattern designation command, a special symbol designation command, a holding ball subtraction command, a holding ball addition command, an error display designation command, a jackpot start designation command, etc. are set in various ways. In step S330, effect control CPU200 performs the process prescribed|regulated by the program corresponding to the received command. Here, four processing control commands are listed in FIGS. 19B to 19E to exemplify specific processing.

FIG. 19B shows the processing S330a when the variation pattern command is fetched as the command processing in step S330.
In this case, effect control CPU200, in step S331, performs the process of setting the symbol command waiting state. This is because the effect control CPU 200 controls the variable display of symbols by sequentially receiving the variation pattern command and the symbol command.

FIG. 19C shows a process S330b when a symbol designating command is fetched as the command process in step S330.
In this case, the effect control CPU 200 first confirms in step S332 whether or not the variation pattern command has been received. If it has not been received, the process is terminated.
When the variation pattern command is already received when the symbol designating command is received, the process proceeds to step S333, and the scenario registration for the accessory origin correction operation is performed first. Then, in step S334, the symbol variation flag is set. The symbol variation flag is provided corresponding to each of the first special symbol, the second special symbol, and the normal symbol, and each flag represents a variation state. For example, a 2-bit first special symbol variation flag FZ1, a second special symbol variation flag FZ2, a normal symbol variation flag FZ3 are prepared, and for each of them, the state of changing, stopping (hit), and stopping (off) is shown. Here, with the start of fluctuation, the corresponding symbol fluctuation flag (one of FZ1, FZ2, and FZ3) is set to a value indicating "during fluctuation".
The symbol variation flag is set to a value indicating "stopped (winning)" for a predetermined time at the end of symbol variation in the case of winning, and then a value indicating "stopping (out)" until the symbol variation starts. Is set to.
In step S335, the effect control CPU 200 performs a fluctuation start process. Then, in response to the start of fluctuation, the fluctuation pattern command is deleted in step S336.

FIG. 19D shows processing S330c when a power-on command is received as the command processing in step S330.
In this case, the effect control CPU 200 performs a clear process of the effect control RAM 202 in step S337. For example, the contents of the command reception/transmission buffer, the input information buffer for the operation unit 60, and the checksum storage area are cleared.
Then, in step S338, an error release command is transmitted, in step S339, the accessory error information is cleared, in step S340, the accessory operation is stopped, in step S341, a scenario of power-on is registered, and in step S342, power is transmitted to the liquid crystal control board 52. Set commands sequentially.

FIG. 19E shows processing S330d when a RAM clear command is fetched as the command processing in step S330.
In this case, the effect control CPU 200 performs a clear process of the effect control RAM 202 in step S343. For example, the contents of the command reception/transmission buffer, the input information buffer for the operation unit 60, and the checksum storage area are cleared.
Then, in step S344, an error cancel command is transmitted, and in step S345, a RAM clear error is set and an error notification timer is set. Furthermore, in step S346, the information regarding the lottery process in the effect control RAM 202 is cleared, and in step S347, the information regarding the scenario is cleared. Then, in step S348, an initial power-on display (RAM clear) command to be transmitted to the liquid crystal control board 52 is set.

The processing according to the command reception has been described above.
The processing of steps S122 to S124 of FIG. 16 as processing according to the above command reception is started only during the period of V blank interrupt counter=0.

Subsequently, the effect control CPU 200 confirms the scheduler update flag in step S130 of FIG. 16 and branches the process. Here, the processes of steps S131 to S134 are performed only when the scheduler update flag is off.
Then, in step S131, the frame update flag is turned on.
Since the scheduler update flag is turned off in step S106 immediately after the frame starts, when the process first proceeds to step S130 in the current frame period, the processes of steps S131 to S134 are performed. Further, since the scheduler update flag is turned off in step S124, the processes of steps S131 to S134 are performed even when a command is received.

The production control CPU 200 performs a process as a scenario scheduler execution in step S132. This is a scenario registration information update process. For example, of the information registered in the scenario channel sCH, when the waiting time (delay) is 0, the processing corresponding to the registered data is executed. That is, the processing according to the scenario number specified in the main scenario table is performed. The main scenario execution line (mcIx), the sub-scenario execution line (scIx), the sub-scenario execution line lmp (lmpIx), etc. are also updated.
In step S133, the effect control CPU 200 performs the sound scheduler execution and output processing. This is update processing of sound data registration information according to the sound sub-scenario specified in the scenario table, and output processing of the sound control signal based on the sound data registration information. The effect control CPU 200 causes the sound controller 230 to perform sound output according to the current scenario progress.

In step S134, the effect control CPU 200 performs a lamp scheduler execution process.
This is a process of updating the lamp data registration information according to the lamp sub-scenario specified in the scenario table.
For example, the effect control CPU 200 performs the following process for each of the lamp channels dwCH0 to dwCH15. First, the main scenario timer (msTm) is compared with the time data (time) in the ramp sub-scenario table. The time data (time) of the ramp sub-scenario table indicates the time (ms) at which the line (the line indicated by the sub-scenario execution line lmp (lmpIx)) is started. Therefore, if the time of the main scenario timer is equal to or longer than the time data (time), the process for that line is performed.
For example, first, it is determined whether or not the current line is the line in which the lamp scenario data end code D_LSEND is described. If it is not the line in which the lamp scenario data end code D_LSEND is described, the effect control CPU 200 acquires the lamp channel dwCH and the lamp number described in the line, and registers the lighting pattern number in the acquired lamp channel dwCH. ..
Further, the registration lighting number (lmpNew) and the execution lighting number (lmpNo) are set in the area corresponding to the lamp channel dwCH. That is, the lamp number acquired from the relevant line of the lamp sub-scenario table is set to the registered lighting number (lmpNew), and "0" is set to the execution lighting number (lmpNo). Also, the value of the sub-scenario execution line lmp (lmpIx) is incremented by one. As described above, the lamp data registration information is updated to the state in which the lamp effect operation to be executed is registered.

In step S134, the lamp data registration information is updated as described above. The lamp driving data creation and the lamp driving data output based on the updated lamp data registration information are performed in steps S141 and S142, which will be described later.

At step S140, effect control CPU 200 branches the process depending on the value of the V blank interrupt counter. If the V blank interrupt counter is "0", the processes of steps S141 to S143 are executed, and if it is "1", these processes are not executed.
In step S141, the effect control CPU 200 creates lamp drive data. That is, the lamp drive data actually output from the serial output controller 240 to the frame driver unit 61 and the board driver unit 62 is generated based on the information registered in each lamp channel dwCH of the lamp data registration information.
Then, in step S142, the generated lamp drive data is transferred to the serial output controller 240 and is controlled to be output as serial data.
In step S143, the effect control CPU 200 performs key event processing. Then, the process returns to step S101.
The process of creating and outputting the lamp drive data in steps S141 and S142 is started only when the V blank interrupt counter=0. That is, these processes are started only in the first half period of the frame.

After the V blank interrupt counter=2, that is, when the end of the frame period is detected, the effect control CPU 200 performs the process at the end of frame in steps S120 to S150.
Here, the production control CPU 200 performs processing such as waiting for drawing completion, clearing the V blank interrupt counter, switching display screens, waiting for preload completion, and starting drawing.

A concrete example of the processing at the end of the frame is shown in FIG.
In step S171, the effect control CPU 200 waits for the completion of drawing. This waits for the completion of drawing the image to be displayed in the next frame period.
As described above, the VRAM 209 is provided with the frame buffers 209A and 209B, and during the frame period in which the display circuit 221 or the like reads and displays one display data, the other frame buffer stores the display data of the next frame. Drawing is done. It is confirmed in step S171 that this drawing is completed.

Note that normally, at the end of this frame period, the drawing of the display data of the next frame is designed to be completed. It is assumed that the drawing is not completed at this point in time when there is some trouble in the drawing process.
Therefore, when the drawing completion waiting occurs, the waiting time may be counted, and depending on the waiting time, a change such as reducing the number of drawing operations accessed in one frame period may be performed.
Further, if the standby is for a while (about 1 ms), the processing of the next frame is delayed a little, so that there may be no particular problem.
In addition, when drawing is not completed no matter how long, the process of the effect control CPU 200 is reset by the WDT circuit 210.

After confirming the completion of drawing, the effect control CPU 200 clears the V blank interrupt counter in step S172.
Then, in step S173, the display screens are swapped. That is, in the VRAM 209, the frame buffers 209A and 209B are switched to read the display data.
Although it is possible to unconditionally switch the frame buffers because the V blank interrupt counter=2, in the present embodiment, the frame buffer switching is performed after the drawing completion confirmation is performed in step S171. Be seen. Therefore, the display data transferred to the display circuit 221 or the like is the display data for which drawing has been completed correctly. In other words, if the drawing is not completed by the second time point of the vertical synchronizing signal, the display data of the frame buffer during drawing is not displayed.

At step S174, effect control CPU 200 confirms the completion of preload.
The preload is normally designed to be completed within one frame period, which is confirmed in step S174.
Even if the preload is delayed for a while, the output of the display data of the next frame is already started in the above step S173, so that it is not a big problem.
After that, the display list preloaded in step S175 is written into the frame buffer opposite to the frame buffer switched to the display data read target in step S173.

After performing the above-described processing at the end of the frame, the frame update flag is turned off in step S151 of FIG. 16, and the process returns to step S101. Then, as described above, the processing for the new frame period is performed.

In addition to the processing of FIG. 16 described above, the effect control CPU 200 executes the processing of FIG. 20 as an interrupt processing every 1 ms, for example. That is, the process of FIG. 20 is a process executed every 1 ms regardless of the frame timing of display data.
The effect control CPU 200 performs a WDT pulse generation process in step S200. The WDT circuit 210 counts every 1 ms by this WDT pulse.
In step S201, the effect control CPU 200 performs motor and solenoid sensor update processing. This is a process of detecting information of each sensor 68S as the origin switch 68 described above.

In step S202, the effect control CPU 200 performs device scheduler execution processing. Specifically, the motor data registration information is updated. Further, in step S203, output processing of motor drive data to the motor driver 70 is performed as device scheduler output processing.
That is, the effect control CPU 200 controls the motor operation at every 1 ms, which is a time interval of about 1/30 of the frame period.

Here, the motor operation table used for the motor operation control according to the motor data registration information will be described. 21A to 21D exemplify four motor operation tables. The motor operation tables are numbered, for example, these are motor operation tables 1, 71, 72, and x.

The motor operation table is a table in which one row (one control item) is composed of three contents of option (OPT), speed (SPEED), and step (STEP). The option (OPT) indicates the control type, the speed (SPEED) and the step (STEP) indicate the instruction value for the control content indicated by the control type.
With this structure, one row (one control item) serves as information defining one control process, and in principle, a series of operation patterns is specified in such a manner that the process of each row is sequentially performed.

As the option (OPT) indicating the control type, in this example, various operation types are defined as an operation type option indicating the control content of the motor operation and a non-operation type option indicating the control content without the motor operation. ..
In the case of the operation system option, the speed (SPEED) is an instruction value indicating the motor drive speed, and the step (STEP) is an instruction value indicating the motor operation range (the number of steps of the stepping motor).
On the other hand, in the case of the non-operation option, the speed (SPEED) is an instruction value that specifies the next process, such as the line to be moved to next (the number of lines to be advanced), the link destination, and the loop count. Steps are not normally used.
As described above, the speed (SPEED) which is the instruction value is shared by the operating system option and the non-operating system option, but the meaning of the instruction content is different.

Note that the step of executing the motor data registration information (step) in FIG. 12C is different from the step (STEP) of the motor operation table described above. The execution step (step) is a variable updated in the motor operation update process in step S202, and the step (STEP) of the motor operation table is information designating the number of drive steps of the motor operation.

The operating options are as follows. The "origin SW" is the origin switch 68 for detecting the position of the movable body accessory operated by each motor.
cw_all: Forward rotation operation: Operates when the origin SW is ON/OFF
cw_on ・・・ Forward rotation: Stop when origin SW is ON, operation when origin SW is OFF
cw_off・・・Forward operation: Operation when the origin SW is ON, stop when the origin SW is OFF
ccw_all・・・Reverse operation: Operates when the origin SW is ON/OFF
ccw_on ・・・Reverse rotation: Stop when origin SW is ON, operation when origin SW is OFF
ccw_off・・・Reverse operation: Operation when the origin SW is ON, stop when the origin SW is OFF
stop・・・Stop operation (no excitation)
keep・・・Stop operation (with excitation)
cw_on2: Forward rotation: Stop when the origin SW is on, operation when the origin SW is off
cw_off2・・・Forward operation: Operation when the origin SW is on, Stop when the origin SW is off
ccw_on2・・・Reverse operation: Stop when origin SW is ON, operation when origin SW is OFF
ccw_off2・・・Reverse rotation: Operation when origin SW is on, stop when origin SW is off
cw_btn・・・Normal operation: Operation when button is pressed, Stop when button is not pressed
ccw_btn・・・Reverse operation: Operation when button is pressed, stop when button is not pressed

The non-operation options are as follows.
sys_ck1・・・Origin SW off: Move to next line, Origin SW on: Move specified number of lines (SPEED value)
sys_ck2・・・Origin SW off: Move specified number of lines (SPEED value), Origin SW on: Move to next line
sys_ck3・・・Origin SW off: Move to next line, Origin SW on: Move specified number of lines (SPEED value)
sys_ck4・・・Origin SW off: Move specified number of lines (SPEED value), Origin SW on: Move to next line
roop_s: Loop start point: Loop count = SPEED value
roop_e...loop end point
link: Link command: The link destination is the motor operation table of the number indicated by the SPEED value.
err_cnt・・・Error counter +1
sys_err...No error command
sys_erc...There is an error command
nor_end・・・Normal end: No origin check
chk_end・・・Check completed: Origin check is performed, error if not origin

The motor operation table as shown in FIG. 21 defines operation patterns.
For example, the motor operation table 1 of FIG. 21A defines an operation pattern as an initial operation process. This operation pattern is as follows.
In sys_ck1 (system check 1) on the first line, it is checked whether or not it is within the origin.
If it is within the origin, the process moves to "7" line destination link (link command) specified by the speed (SPEED: number of lines in this case).
If it is outside the origin, the process moves to the next line, the second line. On the second line, it is moved toward the origin by ccw_on (reverse operation). Here, one step of driving is performed "8" times indicated by step (STEP) at 6 count intervals of the operation count (lcnt) (see FIG. 16C) by "6" designated by speed (SPEED). Since the operation count (lcnt) is updated every 1 ms, the operation of the second line is to drive the stepping motor to return to the origin for 8 steps at a speed of 1 step in 6 ms. Become.
Therefore, in the case of the operation system option, the time required to process one line is SPEED×STEP×1 ms.

Next, on the 3rd line, it is moved toward the origin by ccw_on (reverse operation). In the operation of the third row, the stepping motor is driven at a speed of 1 step in 3 ms, and the number of steps is twice the total number of steps. That is, the operation of returning to the origin is performed at a higher speed than the second line. Since ccw_on is stopped when the origin switch is turned on, the processing of the third line ends when the origin switch is turned on.

Since it should have returned to the origin by the processing of the second and third lines, sys_ck1 (system check 1) on the fourth line checks whether it is within the origin.
If it is within the origin, the process shifts to ccw_all (reverse operation) on the 6th line, which is the "2" line destination specified by the speed (SPEED: number of lines in this case).
If it is outside the origin, the process moves to the next line, which is line 5 (link command). In the link (link command) on the fifth line, the motor operation table 71 (FIG. 21B) is designated, so the retry operation of the motor operation table 71 is executed. When the retry operation of the motor operation table 71 is normally ended (nor_end), this means that the link (link command) on the fifth line has ended, and the process advances to the next sixth line.

In the sixth line, ccw_all (reverse rotation operation) is performed, and the stepping motor is driven to return to the origin by 58 steps at a speed (high speed) of 1 step in 3 ms.
Further, in the next seventh line, similarly, as ccw_all (reverse operation), the stepping motor is driven so as to return toward the origin for 8 steps at a speed (low speed) of 1 step in 6 ms.
The sixth and seventh lines are the pushing operation after confirming that they are within the origin, and the pushing operation is performed in two stages of high speed→low speed.

When the origin is confirmed on the 1st line, or after the 6th and 7th lines have been pushed in, proceed to the link (link command) on the 8th line and speed (SPEED: In this case, the link destination) ), the motor operation table 72 (FIG. 21C) is designated.
The motor operation table 72 defines an operation pattern as a reciprocating operation. When this is normally ended (nor_end), it means that the link (link command) on the 8th line of the motor operation table 1 is ended, and the next 9 lines Go to your eyes. The 9th line indicates nor_end (normal end), and the initial operation processing as the motor operation table 1 is ended here.

Although the initial operation processing as the motor operation table 1 has been described here, each motor operation table specifies the necessary operation for each line, as in this example, and the number of lines to skip and the link destination depending on the case. The operation pattern is defined as a structure in which the motor operation table number and the number of loops can be specified.
Although description is omitted, the motor operation tables of FIGS. 21B, 21C, and 21D, and many other motor operation tables not shown in the drawings are based on the option (OPT), speed (SPEED), and step (STEP) in each line. A motion is designated to specify a series of motion patterns.
FIG. 21B is a motor operation pattern for retry operation, FIG. 21C is a motor operation pattern for reciprocating operation, and FIG. 21D is a motor operation pattern for causing the accessory to "appear→swing 10 times→return". It is an example of a motor operation table showing the respective operation patterns.

Regarding motor control, such motor operation table defines fine motor operations. In steps S202 and S203 of FIG. 20, registration of the sub-scenario in the motor data registration information of FIG. 12C and control according to the motor operation table designated in this sub-scenario are executed.

The effect control CPU 200 sets, in the motor registration information (work), the number of the motor operation table described in the motor sub-scenario table for the motor data registration information shown in FIG. 12C, for example. That is, in the motor data registration information, the execution operation number (no) and the registration operation number (noNew) are set in the motor channel mCHn corresponding to the motor MT(n) that is currently the registration processing target.
In this case, the motor operation table number described in the motor sub-scenario table is written in the registration operation number (noNew). The execution operation number (no) is updated to the motor operation table number (operation pattern number) when it is actually executed, and "0" is set at this point.
As a result, the motor operation table number is registered in each motor channel mCH of the motor data registration information (work) according to the contents of the motor sub-scenario table.

After the motor operation table number is registered, the operation shown in each row of the motor operation table with that number is sequentially designated as the operation to be controlled.
For example, for each of the motors MT(n) (n=0 to 7) corresponding to the motor channels mCH0 to mCH7 of the motor data registration information, the following processing is roughly performed.
In the following description, the data described in the option (OPT) of the motor operation table is "D_OPT", the data described in speed (SPEED) is "D_SPEED", and the data described in step (STEP) is " Notated as "D_STEP".

First, the production control CPU 200 confirms whether or not the execution operation number (no) and the registration operation number (noNew) in the target motor channel mCHn match, and if they do not match, the operation is started and the motor channel mCHn is selected. The corresponding excitation output data is cleared, and the registered operation number (noNew) value is assigned to the execution operation number (no).
In addition, the production control CPU 200, the operation count (lcnt), operation line (ofset), execution step (step), loop start point (roopAddr), loop count (roopCnt), parent number (retNo), return address of the motor channel mCHn. (RetAddr) and error counter (errCnt) are set to 0 respectively. Also, the value of "5A" indicating the parent is set in the attribute (attribute) of the parent (migration source)/child (migration destination).
The above is the process when the control based on the registered motor operation table is started.

After that, the following processing is performed.
The effect control CPU 200 acquires the data of the motor operation table corresponding to the motor MT(n), the execution operation number (no), and the operation line (ofset).
That is, the data “D_OPT”, “D_SPEED”, and “D_STEP” in the row indicated by the operation line (ofset) in the motor operation table indicated by the execution operation number (no) are acquired. Since the operation line (ofset)=0 at first, the data “D_OPT”, “D_SPEED”, and “D_STEP” in the first row of the designated motor operation table are acquired. For example, if the execution operation number (no)=72, acquire “cw_off”, “6”, and “8” in the first row of the motor operation table 72 of FIG. 21C as “D_OPT”, “D_SPEED”, and “D_STEP”. become.

Then, the effect control CPU 200 confirms whether the data “D_OPT” is the data of the operating system option or the data of the non-operating system option.
If it is data of a non-operation option, the processing according to the non-operation option is performed. For example, the processing specified by the above “sys_ck1”, “roop_s”, or the like is performed.

If it is the data of the operation system option, a process involving drive control is performed. For example, the value of the operation count (lcnt) is compared with the value of “D_SPEED” to determine whether it is the update timing of the excitation output data.
In the case of the operation system option, the value of "D_SPEED" indicates the interval of one step drive of the stepping motor. If “D_SPEED”=6, 1 step drive is performed once every 6 times. The operation count (lcnt) is a value that is first incremented to "0" in step S1604 and then incremented, that is, incremented by 1 every 1 ms timer interrupt process.
Therefore, when the operation count (lcnt)=“D_SPEED”−1, the excitation output data update timing comes.

If it is not the update timing of the excitation output data, the operation count (lcnt) is incremented, the processing of the current motor channel mCHn is completed, and the processing of the next motor channel mCH is started.
At the update timing of the excitation output data, the effect control CPU 200 increments the execution step by 1 on the motor data registration information. The execution step (step) is a variable that counts whether or not the number of steps indicated by "D_STEP" acquired from the motor operation table has been reached. Then, the processing corresponding to the operation system option indicated by "D_OPT", for example, the processing for the operation indicated as "cw_all", "cw_on"... Is performed.

The above is the outline of the processing, but as the device scheduler execution processing of step S202 of FIG. 20, the motor data registration information is updated so as to indicate the contents to be sequentially executed as described above. That is, the content of the line (motion line) to be executed is specified every 1 ms in the motor motion table registered in the motor data registration information.
Then, in step S203, effect control CPU 200 controls the serial output controller 240 to generate motor drive data for each motor channel mCHn according to the contents of the designated row of the motor operation table.

In step S204 of FIG. 20, the effect control CPU 200 performs a key input process. That is, the signal corresponding to the operation of the effect buttons 11 and 12, the cross key 13 and the like is confirmed.
Note that, as shown in FIGS. 4 and 8, the detection information of the sensor 68s and the operation information of the effect buttons 11, 12 and the cross key 13 can be detected as serial input data. Therefore, the key input process may be confirmed at the same time as the detection information of the sensor 68s in step S201. Thereby, the detection process can be made efficient.

Although the processing example of the effect control CPU 200 has been described so far, in the above processing example, the effect control CPU 200 performs various kinds of processing in accordance with the frame of the display data.
FIG. 22 shows various timings for each frame period of display data.
Each frame of display data is set to a frame FR0, FR1, FR2,.... For example, the frame FR0 is displayed at time points T0 to T1, and the frame FR1 is displayed at time points T1 to T2.
Since the value of the V blank interrupt counter is cleared in step S150 of FIG. 16 (S172 of FIG. 17), as shown in the figure, it is “0” at the start of the frame and at the middle of the frame (time T0m, T1m, etc.). It becomes "1" and is cleared immediately after it becomes "2".

The drawing process by the drawing circuit 225 is executed for the display data of the next frame within the frame period. For example, the drawing of the display data of the frame FR1 is executed within the time period T0 to T1 which is the display period of the frame FR0. Specifically, since the drawing is started in step S150, the drawing for the next frame is started at the beginning of the frame. This drawing is normally completed within the frame period.
If the drawing started at time T0 is not completed at time T1, for example, the completion is waited at step S171 in FIG.

The preloading by the preloader 220 is executed in the period one frame before as a preparation for drawing. For example, the preload for drawing the display data of the frame FR2 is executed within the display period of the frame FR0 within the time points T0 to T1. Specifically, since it is started in step S103, preloading for the frame two frames ahead is started at the time of the beginning of the frame. Preloading is usually completed within the frame period.
If the preload started at time T0 is not completed at time T1, for example, the completion is waited at step S174 of FIG. Some delay in preloading will delay the start of drawing somewhat.

As the processing of the effect control CPU 200, steps S150, S151, S101, and S103 are performed at each frame start timing SLs. As the main processing, as shown in FIG. 22, switching of the frame buffers 209A and 209B, drawing start, display list creation, and preload start control are performed.
Here, during the frame period indicated by the arrow SL, the processes of repeating steps S121 to S143 are performed.
However, the reception command processing (S122 to S124) is executed only in the first half period of the frame indicated by the arrow CA. This is because these are executed only when the V blank interrupt counter=0.
The received command analysis process is the process shown in FIGS. 18 and 19, but this process has a relatively heavy processing load, and the number of processes increases depending on the number of received commands. Depending on the type of command, it may be necessary to perform lottery for production. In the present embodiment, such processing is performed only in the first half of the frame.
Therefore, for the command signal, for example, for the command signal received in the period indicated by the broken line as the time points T0m to T1m, the command analysis is performed in the period from the time points T1 to T1m.

The ramp data creation/output processing (S141 to S143) is also executed only during the first half period of the frame, which is indicated by arrow CA. This is because these are also executed only when the V blank interrupt counter=0.
This prevents the frame end processing (S150) from being delayed with respect to the frame end timing due to the creation and output of the lamp drive data.
It is assumed that the lamp drive data is not output from the serial output controller 240 because the lamp drive data is not output in the second half period of the frame in step S142. In that case, the LED driver 90 Since the last lamp drive data is maintained, the last light emitting operation is executed.

<7. Process of production control unit of second embodiment>
The processing of the effect control CPU 200 of the second embodiment is shown in FIG. This is an example in which the lamp drive data output control of step S142 of FIG. 16 is changed to be performed at the timing shown as step S144. That is, the lamp drive data is output regardless of the first half/second half of the frame.
However, since the lamp driving data in step S141 is not generated in the second half of the frame, the lamp driving data generated in the immediately preceding first half of the frame is repeatedly output in the second half of the frame.
The other processing of the second embodiment is the same as that described with reference to FIGS.

<8. Process of production control unit of third embodiment>
The processing of the effect control CPU 200 of the third embodiment is shown in FIG.
After the power is turned on, the effect control CPU 200 performs various initial settings in step S300, and then repeats the processing from step S301.

In step S302, the effect control CPU 200 initializes image processing-related. This initialization refers to initialization processing of various variables at the frame start timing.
In step S302, the effect control CPU 200 performs command analysis processing. For example, specifically, the process described in FIGS. 18 and 19.
In step S303, the effect control CPU 200 performs a scenario management process. This scenario management process refers to the process of steps S104 and S132 of FIG.
In step S304, the effect control CPU 200 performs drawing update processing. This is the control of the display list creation and the preload execution start in step S103 of FIG.

In step S305, the effect control CPU 200 performs sound management processing. This sound management process is similar to the process of step S133 of FIG.
In step S306, drawing completion waiting and preload completion waiting are performed. The waiting for the completion of drawing means waiting for the completion of the drawing of the display data of the next frame, which is started in step S312 immediately before. The waiting for completion of preload is waiting for completion of preload for drawing the frame two frames ahead, which was started in step S304 immediately before.

The effect control CPU 200 proceeds from step S307 to step S312 only when the power is turned on for the first time, and starts drawing the first frame. After that, the process proceeds from step S307 to S308.

At step S308, effect control CPU 200 branches the process depending on the value of the V blank interrupt counter. If the V blank interrupt counter is "0", the lamp drive data is created and output is controlled in step S149. That is, the lamp drive data actually output from the serial output controller 240 to the frame driver unit 61 and the board driver unit 62 is generated based on the information registered in each lamp channel dwCH of the lamp data registration information.
Then, the generated lamp driving data is transferred to the serial output controller 240 and controlled so as to be output as serial data.

When the V blank interrupt counter=1, step S309 is not performed. That is, the process of creating and outputting the lamp drive data in step S309 is performed only in the first half period of the frame in which V blank interrupt counter=0.

In step S310, it waits until V blank interrupt counter=2. When the V blank interrupt counter=2, the frame buffer is switched or the V blank interrupt counter is cleared in step S311, and the drawing start control is performed in step S312. Then, the process returns to step S301.

The above-described processing of FIG. 24 differs from the processing of FIG. 16 in the following points.
The command analysis process is performed once immediately after the start of the frame (S302).
-Sound management (S305) is performed immediately after scenario management.
As the scenario management, the scheduler frame update and the scenario scheduler execution process of FIG. 16 are performed once at a time.
After waiting for completion of drawing or preload (S306), lamp data creation/output (S309) is performed.
-Since it waits until the end of the frame period (S310), steps S301 to S312 are performed once in one frame period. Therefore, the sound data output (S305) and the lamp data creation/output (S309) are performed once per frame.

As described above, the processing is simpler than that in the first and second embodiments, and the processing load on the effect control CPU 200 is reduced.
It should be noted that the motor control is performed by an interrupt process, for example, every 1 ms as shown in FIG.

FIG. 25 shows various timings for each frame period according to the third embodiment. Note that the notation format is the same as in FIG.
The timing of the display frame, the value of the V blank interrupt counter, the drawing of the drawing circuit, and the preloading process of the preloader are the same as in FIG.

As the process of the effect control CPU 200, steps S311, S312, S301 to S310 are sequentially performed immediately after each frame start timing SLs and during the frame period indicated by the arrow SL. As the main processing, as shown in FIG. 22, switching of frame buffers 209A and 209B, drawing start, command analysis processing, scenario management, display list creation, preload start, sound management, lamp data creation/output control are sequentially performed. It is performed once within the frame period.

However, the ramp data creation/output is not executed unless it is started within the first half period of the frame indicated by the arrow CA.
This prevents the frame end processing (S311 and S312) from being delayed with respect to the frame end timing due to the creation and output of the lamp drive data.
Note that it is assumed that the lamp drive data is not output from the serial output controller 240 because the lamp drive data output in step S309 is not performed in the second half period of the frame. In that case, the LED driver 90 Since the lamp driving data of the immediately preceding frame is maintained, the immediately preceding light emitting operation is continuously executed.

In this case, the command analysis process (S302) is executed only once immediately after the frame starts. The analysis processing of the received command is a relatively heavy processing load as described above. In the present embodiment, this processing is performed once immediately after the start of the frame, so that the series of processing in FIG. 24 can be completed before the end of the frame period unless a special abnormality occurs. ..
Therefore, regarding the command signal, for example, for the command signal received during the period indicated by the broken line at time points T1 to T2, the command analysis is performed immediately after the time point T2.

<9. Summary and Modifications>
According to the pachinko gaming machine 1 of the above embodiment, the process for effect control can be made efficient, and proper effect control can be realized.
Further, the effect control processing load can be reduced.

Further, the pachinko gaming machine 1 of the embodiment includes a display unit (for example, the main liquid crystal display device 32M or the sub liquid crystal display device 32S) that displays an effect image, and a light emitting unit (for example, the lamp units 63 and 64) that performs a light emitting operation. At least, a control unit (for example, a production control unit 51) that controls the light emission of the light emitting unit is provided. Then, the control means performs the whole or a part of the processing for light emission control of the light emitting means on the frame front end side from the frame start timing until a predetermined time elapses within one frame period of the image displayed on the display means. The period starts during the period, and does not start during the frame end side period, which is the period after the passage of the predetermined time.
The frame end side period is a period from the start of the frame within the frame period to the timing at which the frame ends after a predetermined time has elapsed. For example, it is a second half period when one frame period is divided into a first half and a second half. In the present embodiment, all or part of the processing for light emission control is skipped during this frame end side period.
For example, in the case of the first embodiment, the lamp drive data creation and lamp drive data output processes of steps S141 and S142 of FIG. 16 are not started during the frame end side period.
In the case of the second embodiment, the lamp drive data creation process of step S141 of FIG. 23 is not started during the frame end side period.
In the case of the third embodiment, the lamp drive data creation and lamp drive data output processes of step S309 of FIG. 24 are not started during the frame end side period.
As a result, it is possible to prevent the control for various effects and the like performed together with the image display of the display means from being delayed in time for the next frame. Therefore, it is possible to provide a processing procedure that does not increase the processing load of the effect control unit 51 (especially the 1-chip microcomputer 250) when detecting the frame start timing and performing various effect controls according to the frame period.
Then, it is possible to avoid a delay in the effect control in accordance with the frame timing of the display image and realize an appropriate effect operation.
In particular, in the embodiment, the control unit (production control unit 51) also controls the display unit. In this case, by adjusting the process for the light emission effect to the display control (that is, the frame period), it is possible to improve the efficiency of the process and simplify the timing control and the register configuration for that, but in some cases, just before the end of the frame. There is a case where the processing such as the light emission effect performed in such a case does not end within the frame period, which may delay the processing. Therefore, such a situation can be eliminated by not performing the light emission control during the frame end side period.
It should be noted that the reason why all of the light emission effect is skipped in the second half period of the frame is that even if the LED light emission operation remains the immediately previous light emission operation in the period of 16.6 ms, there is no great influence. With respect to the control of the light emission effect, it is also meaningful to realize appropriate effect that the sound effect and the movable accessory effect are not skipped even in the latter half period of the frame. In other words, skipping all of the light emission effect in the latter half of the frame and not skipping the sound effect process of step S133 and the motor control (movable body accessory effect process) of steps S202 and S203 means that the effect effect is maintained and the frame is maintained. This is effective in that the delay in processing until the end timing can be eliminated.

In the first, second, and third embodiments, the light emission drive data creation process (S141, S309) is performed as part of the light emission control process that the effect control unit 51 does not start in the frame end side period. Including.
As control for light emission production, production scenario management, progress (update) of production content according to production scenario, acquisition of control data according to production content to be executed, generation of drive data for the control, drive data Output. At least the light emission drive data (lamp drive data) is not generated during the frame end side period.
By not generating the light emission drive data, the processing load in the second half of the frame is reduced, and it is possible to prevent the frame switching timing from being missed. As a result, it is possible to prevent the production control at the frame timing from being hindered.
It should be noted that the light emission drive data may be output, and in this case, lighting is performed by the drive data immediately before, but as described above, no problem occurs in actual operation.

In addition, in the first and third embodiments, the production control unit 51 includes a serial transmission process (S142, S309) of the light emission drive data as a part of the process for the light emission control which is not started in the frame end side period. That is, in the control for the light emission effect, at least the light emission drive data output, particularly the serial output, is not executed during the frame end side period.
The serial transmission output of the light emission drive data is a relatively time-consuming process, and if it is executed in the latter half of the frame, there is a high possibility that it will not be completed by the frame switching timing. Therefore, by not performing this in the period of the frame end side, it is possible to prevent that the next frame is not in time.

In the first, second, and third embodiments, the effect control unit 51 uses the V blank interrupt counter that counts based on the V blank signal that is the frame synchronization signal of the displayed image to start (end) the frame. ) The timing and the start timing of the frame end side period are detected (S120, S140). As a result, timing management can be facilitated.

As a modified example of the first and second embodiments, step S134 may be performed only when V blank interrupt counter=0 in step S140. In other words, the scenario update (update of lamp data registration information) is not performed in the latter half of the frame. That is, all the processing for light emission control (S134, S141, S142) is not performed in the second half period of the frame. It should be noted that "all" means all the processes related only to the lamp control.
By doing so, the effect of reducing the processing load in the latter half of the frame can be more exerted. In particular, in the case of the embodiment, the timer of the scenario is advanced as the scenario scheduler frame update in step S104. That is, the scenario always advances by one timing for each frame. Therefore, the progress of the lamp production scenario is ensured, and even if step S134 is not executed, the progress of the scenario is not delayed and appropriate production cannot be performed.
Even during the period in which steps S134, S141, and S142 are not performed, the LED driver 90 is driving the LED 120 based on the immediately preceding light emission drive data, so that the player does not feel a strange light emission state.
Of course, in the first and second embodiments as well, the scenario timer advancement is performed in step S104, so that the scenario inevitably advances by one timing every frame, and the progression of the lamp effect scenario is ensured. Therefore, the scenario will not be delayed.

The pachinko gaming machine 1 of the embodiment is provided with a plurality of effect means including display means (main liquid crystal display device 32M and sub liquid crystal display device 32S) for displaying effect images. That is, there are also rendering means such as the lamp parts 63 and 64, a movable body accessory, and a sound output system. The control unit (production control unit 51) detects the frame start timing of the image displayed by the display unit, and the received command analysis process (S123) takes a predetermined time from the frame start timing within one frame period. It is set to start only in the frame front end side period until the time elapses.
The frame front end side period is a period within a frame period from the frame start time until a predetermined time elapses. For example, it is the first half period when one frame period is divided into the first half and the second half.
For the received command, analysis processing is performed, and the effect content is determined by the analysis result, but the analysis processing of this command starts only in the frame front end side period, and after a predetermined time has elapsed from the frame start, , The analysis process is not started.
As a result, it is possible to prevent the control for various effects and the like performed together with the image display of the display means from being delayed in time for the next frame. The analysis process is a relatively heavy process, such as grasping the content of the received command and corresponding processing according to the content of the command. Therefore, this command analysis is started only during the frame front end side period in time for the next frame start timing.
Therefore, it is possible to provide a processing procedure that does not increase the processing load when the frame start timing is detected and various effect controls are performed in frame synchronization.
In particular, when the effect control unit 51 also controls the display means, the process for light emission effect is subjected to display control, that is, frame synchronization, so that the efficiency of the process can be improved and the timing control and the register configuration therefor can be simplified. However, the received command analysis process may not be completed within the frame period, which may delay the process. Therefore, by limiting the period for starting the command analysis process to the period on the front end side of the frame, it is possible to avoid a situation in which the process is delayed.

In addition, in the first and second embodiments, the effect control unit 51 uses the V blank interrupt counter that counts based on the V blank signal that is the frame synchronization signal of the image displayed on the display unit to set the frame start timing. And the end timing of the frame front end side period is detected (S121). As a result, timing management can be facilitated.

In addition, in the third embodiment, the control unit (effect control unit 51) detects the frame start timing of the image displayed by the display unit, and the received command analysis process is performed within one frame period. It is executed once in response to the detection of the start timing (S302).
As a result, the command analysis process is started immediately after the start timing of the frame. Since the command analysis process is performed only once, the start of the command analysis process does not normally occur in the latter half of the frame period. Therefore, it is possible to prevent the processing from being delayed in time for the frame end timing due to the heavy command analysis processing.

Further, as will be understood from the above, in the processing and modified examples of FIGS. 16 and 23 of the first and second embodiments, the received command analysis processing (S123) is started in the frame end side period. If not, all or part of the process for controlling light emission is not started.
As a result, it is possible to further reduce the processing amount of the effect control unit 51 in the frame rear end side period and prevent the control for various effects and the like performed together with the image display of the display unit from being delayed in time for the next frame. Can be increased.

Further, the pachinko gaming machine 1 of the embodiment includes a plurality of effect means including a display means for displaying effect images, a movable body driven by a motor, and a light emitting means. Moreover, the control means (production control part 51 or production control CPU200) which controls operation|movement of the production means according to the received command is provided.
The effect control CPU 200 executes the drive control regarding the light emitting means as one of the first processes performed according to the frame timing of the display data displayed on the display means. The process performed according to the frame timing is a process of performing a process corresponding to the frame period, such as a process of monitoring the frame timing and defining various process timings. That is, the first process in the embodiment is the main process of FIG. 16 whose execution timing is defined by the frame timing.
On the other hand, the drive control of the motor for the movable body is executed as one of the second processes executed at a predetermined interval shorter than the frame period regardless of the frame timing. The second process is the timer interrupt process of FIG.
As a result, the light emission effect can be realized in accordance with the frame of the display data, while the motor control of the movable body accessory is controlled at a shorter time interval regardless of the frame timing, thereby enabling a fine accessory operation. Becomes
Since the lamp control (and the sound control) is output for each frame timing, the processing load does not become excessive. On the other hand, by performing the motor processing in a cycle shorter than the frame timing, it is possible to avoid delaying the motor operation.

Further, in the embodiment, a display control unit (a functional part as VDP) for controlling the display unit based on a drawing instruction from the control unit (production control CPU 200) is provided. The frame timing is a timing based on the frame synchronization signal output from the display control means.
By confirming the frame timing based on the frame synchronization signal, timing control becomes easy.

The effect control unit 51 also executes the detection of the information of the origin switch of the motor as one of the second processes in step S201 of FIG. That is, the detection of the origin switch information is combined with the motor drive control so that the motor control of the movable body accessory can be appropriately executed. In this case, the origin sensing is also performed at the same 1 ms period as the device scheduler execution process of step S202, whereby the control of the movable body accessory operation (the progress of the scenario, etc.) can be facilitated.

The effect control unit 51 also executes the detection of operation information of the user operation means for effect as one of the second processes in step S204 of FIG. Thereby, the operation of detecting the operation information can be performed finely.
As described above, the 1-chip microcomputer 250 can collectively detect the user operation information and the origin sensing as an input from the parallel/serial conversion unit 260 in FIG. Therefore, by performing the process of step S204 and the process of step S201 at the same time, more efficient external information detection can be performed.

Further, in the first and second embodiments, the control unit (effect control unit 51), for the plurality of frame buffers 209A and 209B, the first area for reading the display data of the image displayed on the display unit, The allocation as the second area for drawing the display data of the frame is sequentially switched. At this time, in the embodiment, at the end of one frame period of the image displayed by the display means (S150), the drawing of the display data of the image of the next frame in the frame buffer area which is the second area is completed. Is confirmed (step S171 in FIG. 17), after the completion of drawing is confirmed, the first area and the second area are switched (S173), and drawing using the frame buffer area switched to the second area is started (S175). ).
By thus confirming the completion of drawing and switching the frame buffer area of the VRAM 209, the influence on the display image can be minimized. That is, the display data transferred to the display circuit 221 or the like becomes the display data in which the drawing has been completed correctly, and if the drawing is not completed by the second time point of the vertical synchronizing signal, the display data in the frame buffer being drawn is displayed. It doesn't happen.
Then, it is possible to realize an image display effect based on appropriate display data output even in a situation where the processing load is relatively high, in which a plurality of effect means including a display means for displaying effect images are controlled.

Further, in the first and second embodiments, the control means (effect control unit 51) allocates the plurality of frame buffers 209A and 209B as the first area and the second area in accordance with the end of one frame period. At the same time as switching (S173), it is confirmed whether a predetermined storage area (D-RAM 202a or VRAM 209) for the image data material for drawing stored in the CG-ROM 206 has been preloaded (S174). After the completion is confirmed, drawing is started using the frame buffer area which is set as the second area by switching (S175).
As described above, since the reference destination of the image data (CG data as an image material) in the display list is not the CG-ROM 206 but the preload area set in the D-RAM 202a or the VRAM 209, drawing by the drawing circuit 225 is performed. Random access to image data that occurs during execution can be speeded up, and drawing processing can be performed even for high-resolution moving images that move rapidly. In other words, by starting the drawing after confirming the completion of preloading, it is possible to maintain the state in which the drawing with such superiority can be surely executed. Therefore, the drawing process using the preloaded image material is appropriately executed. In particular, it is effective to perform drawing after waiting for the completion of preloading as the processing of the one-chip microcomputer 250 in which the processing load tends to increase.

The gaming machine according to the embodiment has a first effect means which is a display means (main liquid crystal display device 32M or sub liquid crystal display device 32S) for displaying effect images, and a movable body role driven by the movable body role product motor 65. It is provided with a second effect means, which is an object, and a third effect means. The third effect means is a sound output system (amplifier 67, speaker 25) and lamps 63, 64.
In the first and second embodiments, the control means (effect control unit 51) controls the third effect means (S133 in FIGS. 16 and 23) by the frame cycle of the display data displayed by the display means. Running. That is, basically, it is performed once per frame.
On the other hand, the drive control of the movable body accessory motor 65 related to the movable body of the second effect means is executed at 1 ms intervals shorter than the frame period regardless of the frame timing (S202 and S203 in FIG. 20).
As a result, the control of the third effect means can be realized in accordance with the frame of the display data, while the movable body accessory motor can be controlled more finely.
For example, in sound control, the processing load does not become excessive by outputting at each frame timing. On the other hand, by performing the motor processing in a cycle shorter than the frame timing, it is possible to avoid delaying the motor operation. Therefore, fine movement of the movable body accessory becomes possible.

Further, when the received command is acquired, the effect control unit 51 further executes the control regarding the third effect means regardless of the frame cycle. That is, when there is a received command in FIGS. 16 and 23, the scheduler update flag is turned off in step S124, and steps S132, S133, and S134 are performed.
As a result, an effect corresponding to the command acquisition can be quickly executed.

In the first and second embodiments, the scenario is not updated (frame update flag is OFF) at the timing when the display frame of the image is detected, which is detected by the display synchronization signal (V blank signal or the like) (S151). In response to this unupdated state, at least the timer is updated in the scenario (S102→S103→S104).
Therefore, in the process of the effect control CPU 200, the scenario progress management can be performed at the optimum timing in relation to the timing of the frame of the display data.

In the first and second embodiments, scenario scheduler frame update/unupdate is managed by the first information (frame update flag), and scenario update (scheduler execution) execution/non-execution is performed by the second information (scheduler). It is managed by the update flag) (S105, S106, S130, S151).
Then, the frame update flag is turned off (not updated) based on the frame synchronization signal (V blank signal). The scheduler update flag is turned off (not executed) in response to the scheduler frame update, and then the state is confirmed in accordance with the frame synchronization signal. If it is OFF (not executed), the scenario update is executed.
As a result, the progress of the scenario timer and the scenario update are managed so that they are performed at different timings, and the execution once in each frame can be managed by a simple process.

Further, in the first and second embodiments, the scenario update information (scheduler update flag) is turned ON (S131) together with the scenario update execution (S132). After being turned on, the scenario update (S131 to S134) is not performed even during the frame period (regardless of the value of the V blank interrupt counter). It is at the beginning timing of the period of the next frame that the scheduler update flag is turned off (S106).
However, when a command is received, the command is immediately turned off (S124) to execute the scenario update.
According to such a process, the main process of the effect control CPU 200 can appropriately update the scenario once per frame without unnecessarily updating the scenario, and easily synchronize the display and other effects. it can.
On the other hand, by immediately executing the scenario update according to the command analysis, it is possible to quickly respond to the command regardless of the progress of the display frame.

Although the embodiments have been described above, the present invention is not limited to the examples given in the embodiments, and various modifications and applications can be considered.
Although an example in which the timing is managed based on the V blank signal as the signal synchronized with the frame of the display data has been given, a vertical synchronization signal other than the V blank signal is used, or timing management within the frame period is performed by counting the horizontal synchronization signal. May go. For example, it is conceivable to use a vertical synchronization signal or a horizontal synchronization signal for the timing management as the frame front end side period and the frame rear end side period described above.
Also, the frame front end side period is not necessarily the period of 16.6 ms in the first half of the frame. It may be a period from the frame start timing to a certain point in the middle of the frame period.
Similarly, the frame rear end side period is not always the period of 16.6 ms in the latter half of the frame. It may be a period from a certain point in the middle of the frame to the end of the frame.

Further, although the present invention shows an example applied to a ball game machine such as the pachinko game machine 1, it can also be applied to a rotating drum type game machine (so-called slot machine).

1 Pachinko gaming machine 20w, 20b Light emitting unit 32M Main liquid crystal display device 32S Sub liquid crystal display device 50 Main control board (main control unit)
51 Production control board (production control unit)
61 frame driver section 62 board driver section 63, 64 light emitting section 65 movable body accessory motor 90 LED driver 200 production control CPU
201 Production control ROM
202 Control RAM
250 microcomputer

Claims (1)

Display means for displaying effect images,
A light emitting means for performing a light emitting operation,
At least control means for controlling the light emission of the light emitting means,
Equipped with
The control means is
The analysis process of the received command can be executed a plurality of times within one frame period of the image displayed on the display unit, and the analysis process is performed within one frame period of the image displayed on the display unit. A gaming machine that starts only in a frame front end side period from when the frame starts to when a predetermined time elapses .

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