JP7090494B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to the structure of a semiconductor device, and particularly relates to a technique effective for being applied to a mounting structure of an inverter IC chip in which a high voltage circuit and a low voltage circuit are mixedly mounted.

In response to global energy saving regulations, the adoption of inverter ICs in home appliances such as air conditioners, air purifiers, and water heaters is rapidly expanding, and inverter ICs are becoming smaller and have higher heat dissipation (lower heat resistance). Development of inverter IC mounting technology (package technology) that meets various demands such as high efficiency (low loss), high reliability (high insulation and long life), and low cost is underway.

As a technique for miniaturizing an inverter IC, a one-chip inverter IC in which various components and circuits required for inverter control are integrated on one semiconductor chip (one chip) is known.

As a background technique in this technical field, for example, there is a technique such as Patent Document 1. Patent Document 1 states that "the distance between the semiconductor chip and the output terminal is equal to or greater than the distance between the input terminal and the semiconductor chip, and the region between the semiconductor chip and the output terminal on the mounting board (die pad) is a circuit component. "Semiconductor devices, which are areas that are not mounted," are disclosed.

Further, Patent Document 2 states that "a first chip for reducing (stepping down) a high voltage signal and a second chip for signal processing are separated, and lead terminals to which a high voltage is directly applied are mutually and other. A semiconductor device that is arranged away from lead terminals and hanging leads of die pads and is filled with a resin layer between the lead terminals to prevent discharge is disclosed.

Further, in Patent Document 3, "a laminate in which a diode chip, an inverter IC chip, and a substrate are laminated is sealed and integrated, and a diode chip is laminated on a control circuit portion on one surface of the inverter IC chip. A semiconductor device in which the other surface of the inverter IC chip is located on the external side "is disclosed.

Japanese Unexamined Patent Publication No. 2014-120582 Japanese Unexamined Patent Publication No. 2016-136608 Japanese Unexamined Patent Publication No. 2016-100502

By the way, the die pad exposed type QFN (Quad Flat Non-lead) structure is effective for miniaturization, cost reduction, and high heat dissipation of the semiconductor package, but it is applied to high voltage applications such as one-chip inverter ICs. In order to secure insulation, it is necessary to secure a certain distance between the high voltage terminal and the die pad (GND) and between the low voltage terminal.

Further, in the conventional QFN structure, since the terminal is small, the electric resistance becomes large and it is difficult to improve the efficiency, and since it is non-lead, there is a concern that the connection reliability with the mounting board may be lowered.

In Patent Document 1, when the potential difference between the input terminal and the die pad or between the output terminal and the die pad is large, discharge may occur if the creepage distance when exposed on the front surface or the back surface of the semiconductor device is short, and the voltage is high. Not suitable for power supply applications. In particular, when the semiconductor device is mounted in a small motor, it is necessary to reduce the outer shape of the device, which makes it more difficult to secure the creepage distance, which is disadvantageous in terms of miniaturization.

Further, since the semiconductor chip on which the output circuit (HEMT) is formed and the matching circuit component which is the auxiliary circuit are independent structures, for example, a one-chip inverter IC in which the output circuit and the control circuit are integrally formed, etc. It cannot be said that the structure is appropriate for a semiconductor device.

In Patent Document 2, since the die pad is not exposed from the resin layer, it is disadvantageous in terms of heat dissipation for power supply applications in which a large current flows, and at the same time, the efficiency may decrease due to an increase in electrical resistance. ..

Further, when mounting a semiconductor device on a plastic mounting substrate, if only the lead terminals are connected, there is a concern that repeated heat loads will be applied to the solder or the like as the joining material and the semiconductor device will be broken at an early stage due to thermal fatigue.

Further, the lead terminal is provided so as to protrude from the surface of the device, and there is a limit to reducing the outer shape of the device.

In Patent Document 3, since the diode chip is laminated on the inverter IC chip, a heat dissipation member having heat dissipation fins is required for heat dissipation of the inverter IC chip, and heat dissipation is ensured for power supply applications in which a large current flows. In addition to increasing the cost of members for this purpose, it is a major factor that hinders the miniaturization of equipment that is important for mounting in a small motor.

Therefore, an object of the present invention is a semiconductor device having an inverter IC chip in which a high-voltage circuit and a low-voltage circuit are mounted, which can be miniaturized while ensuring the insulation inside the semiconductor device. The purpose is to provide a manufacturing method.

Further, another object of the present invention is to reduce the loss in the high voltage circuit and to mount the components on the mounting board in the semiconductor device equipped with the inverter IC chip in which the high voltage circuit and the low voltage circuit are mounted. It is an object of the present invention to provide a semiconductor device capable of improving the performance and a method for manufacturing the same.

In order to solve the above problems, the present invention comprises an inverter IC chip in which an output circuit and a control circuit are formed on the front surface of a semiconductor substrate, a die pad bonded to the back surface of the semiconductor substrate via a bonding material, and the die pad. A first lead arranged along at least one side of the die and electrically connected to the control circuit by a first bonding wire, and an output along the other side of the die pad. A second lead electrically connected to the circuit, the inverter IC chip, a sealing resin covering the surface of the first lead and the second lead, and the semiconductor substrate of the die pad. A surface opposite to the bonding surface of the first lead, a surface opposite to the surface of the first lead connected to the first bonding wire, and a surface of the second lead connecting the second lead to the second bonding wire. Each of the opposite surfaces is exposed from the sealing resin, and the end edge of the first lead and the end edge of the second lead are flush with the end edge of the sealing resin. As described above, the first lead and the second lead are formed so as to be separated from each other with a predetermined distance, and the first lead has the die pad. It has a lead arranged along the side opposite to the other side and a lead arranged along the side intersecting with the other side, and is arranged along the side intersecting with the other side. The distance between the lead and the second lead is longer than the distance between the die pad and the first lead .

Further, the present invention comprises (a) a step of forming an output circuit and a control circuit on the front surface of a semiconductor substrate, (b) a step of joining a die pad to the back surface of the semiconductor substrate with a bonding material after the step (a). (C) The lead frame having a plurality of first leads and a plurality of second leads formed apart from the first leads at a predetermined distance after the step (b). A step of arranging a plurality of die pads, (d) a step of electrically connecting the control circuit and the first lead, and the output circuit and the second lead by wire bonding after the step (d). (E) After the step (d), a step of arranging the lead frame in which the plurality of die pads are arranged in the cavity of the mold, filling the cavity with the molten sealing resin, and curing the process (f). ) Manufacture of a semiconductor device including a step of cutting and molding the sealing resin and the lead frame to separate the semiconductor substrate and the die pad sealed with the sealing resin after the step (e). In the method, the first lead is a lead arranged on a side opposite to the second lead with the die pad interposed therebetween, and a lead arranged in a direction intersecting the arrangement direction of the second lead. The distance between the lead arranged in the direction intersecting the arrangement direction of the second lead and the second lead is longer than the distance between the die pad and the first lead. And.

According to the present invention, in a semiconductor device equipped with an inverter IC chip in which a high-voltage circuit and a low-voltage circuit are mounted together, the semiconductor device and its manufacturing method can be miniaturized while ensuring the insulation inside the semiconductor device. Can be realized.

Further, in a semiconductor device equipped with an inverter IC chip in which a high-voltage circuit and a low-voltage circuit are mounted together, the semiconductor device can reduce the loss in the high-voltage circuit and improve the mounting reliability of each component on the mounting board. And its manufacturing method can be realized.

As a result, for example, it is possible to increase the withstand voltage, increase the reliability, reduce the size, reduce the cost, increase the heat dissipation, and increase the efficiency of the inverter IC chip mounted in the small motor of the home electric appliance.

Issues, configurations and effects other than those described above will be clarified by the description of the following embodiments.

It is a schematic plan view of the semiconductor device which concerns on 1st Embodiment of this invention. FIG. 1 is a cross-sectional view taken along the line AA'in FIG. It is an external view of the semiconductor device shown in FIG. 1. It is a schematic plan view of the semiconductor device which concerns on 2nd Embodiment of this invention. It is an external view of the semiconductor device shown in FIG. It is a schematic plan view of the semiconductor device which concerns on 3rd Embodiment of this invention. It is an external view of the semiconductor device shown in FIG. It is a schematic plan view of the semiconductor device which concerns on 4th Embodiment of this invention. It is an external view of the semiconductor device shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, the parts that are the same or equal to each other are indicated by the same reference numerals in the drawings for the sake of simplification of the description.

The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a schematic plan view schematically showing the plan structure of the semiconductor device 100 according to the present embodiment. FIG. 2 is a cross-sectional view taken along the line AA'in FIG. FIG. 3 is a schematic planar external view schematically showing the planar appearance of the semiconductor device 100 shown in FIG.

The semiconductor device 100 of this embodiment is used as a semiconductor device for driving a small fan motor (three-phase DC motor) mounted on an indoor / outdoor unit of a household air conditioner, for example.

In the semiconductor device 100 of this embodiment, as shown in FIGS. 1 to 3, the output circuit 1a which is a high voltage circuit and the control circuit 1b which is a low voltage circuit are integrally integrated and formed on the surface side of a common semiconductor substrate. The inverter IC chip 1 is connected to the die pad 2 connected to one surface (lower surface) of the inverter IC chip 1 via a bonding material 7, and a plurality of first elements arranged in at least one portion around the die pad 2. It includes a lead 3 and a plurality of second leads 4 to which a higher voltage is applied than the first lead 3.

Further, as shown in FIG. 3, the back surface side of the die pad 2, the first lead 3, and the second lead 4 is exposed to the outside of the semiconductor device 100, and as shown in FIG. 2, the inverter IC chip. The surface side of the first lead 3, the first lead 3 and the second lead 4 is coated with the sealing resin 6. The semiconductor device 100 of this embodiment includes a package in which the ends of the first lead 3 and the second lead 4 are flush with the sealing resin 6, and the distance between the die pad 2 and the second lead 4 is provided. The die pad 2, the first lead 3 and the second lead 4 are arranged in a positional relationship (D1> D5) such that D1 is larger (longer) than the distance D5 between the die pad 2 and the first lead 3. There is.

That is, in the semiconductor device 100 of this embodiment, the inverter IC chip 1 in which the output circuit (high voltage circuit) 1a and the control circuit (low voltage circuit) 1b are formed on the surface of the semiconductor substrate and the bonding material on the back surface of the semiconductor substrate. A die pad 2 joined via 7 and a first lead 3 arranged along at least one side of the die pad 2 and electrically connected to a control circuit (low voltage circuit) 1b by a bonding wire 5 and a die pad 2. A second lead 4 arranged along the other side and electrically connected to the output circuit (high voltage circuit) 1a by a bonding wire 5, an inverter IC chip 1, a first lead 3, and a second lead. The sealing resin 6 for covering the surface of 4 is provided.

Further, the surface of the die pad 2 opposite to the bonding surface with the semiconductor substrate, the surface of the first lead 3 opposite to the connection surface with the bonding wire 5, and the connection of the second lead 4 with the bonding wire 5. Each of the surfaces opposite to the surface is exposed from the sealing resin 6, and the end edge of the first lead 3 and the end edge of the second lead 4 are flush with the end edge of the encapsulating resin 6. Further, the first lead 3 and the second lead 4 are formed so as to be separated from each other with a predetermined (constant) distance. Thereby, the insulating property between the first lead 3 and the second lead 4 can be ensured.

Further, the distance between the first lead 3 and the second lead 4 is such that the distance D1 between the die pad 2 and the second lead 4 is larger (longer) than the distance D5 between the die pad 2 and the first lead 3. The die pad 2, the first lead 3, and the second lead 4 are arranged in such a positional relationship (D1> D5). As a result, the discharge risk between the output circuit 1a (high voltage circuit) and the die pad 2 and the control circuit 1b (low voltage circuit) and the die pad 2 can be equally and minimized.

Here, the output circuit 1a provided in the inverter IC chip 1 is an IGBT formed on a semiconductor substrate made of, for example, silicon (Si), silicon carbide (SiC), silicon nitride (SiN), gallium arsenic (GaAs), or the like. (Insulated Gate Bipolar Transistor), power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), cylister, and other semiconductor devices that control large currents on and off.

Further, the control circuit 1b is a semiconductor element that does not include a semiconductor element that controls on / off of a large current. That is, the control circuit 1b is a semiconductor element in which a large number of ordinary logic circuits, driver circuits, analog circuits, etc. are formed, and a microprocessor or the like is formed as needed, and controls a large current flowing in the output circuit 1a. It can also have a function to do. That is, for example, if the output circuit 1a is a power MOSFET, the gate voltage is controlled. Therefore, the inverter IC chip 1 is provided with both an output circuit 1a portion and a control circuit 1b portion.

However, it is not necessarily limited to the inverter IC chip 1 in which the output circuit 1a portion and the control circuit 1b portion are integrated. Further, for stable power output of the output circuit 1a and stable operation of the control circuit 1b, the other surface on which the output circuit 1a and the control circuit 1b of the inverter IC chip 1 are formed is GND (grounded). It is desirable to use a potential.

In the inverter IC chip 1, a surface different from the surface on which the output circuit 1a and the control circuit 1b are formed (opposite side) is connected to the die pad 2 by a joining material 7. The joining material 7 is made of, for example, a metal containing solder, silver (Ag) or copper (Cu), a conductive adhesive, or the like, and is electrically and mechanically connected.

As the solder constituting the bonding material 7, general eutectic solder, lead-free solder and the like are used, and as the conductive adhesive material, silver (Ag), copper (Cu) and nickel (Ni) are used. A metal filler such as that contained in a resin or composed only of metal is used.

Further, in order to efficiently dissipate the heat generated by the inverter IC chip 1 from the semiconductor device 100 to the outside, the die pad 2 is made of a material having good thermal conductivity, such as copper (Cu), aluminum (Al), or 42 Alloy (iron-nickel alloy). ) Etc.

The output circuit 1a of the inverter IC chip 1 is electrically connected to a plurality of second reeds 4 serving as external terminals of the semiconductor device 100 by bonding wires 5. On the other hand, the control circuit 1b is also electrically connected to the plurality of first leads 3 by the bonding wire 5. The bonding wire 5 is made of, for example, gold (Au), copper (Cu), silver (Ag), aluminum (Al), or the like having low electrical resistance.

The sealing resin 6 for coating the semiconductor device 100 is made of a general molding material such as an epoxy resin, a biphenyl resin and an unsaturated polyester, and is formed by, for example, a transfer molding method using a mold. When this transfer mold method is used, mass production is possible, so that the cost can be significantly reduced.

Further, for example, by adopting a MAP (Molded Array Process) method in which a plurality of semiconductor devices 100 are molded in one mold cavity and then cut and molded into individual pieces, it is further advantageous in terms of mass production and cost. Will be. In particular, by adopting a non-lead structure of, for example, QFN (Quad Flat Package) in which the ends of the first lead 3 and the second lead 4 are flush with the sealing resin 6, it is mounted in a small motor. Therefore, the outer shape of the semiconductor device 100 required for this purpose can be reduced as much as possible.

Further, in order to dissipate the heat generated by the inverter IC chip 1 from the semiconductor device 100 to the outside, it is possible to efficiently dissipate heat by exposing a part of the die pad 2 to the outer surface of the device. Further, the die pad 2 is firmly fixed by connecting to the mounting board with solder or the like, and early breakage from thermal fatigue can be prevented. In addition, in order to produce by the MAP method using the transfer mold method, it is possible to provide the hanging lead 2a on the die pad 2 to improve the productivity.

The semiconductor device 100 of this embodiment shown in FIGS. 1 to 3 can be formed by using, for example, a manufacturing method including the following process flow.

First, an output circuit (high voltage circuit) 1a and a control circuit (low voltage circuit) 1b are formed on the surface of the semiconductor substrate.

Next, the die pad 2 is joined to the back surface of the semiconductor substrate with the joining material 7.

Subsequently, a plurality of die pads 2 are arranged on a lead frame having a plurality of second leads 4 formed at a predetermined distance from the plurality of first leads 3 and the first leads 3.

Next, the control circuit (low voltage circuit) 1b and the first lead 3 and the output circuit (high voltage circuit) 1a and the second lead 4 are electrically connected by wire bonding, respectively.

Subsequently, a lead frame in which a plurality of die pads 2 are arranged is arranged in the cavity of the mold, and the molten sealing resin 6 is filled and cured in the cavity.

Finally, the sealing resin 6 and the lead frame are cut and molded to separate the semiconductor substrate and the die pad 2 sealed by the sealing resin 6.

Here, the voltage applied to the output circuit 1a of the inverter IC chip 1 is as high as several tens V to several hundred V if it is for driving a fan motor mounted on an indoor / outdoor unit of a general household air conditioner, for example. It is a voltage. Further, the voltage applied to the control circuit 1b is a low voltage of several V to ten and several V.

Further, for stable power output of the output circuit 1a and stable operation of the control circuit 1b, the other surface (for example, the back surface) on which the output circuit 1a and the control circuit 1b of the inverter IC chip 1 are formed is It is desirable to use the GND potential.

Therefore, the first lead 3 connected to the control circuit 1b of the inverter IC chip 1 by the bonding wire 5, the second lead 4 connected to the output circuit 1a by the bonding wire 5, and the back surface of the inverter IC chip 1 are connected. When a large potential difference is generated between the die pads 2 and the die pads 2, the first lead 3 and the second lead 4 are exposed on the outer surface of the semiconductor device 100, a certain creepage surface is used to reduce the discharge risk. Distance is needed.

That is, in the distance D1 between the high voltage second lead 4 and the die pad 2 and the distance D5 between the low voltage first lead 3 and the die pad 2, when the outer shape of the semiconductor device 100 is made as small as possible, GND is used. It is necessary to appropriately secure each creepage distance according to the potential difference of. That is, when the insulation distance is D and the potential difference between them is Ve, the dielectric breakdown amount K generally has the following relationship.

Therefore, when the potential difference of the distance D1 between the die pad 2 and the second reed 4 in the semiconductor device 100 is Ve1 and the potential difference of the distance D5 between the die pad 2 and the first reed 3 is Ve5, D1 and D5 are intended. In order to prevent the risk of discharge that does not occur equally and to the minimum, from the equation (1), Ve1 / D1 = Ve5 / D5. That is, D1 = (Ve5 / Ve1) D5. Here, since Ve5 <Ve1, therefore, D5 <D1.

As described above, in the semiconductor device 100 according to the present embodiment, the distance between the second lead 4 to which the output circuit 1a having a higher voltage than the control circuit 1b of the inverter IC chip 1 is connected and the die pad 2 which is the GND potential. By making D1 larger (longer) than the distance D5 between the first lead 3 to which the control circuit 1b is connected and the die pad 2 which is the GND potential, the output circuit 1a (high voltage circuit) -the die pad 2 and the control circuit The discharge risk between 1b (low voltage circuit) and the die pad 2 can be equally and minimized, and high withstand voltage can be realized.

In addition, since the die pad 2 is exposed on the surface of the semiconductor device 100, the heat generated by the inverter IC chip 1 is efficiently dissipated to achieve high heat dissipation, and the die pad 2 is firmly connected to the mounting board, resulting in high reliability. realizable.

Further, by adopting a non-lead structure in which the ends of the first lead 3 and the second lead 4 are flush with the sealing resin 6, miniaturization and cost reduction can be realized. That is, the semiconductor device 100 according to the present embodiment can simultaneously realize high withstand voltage, high heat dissipation, high reliability, miniaturization, and low cost of the semiconductor device 100.

A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. 4 is a schematic plan view schematically showing the plan structure of the semiconductor device 100 according to the present embodiment. FIG. 5 is a schematic planar external view schematically showing the planar appearance of the semiconductor device 100 shown in FIG. Hereinafter, matters different from those of the first embodiment will be mainly described.

In the semiconductor device 100 of this embodiment, as shown in FIGS. 4 and 5, the output circuit 1a which is a high voltage circuit and the control circuit 1b which is a low voltage circuit are integrally integrated and formed on the surface side of a common semiconductor substrate. The inverter IC chip 1 is connected to the die pad 2 connected to one surface (lower surface) of the inverter IC chip 1 via a bonding material 7 (not shown), and a plurality of thirds arranged in at least one portion around the die pad 2. It includes a lead 3 of 1 and a plurality of second leads 4 to which a higher voltage is applied than the first lead 3.

Further, as shown in FIG. 5, the back surface sides of the die pad 2, the first lead 3, and the second lead 4 are exposed to the outside of the semiconductor device 100, and the same as in FIG. 2 of the first embodiment. The surface side of the inverter IC chip 1, the first lead 3, and the second lead 4 is coated with the sealing resin 6. The semiconductor device 100 of this embodiment includes a package in which the ends of the first lead 3 and the second lead 4 are flush with the sealing resin 6, and the distance D2 between the second leads 4 is set. The die pad 2, the first lead 3, and the second lead 4 are arranged in a positional relationship (D2> D5) such that the distance between the die pad 2 and the first lead 3 is larger (longer) than the distance D5.

That is, the semiconductor device 100 of this embodiment includes a plurality of second reeds 4, and is arranged so that the distance between the second reeds 4 is longer than the distance between the die pad 2 and the first reed 3. Has been done.

When the semiconductor device 100 is used as a semiconductor device for driving a small fan motor (three-phase DC motor) mounted on an indoor / outdoor unit of a general household air conditioner, the phase is determined in the output circuit 1a of the inverter IC chip 1. Since the control is performed with a shift of 120 °, a potential difference due to a phase shift occurs between the second leads 4 connected by the bonding wire 5.

The voltage applied to the output circuit 1a is, for example, a high voltage of several tens to several hundreds V for driving a fan motor mounted on an indoor / outdoor unit of a general household air conditioner. Further, the voltage applied to the control circuit 1b of the inverter IC chip 1 is a low voltage of several V to a dozen V.

Further, for stable power output of the output circuit 1a and stable operation of the control circuit 1b, the other surface (for example, the back surface) on which the output circuit 1a and the control circuit 1b of the inverter IC chip 1 are formed is It is desirable to use the GND potential.

Therefore, when a large potential difference is generated between the output circuit 1a of the inverter IC chip 1 and the plurality of second leads 4 connected by the bonding wire 5 and exposed to the outer surface of the semiconductor device 100, the electric discharge is discharged. A certain creepage distance is required to reduce the risk.

On the other hand, the first reed 3 to which the control circuit 1b of the inverter IC chip 1 is connected has a lower voltage than the second reed 4, but secures a creepage distance from the die pad 2 which is a GND potential. There is. That is, the distance D2 between the high voltage second leads 4 and the distance D5 between the low voltage first leads 3 and the die pad 2 cause a potential difference from GND when the outer shape of the semiconductor device is made as small as possible. In addition, it is necessary to properly secure each creepage distance.

That is, when the potential difference of the distance D2 between the second leads 4 in the semiconductor device 100 is Ve2 and the potential difference of the distance D5 between the die pad 2 and the first lead 3 is Ve5, an unintended discharge is performed between D2 and D5. In order to prevent the risk equally and to the minimum, from the equation (1), Ve2 / D2 = Ve5 / D5. That is, D2 = (Ve2 / Ve5) D5. Here, since Ve5 <Ve2, therefore, D5 <D2.

As described above, in the semiconductor device 100 according to the present embodiment, the distance D2 between the second leads 4 to which the output circuit 1a having a higher voltage than the control circuit 1b of the inverter IC chip 1 is connected is set to the control circuit 1b. By making the distance between the first lead 3 connected to the second lead 3 and the die pad 2 which is the GND potential larger (longer) than D5, the discharge risk between the second leads 4 is reduced between the die pad 2 and the first lead 3. High withstand voltage can be realized by minimizing the discharge risk.

A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 6 and 7. FIG. 6 is a schematic plan view schematically showing the plan structure of the semiconductor device 100 according to the present embodiment. FIG. 7 is a schematic planar external view schematically showing the planar appearance of the semiconductor device 100 shown in FIG. Hereinafter, matters different from those of the first and second embodiments will be mainly described.

In the semiconductor device 100 of this embodiment, as shown in FIGS. 6 and 7, the output circuit 1a which is a high voltage circuit and the control circuit 1b which is a low voltage circuit are integrally integrated and formed on the surface side of a common semiconductor substrate. The inverter IC chip 1 is connected to the die pad 2 connected to one surface (lower surface) of the inverter IC chip 1 via a bonding material 7 (not shown), and a plurality of thirds arranged in at least one portion around the die pad 2. It includes a lead 3 of 1 and a plurality of second leads 4 to which a higher voltage is applied than the first lead 3.

Further, as shown in FIG. 7, the back surface sides of the die pad 2, the first lead 3, and the second lead 4 are exposed to the outside of the semiconductor device 100, and the same as in FIG. 2 of the first embodiment. The surface side of the inverter IC chip 1, the first lead 3, and the second lead 4 is coated with the sealing resin 6. The semiconductor device 100 of this embodiment includes a package in which the ends of the first lead 3 and the second lead 4 are flush with the sealing resin 6, and the first lead 3 and the second lead 4 are provided. The die pad 2, the first lead 3, and the second lead 4 are arranged in a positional relationship (D3> D5) such that the distance D3 between them is larger (longer) than the distance D5 between the die pad 2 and the first lead 3. Has been done.

When the semiconductor device 100 is used as a semiconductor device for driving a small fan motor (three-phase DC motor) mounted on an indoor / outdoor unit of a general household air conditioner, the voltage applied to the output circuit 1a is a number. It is a high voltage of 10 V to several hundred V.

On the other hand, the voltage applied to the control circuit 1b of the inverter IC chip 1 is a low voltage of several V to a dozen V.

Further, for stable power output of the output circuit 1a and stable operation of the control circuit 1b, the other surface (for example, the back surface) on which the output circuit 1a and the control circuit 1b of the inverter IC chip 1 are formed is It is desirable to use the GND potential.

Therefore, a large potential difference is generated between the output circuit 1a of the inverter IC chip 1 and the second lead 4 connected by the bonding wire 5, and the control circuit 1b and the first lead 3 connected by the bonding wire 5, and the semiconductor is used. When exposed to the outer surface of the device 100, a certain creepage distance is required to reduce the discharge risk.

On the other hand, the first reed 3 to which the control circuit 1b of the inverter IC chip 1 is connected has a lower voltage than the second reed 4, but secures a creepage distance from the die pad 2 which is a GND potential. There is. That is, when the outer shape of the semiconductor device is made as small as possible in the distance D3 between the high voltage second lead 4 and the low voltage first lead 3 and the distance D5 between the low voltage first lead 3 and the die pad 2. In addition, it is necessary to appropriately secure each creepage distance according to the potential difference with GND.

That is, when the potential difference of the distance D3 between the second lead 4 and the first lead 3 in the semiconductor device 100 is Ve3, and the potential difference of the distance D5 between the die pad 2 and the first lead 3 is Ve5, the potential difference is D3. In order to prevent the unintended discharge risk in D5 equally and to the minimum, from the equation (1), Ve3 / D3 = Ve5 / D5. That is, D3 = (Ve3 / Ve5) D5. Here, since Ve5 <Ve3, therefore, D5 <D3.

As described above, in the semiconductor device 100 according to the present embodiment, the second lead 4 to which the high voltage output circuit 1a is connected is connected to the low voltage control circuit 1b from the control circuit 1b of the inverter IC chip 1. By making the distance D3 between the first leads 3 larger (longer) than the distance D5 between the first leads 3 to which the control circuit 1b is connected and the die pad 2 which is the GND potential, the first leads 3- The discharge risk between the second lead 4 and the first lead 3-die pad 2 can be equally and minimized, and a high withstand voltage can be realized.

A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is a schematic plan view schematically showing the plan structure of the semiconductor device 100 according to the present embodiment. FIG. 9 is a schematic planar external view schematically showing the planar appearance of the semiconductor device 100 shown in FIG. Hereinafter, matters different from those of Examples 1 to 3 will be mainly described.

In the semiconductor device 100 of this embodiment, as shown in FIGS. 8 and 9, the output circuit 1a which is a high voltage circuit and the control circuit 1b which is a low voltage circuit are integrally integrated and formed on the surface side of a common semiconductor substrate. The inverter IC chip 1 is connected to the die pad 2 connected to one surface (lower surface) of the inverter IC chip 1 via a bonding material 7 (not shown), and a plurality of thirds arranged in at least one portion around the die pad 2. It includes a lead 3 of 1 and a plurality of second leads 4 to which a higher voltage is applied than the first lead 3.

Further, as shown in FIG. 9, the back surface sides of the die pad 2, the first lead 3, and the second lead 4 are exposed to the outside of the semiconductor device 100, and the same as in FIG. 2 of the first embodiment. The surface side of the inverter IC chip 1, the first lead 3, and the second lead 4 is coated with the sealing resin 6. The semiconductor device 100 of this embodiment is provided so that the area A2 of the second lead 4 is larger (wider) than the area A1 of the first lead 3. (A2> A1)
When the semiconductor device 100 is used as a semiconductor device for driving a small fan motor (three-phase DC motor) mounted on an indoor / outdoor unit of a general household refrigerator, for example, the current flowing through the output circuit 1a is generally general. If it is for driving a fan motor mounted on an indoor / outdoor unit of a household air conditioner or a compressor of a general household refrigerator, the current is a large current of several A to several ten A.

On the other hand, the current flowing through the control circuit 1b of the inverter IC chip 1 is a small current of several millimeters A to ten and several millimeters A.

Therefore, as the area of the second reed 4 through which a larger current flows than that of the first reed 3 is larger (wider), the electric resistance is reduced to improve the efficiency, and for example, the generation of Joule heat due to the electric resistance is suppressed. Is possible.

Further, when exposed to the outer surface of the semiconductor device 100, the area of the second lead 4 is large (wide), so that high reliability can be realized by being firmly connected to the mounting substrate. That is, in the area A2 of the second lead 4 having a large current and the area A1 of the first lead 3 having a small current, the respective areas are appropriately secured in order to make the outer shape of the semiconductor device as small as possible and improve the withstand voltage. There is a need to.

That is, it is desirable that the area A2 of the second lead 4 and the area A1 of the first lead 3 in the semiconductor device 100 are A1 <A2.

As described above, the semiconductor device 100 according to the present embodiment has a control circuit having a small current in the area A2 of the second lead 4 to which the output circuit 1a in which a large current flows from the control circuit 1b of the inverter IC chip 1 is connected. By making the area A1 of the first lead 3 to which 1b is connected larger (wider), it is possible to suppress an increase in electrical resistance and realize high efficiency, and further, high heat dissipation and high reliability can be realized.

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

1 ... Inverter IC chip 1a ... Output circuit (high voltage circuit)
1b ... Control circuit (low voltage circuit)
2 ... Die pad 2a ... Suspended lead 3 ... First lead 4 ... Second lead 5 ... Bonding wire 6 ... Sealing resin 7 ... Bonding material 100 ... Semiconductor device

Claims (8)

Inverter IC chips with output circuits and control circuits formed on the surface of a semiconductor substrate,
A die pad bonded to the back surface of the semiconductor substrate via a bonding material,
A first lead located along at least one side of the die pad and electrically connected to the control circuit by a first bonding wire.
A second lead located along the other side of the die pad and electrically connected to the output circuit by a second bonding wire.
The inverter IC chip and the sealing resin for covering the surface of the first lead and the second lead are provided.
The surface of the die pad opposite to the bonding surface with the semiconductor substrate, the surface of the first lead opposite to the connection surface with the first bonding wire, and the second lead of the second lead. Each of the surfaces opposite to the connection surface with the bonding wire is exposed from the sealing resin, and the end edge of the first lead and the end edge of the second lead are made of the sealing resin. It is exposed from the sealing resin so as to be flush with the end edge.
The first lead and the second lead are formed so as to be separated from each other with a predetermined distance .
The first lead has a lead arranged along the side opposite to the other side with the die pad interposed therebetween, and a lead arranged along the side intersecting with the other side.
A semiconductor device characterized in that the distance between a lead arranged along a side intersecting the other side and the second lead is longer than the distance between the die pad and the first lead . The semiconductor device according to claim 1.
A semiconductor device characterized in that the distance between the die pad and the second lead is longer than the distance between the die pad and the first lead. The semiconductor device according to claim 1 or 2.
With a plurality of the second leads,
A semiconductor device characterized in that the distance between the second leads is longer than the distance between the die pad and the first lead. The semiconductor device according to any one of claims 1 to 3 .
A semiconductor device characterized in that the area of the second lead is larger than the area of the first lead. (A) A process of forming an output circuit and a control circuit on the surface of a semiconductor substrate,
(B) After the step (a), a step of joining a die pad to the back surface of the semiconductor substrate with a joining material.
(C) The lead frame having a plurality of first leads and a plurality of second leads formed apart from the first leads at a predetermined distance after the step (b). The process of arranging multiple die pads,
(D) After the step (c), a step of electrically connecting the control circuit and the first lead, and the output circuit and the second lead by wire bonding, respectively.
(E) After the step (d), a step of arranging the lead frame in which the plurality of die pads are arranged in a cavity of a mold, filling the cavity with a molten sealing resin, and curing the lead frame.
(F) After the step (e), a step of cutting and molding the sealing resin and the lead frame to separate the semiconductor substrate and the die pad sealed with the sealing resin .
It is a manufacturing method of a semiconductor device including
The first lead has a lead arranged on the side opposite to the second lead with the die pad interposed therebetween, and a lead arranged in a direction intersecting the arrangement direction of the second lead. ,
Manufacture of a semiconductor device, characterized in that the distance between a lead arranged in a direction intersecting the arrangement direction of the second lead and the second lead is longer than the distance between the die pad and the first lead. Method. The method for manufacturing a semiconductor device according to claim 5 .
A method for manufacturing a semiconductor device, characterized in that the distance between the die pad and the second lead is longer than the distance between the die pad and the first lead. The method for manufacturing a semiconductor device according to claim 5 or 6 .
With a plurality of the second leads,
A method for manufacturing a semiconductor device, wherein the distance between the second leads is longer than the distance between the die pad and the first lead. The method for manufacturing a semiconductor device according to any one of claims 5 to 7 .
A method for manufacturing a semiconductor device, wherein the area of the second lead is larger than the area of the first lead.

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