JP7071416B2 - Solid-state image sensor and imaging system - Google Patents

Description

The present invention relates to a solid-state image pickup device and an image pickup system in which a photoelectric conversion layer is formed on a substrate.

In a solid-state image sensor, a configuration is known in which a photoelectric conversion layer includes pixels including a light receiving portion formed on a substrate. Patent Document 1 describes that an organic photoelectric conversion layer is used as the photoelectric conversion layer. Patent Document 1 further describes that a pair of phase difference detection pixels is provided in order to realize pupil division phase difference detection. The phase difference detection pixel has a light-shielding film for blocking a part of incident light between the protective layer provided on the photoelectric conversion layer and the microlens.

Japanese Unexamined Patent Publication No. 2014-67748

However, Patent Document 1 has not proposed a specific configuration for providing a capacitance to an element having a photoelectric conversion layer.

An object of the present invention is to propose a specific configuration in which a capacitance is provided in an element having a photoelectric conversion layer.

The photoelectric conversion element according to the present invention that achieves the above object is such that a plurality of pixel electrodes, a photoelectric conversion layer provided on the plurality of pixel electrodes, and the photoelectric conversion layer are sandwiched between the plurality of pixel electrodes. Between the photoelectric conversion unit including the counter electrode provided in the circuit, one microlens overlapping the plurality of pixel electrodes in plan view, the circuit provided on the substrate, and the photoelectric conversion unit to the circuit. A capacitance provided in the electric path, a first wiring layer provided between the plurality of pixel electrodes and the substrate, and a second wiring layer provided between the first wiring layer and the substrate. It has a wiring layer, and the capacitance is provided in the first wiring provided in the first wiring layer and the second wiring layer, and overlaps with the first wiring in a plan view. It is characterized in that it is composed of the wiring of the above and a first insulating layer formed between the first wiring and the second wiring .

According to the present invention, it is possible to propose a specific configuration in which a capacitance is provided in an element having a photoelectric conversion layer .

It is a block diagram for showing the structural example of a solid-state image sensor. It is a figure for showing the example of the cross-sectional structure of a pixel. It is an equivalent circuit diagram for showing the structural example of a pixel. It is a potential figure of the photoelectric conversion part for demonstrating a signal reading operation. It is a potential figure of the photoelectric conversion part for demonstrating charge discharge operation. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a figure which shows the structure of a pixel array. It is a block diagram for showing the structural example of a solid-state image sensor. It is an equivalent circuit diagram for showing the structural example of a pixel. It is a figure for showing the example of the cross-sectional structure of a pixel. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a block diagram for showing the structural example of a solid-state image sensor. It is a figure for showing the example of the cross-sectional structure of a pixel. It is an equivalent circuit diagram for showing the structural example of a pixel. It is a potential figure of the photoelectric conversion part for demonstrating a signal reading operation. It is a potential figure of the photoelectric conversion part for demonstrating charge discharge operation. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a block diagram for showing the structural example of a solid-state image sensor. It is an equivalent circuit diagram for showing the structural example of a pixel. It is a figure for showing the example of the cross-sectional structure of a pixel. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a block diagram for showing the structural example of a solid-state image sensor. It is a figure for showing the example of the cross-sectional structure of a pixel. It is an equivalent circuit diagram for showing the structural example of a pixel. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a figure for showing the example of the cross-sectional structure of a pixel. It is an equivalent circuit diagram which shows the structural example of the signal reading circuit. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is an equivalent circuit diagram which shows the structural example of the signal reading circuit. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a plane schematic diagram for showing the arrangement example of a signal readout circuit. It is a figure for showing the example of the cross-sectional structure of a pixel. It is an equivalent circuit diagram which shows the structural example of the signal reading circuit. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a timing diagram for demonstrating the operation of a solid-state image sensor. It is a block diagram which shows the configuration example of an image pickup system. It is a plane schematic diagram of a pixel for demonstrating the arrangement example of a pixel electrode.

(First Embodiment)
FIG. 1 is a block diagram for showing a configuration example of the solid-state image sensor 1000. The solid-state image sensor 1000 includes a pixel array 110 in which a plurality of pixels 100 are arranged in a two-dimensional manner, a row drive circuit 120, a vertical signal line 130, a signal processing unit 140, a column selection circuit 150, an output amplifier 170, and a constant current source 180. including.

FIG. 1 shows a case where the pixels 100 have 4 rows × 4 columns, but the number of pixels 100 included in the pixel array 110 is not limited to this.

The row drive circuit 120 is a circuit that controls a plurality of pixels 100 in row units, and includes, for example, a shift register and an address decoder. In this embodiment, the row drive circuit 120 outputs the signals pRes (M), PADD (M), Va (M), Vb (M) and pSEL (M). M is a number representing a row. The row drive circuit 120 functions as a pixel electrode control means for controlling the potential of the pixel electrode of the pixel 100 via a drive capacitance described later.

A plurality of pixels 100 belonging to the same row are connected to a common vertical signal line 130. The signal output from the pixel 100 is transmitted to the signal processing unit 140 via the vertical signal line 130.

The signal processing unit 140 includes a plurality of column signal processing units, each of which is provided for each column of the pixel array 110. Each column signal processing unit may include a CDS circuit for reducing noise, an amplifier for amplifying the signal, a sample hold circuit for holding the signal, and the like. The column signal processing unit outputs a signal when it is selected by the signal CSEL (N) supplied from the column selection circuit 150, and the output signal is transmitted to the output amplifier 170. N is a number representing a column.

FIG. 2 shows a structural example of a cross section of the pixel 100. In this embodiment, the pixel 100 has two photoelectric conversion units PC1 and PC2. Further, the two photoelectric conversion units PC1 and PC2 share an amplification transistor 403 and a selection transistor 404, which will be described later. The pixel array 110 includes a silicon substrate (Si substrate) 300, a lower insulating layer 301 provided on the Si substrate 300, and a wiring layer 302 arranged in the lower insulating layer 301. A MOS transistor is formed on the Si substrate 300, and the wiring layer 302 includes wiring for supplying power to the MOS transistor and wiring for transmitting a signal for controlling the MOS transistor. A part of the wiring included in the wiring layer 302 connects the signal readout circuit (not shown) formed on the Si substrate 300 to the pixel electrode 303. An interlayer insulating layer 304, a photoelectric conversion layer 305, a blocking layer 306, a counter electrode 307, a color filter layer 308, and a microlens layer 309 having a plurality of microlenses are provided on the pixel electrode 303. In the present embodiment, one pixel 100 is provided with two pixel electrodes 303a and 303b, while the counter electrode 307 is commonly provided for a plurality of photoelectric conversion units. Further, the structure is such that the light collected by one microlens is incident on a plurality of photoelectric conversion units. A bayer array can be used as the array of color filters in the color filter layer 308. It can be said that the two pixel electrodes 303a and 303b provided in one pixel 100 are partial electrodes that can be controlled independently of each other.

The two pixel electrodes 303a and 303b provided corresponding to the same microlens are arranged at a distance d from each other to form two photoelectric conversion units. Although not shown in the figure, the pixel electrodes of adjacent pixels may be arranged at a distance D larger than the distance d. The pixel electrode 303a of a certain pixel is provided at a distance d from another pixel electrode 303b of this pixel, and is provided at a distance D from the pixel electrode 303b of an adjacent pixel. By arranging the pixel electrodes in this way, it is possible to suppress the charge generated in response to the light incident on a certain pixel from being accumulated in the photoelectric conversion unit of the adjacent pixel. When each pixel has a color filter, the effect of reducing color mixing can be obtained.

The interlayer insulating layer 304 provided on the pixel electrode 303 is a layer for preventing electrons and holes from passing between the pixel electrode 303 and the photoelectric conversion layer 305, and is, for example, hydrogenated amorphous silicon nitride. It is formed of (a-SiN: H). The thickness of the interlayer insulating layer 304 is set to such a thickness that the currency of electrons and holes due to the tunnel effect is not generated. Specifically, the thickness is preferably 50 nm or more.

The photoelectric conversion layer 305 provided on the pixel electrode 303 via the interlayer insulating layer 304 is a layer having a photoelectric conversion ability that generates an electron-hole pair when receiving incident light. Intrinsic (intrinsic) hydrogenated amorphous silicon (a—Si: H), compound semiconductors and organic semiconductors can be used as the material constituting the photoelectric conversion layer 305. Examples of compound semiconductors include III-VI compound semiconductors such as BN, GaAs, GaP, AlSb, and GaAlAsP, and II-IV compound semiconductors such as CdSe, ZnS, and HdTe. Examples of organic semiconductors include phthalocyanine-based materials such as fullerene, coumarin 6 (C6), rhodamine 6G (R6G), quinacridone, and zinc phthalocyanine (ZnPc), and naphthalocyanine-based materials.

Further, for the photoelectric conversion layer 305, a quantum dot film made of the above-mentioned compound semiconductor as a raw material can be used. Amorphous silicon films, organic semiconductor films, and quantum dot films are suitable because thin films can be easily formed.

Intrinsic semiconductors have a low carrier density, so they are excellent in that a wide depletion layer width can be realized by using them in the photoelectric conversion layer 305. However, N-type and P-type semiconductors are used. Is also good.

A blocking layer 306 is provided on the photoelectric conversion layer 305. The blocking layer 306 of the present embodiment is a layer having a function of preventing holes from being injected from the counter electrode 307 into the photoelectric conversion layer 305, and for example, N + type hydrogenated amorphous silicon is used. In this example, N + type a-SiH is used to prevent the injection of holes, but P + type a-SiH may be used to prevent the injection of electrons. The blocking layer 306 is required to prevent the conductive carrier of either one of the electron and the hole from being injected into the photoelectric conversion layer 305 from the counter electrode 307. As the blocking layer 306, a P-type or N-type semiconductor of the semiconductor material used for the photoelectric conversion layer 305 can be used. In this case, the impurity concentration in the semiconductor used for the blocking layer 306 is higher than the impurity concentration in the semiconductor used for the photoelectric conversion layer 305.

The counter electrode 307 provided on the photoelectric conversion layer 305 via the blocking layer 306 is formed of a material that allows light incident through the microlens layer 309 and the color filter layer 308 to pass through the photoelectric conversion layer 305. To. Specifically, compounds containing indium and tin such as ITO, oxides and the like are used.

A light transmissive layer may be further provided between the counter electrode 307 and the microlens layer 309. The microlens layer 309, the color filter layer 308 and the light transmissive layer are preferably designed so that the focal point of the microlens layer 309 is on the photoelectric conversion layer 305. The light-transmitting layer may be formed of an inorganic substance such as participating Si or silicon nitride, or may be formed of an organic substance.

FIG. 3 is an equivalent circuit diagram of the pixel 100 according to the present embodiment. The pixel 100 includes a photoelectric conversion unit PC1 and PC2 including a blocking layer 306, a photoelectric conversion layer 305, and an interlayer insulating layer 304, and a signal readout circuit 400.

The signal readout circuit 400 includes a reset transistor 401, a drive capacitance 402, an amplification transistor 403, a selection transistor 404, and a changeover switch 405. A reset voltage is supplied to one main node of the reset transistor 401a, and the other main node is connected to the pixel electrode 303a of the photoelectric conversion unit PC1. The node N1 is a common node between the other main node of the reset transistor 401a and the pixel electrode 303a. The reset signal pRES1 is supplied to the control node of the reset transistor 401a. A bias voltage Va is applied to one node of the drive capacitance 402a, and the other node is connected to the node N1. The node N1 is connected to the control node of the amplification transistor 403 via the changeover switch 405. The control node of the amplification transistor 403 is referred to as a node N2. The changeover switch 405 is controlled by the signal pADD. The pixel electrode 303b of the photoelectric conversion unit PC2 is connected to the node N2. A reset transistor 401b and a drive capacitance 402b are further connected to the node N2. The reset signal pRES2 is supplied to the control node of the reset transistor 401b. A bias voltage Vb is applied to one node of the drive capacitance 402b, and the other node is connected to the node N2. The photoelectric conversion unit PC2 is connected to the node N2 via the pixel electrode 303b. A fixed voltage is applied to one main node of the amplification transistor 403, and the other main node is connected to the vertical signal line 130 via the selection transistor 404. The pixel selection signal pSEL is supplied to the control node of the selection transistor 404. When the selection transistor 404 is turned on, the amplification transistor 403 as an intra-pixel amplifier operates as a source follower circuit together with the constant current source 180, and the voltage output according to the potential of the node N1 is a signal processing unit as a pixel signal from the pixel 100. Is entered in. The node N1 is an input unit of an intra-pixel amplifier. The in-pixel amplifier is not limited to the source follower circuit, but may be a source grounded amplifier circuit, or may be an inverter or a differential amplifier composed of a plurality of transistors.

Next, an operation of reading a signal from the pixel 100 according to the present embodiment will be described. Here, for the sake of simplicity, a case where a signal is read from the photoelectric conversion unit PC2 when the changeover switch 405 is in the off state will be described. FIG. 4 is a potential diagram of a photoelectric conversion unit for explaining a signal reading operation. In the figure, the lower the value, the lower the potential for electrons. In the figure, the potential of each region is drawn in the order of the counter electrode 307 (corresponding to the node N2), the photoelectric conversion layer 305, the interlayer insulating layer 304, and the pixel electrode 303b from the left. Here, the blocking layer 306 is omitted for the sake of simplicity. In the figure, black circles represent electrons and white circles represent holes.

In the present embodiment, it is assumed that the reset voltage is 1 [V] and the photoelectric conversion unit drive bias voltage Vs applied to the upper electrode is 3 [V]. Further, it is assumed that the bias voltage Vb can be switched to 5 [V] or 0 [V] by a control circuit (not shown). Since the numbers given here are exemplary, the value of the bias voltage is not limited.

The reading operation of the pixel 100 is realized by performing the following operations a) to f).
a) Reset before storage b) Photo charge storage c) Reset after storage d) N signal reading e) Charge transfer f) S signal reading

In the following, each of the above steps will be described in detail.

a) Reset before accumulation With the bias voltage Vb set to 0 [V], the node N2 is reset to 1 [V] by turning on the reset transistor 401b. After that, when the reset transistor 401b is turned off, kTC noise (kTC1) is generated due to the operation of the reset transistor. As a result, the potential of the node N2, that is, the pixel electrode 303 becomes 1 [V] + kTC1 (FIG. 4A).

b) Photocharge accumulation When light is incident on the photoelectric conversion layer 305 and the pre-accumulation reset is completed, the photocharge accumulation operation starts. The bias voltage Vb is maintained at 0 [V] during the period of photocharge accumulation. Therefore, the potential of the pixel electrode 303b becomes a negative potential with respect to the counter electrode 307 to which the voltage of 3 [V] is applied. Therefore, the electrons in the photoelectric conversion layer 305 are guided toward the counter electrode 307 and are discharged from the counter electrode 307 via the blocking layer 306. On the other hand, the hole is guided toward the pixel electrode 303. Since there is a blocking layer 306, injection from the counter electrode 307 into the photoelectric conversion layer 305 is not performed (FIG. 4 (b-1)).

When the photoelectric conversion layer 305 absorbs incident light, electron-hole pairs are generated according to the amount of incident light. The generated electrons are discharged from the counter electrode 307, while the generated holes move in the photoelectric conversion layer 305 and reach the interface with the interlayer insulating layer 304. However, since the holes cannot move in the interlayer insulating layer 304, they are accumulated in the photoelectric conversion layer 305 (FIG. 4 (b-2)). The holes thus accumulated are used as signal charges based on the incident light. Due to the holes accumulated in the photoelectric conversion layer 305, the potential of the node N2 rises by Vp, and the potential of the node N1 becomes 1 [V] + kTC1 + Vp1.

c) Reset after accumulation The reset transistor 401b is temporarily turned on to reset the node N2 to 1 [V]. Since noise (kTC2) is generated with the operation of the reset transistor 401b, the potential of the node N2 becomes 1 [V] + kTC2. The noise kTC1 generated by the pre-accumulation reset and the noise kTC2 generated by the post-accumulation reset are so-called random noise components that do not correlate with each other.

Even if the node N2 is reset by the reset transistor 401b, the holes accumulated in the photoelectric conversion layer 305 remain in the photoelectric conversion layer 305 (FIG. 4 (c)).

d) N signal read-out The selection transistor 404 is turned on, and a signal corresponding to the potential of the node N2 at this time is output to the vertical signal line 130. The output signal is held by, for example, a column signal processing unit.

e) Charge transfer The bias voltage Vb is changed from 0 [V] to 5 [V]. As a result, the potential of the node N2 fluctuates. The amount of fluctuation of this potential is determined by the ratio of the capacitance of the photoelectric conversion unit to the capacitance value of the drive capacitance 402b. Assuming that the capacitance value of the photoelectric conversion unit is C1, the capacitance value of the drive capacitance 402b is C2, and the positive change amount of the bias voltage Vb is ΔVb, the fluctuation amount ΔVN2 of the potential of the node N2 is expressed by the following equation. ..
ΔVN2 = ΔVb × C1 / (C1 + C2) ... (1)

In the present embodiment, assuming that the capacitance value C1 of the drive capacitance 402b is four times the capacitance value C2 of the photoelectric conversion unit, the amount of change in the potential of the node N2 when the bias voltage Vb is changed by 5 [V] is 4. It becomes [V].

When the potential of the node N2 rises by 4 [V] to 5 [V] + kTC2, the potential of the node N2 and the potential of the counter electrode 307 are reversed. As a result, the slope of the potential in the photoelectric conversion layer 305 is reversed. (Fig. 4 (e-1)). As a result, electrons are injected from the counter electrode 307 into the photoelectric conversion layer 305 via the blocking layer 306. Further, the holes accumulated in the photoelectric conversion layer 305 are guided toward the counter electrode 307 and recombine with the electrons in the blocking layer 306 to disappear. As a result, all the holes accumulated in the photoelectric conversion layer 305 are discharged from the photoelectric conversion layer 305. That is, complete transfer is performed by completely depleting the photoelectric conversion layer 305 (FIG. 4 (e-2)).

Next, when the bias voltage Vb is set to 0 [V] again, the potential of the node N2 becomes negative with respect to the potential of the counter electrode 307. Therefore, when the bias voltage Vb is 5 [V], the photoelectric conversion layer 305 The electrons injected into the capacitor are discharged from the photoelectric conversion layer 305 via the blocking layer 306. Since the amount of electrons emitted in this way is ideally equal to the amount of electrons injected into the photoelectric conversion layer 305, it does not affect the reading of the signal. By setting the bias voltage Vb to 0 [V], the potential of the node N2 also tries to return to 1 [V] + kTC2, but because the blocking layer 306 is provided between the counter electrode 307 and the photoelectric conversion layer 305. In addition, the holes are not injected into the photoelectric conversion layer 305. Therefore, the signal due to the hole accumulated in the photoelectric conversion layer 305 by the optical charge accumulating operation remains as an optical signal component Vp, so that the potential of the node N2 becomes 1 [V] + kTC2 + Vp.

f) The S signal reading selection transistor 404 is turned on, and a signal corresponding to the potential of the node N2 at this time is output to the vertical signal line 130. The output signal is held by, for example, a column signal processing unit. When the signal obtained in this step and the signal obtained by reading the N signal in d) are differentially processed, the noise component kTC2 is canceled out, and as a result, a signal corresponding to the optical signal component Vp is obtained.

The selection transistor 404 may be kept on after reading the N signal.

By the above operation, the pixel signal can be read out.

Next, the operation when the electric charge is discharged without reading the pixel signal based on the electric charge generated in the photoelectric conversion unit will be described. Here, too, the operation of only the photoelectric conversion unit PC2 when the changeover switch 405 is in the off state will be described.

FIG. 5 is a potential diagram of the photoelectric conversion unit for explaining the charge discharge operation. In the figure, the lower the value, the lower the potential for electrons. In the figure, the potential of each region is drawn in the order of the counter electrode 307, the photoelectric conversion layer 305, the interlayer insulating layer 304, and the pixel electrode 303b from the left. Here, the blocking layer 306 is omitted for the sake of simplicity. In the figure, black circles represent electrons and white circles represent holes.

The difference from the pixel signal readout operation described with reference to FIG. 4 is the bias applied to the drive capacitance 402b during the optical charge accumulation periods of (b-1) and (b-2) shown in FIG. It is a point where Vb is 5 [V] (FIG. 5 (b-1), FIG. 5 (b-2)). When the bias voltage Vb = 5 [V] is applied to the drive capacitance 402b, the pixel electrode is given a positive potential with respect to the counter electrode. Therefore, when light is incident on the photoelectric conversion layer 305, the generated holes are guided to the counter electrode by the electric field between the pixel electrode and the counter electrode and discharged.

On the other hand, the electrons generated in the photoelectric conversion layer 305 are guided toward the interlayer insulating layer 304 by the electric field between the pixel electrode and the counter electrode, but are accumulated at the interface between the photoelectric conversion layer 305 and the interlayer insulating layer 304. However, the accumulated electrons are discharged from the counter electrode by resetting the potential of the pixel electrode 303b to 1 [V] by the reset transistor 401b in the step of FIG. 5C. As a result, the electric charge generated in the photoelectric conversion layer 305 in response to the incident light has both holes and electrons discharged from the counter electrode, so that the optical signal component Vp becomes 0.

An example of the operation of the solid-state image sensor 1000 in the present embodiment will be described. FIG. 6 is a timing diagram relating to the operation related to the pixels in the nth row and the (n + 1) th row in the pixel array when the so-called rolling shutter operation is performed. Here, the pixel signals based on the two photoelectric conversion units PC1 and PC2 are read from the pixel on the nth row, and the pixels based on only one of the two photoelectric conversion units PC2 from the pixel on the (n + 1) row. The operation of reading a signal will be described. Therefore, the changeover switch 405 is kept off for the pixel in the (n + 1) th row.

The period related to the signal reading of each line can be roughly divided into a horizontal blanking period HBLNK and a horizontal scanning period HSCAN. The numbers in parentheses for HBLNK, HSCAN and signals and bias voltages are numbers indicating rows in the pixel array. For example, HBLNK (n) means that it is a horizontal blanking period related to the pixel in the nth row in the pixel array. Further, it is assumed that the signals pRES1 and pRES2 are the same as the signals pRES.

Before the start of HBLNK (n), which is the horizontal blanking period of the pixel in the nth row, the charge generated by the photoelectric conversion is accumulated in the photoelectric conversion units PC1 and PC2 of the pixel in the nth row, that is, It is assumed that it is in the state of FIG. 4 (b-1).

At time t1, the signals pSEL (n), pRES (n), and pADD (n) become high (H) levels. The other signals are at low (L) level except for Va (n + 1). As a result, the pixel on the nth row is selected, and the signal from the pixel on the nth row appears on the vertical signal line 130. Further, when the signal pADD (n) and the signal pRES (n) become H level, the nodes N1 and N2 are short-circuited, and this node is reset to 1 [V]. That is, the state shown in FIG. 4 (b-2) is obtained.

When the signal pTN is temporarily set to the H level from the time t2, the signal corresponding to the potential of the node N2 at this time is sample-held by the signal processing unit 140. That is, N signal reading is performed.

By temporarily setting the bias voltages Va (n) and Vb (n) to the H level from time t3, the potential of the node N2 fluctuates according to the amount of electric charge accumulated in the photoelectric conversion units PC1 and PC2. This is the charge transfer operation shown in FIGS. 4 (e-1) and 4 (e-2).

When the signal pTS is temporarily set to the H level from the time t4, the signal corresponding to the potential of the node N2 at this time is sample-held by the signal processing unit 140. That is, the S signal is read out. Since the S signal read at this time is a signal based on the two photoelectric conversion units PC1 and PC2 provided under the same microlens, it can be used as an image pickup signal.

When the signal pRES (n) reaches the H level at time t5, the node N2 is reset to 1 [V] again. That is, the pre-accumulation reset shown in FIG. 4A is performed.

When the signals pSEL (n) and pADD (n) become low level at time t6, the selection state of the pixel in the nth row is canceled and the nodes N1 and N2 are electrically disconnected.

After that, when the horizontal scanning period HSCAN (n) starts, the signal PHST becomes H level at time t7. In response to this, the column selection circuit 150 starts scanning the column signal processing unit. Since the column selection circuit 150 operates in synchronization with a clock signal (not shown), the signal from the column signal processing unit is sequentially output from the output amplifier 170.

After the scanning by the column selection circuit 150 is completed, the bias voltage Va (n + 1) becomes low level at time t8. As a result, the electric charge generated in the photoelectric conversion unit PC1 is accumulated.

At time t9, the signals pSEL (n + 1) and pRES (n + 1) become H level. As a result, the pixel on the nth row is selected, and the signal from the pixel on the n + 1th row appears on the vertical signal line 130. Further, when the signal pRES (n + 1) becomes H level, the node N2 is reset to 1 [V].

When the signal pTN is temporarily set to the H level from the time t10, the signal corresponding to the potential of the node N2 at this time is sample-held by the signal processing unit 140. That is, N signal reading is performed.

By temporarily setting the bias voltages Va (n + 1) and Vb (n + 1) to the H level from time t11, the potential of the node N1 fluctuates according to the amount of electric charge stored in the photoelectric conversion unit PC1, and the photoelectric conversion unit is used. The potential of the node N2 fluctuates according to the amount of electric charge stored in the PC 2. This is the charge transfer operation shown in FIGS. 4 (e-1) and 4 (e-2).

When the signal pTS is temporarily set to the H level from the time t12, the signal corresponding to the potential of the node N2 at this time is sample-held by the signal processing unit 140. That is, the S signal is read out. Since the S signal read at this time is a signal based only on PC2 of the two photoelectric conversion units PC1 and PC2 provided under the same microlens, it can be used as a phase difference detection signal.

When the signal pRES (n + 1) reaches the H level at time t13, the nodes N1 and N2 are reset to 1 [V] again. That is, the pre-accumulation reset shown in FIG. 4A is performed.

When the signal pSEL (n + 1) becomes low level at time t14, the selection state of the pixel in the n + 1th row is canceled.

After that, when the horizontal scanning period HSCAN (n + 1) starts, the bias voltage Va (n + 1) becomes H level at time t15, and the photoelectric conversion unit PC1 returns to a state in which holes are not accumulated.

Further, the signal PHST becomes H level at time t15. In response to this, the column selection circuit 150 starts scanning the column signal processing unit. Since the column selection circuit 150 operates in synchronization with a clock signal (not shown), the signal from the column signal processing unit is sequentially output from the output amplifier 170.

As described above, for the pixel on the nth row, the pixel signal based on the two photoelectric conversion units provided corresponding to the same microlens is read out and used as an image pickup signal. On the other hand, for the pixel in the (n + 1) th row, the pixel signal based on only one of the two photoelectric conversion units provided corresponding to the same microlens is read out. Phase difference detection can be realized by performing difference processing between two pixel signals by reading a pixel signal based only on the photoelectric conversion unit PC1 from one pixel and reading a pixel signal based only on PC2 for another pixel. Therefore, for some pixels, the photoelectric conversion unit on the left side in FIG. 2 may be PC2, and for some pixels, the photoelectric conversion unit on the right side in FIG. 2 may be arranged as PC2.

The operation of the solid-state image sensor 1000 is not limited to the above-mentioned operation, and which pixel is used to read the image pickup signal and which pixel is used to read the phase difference detection signal is, for example, when shooting a still image or when shooting a moving image. It may be switched depending on the case, or may be switched according to the number of pixels for reading the pixel signal.

As described above, according to the present embodiment, it is possible to obtain an image pickup signal and a phase difference detection signal. The pixel according to the present embodiment includes two partial electrodes controlled independently of each other (here, the pixel electrode 303), so that this pixel can be used as both an image pickup pixel and a phase difference detection pixel. can. By doing so, unlike Patent Document 1, it is possible to dynamically change the position of the phase difference detection pixel. Further, in the structure described in Patent Document 1, since a light-shielding film is provided so as to cover a part of the phase difference detection pixel, there is a possibility that the optical characteristics are different from those of the image pickup pixel. On the other hand, according to the pixel according to the present embodiment, there is an advantage that the pixel used as the phase difference detection pixel and the pixel used as the image pickup pixel can have the same optical characteristics.

(Second embodiment)
FIG. 7 is a diagram showing a pixel array 110 according to the present embodiment. Here, a case where pixels of 4 rows × 4 columns are arranged will be described.

Here, the pixels in the first column from the left and the pixels in the first column from the right are fixedly used as the imaging pixels, and the two columns in between are switched to either the phase difference detection pixel or the imaging pixel. An example to be used will be described.

Each pixel 100a in the first column from the left and the first column from the right has the configuration shown in FIG. 3 by fixing the signal pADD to the H level or fixing the control node of the changeover switch 405 to the power supply. , Operates as a pixel for imaging.

For each pixel 100b in the second column from the left, the left side in the figure is the photoelectric conversion unit PC2, and for each pixel 100c in the second column from the right, the right side in the figure is the photoelectric conversion unit PC2. As a result, the phase difference detection operation can be realized in the second column from the left and the second column from the right.

The pixels in the second column from the left and the pixels in the second column from the right may be operated as imaging pixels depending on the operation mode. For example, it can be operated as a phase difference detection pixel when shooting a moving image, and can be operated as an imaging pixel when shooting a still image. Further, for example, the pixels 100b and 100c may be switched between operating as the phase difference detection pixel and operating as the imaging pixel by the user's operation.

(Third embodiment)
FIG. 8 shows a configuration example of the solid-state image sensor according to the present embodiment. The same reference numerals are given to the elements common to the solid-state image sensor shown in FIG. 1. In the following, the differences from the configuration of FIG. 1 will be mainly described.

The solid-state image sensor according to the present embodiment is different from the solid-state image sensor shown in FIG. 1 in that each pixel 100 has independent signal readout circuits 400a and 400b for each photoelectric conversion unit, and each pixel array has one row. It differs in that two vertical signal lines 130a and 130b are provided.

FIG. 9 is an equivalent circuit diagram for showing a configuration example of the pixel 100 according to the present embodiment. The switching transistor is eliminated from the pixel 100 shown in FIG. 3, and an amplification transistor and a selection transistor are added respectively. A signal reading circuit 400a is provided for the photoelectric conversion unit PC1, and the output of the signal reading circuit 400a is supplied to the vertical signal line 130a. The signal readout circuit 400a includes an amplification transistor 403a, a selection transistor 404a, a reset transistor 401a, and a drive capacitance 402a. When the selection transistor 404a is turned on, the amplification transistor 403a operates as a source follower circuit together with the constant current source 180a provided in the vertical signal line 130a. Similarly, a signal reading circuit 400b is provided for the photoelectric conversion unit PC2, and the output of the signal reading circuit 400b is supplied to the vertical signal line 130b. The signal readout circuit 400b includes an amplification transistor 403b, a selection transistor 404b, a reset transistor 401b, and a drive capacitance 402b. When the selection transistor 404b is turned on, the amplification transistor 403b operates as a source follower circuit together with the constant current source 180b provided in the vertical signal line 130b.

In this embodiment, since two vertical signal lines 130a and 130b are provided in each row of the pixel array 110, signals based on the two photoelectric conversion units PC1 and PC2 provided in the same pixel 100 can be used. It can be read in parallel. Therefore, the signal readout circuits 400a and 400b are controlled by a common signal.

FIG. 10 is a cross-sectional view of the pixel 100 according to the present embodiment. As is clear from the figure, a signal readout circuit is provided for each of the two photoelectric conversion units provided under the same microlens.

FIG. 11 is a timing diagram for explaining the operation according to the present embodiment. Also in this embodiment, the rolling shutter operation will be described as an example. The operation shown in FIG. 6 is that the signals based on the two photoelectric conversion units are read out in both the nth line and the (n + 1) line.

In the present embodiment, at time t4, a signal based on each of the two photoelectric conversion units is sample-held in the column signal processing unit. CDS (Correlated Double Sampling) processing can be performed by taking the difference between these signals and the signal sample-held by the column signal processing unit at time t2. By adding the signals after the difference processing, a signal based on the two photoelectric conversion units can be obtained, which can be used as an imaging signal. On the other hand, each of the signals after the difference processing can be used as a phase difference detection signal. Therefore, it is possible to detect the phase difference while acquiring the imaging signal.

The same applies to the signal sample-held at time t12.

Similar to the first embodiment, the present embodiment can also be used as both an image pickup pixel and a phase difference detection pixel by providing two pixel electrodes 303 in which the pixels are controlled independently of each other. can. By doing so, it is possible to dynamically change the position of the phase difference detection pixel. Further, according to the present embodiment, since each pixel has a signal readout circuit, a phase difference detection signal and an image pickup signal can be obtained in parallel.

(Fourth Embodiment)
FIG. 12 is a block diagram for showing a configuration example of the solid-state image sensor according to the present embodiment. Hereinafter, the differences from the first embodiment will be mainly described.

It differs from the solid-state image sensor shown in FIG. 1 in that it has two counter electrodes 307a and 307b and one pixel electrode 303 for each pixel 100, and it does not have a changeover switch 405. Further, the bias voltage given to the drive capacitance is also different in that it is a fixed bias voltage. In the first embodiment, an example in which each pixel has two pixel electrodes as partial electrodes that can be controlled independently of each other has been described, but in the present embodiment, as partial electrodes that can be controlled independently of each other, Two counter electrodes are used.

The two counter electrodes 307a and 307b are configured to be independently controllable, and the row drive circuit 120 supplies bias voltages Vsa and Vsb to the two counter electrodes 307a and 307b. On the other hand, the pixel electrode 303 is common to the two photoelectric conversion units.

FIG. 13 is a cross-sectional view of the pixel 100 according to the present embodiment. In FIG. 2, one pixel is provided with one counter electrode 307, whereas in the present embodiment, each pixel has two counter electrodes 307a and 307b. Further, in FIG. 2, the two pixel electrodes 303a and 303b provided are shared as one pixel electrode 303 in the present embodiment. Along with this, the changeover switch 405 has disappeared, and the two reset transistors 401a and 401b have also become one. In the present embodiment, each pixel has photoelectric conversion units PC1 and PC2 composed of a pixel electrode 303 and counter electrodes 307a and 307b.

The two counter electrodes 307a and 307b provided corresponding to the same microlens are arranged at a distance d from each other to form two photoelectric conversion units. Although not shown in the figure, the facing electrodes of adjacent pixels may be arranged at a distance D larger than the distance d. The facing electrode 307a of a certain pixel is provided at a distance d from another facing electrode 307b of this pixel, and is provided at a distance D from the facing electrode 307b of an adjacent pixel. By arranging the counter electrode in this way, it is possible to suppress the charge generated in response to the light incident on a certain pixel from being accumulated in the photoelectric conversion unit of the adjacent pixel. When each pixel has a color filter, the effect of reducing color mixing can be obtained. The color filter is provided, for example, between the counter electrode and the microlens. Further, by providing a light-shielding film between two adjacent pixels between the color filter and the counter electrode 307, color mixing can be further suppressed. Further, a protective layer may be provided between the color filter and the microlens to reduce the step caused by forming the color filter.

FIG. 14 is an equivalent circuit diagram of the pixel 100 according to the present embodiment. In this embodiment, one node of the drive capacitance 103 is connected to the node N1 and the other node is fixed to the ground potential. Further, bias voltages Vsa and Vsb are supplied to the counter electrodes 307a and 307b, respectively.

FIG. 15 is a potential diagram of a photoelectric conversion unit for explaining a signal reading operation according to the present embodiment. Here, for the sake of simplicity, the operation will be described focusing on one photoelectric conversion unit PC1.

The reading operation of the pixel 100 is realized by performing the following operations a) to f).
a) Reset before storage b) Photo charge storage c) Reset after storage d) N signal reading e) Charge transfer f) S signal reading

In the following, each of the above steps will be described in detail.

a) Reset before accumulation With the bias voltage Vsa of 5 [V] applied to the counter electrode 307, the node N1 is reset to 3 [V] by turning on the reset transistor 401. After that, when the reset transistor 401b is turned off, kTC noise (kTC1) is generated due to the operation of the reset transistor. As a result, the potential of the node N1, that is, the pixel electrode 303 becomes 3 [V] + kTC1 (FIG. 15A).

b) Photocharge accumulation When light is incident on the photoelectric conversion layer 305 and the pre-accumulation reset is completed, the photocharge accumulation operation starts. The bias voltage Vsa is maintained at 5 [V] during the period of photocharge accumulation. Therefore, the potential of the pixel electrode 303b becomes a negative potential with respect to the counter electrode 307 to which the voltage of 3 [V] is applied. Therefore, the electrons in the photoelectric conversion layer 305 are guided toward the counter electrode 307 and are discharged from the counter electrode 307 via the blocking layer 306. On the other hand, the hole is guided toward the pixel electrode 303. Since there is a blocking layer 306, injection from the counter electrode 307 into the photoelectric conversion layer 305 is not performed (FIG. 15 (b-1)).

When the photoelectric conversion layer 305 absorbs incident light, electron-hole pairs are generated according to the amount of incident light. The generated electrons are discharged from the counter electrode 307, while the generated holes move in the photoelectric conversion layer 305 and reach the interface with the interlayer insulating layer 304. However, since the holes cannot move in the interlayer insulating layer 304, they are accumulated in the photoelectric conversion layer 305 (FIG. 15 (b-2)). The holes thus accumulated are used as signal charges based on the incident light. Due to the holes accumulated in the photoelectric conversion layer 305, the potential of the node N2 rises by Vp, and the potential of the node N1 becomes 3 [V] + kTC1 + Vp1.

c) Reset after accumulation The reset transistor 401 is temporarily turned on to reset the node N1 to 3 [V]. Since noise (kTC2) is generated with the operation of the reset transistor 401, the potential of the node N2 becomes 3 [V] + kTC2. The noise kTC1 generated by the pre-accumulation reset and the noise kTC2 generated by the post-accumulation reset are so-called random noise components that do not correlate with each other.

Even if the node N1 is reset by the reset transistor 401, the holes accumulated in the photoelectric conversion layer 305 remain in the photoelectric conversion layer 305 (FIG. 15 (c)).

d) N signal read-out The selection transistor 404 is turned on, and a signal corresponding to the potential of the node N1 at this time is output to the vertical signal line 130. The output signal is held by, for example, a column signal processing unit.

e) Charge transfer The bias voltage Vsa applied to the counter electrode 307a is changed from 5 [V] to 0 [V]. As a result, the potential of the node N1 fluctuates. The amount of fluctuation of this potential is determined by the ratio of the capacity of the photoelectric conversion unit to the capacity value of the drive capacity 402. Assuming that the capacitance value of the photoelectric conversion unit is C1, the capacitance value of the drive capacitance 402 is C2, and the positive change amount of the bias voltage Vsa is ΔVb, the fluctuation amount ΔVN1 of the potential of the node N1 is expressed by the following equation. ..
ΔVN1 = ΔVsa × C1 / (C1 + C2) ... (1)

In the present embodiment, assuming that the capacitance value C1 of the drive capacitance 402 is four times the capacitance value C2 of the photoelectric conversion unit, the amount of change in the potential of the node N1 when the bias voltage Vsa is changed by 5 [V] is 4. It becomes [V].

When the potential of the node N1 rises by 4 [V] to 5 [V] + kTC2, the potential of the node N1 and the potential of the counter electrode 307a are reversed. As a result, the slope of the potential in the photoelectric conversion layer 305 is reversed. (FIG. 15 (e-1)). As a result, electrons are injected from the counter electrode 307 into the photoelectric conversion layer 305 via the blocking layer 306. Further, the holes accumulated in the photoelectric conversion layer 305 are guided toward the counter electrode 307a, and recombine with the electrons in the blocking layer 306 to disappear. As a result, all the holes accumulated in the photoelectric conversion layer 305 are discharged from the photoelectric conversion layer 305. That is, complete transfer is performed by completely depleting the photoelectric conversion layer 305 (FIG. 15 (e-2)).

Next, when the bias voltage Vsa is set to 5 [V] again, the potential of the node N1 becomes negative with respect to the potential of the counter electrode 307. Therefore, when the bias voltage Vsa is 0 [V], the photoelectric conversion layer 305 The electrons injected into the capacitor are discharged from the photoelectric conversion layer 305 via the blocking layer 306. Since the amount of electrons emitted in this way is ideally equal to the amount of electrons injected into the photoelectric conversion layer 305, it does not affect the reading of the signal. By setting the bias voltage Vsa to 5 [V], the potential of the node N1 also tries to return to 3 [V] + kTC2, but because the blocking layer 306 is provided between the counter electrode 307 and the photoelectric conversion layer 305. In addition, the holes are not injected into the photoelectric conversion layer 305. Therefore, the signal due to the hole accumulated in the photoelectric conversion layer 305 by the optical charge accumulating operation remains as an optical signal component Vp, so that the potential of the node N1 becomes 3 [V] + kTC2 + Vp.

f) The S signal reading selection transistor 404 is turned on, and a signal corresponding to the potential of the node N1 at this time is output to the vertical signal line 130. The output signal is held by, for example, a column signal processing unit. When the signal obtained in this step and the signal obtained by reading the N signal in d) are differentially processed, the noise component kTC2 is canceled out, and as a result, a signal corresponding to the optical signal component Vp is obtained.

The selection transistor 404 may be kept on after reading the N signal.

By the above operation, the pixel signal can be read out.

FIG. 18 is a potential diagram of a photoelectric conversion unit for explaining the charge discharge operation according to the present embodiment. In the figure, the lower the value, the lower the potential for electrons. In the figure, the potential of each region is drawn in the order of the counter electrode 307a, the photoelectric conversion layer 305, the interlayer insulating layer 304, and the pixel electrode 303 from the left. Here, the blocking layer 306 is omitted for the sake of simplicity. In the figure, black circles represent electrons and white circles represent holes.

The difference from the pixel signal readout operation described with reference to FIG. 15 is the bias applied to the counter electrode 307a during the photocharge accumulation period of (b-1) and (b-2) shown in FIG. It is a point where Vsa is set to 0 [V] (FIG. 16 (b-1), FIG. 16 (b-2)). When the bias voltage Vsa = 0 [V] is applied to the counter electrode 307a, the pixel electrode has a positive potential with respect to the counter electrode. Therefore, when light is incident on the photoelectric conversion layer 305, the generated holes are guided to the counter electrode by the electric field between the pixel electrode and the counter electrode and discharged.

On the other hand, the electrons generated in the photoelectric conversion layer 305 are guided toward the interlayer insulating layer 304 by the electric field between the pixel electrode and the counter electrode, but are accumulated at the interface between the photoelectric conversion layer 305 and the interlayer insulating layer 304. However, the accumulated electrons are discharged from the counter electrode by resetting the potential of the pixel electrode 303 to 3 [V] by the reset transistor 401 in the step of FIG. 5 (c). As a result, the electric charge generated in the photoelectric conversion layer 305 in response to the incident light has both holes and electrons discharged from the counter electrode, so that the optical signal component Vp becomes 0.

An example of the operation of the solid-state image sensor 1000 in the present embodiment will be described. FIG. 17 is a timing diagram relating to the operation related to the pixels in the nth row and the (n + 1) th row in the pixel array when the so-called rolling shutter operation is performed. Here, the pixel signals based on the two photoelectric conversion units PC1 and PC2 are read from the pixel on the nth row, and the pixels based on only one of the two photoelectric conversion units PC2 from the pixel on the (n + 1) row. The operation of reading a signal will be described.

Before the start of HBLNK (n), which is the horizontal blanking period of the pixel in the nth row, the charge generated by the photoelectric conversion is accumulated in the photoelectric conversion units PC1 and PC2 of the pixel in the nth row, that is, It is assumed that the state is as shown in FIG. 15 (b-1).

At time t1, the signals pSEL (n) and pRES (n) become H level. As a result, the pixel in the nth row is selected, the signal from the pixel in the nth row appears on the vertical signal line 130, and the node N1 is reset to 3 [V]. That is, the state shown in FIG. 15 (b-2) is obtained.

When the signal pTN is temporarily set to the H level from the time t2, the signal corresponding to the potential of the node N1 at this time is sample-held by the signal processing unit 140. That is, N signal reading is performed.

By temporarily setting the bias voltages Vsa (n) and Vsb (n) to the L level from time t3, the potential of the node N1 fluctuates according to the amount of electric charge accumulated in the photoelectric conversion units PC1 and PC2. This is the charge transfer operation shown in FIGS. 15 (e-1) and 15 (e-2).

When the signal pTS is temporarily set to the H level from the time t4, the signal corresponding to the potential of the node N1 at this time is sample-held by the signal processing unit 140. That is, the S signal is read out. Since the S signal read at this time is a signal based on the two photoelectric conversion units PC1 and PC2 provided under the same microlens, it can be used as an image pickup signal.

When the signal pRES (n) reaches the H level at time t5, the node N1 is reset to 3 [V] again. That is, the pre-accumulation reset shown in FIG. 15A is performed.

When the signal pSEL (n) becomes low level at time t6, the selection state of the pixel on the nth row is canceled.

After that, when the horizontal scanning period HSCAN (n) starts, the signal PHST becomes H level at time t7. In response to this, the column selection circuit 150 starts scanning the column signal processing unit. Since the column selection circuit 150 operates in synchronization with a clock signal (not shown), the signal from the column signal processing unit is sequentially output from the output amplifier 170.

Until the bias voltage Vsa (n + 1) reaches the H level (here, 5 [V]) at time t8, the electric charge generated in the photoelectric conversion unit is discharged without being accumulated in the photoelectric conversion layer.

At time t9, the signals pSEL (n + 1) and pRES (n + 1) become H level. As a result, the pixel on the nth row is selected, and the signal from the pixel on the n + 1th row appears on the vertical signal line 130. Further, when the signal pRES (n + 1) becomes H level, the node N1 is reset to 3 [V].

When the signal pTN is temporarily set to the H level from the time t10, the signal corresponding to the potential of the node N2 at this time is sample-held by the signal processing unit 140. That is, N signal reading is performed.

By temporarily setting the bias voltages Vsa (n + 1) and Vsb (n + 1) to the L level from time t11, the potential of the node N1 fluctuates according to the amount of electric charge accumulated in the photoelectric conversion units PC1 and PC2. This is the charge transfer operation shown in FIGS. 15 (e-1) and 15 (e-2). Since the photoelectric conversion unit PC1 is in a state where the electric charge is not accumulated until the time t8, the contribution of the photoelectric conversion unit PC1 to the signal component is only the electric charge accumulated from the time t8 to the time t11.

When the signal pTS is temporarily set to the H level from the time t12, the signal corresponding to the potential of the node N1 at this time is sample-held by the signal processing unit 140. That is, the S signal is read out. Since the S signal read at this time is a signal based only on PC2 of the two photoelectric conversion units PC1 and PC2 provided under the same microlens, it can be used as a phase difference detection signal.

When the signal pRES (n + 1) reaches the H level at time t13, the node N1 is reset to 3 [V] again. That is, the pre-accumulation reset shown in FIG. 15A is performed.

When the signal pSEL (n + 1) becomes low level at time t14, the selection state of the pixel in the n + 1th row is canceled.

After that, when the horizontal scanning period HSCAN (n + 1) starts, the bias voltage Va (n + 1) becomes H level at time t15, and the photoelectric conversion unit PC1 returns to a state in which holes are not accumulated.

Further, after the bias voltage Vsa (n + 1) becomes low level, the signal PHST becomes H level at time t15. In response to this, the column selection circuit 150 starts scanning the column signal processing unit. Since the column selection circuit 150 operates in synchronization with a clock signal (not shown), the signal from the column signal processing unit is sequentially output from the output amplifier 170.

As described above, for the pixel on the nth row, the pixel signal based on the two photoelectric conversion units provided corresponding to the same microlens is read out and used as an image pickup signal. On the other hand, for the pixel in the (n + 1) th row, the pixel signal based on only one of the two photoelectric conversion units provided corresponding to the same microlens is read out and used as a phase difference detection signal. ..

Similar to the first embodiment, the operation of the solid-state image sensor 1000 is not limited to the above-mentioned operation, and which pixel is used to read the image pickup signal and which pixel is used to read the phase difference detection signal is, for example, a still image. It may be switched between the case of shooting a moving image and the case of shooting a moving image, or it may be switched according to the number of pixels for reading a pixel signal.

As described above, according to the present embodiment, it is possible to obtain an image pickup signal and a phase difference detection signal. The pixel according to the present embodiment includes two partial electrodes (here, the counter electrode 307) that are controlled independently of each other, so that the pixel can be used as both an image pickup pixel and a phase difference detection pixel. .. By doing so, unlike Patent Document 1, it is possible to dynamically change the position of the phase difference detection pixel. Further, in the structure described in Patent Document 1, since a light-shielding film is provided so as to cover a part of the phase difference detection pixel, there is a possibility that the optical characteristics are different from those of the image pickup pixel. On the other hand, according to the pixel according to the present embodiment, there is an advantage that the pixel used as the phase difference detection pixel and the pixel used as the image pickup pixel can have the same optical characteristics.

(Fifth Embodiment)
FIG. 18 shows a configuration example of the solid-state image sensor according to the present embodiment. The same reference numerals are given to the elements common to the solid-state image sensor shown in FIG. 1. In the following, the differences from the configuration of FIG. 1 will be mainly described.

The solid-state image pickup device according to the present embodiment is different from the solid-state image pickup device shown in FIG. 1 in that each pixel 100 has two counter electrodes 307a and 307b. Therefore, the row drive circuit 120 is configured to supply the bias Vsa and Vsb applied to the counter electrode in addition to the bias Va and Vb applied to the drive capacitance to the pixels of each row. The two counter electrodes 307a and 307b are arranged so as to face each other so as to sandwich the photoelectric conversion layer with the pixel electrodes 303a and 303b, respectively, thereby forming two photoelectric conversion units PC1 and PC2. In other words, in the present embodiment, the pixel electrode 303 and the counter electrode 307 include partial electrodes that can be controlled independently of each other.

FIG. 19 is an equivalent circuit diagram for showing a configuration example of the pixel 100. In FIG. 3, the bias voltage applied to the counter electrode 307 is only Vs, whereas in the present embodiment, independent bias voltages Vsa and Vsb are applied to the two photoelectric conversion units PC1 and PC2. It is configured as follows.

FIG. 20 is a cross-sectional view for showing a configuration example of the pixel 100. The only difference from FIG. 2 is that the counter electrode 307 is separated into the counter electrodes 307a and 307b. By providing, for example, an insulating member or a light-shielding member between the separated facing electrodes 307a and 307b, crosstalk between the two photoelectric conversion units can be suppressed.

FIG. 21 is a timing diagram for explaining the operation of the solid-state image sensor according to the present embodiment. In this embodiment, a rolling shutter is performed to obtain a pixel signal based on the two photoelectric conversion units from the pixel in the nth row, while one of the two photoelectric conversion units is obtained from the pixel in the (n + 1) row. To obtain a pixel signal based on.

In the present embodiment, the signals other than the bias voltages Vsa and Vsb applied to the counter electrode are the same as those shown in FIG. The bias voltages Vsa and Vsb are the same as those shown in FIG. By doing so, the pixel signal based on the two photoelectric conversion units is obtained from the pixel in the nth row, while the pixel based on one of the two photoelectric conversion units is obtained from the pixel in the (n + 1) row. You can get a signal.

The pixel according to the present embodiment includes two pixel electrodes 303 and two counter electrodes 307 that are controlled independently of each other, so that the pixel can be used as both an image pickup pixel and a phase difference detection pixel. can. By doing so, unlike Patent Document 1, it is possible to dynamically change the position of the phase difference detection pixel. Further, in the structure described in Patent Document 1, since a light-shielding film is provided so as to cover a part of the phase difference detection pixel, there is a possibility that the optical characteristics are different from those of the image pickup pixel. On the other hand, according to the pixel according to the present embodiment, there is an advantage that the pixel used as the phase difference detection pixel and the pixel used as the image pickup pixel can have the same optical characteristics.

(Sixth Embodiment)
FIG. 22 is a block diagram for showing a configuration example of the solid-state image sensor according to the present embodiment. In the solid-state image sensor shown in FIG. 18, all of the pixels 100 in 4 rows × 4 columns have two counter electrodes 307a and 307b. On the other hand, in the present embodiment, among the illustrated pixels, the pixels in the (m + 1) th column and the (m + 2) th column have two counter electrodes 307a and 307b, but the mth column and (m + 3). The pixels in the row are configured to have one counter electrode 307. Further, in FIG. 18, the two counter electrodes 307a and 307b of each pixel have a translational symmetry relationship in the pixel array, but in the present embodiment, the (m + 1) th column and the (m + 2) th column. The counter electrodes 307a and 307b of the pixel are in a line-symmetrical relationship.

FIG. 23 shows a cross-sectional view of the pixels in the m-th column and the (m + 3) column. As shown in the figure, one pixel electrode 303 and one counter electrode 307 are provided, and one photoelectric conversion unit PC is configured by sandwiching the photoelectric conversion layer 305 between them.

FIG. 24 is an equivalent circuit diagram of the pixels in the m-th column and the (m + 3) column. From the pixel configuration shown in FIG. 3, the reset transistor 401b, the drive capacitance 402b, and the changeover switch 405 are eliminated.

The pixels in the (m + 1) column are the same as the equivalent circuit diagram shown in FIG. In the equivalent circuit diagram shown in FIG. 14, the pixels in the (m + 2) column are configured to supply the bias voltage Vsb to the photoelectric conversion unit PC1 and supply the bias voltage Vsa to the photoelectric conversion unit PC2.

The operation according to the present embodiment will be described with reference to the timing diagram of FIG. 25.

An imaging signal is obtained from each pixel on the nth row. The m-th column and the (m + 3) column perform the same operation as the n-th row operation shown in FIG. 17, but are different in the present embodiment in that the pixel has only one photoelectric conversion unit. From the pixels in the (m + 1) th column and the (m + 2) th column, the same operations as those in the nth row shown in FIG. 17 are performed to convert the charges accumulated in the two photoelectric conversion units PC1 and PC2. The signal based on is obtained.

FIG. 25 is a timing diagram for explaining the operation according to the present embodiment. For the (n + 1) th row, the pixels in the mth column and the (m + 3) th column can obtain the imaging signal in the same manner as in the nth row. The signal based on the photoelectric conversion unit on the right side in FIG. 22 is read out in the (m + 1) column, and on the left side in FIG. 22 in the (m + 2) column. The signal based on the photoelectric conversion unit on the left side of the pixel in the (m + 1) column and the photoelectric conversion unit on the right side of the pixel in the (m + 2) column is discharged from the counter electrode without being read out. By doing so, the signals obtained from the pixels in the (m + 1) and (m + 2) rows are used as the phase difference detection signal.

For the (n + 2) th line and subsequent lines, it may be set whether the same operation as the nth line or the same operation as the (n + 1) line is performed depending on the accuracy required for the phase difference detection. That is, according to the present embodiment, it is possible to dynamically switch between the line for obtaining only the image pickup signal and the line for obtaining the phase difference detection signal.

Also in the present embodiment, a part of the pixel is provided with two partial electrodes (here, the counter electrode 307) which are controlled independently of each other, so that this pixel can be used as both an image pickup pixel and a phase difference detection pixel. Can be used. By doing so, unlike Patent Document 1, it is possible to dynamically change the position of the phase difference detection pixel. Further, in the structure described in Patent Document 1, since a light-shielding film is provided so as to cover a part of the phase difference detection pixel, there is a possibility that the optical characteristics are different from those of the image pickup pixel. On the other hand, according to the pixel according to the present embodiment, there is an advantage that the pixel used as the phase difference detection pixel and the pixel used as the image pickup pixel can have the same optical characteristics.

(7th Embodiment)
FIG. 26 is a diagram for explaining the cross-sectional structure of the pixel according to the present embodiment. The difference from each of the above-described embodiments is that a plurality of photoelectric conversion units are laminated. For the sake of brevity, FIG. 26 does not show the interlayer insulating layer 304 and the blocking layer 306.

FIG. 26 shows a configuration in which three photoelectric conversion units PC1, PC2, and PC3 are stacked in order from the semiconductor substrate toward the microlens. The photoelectric conversion unit PC1 includes a photoelectric conversion unit PC1a and PC1b. Such a configuration can be obtained by using a light-transmitting material for each layer interposed between the photoelectric conversion layers 305a, 305b, and 305c. An interlayer insulating layer INS is provided between the pixel electrode 303 of the photoelectric conversion unit PC3 and the counter electrode 307 of the photoelectric conversion unit PC2. Similarly, an interlayer insulating layer INS is provided between the pixel electrode 303 of the photoelectric conversion unit PC2 and the counter electrode 307 of the photoelectric conversion unit PC1. Further, an interlayer insulating layer INS is provided between the counter electrode 307 of the photoelectric conversion unit PC3 and the microlens 309.

Of the three photoelectric conversion units, the uppermost layer absorbs the blue component of the incident light, the second layer absorbs the green component, and the lowermost layer absorbs the red component. When set, the signal components of B, G, and R can be obtained from the light incident on the same microlens without providing a color filter.

In the present embodiment, the photoelectric conversion unit PC2 and PC3 have one pixel electrode and one counter electrode, and the photoelectric conversion unit PC1 includes one counter electrode and two pixel electrodes 303a and 303b. That is, the configuration is such that the imaging signal can be acquired from the photoelectric conversion unit of the second layer close to the microlens of the three layers, and the phase difference detection signal can be acquired from the photoelectric conversion unit PC1 of the lowermost layer.

A signal readout circuit is provided corresponding to each photoelectric conversion layer. As the signal readout circuit, the one described in each of the above embodiments may be applied, or a signal readout circuit having a different configuration may be used.

FIG. 27 shows a configuration example of the signal readout circuit. FIG. 27A is an equivalent circuit diagram of a signal readout circuit corresponding to the photoelectric conversion units PC2 and PC3 among the three photoelectric conversion units PC1 to PC3. A transfer transistor 406 is provided in the configuration of one of the photoelectric conversion units and the signal readout circuit in the structure shown in FIG. FIG. 27B is an equivalent circuit diagram of a signal readout circuit corresponding to the three photoelectric conversion units PC1. From the structure shown in FIG. 3, one photoelectric conversion unit, a reset transistor 401b, a drive capacitance 402b, and a changeover switch 405 are eliminated, and transfer transistors 406a and 406b are provided. The outputs of the signal readout circuits provided corresponding to each photoelectric conversion unit are connected to different vertical signal lines. Similar to each of the above embodiments, the pixels provided in the same row of the pixel array 110 share a vertical signal line.

FIG. 28 shows a timing diagram according to the present embodiment. In this embodiment, an operation of reading an imaging signal from the photoelectric conversion units PC2 and PC3 and reading a phase difference detection signal and an imaging signal from the photoelectric conversion unit PC1 will be described.

At time t1, the signal pSEL (n) and the signal pRES (n) become H level. As a result, the pixel in the nth row is in the selected state, and the node N1 is in the reset state. By sample-holding the signal after the node N1 is reset in the column signal processing unit, the above-mentioned N signal reading operation is performed.

When the signal pTX1 (n) and the signal pTXA1 (n) are set to H level at time t2, and then the bias voltage Va (n) supplied to the drive capacitance is set to H level at time t3, the photoelectric conversion units PC2, PC3 and photoelectric are set to H level. Signals corresponding to the amount of electric charge stored in the conversion unit PC1a are output from the amplification transistor 403, respectively. By sample-holding the signal output from the amplification transistor 403 in the column signal processing unit, the above-mentioned S signal reading operation is performed. For the photoelectric conversion units PC2 and PC3, a noise-reduced imaging signal can be obtained by taking a difference from the signal obtained by reading the N signal. On the other hand, for the photoelectric conversion unit PC1a, a phase difference detection signal with reduced noise can be obtained by taking a difference from the signal obtained by reading the N signal.

When the signal pTXB1 (n) becomes H level at time t4 and then the bias voltage Va (n) becomes H level at time t5, the signal based on the charge accumulated in the photoelectric conversion unit PC1b is transmitted to the photoelectric conversion unit PC1a. It is superimposed on the signal based on the accumulated charge. That is, since it is a signal based on the total charge accumulated in the photoelectric conversion units PC1a and PC1b, the signal output from the amplification transistor 403 can also be used as an image pickup signal. This signal is sample-held by the column signal processing unit. Further, by taking the difference from the signal sample-held before the time t4 after the signal pTXA1 (n) becomes low level, the signal based on the charge accumulated only in the photoelectric conversion unit PC1b can be obtained. Can be calculated. As a result, both the image pickup signal and the phase difference detection signal can be obtained from the photoelectric conversion unit PC1.

Since the operations related to the (n + 1) th line and subsequent lines are the same as those of the nth line, the description thereof will be omitted.

FIG. 29 is a diagram showing another configuration example of the signal readout circuit according to the present embodiment. FIG. 29A is an equivalent circuit diagram of a signal readout circuit corresponding to the photoelectric conversion units PC2 and PC3 among the three photoelectric conversion units PC1 to PC3. FIG. 29B is an equivalent circuit diagram of a signal readout circuit corresponding to the three photoelectric conversion units PC1. The outputs of the signal readout circuits provided corresponding to each photoelectric conversion unit are connected to different vertical signal lines. Similar to each of the above embodiments, the pixels provided in the same row of the pixel array 110 share a vertical signal line.

In the signal readout circuit shown in FIG. 29 (a), the transfer transistor 406 and the drive capacitance are not connected to the node N1 but are connected to the node N1 via the second transfer transistor 407 (a). ) Is different from the configuration.

Similarly, in the signal readout circuit shown in FIG. 29 (b), the transfer transistors 406a and 406b and the drive capacitance are not connected to the node N1, but are connected to the node N1 via the second transfer transistors 407a and 407b, respectively. This is different from the configuration shown in FIG. 27 (b).

Next, the operation of the signal readout circuit shown in FIG. 29 will be described with reference to FIG. 30.

At time t1, the signals pRES (n) and pRES (n) become H level, and the signals pTX2 (n) and pTXA2 (n) become H level. This resets node N1. By sample-holding the signal after the node N1 is reset in the column signal processing unit, the above-mentioned N signal reading operation is performed.

When the signals pTX1 (n) and pTXA1 (n) reach the H level at time t2, and then the bias voltage Va (n) supplied to the drive capacitance temporarily reaches the H level from time t3, the photoelectric conversion units PC2 and PC3 A voltage corresponding to the amount of electric charge stored in the photoelectric conversion unit PC1a is held in the drive capacity 402.

When the signals PTX2 (n) and PTXA2 (n) reach the H level at time t4, the drive capacitance 402 is connected to the node N1. As a result, the signal corresponding to the voltage held in the drive capacitance 402 is output from the amplification transistor 403. By sample-holding the signal output from the amplification transistor 403 in the column signal processing unit, the above-mentioned S signal reading operation is performed. For the photoelectric conversion units PC2 and PC3, a noise-reduced imaging signal can be obtained by taking a difference from the signal obtained by reading the N signal. On the other hand, for the photoelectric conversion unit PC1a, a phase difference detection signal with reduced noise can be obtained by taking a difference from the signal obtained by reading the N signal.

In the subsequent operation of the horizontal blanking period HBLNK (n + 1), the signals pTXB1 and pTXB2 are replaced by the signals pTXA1 and pTXA2 in the horizontal blanking period HBLNK (n) instead of keeping the low level of the signals pTXA1 and pTXA2. It becomes the same waveform as. As a result, for the photoelectric conversion unit PC1, a signal based only on the photoelectric conversion unit PC1b is read out. This signal is used as a phase difference detection signal, and can be used as an image pickup signal by adding it to the signal read from the photoelectric conversion unit PC1a to HBLNK (n). That is, according to the present embodiment, while acquiring the imaging signal from all of the three photoelectric conversion units PC1 to PC3, the phase difference detection signal can also be acquired from the photoelectric conversion unit PC1 in the lowermost layer.

The imaging signal based on PC2 and PC3 is read out twice during this operation, but an image may be formed using only the signal read out during the horizontal blanking period HBLNK (n), or the horizontal blanking may be formed. The image may be formed by adding the signals read out to the ranking period HBLNK (n + 1).

FIG. 31 is a schematic plan view for showing an arrangement example of the signal readout circuit according to the present embodiment. Since the signal readout circuit 400-1 corresponding to the photoelectric conversion unit PC1 has more elements than the signal readout circuits 400-2 and 400-3 corresponding to the photoelectric conversion units PC2 and PC3, as shown in FIG. 31 (a). In addition, it becomes a larger area. The arrangement of the signal readout circuit and the arrangement of the pixel electrodes 303a and 303b can be freely determined. For example, as shown in FIG. 31B, the pixel electrode 303a is arranged so as to cover the signal readout circuit 400-1 and the signal readout circuit 400-2, and the pixel electrode 303b is the signal readout circuit 400-1 and the signal readout circuit. It may be arranged so as to cover 400-3.

In the present embodiment, the configuration in which three photoelectric conversion units PC1 to PC3 are stacked in the direction from the semiconductor substrate to the microlens has been described, but the number of photoelectric conversion units is not limited to three, and may be two or four. It may be more than one.

Further, in the present embodiment, the case where the phase difference detection signal is obtained only from the photoelectric conversion unit of the lowermost layer is illustrated, but the phase difference detection signal may be obtained from other layers as well. However, in order to detect the phase difference, it is preferable that the microlens is designed so that the incident light focuses on the interface on the counter electrode 307 side of the photoelectric conversion layer 305 or the inside of the photoelectric conversion layer 305. Therefore, it is difficult to acquire the phase difference detection signal using the photoelectric conversion unit closest to the microlens, so the phase difference detection signal is acquired from the photoelectric conversion unit excluding the photoelectric conversion unit closest to the microlens. Is preferable.

Also in the present embodiment, by providing the two counter electrodes 307 in which the pixels are controlled independently of each other, the pixels can be used as both the image pickup pixel and the phase difference detection pixel. By doing so, unlike Patent Document 1, it is possible to dynamically change the position of the phase difference detection pixel. Further, in the structure described in Patent Document 1, since a light-shielding film is provided so as to cover a part of the phase difference detection pixel, there is a possibility that the optical characteristics are different from those of the image pickup pixel. On the other hand, according to the pixel according to the present embodiment, there is an advantage that the pixel used as the phase difference detection pixel and the pixel used as the image pickup pixel can have the same optical characteristics.

(8th Embodiment)
FIG. 32 shows the cross-sectional structure of the pixel according to the present embodiment. The difference from FIG. 26 is that one signal readout circuit is provided for each of the three stacked photoelectric conversion units.

FIG. 33 shows an equivalent circuit diagram of the signal readout circuit according to the present embodiment. FIG. 33A is a circuit similar to the signal readout circuit of FIG. 27, and is similar to the signal readout circuit of FIG. 27 in that a common amplification transistor 403 is provided for the plurality of photoelectric conversion units PC1 to PC3. It's different. FIG. 33B is a circuit similar to the signal readout circuit of FIG. 29, and is similar to the signal readout circuit of FIG. 29 in that a common amplification transistor 403 is provided for the plurality of photoelectric conversion units PC1 to PC3. It's different. With such a configuration, the scale of the signal readout circuit can be reduced as compared with the configuration described in the seventh embodiment, which is advantageous for increasing the number of pixels of the pixel array and miniaturizing the pixels.

FIG. 34 is a timing diagram for explaining an operation of reading a signal from a three-layer photoelectric conversion unit when the configuration shown in FIG. 33A is used as the signal reading circuit 400.

First, the signal based on the photoelectric conversion unit PC2 is read out. At time t1, the signals pSEL (n) and pRES (n) become H level, and the gate node N1 of the amplification transistor 403 is reset. After the signal pRES (n) changes to the L level, the column signal processing unit sample-holds the signal output to the vertical signal line 130.

At time t2, the signal pTX11 (n) becomes H level, and at time t3 while the signal pTX11 (n) maintains H level, the bias voltage Va applied to the drive capacitance 402 becomes H level. As a result, a signal based on the electric charge accumulated in the photoelectric conversion unit PC2 is output to the vertical signal line 130, and this signal is sample-held by the column signal processing unit. Also in this embodiment, a signal with reduced noise can be obtained by taking a difference from the signal obtained by resetting the node N1.

From time t4, reading of the signal based on the photoelectric conversion unit PC1 starts. At time t4, when the signal pRES (n) reaches the H level, the node N1 is reset again. As a result, the signal output to the vertical signal line 130 is sample-held by the column signal processing unit.

When the signal pTX12 (n) and the bias voltage Va sequentially reach the H level from time t5, a signal based on the charge accumulated in the photoelectric conversion unit PC1a is output to the vertical signal line 130. The signal output to the vertical signal line 130 is sample-held by the column signal processing unit.

When the signal pTX13 (n) and the bias voltage Va sequentially reach the H level from the time t6, the potential of the node N1 changes according to the amount of electric charge accumulated in the photoelectric conversion unit PC1b. As a result, a signal based on the sum of the charges stored in the photoelectric conversion units PC1a and PC1b is output to the vertical signal line 130. The signal output to the vertical signal line 130 is sample-held by the column signal processing unit. As described in the previous embodiment, the signal sample-held between the time t5 and the time t6 is used as the phase difference detection signal, and the signal read by the operation from the time t6 is used for imaging. It can be used as a signal. Further, by taking the difference between the two, a phase difference detection signal based only on the electric charge accumulated in the photoelectric conversion unit PC1b can be obtained.

From the time t7, the signal based on the photoelectric conversion unit PC3 is read out. Since this operation is the same as the operation of reading a signal based on the photoelectric conversion unit PC2, the description thereof will be omitted.

As described above, individual signals can be read out from the laminated photoelectric conversion units PC1 to PC3.

FIG. 35 is a timing diagram for explaining an operation of reading a signal from a three-layer photoelectric conversion unit when the configuration shown in FIG. 33 (b) is used as the signal reading circuit 400. In the present embodiment, the electric charge accumulated in each photoelectric conversion unit is simultaneously transferred to the corresponding drive capacitance, and then a signal is sequentially output from the amplification transistor. In the following, it is assumed that the capacity value of the capacity associated with the node N1 is sufficiently smaller than the capacity value of each drive capacity.

At time t1, the signals pSEL (n) and pRES (n) become H level, and the gate node N1 of the amplification transistor 403 is reset. After the signal pRES (n) changes to the L level, the column signal processing unit sample-holds the signal output to the vertical signal line 130. Since the signals pTX21 (n), pTX22 (n), pTX23 (n), and pTX24 (n) also reach the H level at time t1, the drive capacities 402a to 402d are also reset.

From time t2, the signals pTX11 (n), pTX12 (n), pTX13 (n), pTX14 (n) become H level, and the signals pTX11 (n), pTX12 (n), pTX13 (n), pTX14 (n). The bias voltage Va to the drive capacitance becomes the H level while the H level is maintained, so that the voltage based on the charge accumulated in each photoelectric conversion unit is held in the corresponding drive capacitances 402a to d.

After that, when the signal pTX21 (n) reaches the H level at time t3, the potential of the node N1 fluctuates according to the charge held in the drive capacitance 402a. As a result, the signal output from the amplification transistor is sample-held by the column signal processing unit. This is a signal based on the photoelectric conversion unit PC2.

Next, when the signal pTX22 (n) reaches the H level at time t4, the potential of the node N1 fluctuates according to the charge held in the drive capacitance 402b. As a result, the signal output from the amplification transistor is sample-held by the column signal processing unit. This is a signal based on the photoelectric conversion unit PC1a. At time t4, the charge based on the photoelectric conversion unit PC2 is held in the node N1, but since the capacity value of the capacitance associated with the node N1 is sufficiently smaller than the capacitance value of each drive capacitance, the signal pTX22 (n). ) Does not have to be reset to the H level before the node N1 is reset. When the capacity value of the capacity associated with the node N1 is so large that it cannot be ignored with respect to the capacity value of each drive capacity, it is necessary to reset the node N1 before setting the signal pTX22 to the H level.

After that, the pTX23 (n) and the pTX24 (n) are sequentially set to the H level, and the signal output from the amplification transistor 403 is sample-held by the column signal processing unit.

As described above, individual signals can be read out from the laminated photoelectric conversion units PC1 to PC3.

The order of reading the signals is not limited to the order shown in FIGS. 34 and 35, and the signal based on the photoelectric conversion unit PC1 may be read out prior to the signal based on the photoelectric conversion units PC2 and PC3.

Also in the present embodiment, as in the seventh embodiment, it is preferable to acquire the phase difference detection signal by using the photoelectric conversion unit excluding the photoelectric conversion unit PC3 closest to the microlens. Further, also in the present embodiment, a configuration having two layers or four or more layers of photoelectric conversion units may be used.

This embodiment also has the advantage that the same effect as that of the seventh embodiment can be obtained, and that a signal based on the total amount of electric charges accumulated in the stacked photoelectric conversion units can be read out.

(9th embodiment)
FIG. 36 is a diagram showing a configuration example of an imaging system. The image pickup system 800 includes, for example, an optical unit 810, a solid-state image pickup element 1000, a video signal processing unit 830, a recording / communication unit 840, a timing control unit 850, a system control unit 860, and a reproduction / display unit 870. The image pickup device 820 includes a solid-state image pickup element 1000 and a video signal processing unit 830. As the solid-state image sensor 1000, the solid-state image sensor described in each of the above embodiments is used.

The optical unit 810, which is an optical system such as a lens, forms an image of the subject by forming an image of light from the subject on the pixel array 110 of the solid-state image sensor 1000 in which a plurality of pixels are arranged two-dimensionally. The solid-state image sensor 1000 outputs a signal corresponding to the light imaged on the pixel array 110 at a timing based on the signal from the timing control unit 850. The signal output from the solid-state image sensor 1000 is input to the video signal processing unit 830, which is a video signal processing unit, and the video signal processing unit 830 performs signal processing according to a method determined by a program or the like. The signal obtained by the processing in the video signal processing unit 830 is sent to the recording / communication unit 840 as image data. The recording / communication unit 840 sends a signal for forming an image to the reproduction / display unit 870, and causes the reproduction / display unit 870 to reproduce / display a moving image or a still image. The recording / communication unit 840 also receives a signal from the video signal processing unit 830 and communicates with the system control unit 860, and also has an operation of recording a signal for forming an image on a recording medium (not shown). conduct.

The system control unit 860 comprehensively controls the operation of the imaging system, and controls the driving of the optical unit 810, the timing control unit 850, the recording / communication unit 840, and the reproduction / display unit 870. Further, the system control unit 860 includes, for example, a storage device (not shown) which is a recording medium, in which a program or the like necessary for controlling the operation of the imaging system is recorded. Further, the system control unit 860 supplies, for example, a signal for switching the drive mode and the sensitivity according to the operation of the user into the image pickup system. Specific examples include changing the line to be read and the line to be reset, changing the angle of view due to electronic zoom, shifting the angle of view due to electronic vibration isolation, and the like. When the sensitivity of the image pickup system is switched according to the input of the user, the sensitivity of the solid-state image pickup device 1000 is also switched according to this change. That is, the system control unit 860 has a function as a sensitivity selection unit for selecting the sensitivity of the image pickup system 800, and the sensitivity of the solid-state image pickup device 1000 is switched according to the selected sensitivity.

The timing control unit 850 controls the drive timing of the solid-state image sensor 1000 and the video signal processing unit 830 based on the control by the system control unit 860. Further, the timing control unit 850 can also function as a sensitivity setting unit for setting the photographing sensitivity of the solid-state image sensor 1000.

(others)
In the first embodiment, it has been described that each pixel has two pixel electrodes 303a and 303b. These two pixel electrodes 303a and 303b may be arranged in various arrangements in the pixel. FIG. 37 is a schematic plan view of pixels for explaining an example of arrangement of pixel electrodes. In FIG. 37, the horizontal direction is the direction along the row of the pixel array, and the direction orthogonal to the horizontal direction is the direction along the column of the pixel array.

FIG. 37A is an example in which the pixel electrodes 303a and 303b are arranged in the direction along the row.

FIG. 37B is an example in which the pixel electrodes 303a and 303b are arranged in the direction along the row.

FIG. 37C is an example in which the pixel electrodes 303a and 303b are arranged along a direction forming an angle of 45 ° with respect to a direction along a row and a direction along a column.

By providing a plurality of pixels as shown in FIGS. 37 (a) to 37 (c), phase difference detection can be performed along a plurality of directions in the pixel array. For example, by arranging a plurality of pixels shown in FIG. 37 (a) in a direction along a column and arranging a plurality of pixels shown in FIG. 37 (b) in a direction along a row, an imaging surface can be obtained. Phase difference detection can be realized in the vertical direction and the horizontal direction. In an imaging system such as a digital camera, it is particularly useful because phase difference detection in a plurality of directions is required instead of phase difference detection in only one direction.

37 (d) and 37 (e) show configuration examples in the case where three or more pixel electrodes 303 are provided.

FIG. 37D is an example of having four pixel electrodes and arranging them in 2 rows × 2 columns. By making it possible to control each pixel electrode independently, it is possible to use them separately as shown in FIG. 37 (1) in one operation mode and to operate as shown in FIG. 37 (b) in another operation mode. That is, it is possible to dynamically switch the direction of phase difference detection.

Similarly, in FIG. 37 (e), the set of pixel electrodes operated at the same time can be dynamically switched.

Although the pixel electrode has been described here, the same effect can be obtained by providing the counter electrode in the same manner as shown in FIG. 37.

Further, in each of the above-described embodiments, an example in which the photoelectric conversion layers are continuous, that is, commonly provided for a plurality of photoelectric conversion units included in the same pixel has been described. The photoelectric conversion layer may be separated by a photoelectric conversion layer separating portion including at least one of an insulating member and a light-shielding member. This makes it possible to improve the accuracy of phase difference detection.

Similarly, the photoelectric conversion layer of adjacent pixels may be separated by a photoelectric conversion layer separating portion including at least one of an insulating member and a light-shielding member.

Further, the shape of the microlens provided in each pixel does not have to be the same. For example, the farther the pixel is from the center of the pixel array 110, the closer the incident angle of the light to the pixel is closer to the semiconductor substrate, so that the signal level obtained even if the solid-state image sensor is irradiated with uniform light. Is higher as it is closer to the center of the pixel array. In consideration of this point, by changing the shape of the microlens, it is possible to obtain a uniform signal for a uniform incident light. More specifically, it is conceivable to change the curvature of the microlenses or to make the cross-sectional shape different.

Each of the above-described embodiments is merely exemplary and can be modified without departing from the ideas of the present invention. For example, the embodiments may be combined with each other.

1000 Solid-state image sensor 100 pixels 303 pixel electrode 305 photoelectric conversion layer 307 facing electrode 309 microlens layer 400 signal readout circuit

Claims (14)

It is a photoelectric conversion element
A photoelectric conversion unit including a plurality of pixel electrodes, a photoelectric conversion layer provided on the plurality of pixel electrodes, and a counter electrode provided so as to sandwich the photoelectric conversion layer between the plurality of pixel electrodes. , One microlens that overlaps with the plurality of pixel electrodes in plan view,
The circuit provided on the board and
The capacitance provided in the electric path from the photoelectric conversion unit to the circuit,
A first wiring layer provided between the plurality of pixel electrodes and the substrate,
It has a second wiring layer provided between the first wiring layer and the substrate, and has.
The capacity is
The first wiring provided in the first wiring layer and
A second wiring provided on the second wiring layer and overlapping the first wiring in a plan view,
A photoelectric conversion element characterized by being composed of a first insulating layer formed between the first wiring and the second wiring. It has a third wiring layer provided between the second wiring layer and the substrate, and has a third wiring layer.
The third wiring of the third wiring layer and the second wiring are electrically connected by the fourth wiring.
The photoelectric conversion element according to claim 1, wherein the thickness of the first insulating layer is thinner than the length of the fourth wiring in the direction intersecting the main surface of the substrate. The circuit is an amplification transistor and
The photoelectric conversion element according to claim 1 or 2, wherein the gate of the amplification transistor and the first wiring are electrically connected to each other. The photoelectric conversion element according to claim 2 , wherein the distance between the second wiring layer and the substrate is larger than the distance between the third wiring layer and the substrate. The photoelectric conversion element according to claim 2 or 4 , wherein another wiring layer is provided between the third wiring layer and the substrate. The photoelectric conversion element according to any one of claims 1 to 5, wherein a fixed potential is supplied to the second wiring. The photoelectric conversion element according to claim 6, wherein the fixed potential is a ground potential. The plurality of pixel electrodes have a first pixel electrode and a second pixel electrode.
The amplification transistor comprises a first amplification transistor.
The photoelectric conversion element according to claim 3, wherein the first amplification transistor is configured to input signals output from the first pixel electrode and the second pixel electrode. .. The photoelectric conversion element according to any one of claims 1 to 8, further comprising a photoelectric conversion layer separating portion including at least one of a light-shielding member and an insulating member between the photoelectric conversion layers. It has a plurality of photoelectric conversion units.
The first photoelectric conversion unit has a first pixel electrode and a second pixel electrode.
The second photoelectric conversion unit has a third pixel electrode and a fourth pixel electrode.
The photoelectric conversion element according to any one of claims 1 to 7, wherein a light-shielding film is provided between the second pixel electrode and the third pixel electrode in a plan view. The photoelectric conversion element according to claim 10, wherein a protective layer is provided on the light-shielding film. The photoelectric conversion element according to any one of claims 1 to 11, wherein the photoelectric conversion layer is made of any of intrinsic hydrogenated amorphous silicon, a compound semiconductor and an organic semiconductor. One of claims 1 to 12, wherein the capacitance is electrically connected to the plurality of pixel electrodes and has a pixel electrode control means for controlling the potential of the pixel electrodes via the capacitance. The photoelectric conversion element according to the above. The photoelectric conversion element according to any one of claims 1 to 13,
An optical system that forms an image on the photoelectric conversion element ,
An imaging system including a video signal processing unit that processes a signal output from the photoelectric conversion element to generate image data.

Images