JP7070023B2 - Arithmetic processing device and control method of arithmetic processing device - Google Patents

Description

The present invention relates to an arithmetic processing apparatus and a control method for the arithmetic processing apparatus.

As a CPU (Central Processing Unit) interrupt control method, a method of controlling interrupts of peripheral devices of a core or a processor by an interrupt control unit in the CPU is used. By controlling the interrupt control unit, the interrupt control unit can determine what interrupt should be processed with the highest priority for each core while taking into account the interrupt status of the entire system. As a method of notifying the interrupt control unit of the interrupt generated in each core, a method of notifying the interrupt by using a dedicated line connecting each core and the interrupt control unit is used.

A technique for correctly distributing received communication packets to each processor is known (see, for example, Patent Document 1). There is known a technique for realizing multiple linkage processing between processor units, improving system throughput and improving real-time responsiveness of a multiprocessor system (see, for example, Patent Document 2).

JP-A-2015-170947 Japanese Unexamined Patent Publication No. 2006-11802

In recent years, the technique of manycore that mounts a plurality of cores on one CPU has been advanced, and a CPU that mounts a plurality of cores is used. The number of dedicated lines used for interrupt notification increases in proportion to the number of cores in the CPU. Therefore, there is a problem that the wiring channel is pressed by the interrupt dedicated line in the process until the interrupt is notified to the interrupt control unit, and the mounting area increases.

In one aspect, it is an object of the present invention to reduce the wiring area of the wiring used for notifying an interrupt from the arithmetic unit to the interrupt control unit.

The arithmetic processing apparatus of the embodiment includes a plurality of arithmetic units, an output unit, a reception unit, and an interrupt control unit.

A plurality of interrupt notification signal lines are connected to each of the plurality of arithmetic units, and each of the interrupt notification signal lines is used to output an interrupt notification signal indicating the occurrence of an interrupt and the type of the interrupt. ..
The output unit outputs data representing the state of the interrupt notification signal received from the plurality of arithmetic units via the interrupt notification signal line and identification information indicating the arithmetic unit that outputs the interrupt notification signal.

Based on the identification information received from the output unit, the receiving unit writes data representing the state of the interrupt notification signal received from the output unit to the register corresponding to the arithmetic unit that outputs the interrupt notification signal.

The interrupt control unit monitors the register, and the interrupt type indicated by the priority information stored in advance and the data written in the register, which is priority information for the interrupt type. Based on the above , the interrupt to be activated is determined, and the signal for activating the determined interrupt is output to the arithmetic unit that outputs the interrupt notification signal for the determined interrupt.

According to the embodiment, it is possible to reduce the wiring area of the wiring used for notifying the interrupt from the arithmetic unit to the interrupt control unit.

It is a figure which shows the wiring method of the CPU of the comparative example. It is a block diagram of the CPU of an embodiment. It is a detailed block diagram of an interrupt notification packet generation part and a packet decoder. It is a figure which shows the format of an interrupt notification packet. It is a flowchart of the control method of embodiment. It is a flowchart of the control method of embodiment. It is a timing chart of each signal of the CPU of an embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
First, the CPU of the comparative example and the problem will be described, and then the CPU of the embodiment will be described.

FIG. 1 is a diagram showing a wiring method of a CPU of a comparative example.
The CPU 11 has a core 21-i (i = 0 to 7) and an interrupt control unit 31.

The core 21-i is connected to the interrupt control unit 31 via the interrupt notification signal line 41-ij (j = 1 to 3) and the interrupt activation signal line 51-i. That is, each core 21-i is connected to the interrupt control unit 31 by four signal lines. Further, in the following description and drawings, core 21-i may be referred to as core i.

The core 21-i notifies the interrupt control unit 31 of an interrupt notification indicating the occurrence and type of an interrupt via the interrupt notification signal line 41-i-j.

Upon receiving the interrupt notification, the interrupt control unit 31 notifies the core 21-i of the activation signal for activating the interrupt via the interrupt activation signal line 51-i.

In the CPU 11 of the comparative example, the interrupt notification signal lines 41-i-j used for interrupt notification increase in proportion to the number of cores 21-i. Therefore, when the number of cores 21-i increases, the interrupt notification signal lines 41-i-j press the wiring channel, and the mounting area increases.

FIG. 2 is a configuration diagram of a CPU according to an embodiment.
The CPU 101 includes a core 111-i (i = 0 to 7), an interrupt notification packet generation unit 121, a packet decoder 131, and an interrupt control unit 141. The CPU 101 is an example of an arithmetic processing device. Further, the number of cores 111-i is an example, and the number is not limited to this. Further, in the following description and drawings, the core 111-i may be referred to as the core i.

The core 111-i performs arithmetic processing. The core 111-i is an example of a calculation unit. The core 111-i is connected to the interrupt notification packet generation unit 121 via the interrupt notification signal line 151-ij (j = 1 to 3). The number of interrupt notification signal lines 151-i-j is an example, and is not limited to this.

The core 111-i outputs an interrupt notification signal indicating the occurrence and type of an interrupt via the interrupt notification signal line 151-i-j. The data representing the state of the signals (interrupt notification signals) of the interrupt notification signal lines 151-i-1 to 151-i-3 are referred to as interrupt ID1 to interrupt ID3, respectively. Further, the interrupt ID1 to the interrupt ID3 may be collectively referred to as an interrupt ID. The interrupt ID is an example of data representing the state of the interrupt notification signal.

The interrupt notification packet generation unit 121 is connected to the packet decoder 131 via the interrupt notification packet signal line 161-k (k = 1 to 4).

The interrupt notification packet generation unit 121 packetizes the received interrupt notification signal and outputs the interrupt notification packet to the packet decoder 131 via the interrupt notification packet signal line 161-k. The interrupt notification packet includes interrupt IDs 1 to ID 3 indicating the states of the signals (interrupt notification signals) of the interrupt notification signal lines 151-i-j, and core IDs indicating cores 111-i that output the interrupt notification signal. The details of the interrupt notification packet will be described later.

The interrupt notification packet generation unit 121 outputs the interrupt ID received from the interrupt notification signal line 151-i-j to the packet decoder 131 via the interrupt notification packet signal lines 161-1 to 161-1. Further, the interrupt notification packet generation unit 121 outputs the core ID indicating the core 111-i that outputs the interrupt notification signal indicating the occurrence of the interrupt to the packet decoder 131 via the interrupt notification packet signal line 161-4. The interrupt notification packet signal line 161-4 may include a plurality of signal lines.

Further, when the interrupt notification packet generation unit 121 simultaneously receives interrupt notification signals indicating the occurrence of an interrupt from a plurality of cores 111-i, the interrupt notification packet generation unit 121 performs arbitration and outputs interrupt notification packets including the interrupt ID in order.

It is desirable that the interrupt notification packet generation unit 121 is arranged at a position close to the core 111-i. The interrupt notification packet generation unit 121 is an example of an output unit.

The packet decoder 131 is connected to the interrupt control unit 141 via the interrupt notification signal line 171-i-j.

The packet decoder 131 outputs the received interrupt ID from the interrupt notification signal line 171-i-j corresponding to the core 111-i indicated by the received core ID.

It is desirable that the packet decoder 131 is arranged at a position close to the interrupt control unit 141. The packet decoder 131 is an example of a receiving unit.

The interrupt control unit 141 is connected to the core 111-i via the interrupt activation signal line 181-i. The interrupt control unit 141 reads the interrupt ID from the packet decoder 131 via the interrupt notification signal line 171-i-j. The interrupt control unit 141 determines the optimum interrupt to be activated from all currently generated interrupts based on the read interrupt ID. The interrupt control unit 141 notifies the core 111-i of the activation signal for activating the interrupt via the interrupt activation signal line 181-i.

In the CPU of the embodiment, the number of interrupt notification packet signal lines 161-k is a signal line segment for identifying the core ID in addition to the three interrupt dedicated lines. Therefore, even if the number of cores 111-i increases, the wiring area of the interrupt notification packet signal line 161-k increases only the signal line for identifying the core ID, and is used for interrupt notification as compared with the CPU of the comparative example. It is possible to reduce the wiring area of the wiring to be used.

FIG. 3 is a detailed configuration diagram of an interrupt notification packet generation unit and a packet decoder.
The interrupt notification packet generation unit 121 includes a register 122-i, a comparison circuit 123-i, an arbiter circuit 124, an AND circuit 125-i, and an OR circuit 126. In FIG. 3, for the sake of simplicity, the cores 111-1 to 111-6, the registers 122-1 to 122-6, the comparison circuits 123-1 to 123-6, and the AND circuits 125-1 to 125-6 are described. Is omitted. Further, in FIG. 3, for the sake of simplicity, the description of the interrupt notification signal lines 151-1-j to 151-6-j is omitted.

The register 122-i receives an interrupt notification signal from the core 111-i via the interrupt notification signal line 151-i-j, and stores an interrupt ID indicating the state of the interrupt notification signal. The registers 122-i write to themselves an interrupt ID indicating the state of the interrupt notification signal received when the register update signal from the arbiter circuit 124 is input.

The comparison circuit 123-i compares the interrupt ID (register value) stored in the registers 122-i with the interrupt notification signal received from the core 111-i. When the register value and the state of the interrupt notification signal received from the core 111-i are different from each other, the comparison circuit 123-i outputs a participation notification signal (participation notification signal is turned on) to the arbiter circuit 124.

Upon receiving the participation notification signal from the comparison circuit 123-i, the arbiter circuit 124 selects the core 111-i and outputs a register update signal to the registers 122-i and the AND circuit 125-i (register update signal is turned on). .. Further, when the arbitration circuit 124 receives the participation notification signal from the plurality of comparison circuits 123-i (that is, the plurality of cores 111-i notify the occurrence of the interrupt at the same time or at a close timing), the arbitration circuit 124 performs arbitration and interrupts. Select the core 111-i to which the ID is transmitted. The arbiter circuit 124 outputs a register update signal (register update signal is turned on) to the register 122-i corresponding to the selected core 111-i and the AND circuit 125-i. When the interrupt ID indicating the state of the interrupt notification signal output by the selected core 111-i is output to the packet decoder 131, the arbiter circuit 124 next selects the core 111-i to transmit the interrupt ID and newly selects it. A register update signal is output (register update signal is turned on) to the register 122-i corresponding to the core 111-i and the AND circuit 125-i. Hereinafter, the same process is repeated, and the interrupt notification packet generation unit 121 outputs the interrupt IDs from the cores 111-i that have notified the occurrence of the interrupt to the packet decoder 131 in order. In the arbitration process, the arbitration circuit 124 selects the core 111-i for transmitting the interrupt ID using, for example, round robin.

The AND circuit 125-i receives an interrupt notification signal from the core 111-i and a register update signal from the arbiter circuit 124. When the AND circuit 125-i receives the register update signal from the arbiter circuit 124 (when the participation notification signal is on), the AND circuit 125-i outputs an interrupt notification packet to the OR circuit 126. The interrupt notification packet includes an interrupt ID (interrupt ID1 to interrupt ID3) indicating the state of the interrupt notification signal from the core 111-i and a core ID indicating the core 111-i. Further, the interrupt ID 1 to the interrupt ID 3 and the core ID are transmitted by different signal lines.

The OR circuit 126 outputs the interrupt notification packet input from the AND circuit 125-i to the packet decoder 131 via the interrupt notification packet signal line 161-k. When the OR circuit 126 outputs the interrupt notification packet, the arbiter circuit 124 may be notified of the completion of the output of the interrupt notification packet. As a result, when the arbitration circuit 124 receives the completion of the output of the interrupt notification packet, the arbitration circuit 124 selects the core 111-i to transmit the interrupt ID next in the arbitration process.

FIG. 4 is a diagram showing the format of the interrupt notification packet.
The interrupt notification packet includes a core ID, an interrupt ID 1, an interrupt ID 2, and an interrupt ID 3. The core ID is notified to the packet decoder 131 via the interrupt notification packet signal line 161-4. The interrupt ID 1, interrupt ID 2, and interrupt ID 3 are notified to the packet decoder 131 via the interrupt notification packet signal lines 161-1 to 161, respectively.

The core ID is information that identifies the core 111-i. For example, core ID = core 0 indicates core 111-0. The core ID is an example of identification information.

The interrupt ID 1 indicates the state (data) of the signal of the interrupt notification signal line 151-i-1 among the interrupt notification signals output by the core 111-i indicated by the core ID.

The interrupt ID 2 indicates the state (data) of the signal of the interrupt notification signal line 151-i-2 among the interrupt notification signals output by the core 111-i indicated by the core ID.

The interrupt ID 3 indicates the state (data) of the signal of the interrupt notification signal line 151-i-3 among the interrupt notification signals output by the core 111-i indicated by the core ID.

Returning to FIG. 3, the explanation will be continued.
The packet decoder 131 includes a core ID decoder 132, an AND circuit 133-i, and registers 134-i. In FIG. 3, for the sake of simplicity, the description of the AND circuits 133-1 to 133-6 and the registers 134-1 to 134-6 is omitted. Further, in FIG. 3, for the sake of simplicity, the description of the interrupt notification signal lines 171-1-j to 171-6-j and the interrupt activation signal lines 181-1 to 181-6 is omitted.

The core ID decoder 132 decodes the received core ID, confirms the core 111-i corresponding to the core ID, and outputs a register update signal to the AND circuit 133-i corresponding to the core 111-i, that is, a register. Turn on the update signal.

The AND circuit 133-i receives the interrupt ID1, the interrupt ID2, and the interrupt ID3 via the interrupt notification packet signal lines 161-1 to 161-3. When the AND circuit 133-i receives the register update signal from the core ID decoder 132 (when the register update signal is on), the AND circuit 133-i outputs the received interrupt ID 1, interrupt ID 2, and interrupt ID 3 to the register 134-i.

Registers 134-i store interrupt ID 1, interrupt ID 2, and interrupt ID 3 received from the AND circuit 133-i.

The interrupt control unit 141 monitors the register 134-i, and reads out the interrupt ID1, the interrupt ID2, and the interrupt ID3 stored in the register 134-i via the interrupt notification signal line 171-i-j, respectively. In this way, the state of the interrupt notification signal from the core 111-i is input to the interrupt control unit 141.

According to the CPU 101 of the embodiment, even if the number of cores 111-i increases, the number of interrupt notification packet signal lines 161-k increases only by the signal line segment for identifying the core ID. The wiring area can be reduced.

5A and 5B are flowcharts of the control method of the embodiment.
In step S501, the core 111-i outputs an interrupt notification signal to the interrupt notification packet generation unit 121 via the interrupt notification signal line 151-i-j. The core 111-i changes the state of the interrupt notification signal to notify the occurrence and type of the interrupt.

In step S502, the comparison circuit 123-i compares the interrupt ID (register value) stored in the registers 122-i with the interrupt notification signal received from the core 111-i. If the register value of the register 122-i and the interrupt signal received from the core 111-i are the same, the control returns to step S501. If there is a difference between the register value of the register 122-i and the interrupt notification signal received from the core 111-i, the control proceeds to step S503.

In step S503, the comparison circuit 123-i that detects the difference between the register value of the register 122-i and the interrupt notification signal received from the core 111-i outputs the participation notification signal to the arbiter circuit 124.

In step S504, the arbitration circuit 124 arbitrates the participation notification, and among the cores 111-i that notify the occurrence of the interrupt, the core 111-i that notifies the interrupt ID to the interrupt control unit 141 (or the packet decoder 131). select. The arbiter circuit 124 outputs a register update signal (register update signal is turned on) to the register 122-i corresponding to the selected core 111-i and the AND circuit 125-i. Here, attention is paid to one of the cores 111-i that have notified the occurrence of an interrupt, and the focused core 111-i is referred to as a corresponding core. When the corresponding core is selected by the arbitration of the arbiter circuit 124, the control proceeds to step S505.

In step S505, when the AND circuit 125-i receives the register update signal from the arbiter circuit 124 (when the participation notification signal is on), the AND circuit 125-i packetizes the interrupt notification signal and outputs the interrupt notification packet to the OR circuit 126.

In step S506, when the register 122-i receives the register update signal from the arbiter circuit 124, the register 122-i updates the interrupt ID (register value) stored in the interrupt ID indicating the state of the received interrupt notification signal.

In step S507, the OR circuit 126 outputs the interrupt notification packet input from the AND circuit 125-i to the packet decoder 131 via the interrupt notification packet signal line 161-k.

In step S508, the received core ID of the received interrupt notification packet is decoded, the core 111-i corresponding to the core ID is confirmed, and the register is updated to the AND circuit 133-i corresponding to the core 111-i. Output the signal, that is, turn on the register update signal.

In step S509, when the register update signal from the core ID decoder 132 is on, the AND circuit 133-i outputs the received interrupt ID 1, interrupt ID 2, and interrupt ID 3 to the register 134-i. The register 134-i updates the stored interrupt ID with the interrupt ID (interrupt ID 1, interrupt ID 2, and interrupt ID 3) input from the AND circuit 133-i.

In step S510, the interrupt control unit 141 reads out the interrupt ID (register value) stored in each of the registers 134-i.

In step S511, the interrupt control unit 141 detects the occurrence and type of an interrupt based on the read register value. The interrupt control unit 141 selects the optimum interrupt from all the generated interrupts, and outputs a start signal for activating the selected interrupt to the core 111-i. For example, the interrupt control unit 141 stores priority information in advance according to the type of interrupt, and based on the type and priority of the interrupt indicated by the read interrupt ID, among all the interrupts that have occurred. Select (determine) the interrupt to be activated.

FIG. 6 is a timing chart of each signal of the CPU of the embodiment.
FIG. 6 describes a case where the cores 111-0 and 111-7 perform interrupt notification.

The first line of FIG. 6 shows the time. The 2nd to 5th lines show various signals related to the interrupt notification of the core 111-0. Specifically, the second line shows the signal state of the interrupt notification signal line 151-0-j, that is, the interrupt ID, and the third line shows the value (register value) stored in the register 122-0. The line shows the output of the comparison circuit 123-0 (participation notification signal), and the fifth line shows the output of the arbiter circuit 124 to the register 122-0 (register update signal).

The 6th to 9th lines show various signals related to the interrupt notification of the core 111-7. Specifically, the 6th line shows the signal state of the interrupt notification signal line 151-7-j, that is, the interrupt ID, and the 7th line shows the value (register value) stored in the register 122-7. The 9th line shows the output of the comparison circuit 123-7 (participation notification signal), and the 9th line shows the output of the arbiter circuit 124 to the register 122-7 (register update signal).

The 10th to 11th lines show the output (interrupt notification packet) of the interrupt notification packet generation unit 121, and the 10th line shows the signals (interrupt ID) of the interrupt notification packet signal lines 161-1 to 161-3. , 11th line shows the signal (core ID) of the interrupt notification packet signal line 161-4.

In FIG. 6, for the sake of simplicity, the interrupt ID and the register value are represented by one character. For example, when the states of the interrupt notification signal lines 151-0-1 to 151-0-3 are Low, Low, and Low, they are expressed as "A".

First, the case where the core 111-0 gives an interrupt notification will be described.
At times t1 to t4, the interrupt ID from the core 111-0 is "A", and the register value of the register 122-0 is "A".

At time t5, the core 111-0 notifies the occurrence of an interrupt, that is, the interrupt ID from the core 111-0 becomes "B". The comparison circuit 123-0 detects the difference between the register value and the interrupt ID from the core 111-0, and the participation notification signal from the comparison circuit 123-0 is turned on (= 1).

The arbiter circuit 124 arbitrates the participation notification, core 111-0 is selected at time t8, and the register update signal from the arbiter circuit 124 to the register 122-0 and the AND circuit 125-0 is turned on (= 1). Then, the register value of the register 122-0 is updated to "B". The AND circuit 125-0 outputs an interrupt ID = B and a core ID = core 0 to the OR circuit 126, and the OR circuit 126 outputs an interrupt notification packet (interrupt ID = B and core ID = core 0) to the packet decoder 131. Output.

Next, the case where the core 111-7 gives an interrupt notification will be described.
At times t1 to t5, the interrupt ID from the core 111-7 is "C", and the register value of the register 122-7 is "C".

At time t6, the core 111-7 notifies the occurrence of an interrupt, that is, the interrupt ID from the core 111-7 becomes "D". The comparison circuit 123-7 detects the difference between the register value and the interrupt ID from the core 111-7, and the participation notification signal from the comparison circuit 123-7 is turned on (= 1).

The arbiter circuit 124 arbitrates the participation notification, core 111-7 is selected at time t11, and the register update signal from the arbiter circuit 124 to the register 122-7 and the AND circuit 125-7 is turned on (= 1). Then, the register value of the register 122-7 is updated to "D". The AND circuit 125-7 outputs an interrupt ID = D and a core ID = core 7 to the OR circuit 126, and the OR circuit 126 outputs an interrupt notification packet (interrupt ID = D and core ID = core 7) to the packet decoder 131. Output.

The following additional notes will be further disclosed with respect to the above embodiments.
(Appendix 1)
Multiple arithmetic units that output interrupt notification signals,
An output unit that outputs data indicating the state of the interrupt notification signal and identification information indicating an arithmetic unit that outputs the interrupt notification signal, and an output unit.
A receiving unit that writes data representing the state of the interrupt notification signal received from the output unit to a register corresponding to the arithmetic unit that outputs the interrupt notification signal based on the identification information received from the output unit.
An interrupt control unit that monitors the register and outputs a signal that activates an interrupt to the arithmetic unit that outputs the interrupt notification signal based on the data written in the register.
Arithmetic processing device having.
(Appendix 2)
The output unit is
When the interrupt notification signal is output from the first calculation unit and the second calculation unit of the plurality of calculation units at the same time, either the first calculation unit or the second calculation unit is selected.
Data indicating the state of the interrupt notification signal output by the selected one and identification information indicating the selected one are output, and after the output, data indicating the state of the interrupt notification signal output by the other and identification information indicating the other are output. The arithmetic processing device according to Appendix 1 that outputs.
(Appendix 3)
Note 2 that the output unit outputs data representing the state of the interrupt notification signal output by the selected one and data representing the state of the interrupt notification signal output by the other to the receiving unit via the same signal line. The arithmetic processing device described.
(Appendix 4)
A plurality of arithmetic units of the arithmetic processing device output an interrupt notification signal, and the interrupt notification signal is output.
The output unit of the arithmetic processing device outputs data indicating the state of the interrupt notification signal and identification information indicating the arithmetic unit that outputs the interrupt notification signal.
Based on the identification information received from the output unit, the receiving unit of the arithmetic processing device displays the state of the interrupt notification signal received from the output unit in the register corresponding to the arithmetic unit that outputs the interrupt notification signal. Write the data to represent,
The interrupt control unit of the arithmetic processing device monitors the register and outputs a signal for invoking an interrupt to the arithmetic unit that outputs the interrupt notification signal based on the data written in the register. Control method.
(Appendix 5)
The output unit is
When the interrupt notification signal is output from the first calculation unit and the second calculation unit of the plurality of calculation units at the same time, either the first calculation unit or the second calculation unit is selected.
Data indicating the state of the interrupt notification signal output by the selected one and identification information indicating the selected one are output, and after the output, data indicating the state of the interrupt notification signal output by the other and identification information indicating the other are output. The control method according to Appendix 4 for outputting.
(Appendix 6)
The output unit outputs the data representing the state of the interrupt notification signal output by the selected one and the data representing the state of the interrupt notification signal output by the other to the receiving unit via the same signal line. The control method described.

101 CPU
111 Core 121 Interrupt notification packet generator 122 Register 123 Comparison circuit 124 Arbiter circuit 125 AND circuit 126 OR circuit 131 Packet decoder 132 Core ID decoder 133 AND circuit 134 Register 141 Interrupt control unit

Claims (4)

A plurality of interrupt notification signal lines are connected to each of the plurality of arithmetic units, and each of the interrupt notification signal lines is used to indicate the occurrence of an interrupt and the type of the interrupt. The plurality of arithmetic units that output interrupt notification signals, and
An output unit that outputs data indicating the state of the interrupt notification signal received from the plurality of arithmetic units via the interrupt notification signal line and identification information indicating the arithmetic unit that outputs the interrupt notification signal.
A receiving unit that writes data representing the state of the interrupt notification signal received from the output unit to a register corresponding to the arithmetic unit that outputs the interrupt notification signal based on the identification information received from the output unit.
While monitoring the register, it is activated based on the priority information stored in advance for the interrupt type and the interrupt type indicated by the data written in the register. An interrupt control unit that determines an interrupt to be interrupted and outputs a signal for activating the determined interrupt to an arithmetic unit that outputs the interrupt notification signal for the determined interrupt.
Arithmetic processing device having. The output unit is
When the interrupt notification signal is output from the first calculation unit and the second calculation unit of the plurality of calculation units at the same time, either the first calculation unit or the second calculation unit is selected.
Data indicating the state of the interrupt notification signal output by the selected one and identification information indicating the selected one are output, and after the output, data indicating the state of the interrupt notification signal output by the other and identification information indicating the other are output. The arithmetic processing apparatus according to claim 1. A claim that the output unit outputs data representing the state of the interrupt notification signal output by the selected one and data representing the state of the interrupt notification signal output by the other to the receiving unit via the same signal line. 2. The arithmetic processing device according to 2. A plurality of arithmetic units included in the arithmetic processing apparatus , wherein the plurality of arithmetic units having a plurality of interrupt notification signal lines connected to each of the plurality of arithmetic units use the interrupt notification signal lines one by one. An interrupt notification signal indicating the occurrence of an interrupt and the type of the interrupt is output.
The output unit of the arithmetic processing apparatus provides data indicating the state of the interrupt notification signal received from the plurality of arithmetic units via the interrupt notification signal line and identification information indicating the arithmetic unit that outputs the interrupt notification signal. Output and
Based on the identification information received from the output unit, the receiving unit of the arithmetic processing device displays the state of the interrupt notification signal received from the output unit in the register corresponding to the arithmetic unit that outputs the interrupt notification signal. Write the data to represent,
The interrupt control unit of the arithmetic processing device monitors the register, and the priority information for the interrupt type, which is stored in advance, and the data written in the register are recorded. Control of an arithmetic processing device that determines an interrupt to be activated based on the type of the interrupt shown and outputs a signal for activating the determined interrupt to an arithmetic unit that outputs the interrupt notification signal for the determined interrupt. Method.

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