JP7030578B2 - Display device - Google Patents

Description

Embodiments of the present invention relate to display devices.

In recent years, various display devices having a built-in touch sensor have been proposed. As an example, a display device is disclosed in which a plurality of electrodes formed on a display panel serve as sensor electrodes when in the touch sensing mode and as common electrodes when in the display mode. As the touch sensing method, either a mutual capacity method or a self-capacity method is applied. In the touch sensing mode, sensing is performed by applying a touch drive voltage to a sensor electrode through a signal line.

Japanese Unexamined Patent Publication No. 2015-12257

An object of the present embodiment is to provide a display device capable of improving reliability.

According to the present embodiment, a display panel having a display unit for displaying an image and a non-display unit surrounding the display unit is provided, and the display panel includes a first organic insulating film and the first organic insulating film. A first substrate having a second organic insulating film arranged above, a bank portion having the first organic insulating film and the second organic insulating film in the non-display portion, and the first substrate facing each other. The second substrate is provided with a seal for adhering the first substrate and the second substrate, and the bank portion includes a first slit penetrating the first organic insulating film and the second organic insulating film. A display device is provided which has a first divided portion and a second divided portion divided by the first slit, and the seal is arranged in the first slit.

FIG. 1 is a plan view showing the appearance of the display device of the present embodiment. FIG. 2 is a plan view showing an example of a configuration of a touch sensor. FIG. 3 is a plan view showing the relationship between the pixel and the sensor electrode shown in FIG. 2. FIG. 4 is a diagram showing a basic configuration of pixels and an equivalent circuit. FIG. 5 is a plan view showing an example of the pixel layout. FIG. 6 is a plan view showing an example of the pixels shown in FIG. FIG. 7 is a cross-sectional view of the first substrate along the line AB shown in FIG. FIG. 8 is a cross-sectional view of the display panel along the CD line shown in FIG. FIG. 9 is a cross-sectional view of the first substrate along the line EF shown in FIG. FIG. 10 is a cross-sectional view of the display panel taken along the line GH shown in FIG. FIG. 11 is a detailed cross-sectional view of the region shown in FIG. FIG. 12 is a plan view showing the position of the slit in the bank portion shown in FIG. FIG. 13 is a cross-sectional view showing a first modification of the present embodiment shown in FIG. FIG. 14 is a plan view showing the position of the slit of the spacer shown in FIG. FIG. 15 is a cross-sectional view showing a second modification of the present embodiment shown in FIG.

Hereinafter, this embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention, which are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is merely an example, and the present invention is used. It does not limit the interpretation. Further, in the present specification and each figure, the same reference reference numerals may be given to the components exhibiting the same or similar functions as those described above with respect to the above-mentioned figures, and the overlapping detailed description may be omitted as appropriate. ..

First, the display device DSP according to the present embodiment will be described in detail. In this embodiment, a case where the display device DSP is a liquid crystal display device will be described.

FIG. 1 is a plan view showing the appearance of the display device DSP of the present embodiment.
In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to the directions parallel to the main surface of the substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In the present specification, the direction toward the tip of the arrow indicating the third direction Z is referred to as upward (or simply upward), and the direction opposite from the tip of the arrow is referred to as downward (or simply downward). Further, it is assumed that there is an observation position for observing the display device DSP on the tip side of the arrow indicating the third direction Z, and the observation position is directed toward the XY plane defined by the first direction X and the second direction Y. Seeing is called plan view.

Here, a plan view of the display device DSP in the XY plane is shown. The display device DSP includes a display panel PNL, a flexible printed circuit board 1, an IC chip 2, and a circuit board 3.

The display panel PNL is a liquid crystal display panel and includes a first substrate SUB1, a second substrate SUB2, a seal SE, a light-shielding layer BM, spacers SP1 to SP4, and a liquid crystal layer LC described later. Further, the display panel PNL includes a display unit DA for displaying an image and a frame-shaped non-display unit NDA surrounding the display unit DA. The second substrate SUB2 faces the first substrate SUB1. The first substrate SUB1 has a mounting portion MA extending in the second direction Y from the second substrate SUB2.

The seal SE is located in the non-display portion NDA and adheres the first substrate SUB1 and the second substrate SUB2. The light-shielding layer BM is located in the non-display portion NDA. The seal SE is provided at a position where it overlaps with the light-shielding layer BM in a plan view. In FIG. 1, the region where the seal SE is arranged and the region where the light-shielding layer BM is arranged are shown by different diagonal lines, and the region where the seal SE and the light-shielding layer BM overlap is shown by cross-hatching. The light-shielding layer BM is provided on the second substrate SUB2.

All of the spacers SP1 to SP4 are located in the non-display portion NDA. The spacer SP1 is located on the outermost circumference of the display panel PNL. The spacer SP2 is located closer to the display unit DA than the spacer SP1. The spacers SP1 and SP2 are superimposed on the seal SE. The spacers SP3 and SP4 are located closer to the display unit DA than the seal SE.

The display unit DA is located inside surrounded by the light-shielding layer BM. The display unit DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y.

The flexible printed circuit board 1 is mounted on the mounting unit MA and connected to the circuit board 3. The IC chip 2 is mounted on the flexible printed circuit board 1. The IC chip 2 may be mounted on the mounting unit MA. The IC chip 2 has a built-in display driver DD that outputs a signal necessary for displaying an image in a display mode for displaying an image. Further, in the illustrated example, the IC chip 2 has a built-in touch controller TC that controls a touch sensing mode for detecting the approach or contact of an object with the display device DSP. In the figure, the IC chip 2 is shown by a alternate long and short dash line, and the display driver DD and the touch controller TC are shown by a dotted line.

The display panel PNL of the present embodiment is a transmissive type having a transmissive display function for displaying an image by selectively transmitting light from the back side of the first substrate SUB1, and light from the front side of the second substrate SUB2. It may be either a reflection type having a reflection display function for displaying an image by selectively reflecting the light, or a semi-transmissive type having a transmission display function and a reflection display function.

Further, although the detailed configuration of the display panel PNL will be omitted here, the display panel PNL has a display mode using a lateral electric field along the main surface of the substrate and a vertical electric field along the normal of the main surface of the substrate. It corresponds to the display mode to be used, the display mode to use the gradient electric field inclined in the diagonal direction with respect to the main surface of the substrate, and the display mode to use the above-mentioned transverse electric field, longitudinal electric field, and gradient electric field in combination as appropriate. Any configuration may be provided. The substrate main surface here is a surface parallel to the XY plane defined by the first direction X and the second direction Y.

The display panel PNL has a first end EG1 and a second end EG2 extending in the first direction X, and a third end EG3 and a fourth end EG4 extending in the second direction Y. ing. The first end portion EG1 faces the second end portion EG2 via the display unit DA. The third end EG3 faces the fourth end EG4 via the display DA. Further, the mounting portion MA is located between the display portion DA and the first end portion EG1. The second substrate SUB2 has a fifth end portion EG5 on the mounting portion MA side.

FIG. 2 is a plan view showing a configuration example of the touch sensor TS. Here, the self-capacity type touch sensor TS will be described, but the touch sensor TS may be a mutual capacity type.

The touch sensor TS includes a plurality of sensor electrodes Rx (Rx1, Rx2 ...) Arranged in a matrix, and a plurality of sensor wirings L (L1, L2 ...). The plurality of sensor electrodes Rx are located on the display unit DA and are arranged in a matrix in the first direction X and the second direction Y. One sensor electrode Rx constitutes one sensor block B. The sensor block B is the smallest unit capable of touch sensing. The plurality of sensor wirings L extend along the second direction Y in the display unit DA, and are arranged in the first direction X. Each of the sensor wirings L is provided at a position superimposing on the signal line S described later, for example. Further, each of the sensor wirings L is drawn out to the non-display unit NDA and electrically connected to the IC chip 2 via the flexible printed circuit board 1.

Here, attention is paid to the relationship between the sensor wirings L1 to L3 arranged in the first direction X and the sensor electrodes Rx1 to Rx3 arranged in the second direction Y. The sensor wiring L1 overlaps with the sensor electrodes Rx1 to Rx3 and is electrically connected to the sensor electrodes Rx1.

The sensor wiring L2 overlaps with the sensor electrodes Rx2 and Rx3 and is electrically connected to the sensor electrodes Rx2. The dummy wiring D20 is separated from the sensor wiring L2. The dummy wiring D20 overlaps with the sensor electrode Rx1 and is electrically connected to the sensor electrode Rx1. The sensor wiring L2 and the dummy wiring D20 are located on the same signal line.

The sensor wiring L3 overlaps with the sensor electrode Rx3 and is electrically connected to the sensor electrode Rx3. The dummy wiring D31 overlaps with the sensor electrode Rx1 and is electrically connected to the sensor electrode Rx1. The dummy wiring D32 is separated from the dummy wiring D31 and the sensor wiring L3. The dummy wiring D32 overlaps with the sensor electrode Rx2 and is electrically connected to the sensor electrode Rx2. The sensor wiring L3 and the dummy wirings D31 and D32 are located on the same signal line.

In the touch sensing mode, the touch controller TC applies a touch drive voltage to the sensor wiring L. As a result, a touch drive voltage is applied to the sensor electrode Rx, and sensing is performed on the sensor electrode Rx. The sensor signal corresponding to the sensing result at the sensor electrode Rx is output to the touch controller TC via the sensor wiring L. The touch controller TC or an external host detects whether or not the object is approaching or touching the display device DSP and the position coordinates of the object based on the sensing signal.
In the display mode, the sensor electrode Rx functions as a common electrode to which a common voltage (Vcom) is applied. The common voltage is applied from the voltage supply unit included in the display driver DD, for example, via the sensor wiring L.

FIG. 3 is a plan view showing the relationship between the pixel PX and the sensor electrode Rx shown in FIG. In FIG. 3, the direction that intersects the second direction Y at an acute angle counterclockwise is defined as the direction D1, and the direction that intersects the second direction Y at an acute angle clockwise is defined as the direction D2. The angle θ1 formed by the second direction Y and the direction D1 is substantially the same as the angle θ2 formed by the second direction Y and the direction D2.

One sensor electrode Rx is arranged over a plurality of pixels PX. In the illustrated example, the pixel PX located in the odd-numbered rows along the second direction Y extends along the direction D1. Further, the pixel PX located on the even-numbered rows along the second direction Y extends along the direction D2. The pixel PX here indicates a minimum unit that can be individually controlled according to a pixel signal, and may be referred to as a sub-pixel. Further, the minimum unit for realizing color display may be referred to as a main pixel MP. The main pixel MP is configured to include a plurality of sub-pixels PX that display different colors from each other. In one example, the main pixel MP includes a red pixel that displays red, a green pixel that displays green, and a blue pixel that displays blue as sub-pixel PX. Further, the main pixel MP may include a white pixel that displays white.
In one example, 60 to 70 main pixel MPs are arranged along the first direction X, and 60 to 70 main pixel MPs are arranged along the second direction in one sensor electrode Rx.

FIG. 4 is a diagram showing a basic configuration of a pixel PX and an equivalent circuit.
The plurality of scanning lines G are connected to the scanning line driving circuit GD. The plurality of signal lines S are connected to the signal line drive circuit SD. The scanning line G and the signal line S do not necessarily have to extend linearly, and a part of them may be bent. For example, it is assumed that the signal line S extends in the second direction Y even if a part of the signal line S is bent.

The common electrode CE is provided for each sensor block B. The common electrode CE is connected to a voltage supply unit CD of a common voltage (Vcom) and is arranged over a plurality of pixels PX. Further, the common electrode CE is also connected to the touch controller TC as described above, and forms the sensor electrode Rx to which the touch drive voltage is applied in the touch sensing mode.

Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and the like. The switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line G and the signal line S. The scanning line G is connected to the switching element SW in each of the pixels PX arranged in the first direction X. The signal line S is connected to the switching element SW in each of the pixels PX arranged in the second direction Y. The pixel electrode PE is electrically connected to the switching element SW. Each of the pixel electrode PEs faces the common electrode CE, and the liquid crystal layer LC is driven by the electric field generated between the pixel electrode PE and the common electrode CE. The holding capacitance CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

FIG. 5 is a plan view showing an example of the pixel layout.
The scanning lines G1 to G3 extend linearly along the first direction X, respectively, and are arranged at intervals in the second direction Y. The signal lines S1 to S3 extend substantially along the second direction Y, and are arranged at intervals in the first direction X.

The pixel electrodes PE1 and PE2 are arranged between the scanning lines G1 and G2. The pixel electrodes PE1 and PE2 are arranged along the first direction X. The pixel electrodes PE3 and PE4 are arranged between the scanning lines G2 and G3. The pixel electrodes PE3 and PE4 are arranged along the first direction X. The pixel electrodes PE1 and PE3 are arranged between the signal lines S1 and S2, and the pixel electrodes PE2 and PE4 are arranged between the signal lines S2 and S3.

The pixel electrodes PE1 and PE2 have band electrodes Pa1 and Pa2 extending along the direction D1, respectively. The pixel electrodes PE3 and PE4 have band electrodes Pa3 and Pa4 extending along the direction D2, respectively. In the illustrated example, the number of band electrodes Pa1 to Pa4 is two, but it may be one or three or more.

The common electrode CE1 is arranged over the pixels PX1 and PX2. The common electrode CE2 is arranged over the pixels PX3 and PX4. The common electrodes CE1 and CE2 are arranged in the second direction Y. The common electrodes CE1 and CE2 are included in one sensor electrode Rx shown in FIG. The common electrode CE1 is superimposed on the signal lines S1 to S3. The pixel electrodes PE1 and PE2 are superimposed on the common electrode CE1. The common electrode CE2 is superimposed on the signal lines S1 to S3. The pixel electrodes PE3 and PE4 are superimposed on the common electrode CE2. In the illustrated example, the scan line G2 is located between the common electrodes CE1 and CE2.

The bridge portion BR corresponds to the area shown by diagonal lines in the figure. The bridge portion BR is located between the common electrode CE1 and the common electrode CE2, and is superimposed on the signal line S2. The bridge portion BR is integrally formed with the common electrode CE1 and the common electrode CE2, and electrically connects the common electrode CE1 and the common electrode CE2. The bridge portion BR is included in the sensor electrode Rx as well as the common electrode CE1 and the common electrode CE2.

FIG. 6 is a plan view showing an example of the pixels shown in FIG. Here, the main part will be described by focusing on the pixel PX1 surrounded by the scanning lines G1 and G2 and the signal lines S1 and S2 shown in FIG. Note that FIG. 6 shows the configuration on the first substrate SUB1.

The switching element SW is arranged on the first substrate SUB1. The switching element SW is electrically connected to the scanning line G2 and the signal line S2. The switching element SW includes a semiconductor layer SC and a drain electrode DE.

A part of the semiconductor layer SC is arranged so as to overlap the signal line S2, and the other part extends between the signal lines S1 and S2 and is formed in a substantially U shape. The semiconductor layer SC intersects the scanning line G2 at a position overlapping the signal line S2, and also intersects the scanning line G2 between the signal lines S1 and S2. In the scanning line G2, the region superimposing on the semiconductor layer SC functions as the gate electrodes GE1 and GE2, respectively. That is, the switching element SW of the illustrated example has a double gate structure. The semiconductor layer SC is electrically connected to the signal line S2 through the through hole CH1 at one end SCA, and is electrically connected to the drain electrode DE through the through hole CH2 at the other end SCB.

The drain electrode DE is formed in an island shape and is arranged between the signal line S1 and the signal line S2. In the switching element SW, the drain electrode DE may be referred to as a source electrode.

The pixel electrode PE1 includes a base BS integrated with a plurality of band electrodes Pa1. The base BS overlaps with the drain electrode DE and is electrically connected to the drain electrode DE.

FIG. 7 is a cross-sectional view of the first substrate SUB1 along the line AB shown in FIG.
The first substrate SUB1 includes an insulating substrate 10, insulating films 11 to 16, semiconductor layer SC, scanning line G2, signal line S2, metal wiring ML2, common electrode CE1, bridge portion BR, alignment film AL1, and the like.

The insulating substrate 10 is a substrate having light transmittance such as a glass substrate or a flexible resin substrate. The insulating film 11 is located on the insulating substrate 10. The semiconductor layer SC is located on the insulating film 11 and is covered with the insulating film 12. The semiconductor layer SC is formed of, for example, polycrystalline silicon, but may be formed of amorphous silicon or an oxide semiconductor.

The gate electrode GE1 which is a part of the scanning line G2 is located on the insulating film 12 and is covered with the insulating film 13. Other scanning lines (not shown) are also located on the same layer as the scanning line G2. The scanning line G2 includes metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), and chromium (Cr), and these metal materials. It is formed of a combined alloy or the like, and may have a single-layer structure or a multi-layer structure. In one example, the scan line G2 is formed of a molybdenum-tungsten alloy.

The signal line S2 is located on the insulating film 13 and is covered with the insulating film (first organic insulating film) 14. Other signal lines (not shown) are also located on the same layer as the signal line S2. The signal line S2 is formed of the above-mentioned metal material, an alloy in which the above-mentioned metal materials are combined, or the like, and may have a single-layer structure or a multi-layer structure. In one example, the signal line S2 is a laminate in which a first layer containing titanium (Ti), a second layer containing aluminum (Al), and a third layer containing titanium (Ti) are laminated in this order. The signal line S2 is in contact with the semiconductor layer SC through the through hole CH1 penetrating the insulating film 12 and the insulating film 13.

The metal wiring ML2 is located on the insulating film 14 and is covered with the insulating film (second organic insulating film) 15. The metal wiring ML2 is formed of the above-mentioned metal material, an alloy in which the above-mentioned metal materials are combined, or the like, and may have a single-layer structure or a multi-layer structure. In one example, the metal wiring ML2 is a laminate in which a first layer containing titanium (Ti), a second layer containing aluminum (Al), and a third layer containing titanium (Ti) are laminated in this order, or The first layer containing molybdenum (Mo), the second layer containing aluminum (Al), and the third layer containing molybdenum (Mo) are laminated in this order.

The common electrode CE1 and the bridge portion BR are located on the insulating film 15 and are covered with the insulating film (inorganic insulating film) 16. The common electrode CE1 and the bridge portion BR are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode CE1 is in contact with the metal wiring ML2 through the through hole CH3 penetrating the insulating film 15. The alignment film AL1 is located on the insulating film 16.

The insulating films 11 to 13 and the insulating film 16 are inorganic insulating films formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure. It may have a multi-layer structure. The insulating films 14 and 15 are organic insulating films formed of an organic insulating material such as acrylic resin.

As described above, the common electrode CE1 also functions as the sensor electrode Rx, and the metal wiring ML2 also functions as the sensor wiring L electrically connected to the sensor electrode Rx.

FIG. 8 is a cross-sectional view of the display panel PNL along the CD line shown in FIG. The illustrated example corresponds to an example to which a display mode using a transverse electric field is applied.

In the first substrate SUB1, the signal lines S1 and S2 are located on the insulating film 13 and are covered with the insulating film 14. The metal wirings ML1 and ML2 are located directly above the signal lines S1 and S2, respectively. The pixel electrode PE1 is located on the insulating film 16 and is covered with the alignment film AL1. The pixel electrode PE1 is a transparent electrode formed of a transparent conductive material such as ITO or IZO.

The second substrate SUB2 includes an insulating substrate 20, a light-shielding layer BM, a color filter CF, an overcoat layer OC, an alignment film AL2, and the like.

Like the insulating substrate 10, the insulating substrate 20 is a substrate having light transmittance such as a glass substrate or a resin substrate. The light-shielding layer BM and the color filter CF are located on the side of the insulating substrate 20 facing the first substrate SUB1. The color filter CF is arranged at a position facing the pixel electrode PE1, and a part of the color filter CF overlaps the light-shielding layer BM. The color filter CF includes a red color filter CFR, a green color filter CFG, and a blue color filter CFB. The overcoat layer OC covers the color filter CF. The overcoat layer OC is formed of a transparent resin. The alignment film AL2 covers the overcoat layer OC. The alignment film AL1 and the alignment film AL2 are formed of, for example, a material exhibiting horizontal orientation.

The first substrate SUB1 and the second substrate SUB2 described above are arranged so that the alignment film AL1 and the alignment film AL2 face each other. The first substrate SUB1 and the second substrate SUB2 are adhered by a seal with a predetermined cell gap formed. The liquid crystal layer LC is held between the alignment film AL1 and the alignment film AL2. The liquid crystal layer LC includes a liquid crystal molecule LM. The liquid crystal layer LC is composed of a positive type (positive dielectric anisotropy) liquid crystal material or a negative type (negative dielectric anisotropy) liquid crystal material.

The optical element OD1 including the polarizing plate PL1 is adhered to the insulating substrate 10. The optical element OD2 including the polarizing plate PL2 is adhered to the insulating substrate 20. The optical element OD1 and the optical element OD2 may be provided with a retardation plate, a scattering layer, an antireflection layer, and the like, if necessary.

In such a display panel PNL, in an off state in which an electric field is not formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecule LM is initially placed in a predetermined direction between the alignment film AL1 and the alignment film AL2. It is oriented. In such an off state, the light emitted from the lighting device IL toward the display panel PNL is absorbed by the optical element OD1 and the optical element OD2, resulting in dark display. On the other hand, in the on state where an electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecule LM is oriented in a direction different from the initial orientation direction by the electric field, and the orientation direction is controlled by the electric field. .. In such an on state, a part of the light from the illuminating device IL passes through the optical element OD1 and the optical element OD2 and becomes a bright display.

FIG. 9 is a cross-sectional view of the first substrate SUB1 along the line EF shown in FIG. In the illustrated first substrate SUB1, the layer below the insulating film 13 and the alignment film AL1 are not shown.

The first substrate SUB1 includes the above-mentioned drain electrodes DE, signal lines S1 and S2, metal electrodes ME, transparent electrodes TE, metal wirings ML1 and ML2, insulating films 13 to 16, pixel electrodes PE1, and a bridge portion BR.

The signal lines S1 and S2 and the drain electrode DE are located on the insulating film 13 and are covered with the insulating film 14. The drain electrode DE is located in the same layer as the signal lines S1 and S2, and is formed of the same material as the signal lines S1 and S2. The insulating film 14 has a through hole (first through hole) CH 11 that penetrates to the drain electrode DE.

The metal wirings ML1 and ML2 and the metal electrode ME are located on the insulating film 14 and are covered with the insulating film 15. The metal electrode ME is in contact with the drain electrode DE in the through hole CH11. The metal electrode ME is located in the same layer as the metal wirings ML1 and ML2, and is formed of the same metal material as the metal wirings ML1 and ML2. The insulating film 15 is located on the insulating film 14 and has a through hole (second through hole) CH 21 that penetrates to the metal electrode ME. In the present embodiment, the film thickness of the insulating film 14 is about 2.5 μm, and the film thickness of the insulating film 15 is about 1.5 μm.

The transparent electrode TE and the bridge portion BR are located on the insulating film 15 and are covered with the insulating film 16. The transparent electrode TE is in contact with the metal electrode ME in the through hole CH21. The transparent electrode TE and the bridge portion BR are located in the same layer as the common electrodes CE1 and CE2 shown in FIG. 5, and are formed of the same transparent conductive material as the common electrodes CE1 and CE2. The bridge portion BR is located directly above the signal line S2 and the metal wiring ML2. The insulating film 16 is located on the insulating film 15 and has a through hole (third through hole) CH 31 penetrating to the transparent electrode TE.

The base BS of the pixel electrode PE1 is located on the insulating film 16 and is covered with an alignment film AL1 (not shown). The pixel electrode PE1 is in contact with the transparent electrode TE in the through hole CH31. Further, the pixel electrode PE1 is electrically connected to the metal electrode ME.

FIG. 10 is a cross-sectional view of the display panel PNL along the line GH shown in FIG. FIG. 10 shows the non-display unit NDA of the display panel PNL.
The first substrate SUB1 includes peripheral wirings WR1 to WR3 and peripheral electrodes PRE in the non-display unit NDA. The peripheral wiring WR1 is arranged on the insulating film 12 and covered with the insulating film 13. The peripheral wiring WR1 is arranged in the same layer as the scanning line, and is formed of the same material as the scanning line. The peripheral wiring WR2 is arranged on the insulating film 13 and covered with the insulating film 14. The peripheral wiring WR2 is arranged in the same layer as the signal line, and is formed of the same material as the signal line. The peripheral wiring WR3 and the peripheral electrode PRE are arranged on the insulating film 16 and covered with the alignment film AL1. The peripheral wiring WR3 and the peripheral electrode PRE are arranged in the same layer as the pixel electrode and are formed of the same material as the pixel electrode.

The first substrate SUB1 has a groove GR that penetrates the insulating films 14 and 15 to the insulating film 13 in the non-display portion NDA. The groove GR is located in a region overlapping the seal SE. In the present embodiment, the width W1 of the groove portion GR is about 90 μm. The groove GR can block the intrusion route of moisture transmitted through the insulating films 14 and 15 from the outside of the display panel PNL.

The insulating film 16 is arranged on the insulating film 15 and is also arranged inside the groove GR. The insulating film 16 is in contact with the side surface of the groove GR. Since the side surface of the groove GR has a step formed by the insulating films 14 and 15, the insulating film 16 easily adheres to the side surface of the groove GR. Further, the peripheral electrode PRE and the alignment film AL1 are also arranged inside the groove GR.

The first substrate SUB1 has a bank portion BA composed of insulating films 14 and 15 in the non-display portion NDA. The bank portion BA is located between the third end portion EG3 of the display panel PNL and the groove portion GR, and projects toward the second substrate SUB2 side. The bank portion BA faces the spacer SP1. Further, the bank portion BA has slits SL1 to SL3. In the present embodiment, the width W2 of the bank portion BA is about 60 μm.

The light-shielding layer BM has a slit SL11 that penetrates to the insulating substrate 20. The intrusion path of moisture transmitted through the light-shielding layer BM can be blocked by the slit SL11. Since the first substrate SUB1 is provided with the peripheral wiring WR1 at a position overlapping the slit SL11, light leakage from the slit SL11 can be suppressed.

The light-shielding layer BM has a slit SL12 in a region overlapping the liquid crystal layer LC. Therefore, the transfer path of the electric charge to the display unit DA via the light-shielding layer BM can be blocked by the slit SL12. Thereby, in the manufacturing process of the display panel PNL, it is possible to suppress the concentration of static electricity on the display unit DA and prevent the display panel PNL from being damaged. Since the first substrate SUB1 is provided with the peripheral wiring WR2 at a position overlapping the slit SL12, light leakage from the slit SL12 can be suppressed. Further, the color filters CFR and CFB are arranged in the slit SL12 so as to overlap each other in the third direction Z. Therefore, it is possible to suppress light leakage from the slit SL12 even for the light transmitted around the peripheral wiring WR2.

The spacers SP1 to SP4 are arranged on the second substrate SUB2 and project to the first substrate SUB1 side. The spacers SP1 to SP4 are made of a resin material. Further, a color filter CFB for height adjustment is arranged at a position overlapping the spacers SP1 and SP2. In this embodiment, the width W3 of the spacer SP1 is about 50 μm. The alignment film AL2 does not cover the spacers SP1 to SP4.

The end BAE of the bank portion BA and the end SPE of the spacer SP1 are located at the third end portion EG3 of the display panel PNL. That is, the bank portion BA and the spacer SP1 are arranged on the cut line as members for supporting the display panel PNL when the display panel PNL is cut from a large size to a single piece in the manufacturing process. Therefore, it is possible to suppress the deformation of the display panel PNL due to the force applied when the display panel PNL is cut, and to suppress the cutting defect. Similarly, the bank portion BA and the spacer SP1 are placed on the cut line of the second end portion EG2 and the fourth end portion EG4 of the display panel PNL shown in FIG. 1 and the fifth end portion EG5 of the second substrate SUB2. positioned.

FIG. 11 is a detailed cross-sectional view of the region AR shown in FIG.
The slits SL1 to SL3 penetrate the insulating films 14 and 15 to the insulating film 13. The seal SE has entered the slits SL1 to SL3. Further, the bank portion BA has divided portions DD1 to DD4 divided by the slits SL1 to SL3. The divided portion DD1 is located on the display portion DA side of the third end portion EG3. The division unit DD2 is located on the display unit DA side of the division unit DD1. The division unit DD3 is located on the display unit DA side of the division unit DD2. The division unit DD4 is located on the display unit DA side of the division unit DD3. The slit SL1 is located between the divided portion DD1 and the divided portion DD2. The slit SL2 is located between the divided portion DD2 and the divided portion DD3. The slit SL3 is located between the divided portion DD3 and the divided portion DD4.

The insulating film 16 covers the divided portions DD1 to DD4 and extends to the third end portion EG3. Further, in the illustrated example, the alignment film AL1 covers the divided portions DD3 and DD4 and extends to the slit SL2, and does not cover the divided portions DD1 and DD2. The alignment film AL1 is not limited to the illustrated example, and may cover the divided portions DD1 and DD2 and extend to the third end portion EG3.

The insulating film 14 is divided into the divided portions DD41 to DD44 by the slits SL1 to SL3. The insulating film 15 is divided into the divided portions DD51 to DD54 by the slits SL1 to SL3. That is, the divided portion DD1 is composed of the divided portions D41 and D51, the divided portion DD2 is composed of the divided portions D42 and D52, the divided portion DD3 is composed of the divided portions D43 and D53, and the divided portion DD4 is composed of the divided portions D44 and D54. It is composed of.

The split portion D41 has a width W41, the split portion D42 has a width W42, the split portion D43 has a width W43, and the split portion D44 has a width W44. In the present embodiment, the widths W41 to W44 are 10 μm or more, respectively. Further, the slit SL1 has a width W45 between the split portion D41 and the split portion D42, the slit SL2 has a width W46 between the split portion D42 and the split portion D43, and the slit SL3 is split with the split portion D43. It has a width W47 with the portion D44. In the present embodiment, the widths W45 to W47 are 3.5 μm or more, respectively. Further, as shown in FIG. 10, the width W2 obtained by adding the widths W41 to W47 is about 60 μm.

The split portion D51 has a width W51, the split portion D52 has a width W52, the split portion D53 has a width W53, and the split portion D54 has a width W54. In the present embodiment, the widths W51 to W54 are 8 μm or more, respectively. Further, the slit SL1 has a width W55 between the split portion D51 and the split portion D52, the slit SL2 has a width W56 between the split portion D52 and the split portion D53, and the slit SL3 is split with the split portion D53. It has a width W57 with and from the portion D54. In the present embodiment, the widths W55 to W57 are 4 μm or more, respectively.

In the divided portion DD1, the width W41 of the divided portion D41 is larger than the width W51 of the divided portion D51. In the divided portion DD2, the width W42 of the divided portion D42 is larger than the width W52 of the divided portion D52. In the divided portion DD3, the width W43 of the divided portion D43 is larger than the width W53 of the divided portion D53. In the divided portion DD4, the width W44 of the divided portion D44 is larger than the width W54 of the divided portion D54. Further, the width W55 of the portion of the slit SL1 penetrating the insulating film 15 is larger than the width W45 of the portion penetrating the insulating film 14. Similarly, in the slit SL2, the width W56 is larger than the width W46. In the slit SL3, the width W57 is larger than the width W47.

The slit SL1 has side surfaces SS1 and SS2. The slit SL2 has side surfaces SS3 and SS4. The slit SL3 has side surfaces SS5 and SS6. The side surfaces SS1 to SS6 each have a step between the insulating film 14 and the insulating film 15. Since the slits SL1 to SL3 are formed by separately patterning the insulating films 14 and 15, the side surfaces SS1 to SS6 have a step.

The plurality of fillers 100 are diffused in the seal SE. Each of the fillers 100 has a diameter DM. Spacing between the split section DD1 and the spacer SP1, GP1, spacing between the split section DD2 and the spacer SP1, GP2, spacing between the split section DD3 and the spacer SP1, GP3, spacing between the split section DD4 and the spacer SP1. GP4 is substantially equal to the diameter DM of the filler 100. Therefore, the fillers 100 are interposed between the divided portions DD1 to DD4 and the spacer SP1 without overlapping each other in the third direction Z. The diameter DM is, for example, about 0.5 μm. The filler 100 has no adhesive force, and the first substrate SUB1 and the second substrate SUB are adhered by the adhesive force of the seal SE.

For example, when the bank portion BA does not have the slits SL1 to SL3, the seal SE is extruded from between the bank portion BA and the spacer SP1 when the first substrate SUB1 and the second substrate SUB2 are bonded. The filler 100 is densely packed between the bank portion BA and the spacer SP1. Therefore, there is a risk that the adhesive force between the first substrate SUB1 and the second substrate SUB2 will decrease.

According to the present embodiment, the bank portion BA has the insulating film 14 and the slits SL1 to SL3 penetrating the insulating film 15. The seal SE has entered the inside of the slits SL1 to SL3. Therefore, the filler 100 can be evenly dispersed in the slits SL1 to SL3 together with the seal SE, and the filler 100 can be prevented from being densely arranged between the bank portion BA and the spacer SP1. Further, the slits SL1 to SL3 can increase the adhesive area between the seal SE and the bank portion BA. Therefore, it is possible to suppress a decrease in the adhesive force between the first substrate SUB1 and the second substrate SUB2. Further, even when the bank portion BA has the slits SL1 to SL3, the support function of the bank portion BA can be maintained when the display panel PNL is cut into a single piece from a large size. Therefore, the reliability of the display device DSP can be improved.
In the illustrated example, the bank portion BA has three slits SL1 to SL3, but the bank portion BA may have one or two slits, or four or more slits. May have.

FIG. 12 is a plan view showing the positions of the slits SL1 to SL3 of the bank portion BA shown in FIG. In FIG. 12, the groove portion GR is indicated by an upward-sloping diagonal line, and the bank portion BA is indicated by an upward-sloping diagonal line. Further, the seal SE is shown by a dotted line.
The bank portion BA has a first portion BA1 and a second portion BA2 extending in the first direction X, and a third portion BA3 and a fourth portion BA4 extending in the second direction Y. The first part BA1 and the second part BA2 are connected to the third part BA3 and the fourth part BA4, respectively. The first portion BA1 is located between the display portion DA and the first end portion EG1. The second portion BA2 is located between the display portion DA and the second end portion EG2. The third portion BA3 is located between the display portion DA and the third end portion EG3. The fourth portion BA4 is located between the display portion DA and the fourth end portion EG4. The bank portion BA has slits SL1 to SL3 in the second portion BA2, the third portion BA3, and the fourth portion BA4. That is, the slits SL1 to SL3 are located between the second end portion EG2 and the display unit DA, between the third end portion EG3 and the display unit DA, and between the fourth end portion EG4 and the display unit DA. There is.

The groove portion GR has a first portion GR1 and a second portion GR2 extending in the first direction X, and a third portion GR3 and a fourth portion GR4 extending in the second direction Y. The first portion GR1 and the second portion GR2 are connected to the third portion GR3 and the fourth portion GR4, respectively. The first portion GR1 is located on the display portion DA side of the first portion BA1 of the bank portion BA. The second portion GR2 is located on the display portion DA side of the second portion BA2 of the bank portion BA. The third portion GR3 is located on the display portion DA side of the third portion BA3 of the bank portion BA. The fourth portion GR4 is located on the display portion DA side of the fourth portion BA4 of the bank portion BA.

The seal SE has a first portion SE1 and a second portion SE2 extending in the first direction X, and a third portion SE3 and a fourth portion SE4 extending in the second direction Y. The first portion SE1 and the second portion SE2 are connected to the third portion SE3 and the fourth portion SE4, respectively. In the illustrated example, the first portion SE1 overlaps the first portion GR1 of the groove portion GR, but does not overlap with the first portion BA1 of the bank portion BA. The second portion SE2 overlaps the second portion GR2 of the groove portion GR and the second portion BA2 of the bank portion BA. The third portion SE3 overlaps the third portion GR3 of the groove portion GR and the third portion BA3 of the bank portion BA. The fourth portion SE4 overlaps the fourth portion GR4 of the groove portion GR and the fourth portion BA4 of the bank portion BA. Further, the width W21 of the first portion SE1 is larger than the width W22 of the second portion SE2, the width W23 of the third portion SE3, and the width W24 of the fourth portion SE4.

The bank portion BA does not have slits SL1 to SL3 in the first portion BA1. Since the width of the non-display portion NDA on the first end EG1 side is wider than the width of the non-display portion NDA on the second end EG2 to the fourth end EG4 side, the first portion SE1 of the seal SE is the bank portion BA. It does not extend to the position where it overlaps with the first part BA1. Therefore, the slits SL1 to SL3 may not be formed in the first portion BA1. Further, since the first portion SE1 of the seal SE has a width larger than that of the second portion SE2 to the fourth portion SE4, the adhesive strength of the first portion SE1 is higher than that of the second portion SE2 to the fourth portion SE4, respectively. Stronger than the adhesive strength of. Therefore, even if the first portion SE1 overlaps with the first portion BA1 of the bank portion BA, the slits SL1 to SL3 may not be formed in the first portion BA1.

Next, a modification of the present embodiment will be described in detail.
FIG. 13 is a cross-sectional view showing a first modification of the present embodiment shown in FIG. 13 is different from the configuration shown in FIG. 11 in that the spacer SP1 has slits SL21 and SL22.
The slits SL21 and SL22 penetrate the spacer SP1 to the overcoat layer OC. The seal SE has entered the slits SL21 and SL22. Further, the spacer SP1 has divided portions SP11, SP12, and SP13 divided by the slits SL21 and SL22. The split portion SP11 is located on the display portion DA side of the third end portion EG3. The division unit SP12 is located on the display unit DA side of the division unit SP11. The division unit SP13 is located on the display unit DA side of the division unit SP12. The slit SL21 is located between the split portion SP11 and the split portion SP12. The slit SL22 is located between the split portion SP12 and the split portion SP13.

The split portion SP11 has a width W11, the split portion SP12 has a width W12, and the split portion SP13 has a width W13. In the present embodiment, the widths W11 to W13 are 7 μm or more, respectively. Further, the slit SL21 has a width W14 between the split portion SP11 and the split portion SP12, and the slit SL22 has a width W15 between the split portion SP12 and the split portion SP13. In the present embodiment, the widths W14 and W15 are 10 μm or more, respectively. Further, as shown in FIG. 10, the width W3 obtained by adding the widths W11 to W15 is about 50 μm.

The split portion SP11 faces the split portion DD1 of the bank portion BA. The split portion SP12 faces the split portion DD2 of the bank portion BA. The split portion SP13 faces the split portion DD4 of the bank portion BA. That is, the divided portions SP11 to SP13 of the spacer SP1 are arranged at positions facing any of the divided portions DD1 to DD4 of the bank portion BA, respectively.

Even when the spacer SP1 has the slits SL21 and SL22, the filler 100 can be evenly dispersed in the slits SL21 and SL22 together with the seal SE. Further, the slits SL21 and SL22 can increase the adhesive area between the seal SE and the spacer SP1. Further, even when the spacer SP1 has the slits SL21 and SL22, the support function of the spacer SP1 when the display panel PNL is cut into a single piece from a large size can be maintained. In the illustrated example, the spacer SP1 has two slits SL21 and SL22, but the spacer SP1 may have one slit or three or more slits. Is also good.
Even in such a modified example, the same effect as described above can be obtained.

FIG. 14 is a plan view showing the positions of the slits SL21 and SL22 of the spacer SP shown in FIG. In FIG. 14, the spacer SP1 is shown by a diagonal line rising to the left.
The spacer SP1 has a first portion SPP1 and a second portion SPP2 extending in the first direction X, and a third portion SPP3 and a fourth portion SPP4 extending in the second direction Y. The first part SPP1 and the second part SPP2 are connected to the third part SPP3 and the fourth part SPP4, respectively. The first portion SPP1 is located between the display portion DA and the first end portion EG1. The second portion SPP2 is located between the display portion DA and the second end portion EG2. The third portion SPP3 is located between the display portion DA and the third end portion EG3. The fourth portion SPP4 is located between the display portion DA and the fourth end portion EG4. The spacer SP1 has slits SL21 and SL22 in the second portion SPP2, the third portion SPP3, and the fourth portion SPP4. That is, the slits SL21 and SL22 are located between the second end portion EG2 and the display unit DA, between the third end portion EG3 and the display unit DA, and between the fourth end portion EG4 and the display unit DA. There is.

In the illustrated example, the first portion SE1 of the seal SE does not overlap the first portion SPP1 of the spacer SP1. The second portion SE2 overlaps the second portion SPP2 of the spacer SP1. The third portion SE3 overlaps with the third portion SPP3 of the spacer SP1. The fourth portion SE4 overlaps with the fourth portion SPP4 of the spacer SP1.

The spacer SP1 does not have the slits SL21 and SL22 in the first portion SPP1. Since the width of the non-display portion NDA on the first end EG1 side is wider than the width of the non-display portion NDA on the second end EG2 to the fourth end EG4 side, the first portion SE1 of the seal SE is the first of the spacer SP1. It does not extend to the position where it overlaps with one partial SPP1. Therefore, the slits SL21 and SL22 may not be formed in the first portion SPP1. Further, since the first portion SE1 of the seal SE has a width larger than that of the second portion SE2 to the fourth portion SE4, the adhesive strength of the first portion SE1 is higher than that of the second portion SE2 to the fourth portion SE4, respectively. Stronger than the adhesive strength of. Therefore, even if the first portion SE1 overlaps with the first portion SPP1 of the spacer SP1, the slits SL21 and SL22 may not be formed in the first portion SPP1.

FIG. 15 is a cross-sectional view showing a second modification of the present embodiment shown in FIG. FIG. 15 is different from the configuration shown in FIG. 11 in that the slit SL1 does not penetrate the insulating film 14.
That is, the slit SL1 penetrates the insulating film 15 to the insulating film 14. The slits SL2 and SL3 do not have to penetrate the insulating film 14. Alternatively, one or two of the slits SL1 to SL3 may be slits that do not penetrate the insulating film 14.
Even in such a modified example, the same effect as described above can be obtained.

As described above, according to the present embodiment, it is possible to obtain a display device capable of improving reliability.

The main configuration disclosed in this embodiment is applicable to a liquid crystal display device. In addition, the expression "substantially equal" in the present specification takes into consideration errors in the manufacturing process. Further, in the present embodiment, the width of the member arranged on the first substrate SUB1 such as the bank portion BA is measured on the most insulating substrate 10 side, and is arranged on the second substrate SUB2 such as the spacer SP1. The width of the member shall be measured on the side of the insulating substrate 20 most.

In addition, although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

DSP ... Display device, PNL ... Display panel, SUB1 ... 1st board, SUB2 ... 2nd board,
SE ... seal, DA ... display unit, NDA ... non-display unit, 14, 15, 16 ... insulating film,
BA ... Bank, SL1, SL2, SL3, SL21, SL22 ... Slit,
DD1 to DD4 ... Divided part, DE ... Drain electrode, SW ... Switching element,
CH11, CH21, CH31 ... Through holes, ME ... Metal electrodes, PE ... Pixel electrodes,
TE ... transparent electrode, GR ... groove, W41 to W47, W51 to W57 ... width,
SS1 to SS6 ... side surface, EG1 ... first end, EG2 ... second end, EG3 ... third end,
EG4 ... 4th end, MA ... mounting part, SP1 ... spacer, 100 ... filler,
DM ... Diameter, SP11, SP12, SP13 ... Divided part.

Claims (15)

A display panel having a display unit for displaying an image and a non-display unit surrounding the display unit is provided.
The display panel is
It is composed of an insulating substrate, a first organic insulating film, a second organic insulating film arranged on the first organic insulating film, and the first organic insulating film and the second organic insulating film in the non-display portion. A first board with a bank, and
The second substrate facing the first substrate and
A seal for adhering the first substrate and the second substrate is provided.
The bank portion has a first organic insulating film, a first slit penetrating the second organic insulating film, and a first divided portion and a second divided portion divided by the first slit. It protrudes from the insulating substrate side to the second substrate side and is located closer to the outer peripheral end portion of the display panel than the display unit.
The seal is placed in the first slit and
A display device in which the width of the portion of the first slit penetrating the second organic insulating film is larger than the width of the portion of the first slit penetrating the first organic insulating film . The first substrate has a groove portion that penetrates the first organic insulating film and the second organic insulating film in the non-display portion.
The bank portion is located between the end portion of the display panel and the groove portion .
The width of the portion of the groove portion penetrating the first organic insulating film is larger than the width of the portion of the first slit penetrating the first organic insulating film.
The width of the portion of the groove portion penetrating the second organic insulating film is larger than the width of the portion of the first slit penetrating the second organic insulating film.
The display device according to claim 1 , wherein the width of the groove portion is larger than the width of the bank portion . The first substrate has a switching element having a drain electrode and a switching element in the display unit .
A metal electrode in contact with the drain electrode in the first through hole penetrating the first organic insulating film to the drain electrode,
The display device according to claim 2, further comprising a pixel electrode electrically connected to the metal electrode. The first substrate further comprises a transparent electrode in contact with the metal electrode in a second through hole penetrating the second organic insulating film to the metal electrode.
An inorganic insulating film located on the second organic insulating film and having a third through hole penetrating to the transparent electrode is provided.
The display device according to claim 3, wherein the pixel electrode is located on the inorganic insulating film and is in contact with the transparent electrode in the third through hole. The width of the first organic insulating film of the first partitioning portion is larger than the width of the second organic insulating film of the first partitioning portion.
The display device according to any one of claims 1 to 4, wherein the width of the first organic insulating film of the second divided portion is larger than the width of the second organic insulating film of the second divided portion. The display device according to any one of claims 1 to 5 , wherein the side surface of the first slit has a step between the first organic insulating film and the second organic insulating film. The display panel includes a first end portion and a second end portion extending in a first direction, a third end portion and a fourth end portion extending in a second direction intersecting the first direction, and the display. It has a mounting portion between the portion and the first end portion, and has.
The first slit is located between the second end and the display, between the third end and the display, and between the fourth end and the display. The display device according to any one of claims 1 to 6 . The bank portion has a first organic insulating film, a second slit penetrating the second organic insulating film, and a third divided portion divided by the second slit.
The display device according to any one of claims 1 to 7 , wherein the seal is arranged in the second slit. The display device according to any one of claims 1 to 8 , wherein the bank portion has a third slit that penetrates the second organic insulating film to the first organic insulating film. The second substrate is located in the vicinity of the outer peripheral end portion of the display panel, and includes a spacer protruding toward the first substrate side.
The display device according to any one of claims 1 to 9 , wherein the bank portion faces the spacer. In addition, the seal is provided with a plurality of diffused fillers.
The display device according to claim 10 , wherein the distance between the first division portion and the spacer and the distance between the second division portion and the spacer are substantially equal to the diameter of the filler. The display device according to claim 10 , wherein the end portion of the bank portion and the end portion of the spacer are located at the end portion of the display panel. The spacer has a fourth slit penetrating the spacer, and a fourth division portion and a fifth division portion divided by the fourth slit.
The display device according to any one of claims 10 to 12 , wherein the seal is arranged in the fourth slit. The display panel includes a first end portion and a second end portion extending in a first direction, a third end portion and a fourth end portion extending in a second direction intersecting the first direction, and the display. It has a mounting portion between the portion and the first end portion, and has.
The fourth slit is located between the second end and the display, between the third end and the display, and between the fourth end and the display. The display device according to claim 13 . The spacer has a fifth slit penetrating the spacer and a sixth divided portion divided by the fifth slit.
The display device according to claim 13 , wherein the seal is arranged in the fifth slit.

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