JP2019152719A - Display - Google Patents

Abstract

To provide a display that can prevent a deterioration in display quality.SOLUTION: A display comprises: a scan line extending in a first direction; and a switching element including a semiconductor layer overlapping at least part of the scan line and a drain electrode connected to the semiconductor layer. The drain electrode has a first portion in connection with the semiconductor layer and a second portion between the scan line and the first portion. The first portion projects from the second portion in a second direction intersecting the first direction.SELECTED DRAWING: Figure 5

Description

  Embodiments described herein relate generally to a display device.

  In recent years, various display devices incorporating a touch sensor have been proposed. In one example, a display device is disclosed that serves as a sensor electrode when a plurality of electrodes formed on a display panel are in a touch sensing mode, and serves as a common electrode when in a display mode. As the touch sensing method, either a mutual capacitance method or a self-capacitance method is applied. In the touch sensing mode, sensing is performed by applying a touch drive voltage to the sensor electrode through a signal line.

JP 2015-122057 A

  An object of the present embodiment is to provide a display device capable of suppressing deterioration in display quality.

  According to this embodiment, the switching element includes: a scanning line extending in the first direction; a semiconductor layer overlapping at least a part of the scanning line; and a drain electrode connected to the semiconductor layer. The drain electrode includes a first portion in contact with the semiconductor layer, and a second portion between the scan line and the first portion, and the first portion is formed from the second portion to the first portion. A display device is provided that protrudes in a second direction that intersects one direction.

FIG. 1 is a perspective view showing a configuration of a display device according to the present embodiment. 2 is a plan view illustrating a configuration example of a touch sensor provided in the display device illustrated in FIG. FIG. 3 is a diagram showing an equivalent circuit of the display panel shown in FIG. FIG. 4 is a plan view showing an example of a pixel layout. FIG. 5 is a plan view showing an example of the pixel shown in FIG. FIG. 6 is a cross-sectional view of the first substrate along the line AB shown in FIG. FIG. 7 is a plan view showing a configuration of a comparative example of the drain electrode and the light shielding layer. FIG. 8 is a plan view showing the configuration of the drain electrode and the light shielding layer of the present embodiment. FIG. 9 is a cross-sectional view of the display device taken along the line CD shown in FIG. FIG. 10 is a cross-sectional view of the display device taken along line EF shown in FIG. FIG. 11 is a plan view showing the configuration of the light shielding layer, the main spacer, and the sub-spacer of the present embodiment. FIG. 12 is a plan view showing a modification of the drain electrode of this embodiment.

  Hereinafter, the present embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the sake of clarity, the drawings may be schematically represented with respect to the width, thickness, shape, etc. of each part as compared to actual aspects, but are merely examples, and The interpretation is not limited. In addition, in the present specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are denoted by the same reference numerals, and repeated detailed description may be omitted as appropriate. .

  In the present embodiment, a liquid crystal display device will be described as an example of the display device DSP. Note that the main configuration disclosed in this embodiment includes a self-luminous display device having an organic electroluminescence display element, an electronic paper display device having an electrophoretic element, and a micro electro mechanical systems (MEMS). The present invention can also be applied to a display device to which application is applied or a display device to which electrochromism is applied.

FIG. 1 is a perspective view showing the configuration of the display device DSP according to the present embodiment.
FIG. 1 shows a three-dimensional space defined by a first direction X, a second direction Y perpendicular to the first direction X, and a third direction Z perpendicular to the first direction X and the second direction Y. ing. In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to the direction parallel to the main surface of the substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In this specification, a direction toward the tip of the arrow indicating the third direction Z is referred to as upward (or simply upward), and a direction opposite from the tip of the arrow is referred to as downward (or simply downward). In addition, it is assumed that there is an observation position for observing the display device DSP on the tip side of the arrow indicating the third direction Z, and from this observation position, the XY plane defined by the first direction X and the second direction Y is directed. This is called planar view.

  As shown in FIG. 1, the display device DSP includes a display panel PNL, a flexible printed circuit board 1, an IC chip 2, and a circuit board 3.

  The display panel PNL includes a first substrate SUB1 and a second substrate SUB2 disposed to face the first substrate SUB1. The display panel PNL includes a display unit DA that displays an image and a non-display unit NDA that surrounds the display unit DA. The display panel PNL includes a plurality of pixels PX in the display unit DA.

  The first substrate SUB1 has a mounting portion MA that extends outward from a region overlapping the second substrate SUB2. The three side edges of the first substrate SUB1 are aligned with the three side edges of the second substrate SUB2 in the third direction Z. The length of the side edge parallel to the first direction X of the first substrate SUB1 is substantially equal to the length of the side edge parallel to the first direction X of the second substrate SUB2. Further, the length of the side edge parallel to the second direction Y of the first substrate SUB1 is larger than the length of the side edge parallel to the second direction Y of the second substrate SUB2. That is, the area parallel to the XY plane of the first substrate SUB1 is larger than the area parallel to the XY plane of the second substrate SUB2. Here, the XY plane is a plane defined by the first direction X and the second direction Y.

  In the illustrated example, the flexible printed circuit board 1 is mounted on the mounting portion MA in the non-display portion NDA. The flexible printed circuit board 1 is electrically connected to the display panel PNL. The circuit board 3 is mounted under the flexible printed circuit board 1 and is electrically connected to the flexible printed circuit board 1. The IC chip 2 is mounted on the flexible printed circuit board 1. The IC chip 2 may be mounted on the mounting part MA. The IC chip 2 functions as a signal supply source that supplies signals necessary for driving the display panel PNL.

  The display panel PNL of the present embodiment has a transmissive display function for displaying an image by selectively transmitting light from the back side of the first substrate SUB1, and light from the front side of the second substrate SUB2. May be either a reflective type having a reflective display function for displaying an image by selectively reflecting the light, or a transflective type having a transmissive display function and a reflective display function.

  The detailed configuration of the display panel PNL is omitted here, but the display panel PNL has a display mode that uses a horizontal electric field along the main surface of the substrate and a vertical electric field along the normal of the main surface of the substrate. Corresponding to the display mode to be used, the display mode using a gradient electric field inclined in an oblique direction with respect to the main surface of the substrate, and the display mode using an appropriate combination of the above horizontal electric field, vertical electric field, and gradient electric field Any configuration may be provided. Here, the substrate main surface is a surface parallel to the XY plane defined by the first direction X and the second direction Y.

  FIG. 2 is a plan view showing a configuration example of the touch sensor TS provided in the display device DSP shown in FIG. Here, a mutual capacitance type touch sensor TS will be described, but the touch sensor TS may be a self-capacitance type.

  The touch sensor TS includes drive electrodes TX1 to TXn, detection electrodes RX1 to RXm, a flexible printed circuit board 4, a touch detection IC chip 5, and the like. Note that n and m are integers of 2 or more, for example. The flexible printed circuit board 4 is connected to the second board SUB2. The touch detection IC chip 5 is mounted on the flexible printed circuit board 4.

  The drive electrodes TX1 to TXn are arranged on the first substrate SUB1. The plurality of drive electrodes TX1 to TXn are each formed in a strip shape, extend in the second direction Y, and are arranged at intervals in the first direction X. In the touch sensing mode for detecting the approach or contact of an object to the display device DSP, a touch drive voltage is applied to the drive electrodes TX1 to TXn. In the display mode for displaying an image, the drive electrodes TX1 to TXn function as a common electrode CE to which a common voltage (Vcom) is applied. The common voltage is applied from, for example, a common electrode driving circuit included in the IC chip 2.

  The detection electrodes RX1 to RXm are arranged on the second substrate SUB2. The plurality of detection electrodes RX1 to RXm are each formed in a strip shape, extend in the first direction X, and are arranged at intervals in the second direction Y. The plurality of detection electrodes RX1 to RXm intersect with the plurality of drive electrodes TX1 to TXn in the display unit DA. The detection electrodes RX1 to RXm are electrically connected to the touch detection IC chip 5 via the lead wires LD located in the non-display portion NDA and the flexible printed circuit board 4. The lead wire LD is electrically connected to the detection electrodes RX1 to RXm on a one-to-one basis. The lead wire LD is preferably formed of a thin metal wire from the viewpoint of reducing resistance.

FIG. 3 is a diagram showing an equivalent circuit of the display panel PNL shown in FIG.
The plurality of pixels PX are arranged in a matrix in the first direction X and the second direction Y. Here, the pixel indicates a minimum unit that can be individually controlled in accordance with a pixel signal, and exists, for example, in a region including a switching element arranged at a position where a scanning line and a signal line, which will be described later, intersect. .

  The display panel PNL includes a plurality of scanning lines G, a plurality of signal lines S, a common electrode CE, and the like in the display unit DA. Each scanning line G extends in the first direction X and is aligned in the second direction Y. The signal lines S extend in the second direction Y and are aligned in the first direction X, respectively. Note that the scanning lines G and the signal lines S do not necessarily extend linearly, and some of them may be bent. The common electrode CE is disposed over the plurality of pixels PX. The scanning line G, the signal line S, and the common electrode CE are each drawn out to the non-display portion NDA. In the non-display portion NDA, the scanning line G is connected to the scanning line driving circuit GD, the signal line S is connected to the signal line driving circuit SD, and the common electrode CE is connected to the common electrode driving circuit CD. The signal line driving circuit SD, the scanning line driving circuit GD, and the common electrode driving circuit CD may be formed on the first substrate, or a part or all of them may be built in the IC chip 2 shown in FIG. May be.

  Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and the like. The switching element SW is composed of, for example, a thin film transistor (TFT) and is electrically connected to the scanning line G and the signal line S. More specifically, the switching element SW includes a gate electrode WG, a source electrode WS, and a drain electrode WD. The gate electrode WG is electrically connected to the scanning line G. In the illustrated example, an electrode electrically connected to the signal line S is referred to as a source electrode WS, and an electrode electrically connected to the pixel electrode PE is referred to as a drain electrode WD. The pixel electrode PE is electrically connected to the switching element SW.

  The scanning line G is connected to the switching element SW in each of the pixels PX arranged in the first direction X. The signal line S is connected to the switching element SW in each of the pixels PX arranged in the second direction Y. Each pixel electrode PE faces the common electrode CE, and drives the liquid crystal layer LC by an electric field generated between the pixel electrode PE and the common electrode CE. The storage capacitor CS is formed between, for example, an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

FIG. 4 is a plan view showing an example of a pixel layout.
In FIG. 4, a direction that intersects the second direction Y at an acute angle counterclockwise is defined as a direction D1, and a direction that intersects the second direction Y at an acute angle clockwise is defined as a direction D2. The angle θ1 formed by the second direction Y and the direction D1 is substantially the same as the angle θ2 formed by the second direction Y and the direction D2.

  The scanning lines G1 to G3 each extend linearly along the first direction X and are arranged at intervals in the second direction Y. Each of the signal lines S1 to S3 extends substantially along the second direction Y, and is arranged in the first direction X at intervals.

  The pixel electrodes PE1 and PE2 are disposed between the scanning lines G1 and G2. The pixel electrodes PE1 and PE2 are arranged along the first direction X. The pixel electrodes PE3 and PE4 are disposed between the scanning lines G2 and G3. The pixel electrodes PE3 and PE4 are arranged along the first direction X. The pixel electrodes PE1 and PE3 are disposed between the signal lines S1 and S2, and the pixel electrodes PE2 and PE4 are disposed between the signal lines S2 and S3.

  The pixel electrodes PE1 and PE2 respectively have band electrodes Pa1 and Pa2 extending along the direction D1. The pixel electrodes PE3 and PE4 have band electrodes Pa3 and Pa4 extending along the direction D2, respectively. In the illustrated example, the number of strip electrodes Pa1 to Pa4 is three, but may be one or two, or may be four or more. Note that the common electrode CE (not shown) is disposed over the pixels PX1 to PX4.

  FIG. 5 is a plan view showing an example of the pixel shown in FIG. Here, the main part will be described focusing on the pixel PX1 surrounded by the scanning lines G1 and G2 and the signal lines S1 and S2 shown in FIG.

  The switching element SW is electrically connected to the scanning line G2 and the signal line S2. The switching element SW includes a semiconductor layer SC and a drain electrode WD.

  The semiconductor layer SC is arranged so that a part thereof overlaps with the signal line S2, and the other part extends between the signal lines S1 and S2 and is formed in a substantially U shape. Further, the semiconductor layer SC overlaps at least a part of the scanning line G2. The semiconductor layer SC intersects the scanning line G2 at a position overlapping the signal line S2, and also intersects the scanning line G2 between the signal lines S1 and S2. In the scanning line G2, regions overlapping with the semiconductor layer SC function as gate electrodes GE1 and GE2, respectively. That is, the switching element SW in the illustrated example has a double gate structure. The semiconductor layer SC is electrically connected to the signal line S2 through the through hole CH1 at one end SCA, and is electrically connected to the drain electrode WD through the through hole CH2 at the other end SCB.

  The drain electrode WD is formed in an island shape and is disposed between the signal line S1 and the signal line S2. The drain electrode WD has a first part PT1 that overlaps the through hole CH2, and a second part PT2 between the scanning line G2 and the first part PT1. In the drawing, the first portion PT1 is indicated by hatching. The first part PT1 protrudes in the second direction Y from the second part PT2. The first portion PT1 has a width W1 in the first direction X, and the second portion PT2 has a width W2 in the first direction X. The width W2 is larger than the width W1. Further, the through hole CH2 has a width W3 in the first direction X. In the illustrated example, the width W1 is equal to the width W3. That is, the first portion PT1 is formed in a size equivalent to the through hole CH2 in plan view. The first portion PT1 may be formed larger than the through hole CH2, and the width W1 may be larger than the width W3. Further, the width of the first portion PT1 in the second direction Y may be larger than, equal to, or smaller than the width of the through hole CH2 in the second direction Y.

  The pixel electrode PE1 includes a base portion BS1 integrated with a plurality of band electrodes Pa1. Base BS1 overlaps with drain electrode WD and is electrically connected to drain electrode WD. In the illustrated example, the base BS1 overlaps with the second portion PT2. A connection part that connects the pixel electrode PE1 and the switching element SW will be described later.

FIG. 6 is a cross-sectional view of the first substrate SUB1 along the line AB shown in FIG.
The first substrate SUB1 includes an insulating substrate 10, insulating films 11 to 15, a semiconductor layer SC, a scanning line G2, a signal line S2, a common electrode CE, a metal wiring ML2, an alignment film AL1, and the like.

  The insulating substrate 10 is a light transmissive substrate such as a glass substrate or a flexible resin substrate. The insulating film 11 is located on the insulating substrate 10. The semiconductor layer SC is located on the insulating film 11 and is covered with the insulating film 12. The semiconductor layer SC is formed of, for example, polycrystalline silicon, but may be formed of amorphous silicon or an oxide semiconductor.

  The gate electrode GE1, which is a part of the scanning line G2, is located on the insulating film 12 and is covered with the insulating film 13. Other scanning lines (not shown) are also located in the same layer as the scanning line G2. The scanning line G2 is made of metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), and chromium (Cr), and these metal materials. It is formed of a combined alloy or the like, and may have a single layer structure or a multilayer structure. In one example, the scanning line G2 is formed of a molybdenum-tungsten alloy.

  The signal line S <b> 2 is located on the insulating film 13 and is covered with the insulating film 14. Other signal lines (not shown) are also located in the same layer as the signal line S2. The signal line S2 is formed of the above metal material or an alloy in which the above metal materials are combined, and may have a single layer structure or a multilayer structure. In one example, the signal line S2 is a stacked body in which a first layer containing titanium (Ti), a second layer containing aluminum (Al), and a third layer containing titanium (Ti) are stacked in this order. The signal line S2 is in contact with the semiconductor layer SC through a through hole CH1 that penetrates the insulating film 12 and the insulating film 13.

  The common electrode CE is located on the insulating film 14. The common electrode CE is a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

  The metal wiring ML2 is located on the common electrode CE and is covered with the insulating film 15. The metal wiring ML2 is formed of the above metal material or an alloy combining the above metal materials, and may have a single layer structure or a multilayer structure. In one example, the metal wiring ML2 is a stacked body in which a first layer including titanium (Ti), a second layer including aluminum (Al), and a third layer including titanium (Ti) are stacked in this order, or A stacked body in which a first layer including molybdenum (Mo), a second layer including aluminum (Al), and a third layer including molybdenum (Mo) are stacked in this order. The alignment film AL1 is located on the insulating film 15.

  The insulating films 11 to 13 and the insulating film 15 are inorganic insulating films formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure. A multilayer structure may be used. The insulating film 14 is an organic insulating film formed of an organic insulating material such as an acrylic resin, for example.

FIG. 7 is a plan view showing a configuration of a comparative example of the drain electrode WD and the light shielding layer BM.
The light shielding layer BM includes a first light shielding layer BM11 extending in the first direction X, and second light shielding layers BM21 and BM22 extending in the second direction Y. The first light shielding layer BM11 overlaps the drain electrode WD. The second light shielding layer BM21 is superimposed on the signal line S1. The second light shielding layer BM22 overlaps with the signal line S2.

  In the comparative example shown in FIG. 7, the drain electrode WD has a width W2 even at the position where the through hole CH2 is formed. That is, as compared with the present embodiment, the drain electrode WD does not have the first portion protruding in the second direction Y. Further, the drain electrode WD has corner portions CN1 and CN2 that extend to the outside of the region overlapping the first light shielding layer BM11. Therefore, the light reflected by the corner portions CN1 and CN2 may leak from the first light shielding layer BM11 and the contrast of the display device may be lowered. Further, when the width W11 of the first light shielding layer BM11 is increased to cover the corner portions CN1 and CN2, the aperture ratio is reduced.

FIG. 8 is a plan view showing the configuration of the drain electrode WD and the light shielding layer BM of the present embodiment.
The present embodiment shown in FIG. 8 is different from the comparative example shown in FIG. 7 in that the corner portions CN1 and CN2 of the drain electrode WD are not formed. Further, the first light shielding layer BM11 has a protrusion PR that overlaps the first portion PT1. The protrusion PR protrudes in the second direction Y. The width W12 of the first light shielding layer BM11 is smaller than the width W11 of the first light shielding layer BM1 of the comparative example shown in FIG.

  According to the present embodiment, the drain electrode WD has the first portion PT1 protruding from the second portion PT2. That is, it is possible to leave the first portion PT1, which is a region overlapping with the through hole CH2, and to delete the corner portions CN1 and CN2 unnecessary for the contact. Accordingly, light leakage from the corner portions CN1 and CN2 can be suppressed. Accordingly, it is possible to suppress a decrease in contrast of the display device.

  Further, the first light shielding layer BM11 has a protruding portion PR. That is, by making the shape of the first light shielding layer BM11 along the shape of the drain electrode WD, the width W12 of the first light shielding layer BM11 can be reduced. Therefore, the area of the light shielding layer BM can be reduced, and the aperture ratio can be improved as compared with the comparative example.

  FIG. 9 is a cross-sectional view of the display device DSP along the line CD shown in FIG. The illustrated example corresponds to an example in which an FFS (Fringe Field Switching) mode, which is one of display modes using a horizontal electric field, is applied.

  In the first substrate SUB1, the signal lines S1 and S2 and the drain electrode WD are located on the insulating film 13 and covered with the insulating film 14. The first portion PT1 is in contact with the semiconductor layer SC in the through hole CH2 that penetrates the insulating films 12 and 13. The insulating films 12 and 13 correspond to an insulating film between the drain electrode WD and the semiconductor layer SC. The metal wirings ML1 and ML2 are located immediately above the signal lines S1 and S2, respectively. The pixel electrode PE1 is located on the insulating film 15 and is covered with the alignment film AL1. The pixel electrode PE1 is a transparent electrode formed of a transparent conductive material such as ITO or IZO.

The second substrate SUB2 includes an insulating substrate 20, a light shielding layer BM, a color filter CF, an overcoat layer OC, an alignment film AL2, and the like.
The insulating substrate 20 is a substrate having optical transparency such as a glass substrate or a resin substrate, like the insulating substrate 10. The light shielding layer BM and the color filter CF are located on the side of the insulating substrate 20 facing the first substrate SUB1. The color filter CF is disposed at a position facing the pixel electrode PE1, and a part of the color filter CF overlaps the light shielding layer BM. The overcoat layer OC covers the color filter CF. The overcoat layer OC is formed of a transparent resin. The alignment film AL2 covers the overcoat layer OC. The alignment film AL1 and the alignment film AL2 are made of, for example, a material exhibiting horizontal alignment.

  The first substrate SUB1 and the second substrate SUB2 described above are arranged so that the alignment film AL1 and the alignment film AL2 face each other. The first substrate SUB1 and the second substrate SUB2 are bonded with a sealing material in a state where a predetermined cell gap is formed. The liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2, and is held between the alignment film AL1 and the alignment film AL2. The liquid crystal layer LC includes liquid crystal molecules LM. The liquid crystal layer LC is composed of a positive type (positive dielectric anisotropy) liquid crystal material or a negative type (negative dielectric anisotropy) liquid crystal material.

  The detection electrode RX is located on the insulating substrate 20. The detection electrode Rx may be formed of a conductive layer containing metal, a transparent conductive material such as ITO or IZO, or a transparent conductive layer may be laminated on the conductive layer containing metal, or conductive May be formed of a conductive organic material, a fine conductive material dispersion, or the like.

  The optical element OD1 including the first polarizing plate PL1 is located between the insulating substrate 10 and the illumination device BL. The optical element OD2 including the second polarizing plate PL2 is located on the detection electrode RX. The optical element OD1 and the optical element OD2 may include a retardation plate, a scattering layer, and an antireflection layer as necessary.

  In such a display panel PNL, in an off state in which no electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules LM are initially set in a predetermined direction between the alignment film AL1 and the alignment film AL2. Oriented. In such an off state, the light emitted from the illumination device IL toward the display panel PNL is absorbed by the optical element OD1 and the optical element OD2, and dark display is performed. On the other hand, in the ON state in which an electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules LM are aligned in a direction different from the initial alignment direction by the electric field, and the alignment direction is controlled by the electric field. . In such an on state, a part of the light from the illumination device IL is transmitted through the optical element OD1 and the optical element OD2, and a bright display is obtained.

FIG. 10 is a cross-sectional view of the display device DSP along the line E-F shown in FIG.
The insulating film 14 has a through hole CH3 that penetrates to the drain electrode WD. Further, the insulating film 15 has a through hole CH4 connected to the through hole CH3. The base BS1 of the pixel electrode PE1 is in contact with the second portion PT2 of the drain electrode WD via the through holes CH3 and CH4.

FIG. 11 is a plan view showing the configuration of the light shielding layer BM, the main spacer MSP, and the sub-spacer SSP of the present embodiment.
The main spacer MSP overlaps the position where the first light shielding layer BM11 and the second light shielding layer BM23 intersect. The sub-spacer SSP overlaps the position where the first light shielding layer BM11 and the second light shielding layer BM26 intersect. Although not shown, the main spacer MSP and the sub-spacer SSP are made of a resin material and are disposed between the first substrate SUB1 and the second substrate SUB2. The main spacer MSP forms a cell gap between the first substrate SUB1 and the second substrate SUB2. The cell gap is, for example, 2 to 5 μm. The sub-spacer SSP has a height lower than that of the main spacer MSP.

  In addition, the light shielding layer BM has an extended portion EX1 at a position where the first light shielding layer BM11 and the second light shielding layer BM23 intersect, and at a position where the first light shielding layer BM11 and the second light shielding layer BM26 intersect. It has an extension part EX2. The extension part EX1 overlaps with the main spacer MSP, and is extended substantially concentrically with the main spacer MSP in plan view. The extension part EX2 overlaps with the sub-spacer SSP and is extended substantially concentrically with the sub-spacer SSP in plan view.

  In the illustrated example, the drain electrodes WD1 and WD2 overlap the extended portion EX1. The first light shielding layer BM11 has a protruding portion PR at a position overlapping the drain electrode WD3. The second light shielding layer BM26 side of the drain electrode WD4 overlaps with the extension part EX2. In addition, the second light shielding layer BM26 side of the drain electrode WD5 overlaps the extended portion EX2. The projecting part PR of the light shielding layer BM is not arranged at a position overlapping the extended parts EX1 and EX2. That is, the extended portions EX1 and EX2 are formed with priority over the projecting portion PR.

FIG. 12 is a plan view showing a modification of the drain electrode WD of the present embodiment. For example, the shape of the drain electrode WD may be the shape shown in FIG.
As shown in FIG. 12A, FIG. 12B, and FIG. 12C, the first portion PT1 and the second portion PT2 of the drain electrode WD have rounded portions. The shape is not limited to a rectangular shape, and may be a circular shape.
In such a modification, the same effect as described above can be obtained.

  As described above, according to the present embodiment, it is possible to obtain a display device capable of suppressing a reduction in display quality.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DSP ... display device, G ... scanning line, SW ... switching element, SC ... semiconductor layer,
WD ... drain electrode, PT1 ... first part, PT2 ... second part,
W1, W2, W3, W11, W12 ... width, Ch2 ... through hole, 12, 13 ... insulating film,
BM ... light shielding layer, BM11 ... first light shielding layer, BM21 to BM26 ... second light shielding layer,
PR ... protrusion, MSP ... main spacer, SSP ... sub-spacer,
EX1, EX2 ... extended portion, RX ... detection electrode, TX ... drive electrode, PE ... pixel electrode.

Claims (6)

A scanning line extending in a first direction;
A switching element comprising: a semiconductor layer overlapping at least a part of the scanning line; and a drain electrode connected to the semiconductor layer,
The drain electrode has a first portion in contact with the semiconductor layer, and a second portion between the scanning line and the first portion,
The display device, wherein the first portion protrudes from the second portion in a second direction intersecting the first direction. Furthermore, an insulating film between the semiconductor layer and the drain electrode is provided,
The width of the second portion in the first direction is greater than the width of the first portion in the first direction,
The first portion is in contact with the semiconductor layer in the through hole that penetrates the insulating film,
The display device according to claim 1, wherein a width of the first portion in the first direction is equal to a width of the through hole in the first direction. And a light-shielding layer having a first light-shielding layer extending in the first direction and overlapping the drain electrode, and a second light-shielding layer extending in the second direction,
The display device according to claim 1, wherein the first light-shielding layer has a protruding portion that overlaps the first portion. A spacer that overlaps with a position where the first light shielding layer and the second light shielding layer intersect;
The light shielding layer has an extended portion at a position where the first light shielding layer and the second light shielding layer intersect,
The display device according to claim 3, wherein the protruding portion of the light shielding layer is not disposed at a position overlapping the extension portion.   5. The apparatus according to claim 1, further comprising: a plurality of detection electrodes extending in the first direction and arranged in the second direction; and a plurality of drive electrodes extending in the second direction and arranged in the first direction. The display device according to any one of the above. And a pixel electrode electrically connected to the switching element,
The display device according to claim 1, wherein the pixel electrode is in contact with the second portion.

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