JP7027983B2 - リードフレーム - Google Patents
リードフレーム Download PDFInfo
- Publication number
- JP7027983B2 JP7027983B2 JP2018047522A JP2018047522A JP7027983B2 JP 7027983 B2 JP7027983 B2 JP 7027983B2 JP 2018047522 A JP2018047522 A JP 2018047522A JP 2018047522 A JP2018047522 A JP 2018047522A JP 7027983 B2 JP7027983 B2 JP 7027983B2
- Authority
- JP
- Japan
- Prior art keywords
- frame
- transistor
- metal plate
- terminal
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
3、5:トランジスタ
4、6:ダイオード
7a-7d:銅ブロック
8:ハンダ
9:樹脂パッケージ
12、15、22、25:放熱板
13、16、26:継手
14:パワー端子
15a、15b:制御端子
14s1、14s2、43s1、43s2:接合部
40:リードフレーム
42:第1フレーム
42a、43a:連結部
43:第2フレーム
51:ボンディングワイヤ
Claims (3)
- 金属板に固定されている半導体チップが樹脂パッケージに封止されているとともに、前記半導体チップと導通している第1端子が前記樹脂パッケージの一面から延びており、前記半導体チップと導通している第2端子が前記一面の反対側の面から延びている半導体装置の製造に用いるリードフレームであり、
前記金属板よりも薄く、前記第1端子を支持しているとともに前記金属板に接合されている第1フレームと、
前記金属板よりも薄く、前記第2端子を支持しており、前記金属板の法線方向からみて前記第1フレームとは反対側に位置しており、前記金属板に接合されている第2フレームと、
を備えている、半導体装置製造用のリードフレーム。 - 前記第1フレームと前記第2フレームの少なくとも一方は、平面を規定する3点の接合箇所を含むように前記金属板に接合されている、請求項1に記載のリードフレーム。
- 前記第1フレームまたは前記第2フレームの前記金属板との接合部が、前記金属板の縁と前記半導体チップとの間に延びている、請求項1又は2に記載のリードフレーム。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018047522A JP7027983B2 (ja) | 2018-03-15 | 2018-03-15 | リードフレーム |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018047522A JP7027983B2 (ja) | 2018-03-15 | 2018-03-15 | リードフレーム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019161084A JP2019161084A (ja) | 2019-09-19 |
JP7027983B2 true JP7027983B2 (ja) | 2022-03-02 |
Family
ID=67994963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018047522A Active JP7027983B2 (ja) | 2018-03-15 | 2018-03-15 | リードフレーム |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7027983B2 (ja) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010098165A (ja) * | 2008-10-17 | 2010-04-30 | Yamaha Corp | 半導体装置、半導体装置の製造方法、及び、リードフレームユニット |
JP5805029B2 (ja) * | 2012-08-08 | 2015-11-04 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP6178555B2 (ja) * | 2012-09-07 | 2017-08-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP6152842B2 (ja) * | 2014-11-04 | 2017-06-28 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
-
2018
- 2018-03-15 JP JP2018047522A patent/JP7027983B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2019161084A (ja) | 2019-09-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11075190B2 (en) | Semiconductor device and semiconductor device fabrication method | |
JP3910383B2 (ja) | パワーモジュールおよびインバータ | |
JP3847676B2 (ja) | パワー半導体装置 | |
US9171774B2 (en) | Power semiconductor module and method of manufacturing the same | |
US9831160B2 (en) | Semiconductor device | |
US20150028466A1 (en) | Semiconductor device and manufacturing method thereof | |
WO2016084622A1 (ja) | 半導体装置 | |
JP2009278134A (ja) | パワーモジュールおよびインバータ | |
KR102011559B1 (ko) | 반도체 장치 및 그 제조 방법 | |
CN110600457B (zh) | 半导体装置 | |
JP2018157157A (ja) | 半導体装置とその製造方法 | |
JP5409889B2 (ja) | インバータ | |
JP4403166B2 (ja) | パワーモジュールおよび電力変換装置 | |
US10950526B2 (en) | Semiconductor device | |
JP5904041B2 (ja) | 半導体装置 | |
US11201099B2 (en) | Semiconductor device and method of manufacturing the same | |
JP7027983B2 (ja) | リードフレーム | |
JP4449724B2 (ja) | 半導体モジュール | |
JP2011172483A (ja) | インバータ | |
JP5273265B2 (ja) | 電力用半導体装置 | |
US10903138B2 (en) | Semiconductor device and method of manufacturing the same | |
JP2014154770A (ja) | 半導体装置、及び、半導体装置の製造方法 | |
JP4978445B2 (ja) | リードフレームおよび半導体装置の製造方法 | |
JP5202685B2 (ja) | インバータ | |
JP2021027146A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20200401 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210308 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220107 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220118 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220131 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 7027983 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |