JP7021624B2 - Series multiplex power converter and its control method - Google Patents

Description

The present invention relates to a modular multi-level cascade transducer (MMCC) of a single star bridge cell (SSBC) interconnected to a three-phase alternating current system, and in particular, a technique for equalizing thermal obligations due to loss of each unit. Regarding.

Patent Document 1 discloses an example of a power conversion device which is interconnected with a system power supply having a frequency of 50 Hz or 60 Hz and has three bridge cells B connected in series to form one phase of MMCC.

FIG. 8 shows the configuration of a power conversion device in which two bridge cells B are connected in series per phase. As shown in FIG. 8, the bridge cell B (unit 11) is composed of four switching elements U1, V1, X1, Y1 and a capacitor C1.

There is a method of obtaining a gate signal by comparing the voltage command value Vref with a fixed gate threshold value instead of a carrier triangle wave. Comparing the voltage command value and the fixed gate threshold value, one pulse is driven per period of the fundamental wave. Patent Document 1 is characterized by driving with one pulse per period of the fundamental wave. FIG. 9 shows a one-pulse drive waveform in a two-bridge cell B configuration.

Further, in the example of FIG. 9, the relationship between the fixed gate thresholds Vth1a, Vth1b, Vth2a, Vth2b and the gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2 (that is, the on / off state of the switching element) is as follows. It is assigned as.

If Vref> Vth1a, the switching element U1 is turned on, the switching element X1 is turned off, if Vref <Vth1a, the switching element U1 is turned off, and the switching element X1 is turned on.

If Vref> Vth2a, the switching element U2 is turned on, the switching element X2 is turned off, if Vref <Vth2a, the switching element U2 is turned off, and the switching element X2 is turned on.

If Vref> Vth2b, the switching element Y2 is turned on, the switching element V2 is turned off, if Vref <Vth2b, the switching element Y2 is turned off, and the switching element V2 is turned on.

If Vref> Vth1b, the switching element Y1 is turned on, the switching element V1 is turned off, if Vref <Vth1b, the switching element Y1 is turned off, and the switching element V1 is turned on.

When the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b and the voltage command value Vref have the same value, either of the two switching elements may be turned on and either may be turned off.

By this operation, the waveform of FIG. 9 is obtained as the output voltages Vo1 and Vo2 of the first and second units 11 and 12, and the total output voltage Vo. FIG. 9 shows a configuration in which two first and second units 11 and 12 are connected in series, but if a plurality of units are connected in multiplex and a plurality of gate threshold values are prepared, a total output voltage Vo close to a sine wave can be obtained.

In addition, since each switching element switches up to once (one turn-on, one turn-off) for one period of the fundamental wave of the output voltage, the gate signal is compared with the carrier triangle wave with a high frequency and the voltage command value. The number of switchings is smaller than that of the generation method, and the switching loss can be reduced.

In the configuration of FIG. 8, since only the capacitor is connected to the DC portion of the unit, only the reactive power can be handled. Therefore, it is used as a static power compensator. However, if a battery or other power conversion device is connected to the DC portion of the unit, it can also be used as a device for inputting / outputting active power.

Japanese Unexamined Patent Publication No. 2014-100026

However, the gate signal generation method shown in FIG. 9 has a problem that the loss generated in each unit varies greatly. FIG. 10 shows such an example.

In FIG. 10, the amplitude of the voltage command value Vref is smaller than that in FIG. 9, and the absolute value of the voltage command value Vref is smaller than the absolute values of the gate thresholds Vth1a and Vth1b. At this time, the switching element X1 and the switching element Y1 are always ON, and only conduction loss occurs. The switching element U1 and the switching element V1 are always OFF, and the loss is zero. Both the conduction loss and the switching loss occur in the switching elements U2, V2, X2, and Y2.

However, since the switching elements X2 and Y2 are always turned on during the period when the output voltage Vo2 is zero, the time for the current to pass through the switching elements X2 and Y2 is longer than the time of the switching elements U2 and V2, and the switching elements X2 and Y2 The conduction loss generated in the above is also larger than that of the switching elements U2 and V2.

As described above, the loss (total of conduction loss and switching loss) generated in each unit and each switching element varies greatly depending on the output voltage. In this case, if the cooling design is performed according to the unit having the maximum loss or the switching element, the design becomes excessive for the unit having a small loss, and the cost and the device volume increase.

On the other hand, if the cooling design is changed for each unit, it takes time to design, the mass production effect of the unit is not obtained, the cost increases, and the assembly of the device becomes complicated.

Further, in the case of a grid-connected inverter, it may be required to support fold ride-through (FRT) that continues operation even when a momentary low occurs. At the momentary low, switching loss occurs only in a small number of units, and the switching loss generated in most of the remaining units becomes zero. When the system is unstable and the frequency of instantaneous lows is high, heat exhaustion occurs due to the concentration of heat duty only on a specific switching element, which shortens the life of the device.

From the above, it is an issue to make the loss generated in each unit and each switching element uniform in the series multiplex power conversion device.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof is configured by connecting a plurality of bridge cell units in series in each phase and connecting them in series with a three-phase AC system power supply. In a multi-power conversion device, the gate signal of the switching element is compared between the voltage command value and two types of gate thresholds that take a constant value for at least one cycle of the voltage command value for each unit. The gate threshold value in each of the units per phase is set to a different value, the gate threshold value is periodically switched, and the switching cycle of the gate threshold value is the voltage command value. It is characterized by being an integral multiple of the period.

Further, as one aspect thereof, the gate threshold value is switched at the peak on the plus side of the voltage command value.

Further, as one aspect thereof, the first unit and the second unit are provided in each phase as the bridge cell, and the gate thresholds Vth1a and Vth1b of the first unit have the same absolute value and opposite symbols. The gate thresholds Vth2a and Vth2b of the second unit have the same absolute value and opposite signs, and the gate thresholds Vth1a, Vth1b, Vth2a, and Vth2b have the magnitude relationship shown in Table 1 below. It is a feature.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle.

As another embodiment, the bridge cell is provided with a first unit, a second unit, a third unit, and a fourth unit in each phase, and the gate thresholds Vth1a and Vth1b of the first unit are absolute to each other. The values are equal and the signs are opposite, and the gate thresholds Vth2a and Vth2b of the second unit have the same absolute value and opposite signs, and the gate thresholds Vth3a and Vth3b of the third unit are opposite. The absolute values of Vth4a and Vth4b of the gate threshold of the fourth unit are equal to each other and the signs are opposite to each other, and the gate thresholds Vth1a, Vth1b, Vth2a are equal to each other and have opposite signs. , Vth2b, Vth3a, Vth3b, Vth4a, Vth4b are characterized by having a magnitude relationship shown in Table 2 below.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle.

Further, as another embodiment, as the bridge cell, a first unit, a second unit, a third unit, and a fourth unit are provided in each phase, and the gate thresholds Vth1a and Vth1b of the first unit are coded with each other. Are opposite values, Vth2a and Vth2b of the gate threshold value of the second unit are opposite in sign, and Vth3a and Vth3b of the gate threshold value of the third unit are opposite in sign. The gate thresholds Vth4a and Vth4b of the fourth unit have opposite signs to each other, and | Vth1a-Vth1b | and | Vth2a-Vth2b | and | Vth3a-Vth3b | And | Vth4a-Vth4b | are constant values, and the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b are characterized in that they have a magnitude relationship as shown in Table 3 below.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle.

According to the present invention, in a series multiplex power conversion device, it is possible to make the loss generated in each unit and each switching element uniform.

The block diagram which shows the pulse width modulation circuit in Embodiment 1. FIG. A time chart showing an example of a gate threshold value and each waveform in the first embodiment. The block diagram which shows the pulse width modulation circuit in Embodiments 2 and 3. A time chart showing an example of a gate threshold value and each waveform in the second embodiment. A time chart showing the output active power of the unit according to the threshold switching pattern. A time chart showing an example of a gate threshold value and each waveform in the third embodiment. The time chart which shows the output active power of the unit in Embodiment 3. A circuit configuration diagram showing an example of a series multiplex power converter. A time chart showing an example of a gate threshold value and each waveform in the prior art. A time chart showing an example of a gate threshold value and each waveform when the amplitude of the voltage command value is small in the prior art.

Hereinafter, embodiments 1 to 3 of the series multiplex power conversion device according to the present invention will be described in detail with reference to FIGS. 1 to 8.

[Embodiment 1]
In the first embodiment, a method of equalizing the loss generated in each unit and each switching element will be described by taking the series multiplex power conversion device shown in FIG. 8 as an example. First, the configuration of the series multiplex power converter shown in FIG. 8 will be described.

As shown in FIG. 8, the series multiplex power conversion device according to the first embodiment includes two first units 11,21,31 and second units 12,22,32 in each phase. The switching elements U1, V1, X1, Y1 are bridge-connected to the first unit 11,2,31, and the switching elements U2, V2, X2, Y2 are bridge-connected to the second unit 12. A capacitor C1 is connected between the common connection point of the switching elements U1 and V1 and the common connection point of the switching elements X1 and Y1, and the common connection point of the switching elements U2 and V2 and the common connection point of the switching elements X2 and Y2. A capacitor C2 is connected between them.

The common connection point between the switching element U1 of the first unit 11,21,31 and the switching element X1 is connected to each phase of the three-phase AC system power supply 1 via the reactor L. The common connection points of the switching elements V1 and Y1 of the first unit 11,2,31 and the common connection points of the switching elements U2 and X2 of the second units 12, 22 and 32 are connected. The common connection points of the switching element V2 of the second units 12, 22 and 32 and the switching element Y2 are connected to each other.

The output voltage Vo1 of the first unit 11 is set between the common connection point of the switching elements U1 and X1 and the common connection point of the switching elements V1 and Y1, and the common connection point of the switching elements U2 and X2 and the common connection point of the switching elements V2 and Y2 are common. The output voltage Vo2 of the second unit 12 is set between the connection point and the connection point. Further, the total output voltage Vo is defined between the common connection point of the switching elements U1 and X1 of the first unit 11 and the common connection point of the switching elements V2 and Y2 of the second unit 12.

FIG. 1 shows a block diagram of the pulse width modulation circuit of the first embodiment. The input signal p is a signal that gradually increases from 0 to 1 in the switching cycle of the gate threshold value. The input signal p corresponds to the horizontal axis (time axis) of the waveform shown in FIG.

The table 2 inputs the input signal p, refers to the gate threshold value Vth1a corresponding to the input signal p stored in advance, and outputs the input signal p.

The adders 1a, 1b, and 1c add fixed offset values 1/2, 1/4, and 3/4 to the input signal p, respectively. Table 2 inputs the input signals p + 1/2, p + 1 / 4, p + 3/4, refers to the numerical values after the decimal point of the input signals p + 1/2, p + 1 / 4, p + 3/4, and corresponds to the gate thresholds Vth1b, Vth2a. , Vth2b is output. The table 2 itself is the same as the table 2 for calculating the gate threshold value Vth1a, and only the input signal is different from p, p + 1/2, p + 1 / 4, p + 3/4.

Vth1a and Vth1b are gate threshold values for the first unit 11. Vth2a and Vth2b are gate threshold values for the second unit 12.

The voltage command value Vref may be given a sine wave having a predetermined amplitude and frequency, or may be obtained by feedback control that makes the output voltage or output current according to the command value.

The subtractors 3a to 3d calculate the difference between the voltage command value Vref and the gate thresholds Vth1a, Vth1b, Vth2a, and Vth2b, respectively.

The comparators 4a to 4d input the calculation results of the subtractors 3a to 3d and compare with 0. However, the magnitude relationship is different between the comparators 4a and 4c and the comparators 4b and 4d.

The comparator 4a outputs 1 when the calculation result of the subtractor 3a is larger than 0, that is, when Vref> Vth1a, and outputs 0 when Vref ≦ Vth1a. The comparator 4b outputs 1 when the calculation result of the subtractor 3b is smaller than 0, that is, when Vref <Vth1b, and outputs 0 when Vref ≧ Vth1b. The comparator 4c outputs 1 when the calculation result of the subtractor 3c is larger than 0, that is, when Vref> Vth2a, and outputs 0 when Vref ≦ Vth2a. The comparator 4d outputs 1 when the calculation result of the subtractor 3d is smaller than 0, that is, when Vref <Vth2b, and outputs 0 when Vref ≧ Vth2b.

The dead time processors 5a to 5d take the outputs of the comparators 4a to 4d as inputs, add a dead time, and generate gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2. Note that GU1, GX1, GV1, GY1, GU2, GX2, GV2, and GY2 are gate signals of the switching elements U1, X1, V1, Y1, U2, X2, V2, and Y2 in FIG.

The contents of the table in the first embodiment are shown in FIG. In FIG. 2, the horizontal axis is the input signal p, and the vertical axis is the gate threshold value Vth. The gate threshold value Vth1a corresponding to the input signal p is shown by a thick solid line, and the gate threshold value Vth1b corresponding to the input signal p + 1/2 is shown by a broken line. Similarly, the gate threshold value Vth2a corresponding to the input signal p + 1/4 is shown by a thick solid line, and the gate threshold value Vth2b corresponding to the input signal p + 3/4 is shown by a broken line.

The waveform of FIG. 2 shows a range of 0 <p <2. Even when the input signal p is outside the range of FIG. 2, if n is an integer, the waveform of the gate threshold value Vth has a periodicity in which Vth (n + p) = Vth (p) is established.

In FIG. 2, there is a relationship of Vth1a = −Vth1b and Vth2a = −Vth2b.

Table 1 below is a table showing the relationship between the period of the voltage command value Vref and the magnitude of each gate threshold value in FIG.

As can be seen from FIG. 2 and Table 1, each gate threshold has a constant value for at least one cycle of the voltage command value Vref.

In the first embodiment, the gate signal is switched to that of another unit by periodically changing the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b to be compared with the voltage command value Vref for the gate signal generation, and the unit It equalizes the loss that occurs.

FIG. 2 also shows the gate signals GU1, GX1, GV1, GY1, GU2, GX2, GV2, GY2 of each switching element obtained by the first embodiment, and the output voltages Vo1 and Vo2 of the unit. When each gate signal is 1, the corresponding switching element is turned on. When each gate signal is 0, the corresponding switching element is turned off.

The gate thresholds Vth1a, Vth1b, Vth2a, and Vth2b are changed at the timing of the phase at which the voltage command value Vref becomes the maximum (the peak on the plus side). By periodically inverting the magnitude relationship between the gate threshold value Vth1a and the gate threshold value Vth1b, the ON times of all the switching elements are made uniform, and the conduction loss is made equal.

As for the switching loss, since the switching element that performs the switching operation is replaced in the unit of one cycle of the fundamental wave of the output voltage, it is possible to avoid switching of a specific switching element only in a specific phase. If the operation is in a steady state and the voltage command value Vref and the waveform of the output current do not change, the switching losses of all the switching elements U1, V1, X1, Y1, U2, V2, X2, Y2 should be aligned under any conditions. Can be done.

In FIG. 2, since the amplitude of the voltage command value Vref is smaller than the gate threshold value having the maximum absolute value, the waveform of the total output voltage Vo has the same three levels as in FIG. When the amplitude of the voltage command value Vref is larger than the gate threshold value having the maximum absolute value, the waveform of the total output voltage Vo becomes 5 levels as shown in FIG. Even under this condition, the switching losses of all the switching elements can be made uniform.

As shown above, according to the first embodiment, the loss generated in each unit and each switching element can be made uniform. This facilitates the thermal design of the series multiplex power converter and eliminates the situation where the temperature of only a specific unit fluctuates greatly when the load fluctuates, so that thermal fatigue of the switching element or the unit can be prevented.

As a result, the life of the series multiplex power converter can be extended. Further, by making the loss uniform, it is possible to eliminate the excessive design for the unit having a small loss, and to reduce the cost and size of the series multiplex power conversion device. In addition, the output power obligation of each unit can be made uniform.

[Embodiment 2]
In the second embodiment, the bridge cell B is extended to four series multiplex connections in each phase. In the first embodiment, the first and second units are provided in each phase, but in the second embodiment, the first to fourth units are provided in each phase. FIG. 3 shows a block diagram of the pulse width modulation circuit of the second embodiment. The same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The adders 1d, 1e, 1f, and 1g add 1/8, 5/8, 3/8, and 7/8 to the input signal p, respectively. In Table 2, input signals p + 1/8, p + 5/8, p + 3/8, p + 7/8 are input, and the numerical values after the decimal point of the input signals p + 1/8, p + 5/8, p + 3/8, p + 7/8 are referred to. , The corresponding gate thresholds Vth3a, Vth3b, Vth4a, Vth4b are output.

The subtractors 3e to 3h calculate the difference between the voltage command value Vref and the gate thresholds Vth3a, Vth3b, Vth4a, and Vth4b, respectively. The comparators 4e to 4h input the calculation results of the subtractors 3e to 3h and compare with 0. However, the magnitude relationship is different between the comparators 4e and 4g and the comparators 4f and 4h.

The comparator 4e outputs 1 when the calculation result of the subtractor 3e is larger than 0, that is, when Vref> Vth3a, and outputs 0 when Vref ≦ Vth3a. The comparator 4f outputs 1 when the calculation result of the subtractor 3f is smaller than 0, that is, when Vref <Vth3b, and outputs 0 when Vref ≧ Vth3b. The comparator 4g outputs 1 when the calculation result of the subtractor 3g is larger than 0, that is, when Vref> Vth4a, and outputs 0 when Vref ≦ Vth4a. The comparator 4h outputs 1 when the calculation result of the subtractor 3h is smaller than 0, that is, when Vref <Vth4b, and outputs 0 when Vref ≧ Vth4b.

The dead time processors 5e to 5h take the outputs of the comparators 4e to 4h as inputs, add a dead time, and generate gate signals GU3, GX3, GV3, GY3, GU4, GX4, GV4, GY4. The GU3, GX3, GV3, GY3, GU4, GX4, GV4, and GY4 are gate signals of the switching elements U3, X3, V3, Y3 of the third unit, and U4, X4, V4, Y4 of the fourth unit.

The contents of the table in the second embodiment are shown in FIG. Since the number of units increased to 4 in each phase, the gate threshold value Vth to be output also takes 8 values. These eight values are periodically switched according to the input signal p, and are output as gate thresholds Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b.

In FIG. 4, the gate thresholds Vth1a, Vth2a, Vth3a, and Vth4a are shown by solid lines, and the gate thresholds Vth1b, Vth2b, Vth3b, and Vth4b are shown by broken lines. Further, there is a relationship of Vth1a = −Vth1b, Vth2a = −Vth2b, Vth3a = −Vth3b, Vth4a = −Vth4b.

Table 2 below is a table showing the relationship between the period of the voltage command value Vref and the magnitude of each gate threshold value in FIG.

The second embodiment also has an effect of reducing the capacitor capacity of the unit at the time of input / output of active power. This effect will be described with reference to FIG.

The second waveform from the top of FIG. 5 shows the same waveform as the output voltage Vo1 of FIG.

On the other hand, as another gate threshold value Vth (p), as shown in the third waveform from the top of FIG. 5, Vth (p) is monotonically decreased when 0 <p <4/8, and Vth (Vth) when 4/8 <p <1. A method of monotonically increasing p) is also conceivable. The output voltage of the first unit 11 generated by this gate threshold value is set to Vo1'.

Considering the case where the unit outputs active power, the output current Io is set to the fifth waveform from the top of FIG. 5 (a sine wave having the same phase as the voltage command value Vref). The output power of the unit can be obtained by Po1 = Vo1 × Io1, Po1 ′ = Vo1 ′ × Io1. FIG. 5 shows the waveforms of the output power Po1 and the output power Po1'.

Looking at the output power Po1', the width of the pulse A is the smallest (zero), and the width of the pulse B is the largest. The change from pulse A to pulse B takes two cycles of fundamental wave, the change from pulse B to pulse A takes two cycles of fundamental wave, and the pulsation cycle of output power is four cycles of fundamental wave.

On the other hand, the output power Po1 sandwiches the pulse C and the pulse D in the middle of the change from the pulse A to the pulse B. The change from pulse A to pulse C increases the pulse width, the change from pulse C to pulse D decreases the pulse width, the change from pulse D to pulse B increases the pulse width, and the change from pulse B to pulse A increases. The pulse width decreases with the change to. The changes of pulse A → pulse C, pulse C → pulse D, and pulse D → pulse B each take one fundamental wave cycle, and the pulsating cycle of the output power is two fundamental wave cycles.

Since the impedance of the capacitor (= 1 / 2πfC, f: frequency, C: capacitor capacity) is inversely proportional to the frequency, the smaller the period of the power pulsation, the smaller the impedance, and the smaller the capacitor voltage pulsation can be. Therefore, if the allowable capacitor voltage pulsation is the same, the capacitor capacity can be made smaller in the case of the output power Po1 (Vo1) than in the case of the output power Po1'(Vo1').

That is, the pattern of the gate threshold table of the second embodiment that outputs the output power Po1 (Vo1) has an effect that the capacitor capacity can be reduced as compared with the pattern that outputs the output power Po1'(Vo1').

As shown above, according to the second embodiment, the same effect as that of the first embodiment can be obtained. Further, in the second embodiment, since the cycle of the output power pulsation can be shortened, the capacity of the cell capacitor can be reduced, and the size and cost of the series multiplex power conversion device can be reduced.

In addition, since each unit does not output a zero-phase voltage in the second embodiment as compared with the third embodiment described later, the design of insulation (withstand voltage) becomes easier.

[Embodiment 3]
The third embodiment is an example in which the main circuit configuration and the pulse width modulation circuit are the same as those in the second embodiment, but the table 2 of the gate threshold is used as a different pattern. The pattern of the table 2 in the third embodiment is shown in FIG.

The third embodiment is characterized in that | Vth (p) -Vth (p + 1/2) | = 1 is always established. That is, | Vth1a-Vth1b |, | Vth2a-Vth2b |, | Vth3a-Vth3b |, and | Vth4a-Vth4b | are set to constant values in all the input signals p.

Table 3 below is a table showing the relationship between the period of the voltage command value Vref and the magnitude of each gate threshold value in FIG.

FIG. 7 shows the waveform of the output active power (output power) Po1 (= Vo × Io) of the unit in the third embodiment. Similar to FIG. 5, the output current Io is a sine wave having the same phase as the voltage command value Vref.

In the waveform of the output active power (output power) Po1 in the third embodiment, a pulse having a large width and a pulse having a small width (or a pulse having a width of zero) are alternately arranged. By this operation, since the pulsation of the output power of the unit is centered on the one of the fundamental wave one cycle component, if the allowable capacitor voltage pulsation is the same magnitude, the capacitor capacity can be made smaller than that of the second embodiment.

On the other hand, since a zero-phase voltage is applied to the unit, it is required to design insulation (withstand voltage) in consideration of the zero-phase voltage.

As shown above, according to the third embodiment, the same effect as that of the first embodiment can be obtained. Further, in the third embodiment, the cycle of the output power pulsation can be further shortened as compared with the second embodiment, so that the device can be configured with a smaller capacitor capacity.

Although the above description has been made in detail only for the specific examples described in the present invention, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. It goes without saying that such modifications and modifications fall within the scope of the claims.

In the first to third embodiments, the gate threshold switching cycle (that is, the period during which the gate threshold remains constant) coincides with the voltage command value Vref cycle. The present invention can be implemented even if the switching cycle of the gate threshold value is an integral multiple of the cycle of the voltage command value Vref.

In each embodiment, a control method for a representative one-phase bridge cell unit in a series multiplex power converter has been described. A gate signal is generated for the remaining two-phase units in the same manner. The only difference between the control methods in each phase is that the phase of the voltage command value Vref is shifted by 120 °.

1a to 1g ... Adder 2 ... Table 3a to 3h ... Subtractor 4a to 4h ... Comparator 5a to 5h ... Dead time processor

Claims (6)

It is a series multiplex power converter that is configured by connecting multiple bridge cell units in series in each phase and is interconnected with a three-phase AC system power supply.
For each unit, a pulse width modulation circuit that generates a gate signal of a switching element by comparing a voltage command value with two types of gate threshold values that take a constant value for at least one cycle of the voltage command value. Prepare,
The gate thresholds in each of the units per phase all take different values and
The gate threshold is switched periodically,
A series multiplex power conversion device characterized in that the switching cycle of the gate threshold value is an integral multiple of the cycle of the voltage command value. The series multiplex power conversion device according to claim 1, wherein the gate threshold value is switched at the peak on the positive side of the voltage command value. Each phase is provided with a first unit and a second unit as the bridge cell.
The gate thresholds Vth1a and Vth1b of the first unit have absolute values equal to each other and signs opposite to each other.
The gate thresholds Vth2a and Vth2b of the second unit have the same absolute value and opposite signs.
The series multiplex power conversion device according to claim 2, wherein the gate threshold values Vth1a, Vth1b, Vth2a, and Vth2b have a magnitude relationship shown in Table 1 below.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle. As the bridge cell, a first unit, a second unit, a third unit, and a fourth unit are provided in each phase.
The gate thresholds Vth1a and Vth1b of the first unit have the same absolute value and opposite signs.
The gate thresholds Vth2a and Vth2b of the second unit have the same absolute value and opposite signs.
The gate thresholds Vth3a and Vth3b of the third unit have the same absolute value and opposite signs.
The gate thresholds Vth4a and Vth4b of the fourth unit have the same absolute value and opposite signs.
The series multiplex power conversion device according to claim 2, wherein the gate thresholds Vth1a, Vth1b, Vth2a, Vth2b, Vth3a, Vth3b, Vth4a, and Vth4b have a magnitude relationship shown in Table 2 below.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle. As the bridge cell, a first unit, a second unit, a third unit, and a fourth unit are provided in each phase.
The gate thresholds Vth1a and Vth1b of the first unit have opposite signs to each other.
The gate thresholds Vth2a and Vth2b of the second unit have opposite signs to each other.
The gate thresholds Vth3a and Vth3b of the third unit have opposite signs to each other.
The gate thresholds Vth4a and Vth4b of the fourth unit have opposite signs to each other.
| Vth1a-Vth1b | and | Vth2a-Vth2b | and | Vth3a-Vth3b | The series multiplex power conversion device according to claim 2, wherein Vth4a and Vth4b have a magnitude relationship shown in Table 3 below.

p: A value that gradually changes from 0 to 1 in the gate threshold switching cycle. It is a control method for a series multiplex power converter that is configured by connecting multiple bridge cell units in series in each phase and is interconnected with a three-phase AC system power supply.
For each of the units, the voltage command value is compared with two types of gate thresholds that take a constant value for at least one cycle of the voltage command value to generate a gate signal for the switching element.
The gate thresholds in each of the units per phase all take different values and
The gate threshold is switched periodically,
A control method for a series multiplex power conversion device, wherein the switching cycle of the gate threshold value is an integral multiple of the cycle of the voltage command value.

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