JP2000324845A - Power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an output voltage waveform in which harmonies are not increased even during operation under bypass state while simplifying a PWM circuit provided for each element and reducing the size thereof. SOLUTION: The power converter producing a variable frequency, variable voltage polyphase AC power by connecting at least two outputs of an inverter 11 comprising a switching element comprises a pulse width modulation circuit 18-2 provided for each phase in order to switch the switching elements of the plurality of inverters, and a circuit 18-3 for distributing a gate pulse from the pulse width modulation circuit 18-2 to the inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter for connecting two or more outputs of an inverter having a switching element to obtain a variable frequency, variable voltage polyphase AC power.

[0002]

2. Description of the Related Art As a conventional control device for an AC motor such as an induction motor controlled by a variable speed, a PWM control type voltage multiplex inverter device shown in FIG. 11 is known. FIG.
In the voltage multiplex inverter device shown in FIG. 1, a single-phase inverter in which two single-phase inverters 11 are connected in series has one
A motor 12 comprising an inverter in a star-connected configuration
Drive.

FIG. 12 shows a single-phase inverter. As shown in FIG. 12, the single-phase inverter includes a DC power supply 15 and a single-phase bridge inverter 16,
An AC having a desired voltage and frequency is supplied by the WM control.

The switching of the individual elements of each single-phase inverter 11 shown in FIG. 11 is performed, for example, in U1 shown in FIG. 11 by using a carrier wave a and the carrier wave a by the PWM circuits 14-1 and 14-2. 5 is compared with the voltage reference Vuref, and is controlled by the gate pulses e and f obtained as a result.

Further, as a method of obtaining a switching signal of each single-phase inverter in a multiplex inverter, see pages 125 and 126 of "Semiconductor Power Conversion Circuit" (published by the Institute of Electrical Engineers of Japan / Ohm Corporation) and US Pat. No. 4,674. 024
As described in U.S. Pat. No. 5,625,545, the phase of the carrier signal is shifted using a phase shift circuit 14-7 with respect to another single-phase inverter, and each element of each single-phase inverter is shifted. In general, a method of using a control circuit 14 that provides a PWM circuit for each time and outputs a gate pulse is used.

FIG. 13 shows an output voltage waveform. According to FIG. 13, the output voltages U1 and U2 of the two single-phase inverters are alternately switched to obtain a waveform that is closer to a sine wave overall than the output voltage waveform of one single-phase inverter. Have been. In FIG. 11, an example has been described in which there are two single-phase inverters corresponding to one. However, it is clear that improved results can be obtained with three or more single-phase inverters.

[0007]

However, in the conventional method of controlling a multiplex inverter configured as described above,
It is necessary to add a PWM circuit and a phase shift circuit for each switching element, and when multiplexing, there is an economical problem because the device becomes large.

In general, in a multiplex operation using a single-phase inverter, when one single-phase inverter fails, the output of the single-phase inverter is short-circuited, and power is supplied to the load only by another single-phase inverter in a bypass state. Can be supplied. However, if the phase shift circuit is left as it is in the control circuit and only one single-phase inverter is in the bypass state, the output voltage of the bypassed single-phase inverter is not reflected in the output voltage, so that the harmonics of the output voltage increase. I do.

In view of the above problems, it is an object of the present invention to simplify and downsize a PWM circuit applied to each element of an apparatus and to obtain an output voltage waveform which does not increase harmonics even when operated in a bypass state. And

[0010]

In order to achieve the above object, the invention according to claim 1 is to connect two or more outputs of an inverter comprising a switching element and to provide a multi-phase AC power having a variable frequency and a variable voltage. In the obtained power converter, the switching of the switching elements of the plurality of inverters is determined for each phase by one pulse width modulation circuit and to which inverter the gate pulse output from the pulse width modulation circuit is distributed. Control means for controlling by the distribution circuit.

The invention according to claim 2 is characterized in that the distribution circuit has means for storing the order of occurrence of switching of the switching elements of each inverter and the current switching state, and sequentially switching the switching elements. Features.

Further, the invention according to claim 3 is provided for each phase in a power converter for obtaining two or more outputs of a single-phase inverter in series to obtain multi-phase AC power of variable frequency and variable voltage. A pulse width modulation circuit, a voltage reference conversion circuit that converts a voltage reference so that a single phase and amplitude carrier and pulse width modulation can be performed, and a switching generation order of switching elements in each single-phase inverter and a current switching state. Of the elements that have been switched in the opposite direction to the change in the output voltage due to the change in the output voltage,
A distribution circuit that outputs a gate pulse output from the pulse width modulation circuit to an element that has not been switched for the longest period.

According to a fourth aspect of the present invention, since one of the plurality of single-phase inverters is used in a bypass state, a gate pulse is distributed to other single-phase inverters except the single-phase inverter in the bypass state. A circuit is provided.

According to a fifth aspect of the present invention, there is provided a power converter for connecting a plurality of three-phase inverters to obtain multi-phase AC power of variable frequency and variable voltage, wherein one pulse width modulation circuit is provided for each phase. A voltage reference conversion circuit for converting a voltage reference so as to be able to perform pulse width modulation with a carrier having a single phase and amplitude; A gate pulse output from the pulse width modulation circuit is output to an element that has not been switched for the longest time among the elements that have been switching in the direction opposite to the change in the output voltage due to the change in the output voltage. And a distribution circuit.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of the present invention. Note that, in the components of the embodiment shown in FIG. 1, the same components as those in FIG. 10 is different from FIG. 10 in that a voltage reference conversion circuit 18- converts a voltage reference so that the gate pulse control circuit 14 of each inverter can be controlled by pulse width modulation with a single carrier and a single comparison circuit in FIG. 1, a PWM circuit 18-2 including a single carrier and a single comparison circuit, and a control circuit 18 including a distribution circuit 18-3. Hereinafter, the description will be made on behalf of the U phase, but V, W
The same applies to phases.

In the voltage reference conversion circuit 18-1, the voltage reference V
uref, based on the voltage level that the phase should output,
The voltage reference is converted and output so that PWM control can be performed with a single carrier and a single comparison circuit.

FIG. 2 and FIG. 3 show the concept of the correspondence between the voltage levels of the outputs of the multiplex inverter in which the voltage levels of the phase outputs are five levels from -2 to +2 and the conversion of the voltage reference. Here, the voltage reference is normalized from -1 to +1.

FIG. 2 shows carriers C1 to C4 with respect to a voltage reference before conversion. As shown in FIG. 3, in the present embodiment, the voltage reference is converted such that the amplitude of the carrier is -1 to +1 in consideration of the relative relationship between the voltage reference and the carrier. For example, as shown in FIG.
/ 2, a phase voltage having a pulse width determined from the relationship between the carrier and the voltage reference can be obtained. In order to output a similar pulse width using the single carrier shown in FIG. 3, the following conversion is performed.

Eu = (Vuref-／) × 4 (1) Eu: U-phase voltage reference after conversion The other regions are similarly converted as follows.

When the voltage reference is in the range of +1/2 to +1, Eu = (Vuref − ／) × 4 (2) When the voltage reference is in the range of −1/2 to 0, Eu = (Vuref + ／) × 4 (3) When the voltage reference is in the range of −1 to − ／, Eu = (Vuref + ３) × 4 (4) Voltage after the above conversion The reference is PWM in the PWM circuit 18-2.
The gate pulse is output under M control.

In the distribution circuit 18-3, the element m to be switched next is determined, a gate pulse p is output to the determined element, and a gate is applied to the other elements so that the previous switching state is continued. Output pulse.

Next, a distribution circuit 18- in a multiple inverter in which at least two or more single-phase inverters are connected in series.
Operation 3 will be described in detail. FIG. 4 shows a detailed diagram of the distribution circuit 18-3 of the power converter.

First, the voltage level 1 of the phase voltage to be output from the voltage reference in the output voltage level determining circuit 20 is shown in FIG.
As shown in (1), it is determined according to the magnitude of the voltage reference. Next, the element m to be switched next is determined by the switching element selection circuit 21 from the voltage level l. The switching element selection circuit 21 includes a single-phase inverter selection circuit 22
And an element selection circuit 23 in a single-phase inverter.

As shown in FIG. 5, the single-phase inverter selection circuit 22 has a voltage level -1 that can be output from the single-phase inverter.
From +1 to +1 respectively,
a, 24b and 24c are prepared. Each single-phase inverter belongs to one queue from each output state. At this time, the queues 24a, 24b, 24c also have information as to the order in which the voltage levels have changed.

The output voltage level of a phase is the sum of the outputs of these single-phase inverters. For example, in FIG. 5, U1 and U2 belong to the queue 24b of level 0, and U1
Indicates that the level is 0. The output voltage level of the phase is 0.

The single-phase inverter selection circuit 22 receives the voltage level 1 of the phase voltage to be output from the output voltage level determination circuit 20, compares it with the current output voltage level before switching, which is known from the state of the queue, and outputs the output voltage. If the level is high, the output level of the single-phase inverter at the head of the minimum level of the queue is increased by one, and the output voltage level of the phase is increased. In this way, the single-phase inverter q to be switched is determined.

Next, the element selection circuit 23 in the single-phase inverter
The operation of FIG. In the single-phase inverter element selection circuit 23, an element to be switched is determined for the single-phase inverter q that changes the voltage level determined by the single-phase inverter selection circuit 22.

FIG. 6 shows the switching state of each element and its transition with respect to the output voltage level of the single-phase inverter. The numbers indicate the output voltage level of the single-phase inverter, + and-in 0 indicate the states of the two arms in the single-phase inverter, + indicates that the upper element is on, and-indicates that the lower element is on. To indicate that The switching state is 26a, 26
b, 26c, and 26d. The switching state where the output voltage level of the single-phase inverter is 0 is 26a,
26c.

In this embodiment, in order to disperse the switching of the elements, when the level was previously 0, which switching state was stored as a flag, the element to be switched next is determined. For example, F
When the output voltage level of the inverter changes from +1 to 0 when LG = 0, the switching element is selected so that the next state becomes 26b. Conversely, if FLG = 1, 26
The switching element is selected so as to be c. The same applies when the output voltage level changes from -1 to 0. Thus, the switching element m is determined.

For the elements not selected,
The previous switching signals e ', f', g ', and h' are continuously output from the states of the queues 24a, 24b, and 24c. The gate pulse allocating circuit 25 outputs the gate pulse p output from the PWM circuit 18-2 to the element m selected by the switching element selection circuit 21, and outputs the switching element selection circuit 21 to the other elements. Switching signals e ', f', g ', h output from
Is output.

As described above, in the first embodiment, in a multiplex inverter in which two single-phase inverters are connected in series for each phase, one PWM circuit 18-2 and a circuit 18-3 for distributing gate pulses are provided. Control can be used, and the circuit configuration can be made compact. Also, cues 24a, 24b,
26c, the switching method of each single-phase inverter can be dispersed by a control method of switching the single-phase inverter that has not changed its output state for the longest time among the single-phase inverters that can realize the change of the output voltage level. Switching loss can be balanced.

Although two single-phase inverters are connected to one corresponding to the case described above, if three or more multiplex connections are performed, the number of single-phase inverters stored in the queues 24a, 24b, and 25c is increased. Thus, the same processing can be performed.

Therefore, the control of each element of the multiplex inverter in which two or more single-phase inverters are connected can be performed by one PWM circuit and a gate pulse distribution circuit, so that the number of parts is reduced and the switching loss of each element is reduced. Can be balanced.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. The main circuit configuration is the same as in FIG. In the components of the embodiment shown in FIG. 7, the same components as those in FIG.
The description is omitted by giving the same number.

The difference from FIG. 4 is that an initialization circuit 27 for queues 24a, 24b, 24c is added to the single-phase inverter selection circuit 22. Since the switching of the single-phase inverter is performed by shifting the level of the queue, if the information is not included in the queue, the switching signal is not transmitted and the bypass state is enabled. In a similar manner, a plurality of single-phase inverters can be simultaneously operated in bypass. Therefore, one or more single-phase inverters can be operated in bypass, and hardware changes such as PWM circuit changes are not required.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. In addition, in the components of the embodiment shown in FIGS. 8 and 9, the same components as those in FIGS. 1 and 4 are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 8, the power conversion device is a double inverter in which two sets of three-phase inverters are connected by reactors 28a and 28b. The difference from FIG. 1 is that the main circuit configuration is changed from a series connection of single-phase inverters to a parallel connection of three-phase inverters, and that a gate pulse signal line in the control circuit 18 is different.

The difference from FIG. 4 is that the configuration of the switching element selection circuit 21 is different. In the switching element selection circuit 21 shown in FIG. 9, for a three-phase inverter, each switching is controlled by a three-phase inverter switching element selection circuit 29.

As in the case of the single-phase inverter, a queue as shown in FIG. 10 is considered for the three-phase inverter in order to store the past switching state. In the three-phase inverter, the arm of each phase has only two states, positive and negative, and queues 30a and 30b are prepared in each state. The output state of each phase of the three-phase inverter is stored in one of these queues. The output voltage level of the phase is the average value of these additions.

The switching element selection circuit 21 receives the output voltage level 1 of the phase to be output from the output voltage level determination circuit 20, and compares the output voltage level with the current output voltage level determined from the state of the queue. I do.
If the voltage level to be output is high, the negative side queue 3
The switching of the first inverter at 0b is made positive, and the output voltage level of the phase is raised. Conversely, if the voltage level to be output is low, the switching of the first inverter in the positive queue 30a is made negative, and the output voltage level of the phase is lowered. In this way, the element m to be switched is determined.

As described above, in the third embodiment, in a multiplex inverter in which two three-phase inverters are connected in parallel, control can be performed using one PWM circuit 18-2 and a circuit 18-3 for distributing gate pulses. The circuit configuration can be made compact. Further, among the three-phase inverters capable of realizing a change in the output voltage level by using the queues 30a and 30b, the switching of each three-phase inverter can be distributed by a control method of switching the three-phase inverter that has been switched most recently. In the above, the case where the three-phase inverters are duplicated has been described. However, in the case where the multiplexing of the three-phase inverters or more is performed, the same processing can be performed by increasing the number of the three-phase inverters stored in the queues 30a and 30b.

Accordingly, each element of the multiplex inverter which connects two or more three-phase inverters can be controlled by one PWM circuit and a gate pulse distribution circuit, and the number of parts is reduced, and the switching loss of each element is reduced. Can be balanced.

[0044]

As described above, according to the present invention, the PWM circuit applied to each element of the device is simplified and downsized, and an output voltage waveform that does not increase harmonics even when operated in a bypass state is obtained. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an output voltage level and a voltage reference with respect to a voltage reference before conversion according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing an output voltage level and a voltage reference with respect to a converted voltage reference according to the first embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing a single-phase inverter gate pulse control circuit according to the first embodiment of the present invention.

FIG. 5 is a conceptual diagram showing a queue for determining a single-phase inverter to be switched in the first embodiment of the present invention.

FIG. 6 is a conceptual diagram showing a state transition for determining a switching element according to the first embodiment of the present invention.

FIG. 7 is a schematic configuration diagram showing a second embodiment of the present invention.

FIG. 8 is a schematic configuration diagram showing a third embodiment of the present invention.

FIG. 9 is a schematic configuration diagram showing a three-phase inverter gate pulse control circuit according to a third embodiment of the present invention.

FIG. 10 is a conceptual diagram showing a queue for determining a three-phase inverter to be switched according to a third embodiment of the present invention.

FIG. 11 is a schematic configuration diagram showing a conventional multiple inverter device of a multiple PWM control method.

12 is a schematic configuration diagram showing the single-phase inverter shown in FIG.

13 is a waveform chart showing an output waveform of the multiplexed inverter shown in FIG.

[Explanation of symbols]

11: Single-phase inverter, 12: AC motor, 14, 18
... Control circuit, 15 ... DC power supply, 16 ... Single-phase reverse bridge reverse converter, 18-1 ... Voltage reference conversion circuit, 18-2 ... PW
M circuit, 18-3 distribution circuit, 20 output voltage level determination circuit, 21 switching element selection circuit, 22 single-phase inverter selection circuit, 23 single-phase inverter element selection circuit, 24a, 24b, 24c single First-in first-out queues for phase inverters, 25: gate pulse allocation circuit, 26a, 26b, 26c, 26d: single-phase inverter switching state, 27: queue initialization circuit, 28a,
28b: coupling reactor, 29: three-phase inverter switching element selection circuit, 30a, 30: first-in first-out queue for three-phase inverter.

Claims (5)

[Claims] 1. A power converter for connecting two or more outputs of an inverter having a switching element to obtain variable-frequency, variable-voltage polyphase AC power, wherein switching of the switching elements of the plurality of inverters is performed for each phase. A power conversion device, comprising: a pulse width modulation circuit; and a control unit that controls the distribution of the gate pulse output from the pulse width modulation circuit to an inverter. . 2. The distribution circuit according to claim 1, wherein the distribution circuit includes means for storing a switching order of switching elements of each inverter and a current switching state, and sequentially switching the switching elements. Power converter. 3. A pulse width modulation circuit provided for each phase in a power converter for obtaining two or more outputs of a single-phase inverter having a switching element in series to obtain multi-phase AC power of variable frequency and variable voltage. And a voltage reference conversion circuit that converts a voltage reference so as to be able to perform pulse width modulation with a carrier having a single phase and amplitude, and stores a switching generation order and a current switching state of the switching elements in each single-phase inverter, Of the elements that have been switched in the opposite direction to the change in the output voltage due to the change in the output voltage,
A power distribution device that outputs a gate pulse output from the pulse width modulation circuit to an element that has not been switched for the longest period. 4. A circuit for distributing a gate pulse to other single-phase inverters other than the single-phase inverter in the bypass state in order to use one of the plurality of single-phase inverters in a bypass state. The power converter according to claim 3, characterized in that: 5. A power converter for connecting a plurality of three-phase inverters to obtain variable-frequency, variable-voltage polyphase AC power, wherein one pulse width modulation circuit is provided for each phase, and a single phase and amplitude A voltage reference conversion circuit for converting a voltage reference so as to be able to perform pulse width modulation with a carrier; storing a switching generation order and a current switching state of switching elements of the three-phase inverters; And a distribution circuit that outputs a gate pulse output from the pulse width modulation circuit to an element that has not been switched for the longest time among the elements that have been switching in the direction opposite to the voltage change. Characteristic power converter.