JP7007092B2 - メモリ装置のデータアドレッシング方法及びメモリ装置並びにメモリモジュール - Google Patents

メモリ装置のデータアドレッシング方法及びメモリ装置並びにメモリモジュール Download PDF

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JP7007092B2
JP7007092B2 JP2017028878A JP2017028878A JP7007092B2 JP 7007092 B2 JP7007092 B2 JP 7007092B2 JP 2017028878 A JP2017028878 A JP 2017028878A JP 2017028878 A JP2017028878 A JP 2017028878A JP 7007092 B2 JP7007092 B2 JP 7007092B2
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address
subset
column
address bits
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JP2017157209A (ja
JP2017157209A5 (enExample
Inventor
牧 天 張
迪 民 牛
宏 忠 ツェン
サン ヨン 林
寅 東 金
ジャン ソク チェ，
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
JP2017028878A 2016-03-03 2017-02-20 メモリ装置のデータアドレッシング方法及びメモリ装置並びにメモリモジュール Active JP7007092B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201662303353P 2016-03-03 2016-03-03
US62/303,353 2016-03-03
US201662347569P 2016-06-08 2016-06-08
US62/347,569 2016-06-08
US15/227,911 US9837135B2 (en) 2016-03-03 2016-08-03 Methods for addressing high capacity SDRAM-like memory without increasing pin cost
US15/227,911 2016-08-03

Publications (3)

Publication Number Publication Date
JP2017157209A JP2017157209A (ja) 2017-09-07
JP2017157209A5 JP2017157209A5 (enExample) 2020-04-02
JP7007092B2 true JP7007092B2 (ja) 2022-01-24

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JP2017028878A Active JP7007092B2 (ja) 2016-03-03 2017-02-20 メモリ装置のデータアドレッシング方法及びメモリ装置並びにメモリモジュール

Country Status (5)

Country Link
US (2) US9837135B2 (enExample)
JP (1) JP7007092B2 (enExample)
KR (1) KR102753865B1 (enExample)
CN (1) CN107154270B (enExample)
TW (1) TWI688857B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714487B (zh) * 2017-12-28 2020-12-21 慧榮科技股份有限公司 記憶卡控制器以及使用於記憶卡控制器的方法
US10866746B2 (en) 2017-12-28 2020-12-15 Silicon Motion Inc. Memory addressing methods and associated controller, memory device and host
WO2020219293A1 (en) 2019-04-26 2020-10-29 Rambus Inc. Memory controller partitioning for hybrid memory system
US11164613B2 (en) 2019-12-02 2021-11-02 Micron Technology, Inc. Processing multi-cycle commands in memory devices, and related methods, devices, and systems

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001014842A (ja) 1999-06-28 2001-01-19 Toshiba Corp 半導体記憶装置及びメモリ混載ロジックｌｓｉ
JP2001101865A (ja) 2000-09-01 2001-04-13 Mitsubishi Electric Corp 半導体メモリ装置

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US6108745A (en) * 1997-10-31 2000-08-22 Hewlett-Packard Company Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes
US6493814B2 (en) * 2001-03-08 2002-12-10 International Business Machines Corporation Reducing resource collisions associated with memory units in a multi-level hierarchy memory system
US7093059B2 (en) * 2002-12-31 2006-08-15 Intel Corporation Read-write switching method for a memory controller
KR100660892B1 (ko) 2005-11-21 2006-12-26 삼성전자주식회사 더블 펌프드 어드레스 스킴의 메모리 장치에서 고속 동작을위해 확장된 유효 어드레스 윈도우로 유효 커맨드를샘플링하는 회로 및 방법
US7936639B2 (en) * 2007-09-27 2011-05-03 Micron Technology, Inc. System and method for processing signals in high speed DRAM
US8130576B2 (en) 2008-06-30 2012-03-06 Intel Corporation Memory throughput increase via fine granularity of precharge management
EP3467832B1 (en) * 2010-12-17 2020-05-20 Everspin Technologies, Inc. Memory controller and method for interleaving dram and mram accesses
US9251874B2 (en) 2010-12-21 2016-02-02 Intel Corporation Memory interface signal reduction
US10902890B2 (en) 2012-06-22 2021-01-26 Intel Corporation Method, apparatus and system for a per-DRAM addressability mode
US9104646B2 (en) 2012-12-12 2015-08-11 Rambus Inc. Memory disturbance recovery mechanism
CN105027213A (zh) * 2013-03-12 2015-11-04 惠普发展公司，有限责任合伙企业 可编程地址映射和存储器访问操作
KR20150040481A (ko) 2013-10-07 2015-04-15 에스케이하이닉스 주식회사 메모리 장치, 메모리 장치 및 메모리 시스템의 동작방법
EP3069344B1 (en) 2013-11-11 2019-01-09 Rambus Inc. High capacity memory system using standard controller component

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2001014842A (ja) 1999-06-28 2001-01-19 Toshiba Corp 半導体記憶装置及びメモリ混載ロジックｌｓｉ
JP2001101865A (ja) 2000-09-01 2001-04-13 Mitsubishi Electric Corp 半導体メモリ装置

Also Published As

Publication number Publication date
US9837135B2 (en) 2017-12-05
CN107154270A (zh) 2017-09-12
CN107154270B (zh) 2019-07-30
TWI688857B (zh) 2020-03-21
US10504572B2 (en) 2019-12-10
KR102753865B1 (ko) 2025-01-15
JP2017157209A (ja) 2017-09-07
KR20170104116A (ko) 2017-09-14
TW201732601A (zh) 2017-09-16
US20170256311A1 (en) 2017-09-07
US20180102152A1 (en) 2018-04-12

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