JP6992700B2 - CCD image sensor - Google Patents

Description

The present invention relates to a CCD image sensor.

A conventional CCD (Charge Coupled Device) image sensor has a transfer channel region that generates a signal charge in response to light incident, and a plurality of transfer electrodes that are provided on the transfer channel region via an insulating film to transfer the signal charge. , The pixel separation area that electrically separates the transfer channel areas, the overflow gate area adjacent to the transfer channel area on the opposite side to the side where the pixel separation area and the transfer channel area are adjacent, and the overflow gate area adjacent to the overflow gate area. It has an overflow / drain area.

In the conventional CCD image sensor configured as described above, a signal charge is generated in the transfer channel region by the incident of light, and by applying a voltage to a plurality of transfer electrodes, the signal charge in the transfer channel region is output as an output unit. Transferred to.

The overflow gate region and the overflow drain region are provided to discharge the excess signal charge generated when the excess light is incident on the CCD image sensor. The overflow gate region has a lower P-type impurity concentration than the pixel separation region, and functions as an overflow gate together with a transfer electrode provided on the overflow gate region. By applying a voltage to the transfer electrode, the excess signal charge in the transfer channel region is discharged to the overflow drain region via the overflow gate region. By controlling the voltage applied to the transfer electrode, the amount of excess signal charge discharged to the overflow drain region is controlled (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2010-258155

However, in the conventional CCD image sensor, the transfer electrode controls both the operation control of the transfer of the signal charge in the transfer channel region and the control of the emission amount of the excess signal charge to the overflow drain region, resulting in an excess signal charge. The control of the emission amount of the signal charge depends on the transfer operation of the signal charge, which is the original function of the transfer electrode. Therefore, there is a problem that it becomes difficult to control the amount of excessive signal charge emitted by the transfer electrode.

Therefore, the present invention has been made to solve such a problem of the prior art, and an object of the present invention is to facilitate control of an excessive amount of signal charge emission and to provide a highly sensitive CCD image sensor. And.

In order to achieve the above object, the CCD image sensor of the present invention extends in the first direction and is provided on a transfer channel region and a transfer channel region that generate a signal charge in response to light incident. Provided at one end of a pixel region comprising a transfer electrode extending in a second direction orthogonal to the first direction and transferring a signal charge in the first direction, and a pixel region in the direction in which the signal charge is transferred. A charge storage region that stores the signal charge transferred from the pixel region and a first overflow drain region that discharges the excess signal charge stored in the charge storage region among the signal charges stored in the charge storage region. An overflow gate electrode provided between the charge storage region and the first overflow / drain region and to which a control voltage for controlling the amount of excess signal charge is applied, and an overflow gate electrode extending in the first direction, the first A first overflow gate area adjacent to the transfer channel area in the second direction, an extension in the first direction, adjacent to the first overflow gate area in the second direction, and via the first overflow gate area. The saturation level of the charge capacity of the charge storage region controlled by the overflow gate electrode is controlled by the first overflow gate region, which comprises a second overflow drain region for discharging excess signal charge in the transfer channel region. Is less than the saturation level of the charge capacitance in the transfer channel region .

The CCD image sensor of the present invention configured as described above has a first overflow / drain region that discharges excess signal charge accumulated in the charge storage region, and a control voltage that controls the amount of excess signal charge discharged. By providing the overflow gate electrode to which the signal is applied, it is possible to easily control the emission amount of the excess signal charge and provide a highly sensitive CCD image sensor.

The plan view which shows the whole structure of the CCD image sensor which is Embodiment 1 of this invention. The plan view which shows the structure of a part of the CCD image sensor which is Embodiment 1 of this invention. FIG. 2 is a cross-sectional view taken from the cutting line AA of FIG. 2 of the CCD image sensor according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken from the cutting line BB of FIG. 2 of the CCD image sensor according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken from the cutting line CC of FIG. 2 of the CCD image sensor according to the first embodiment of the present invention. The schematic diagram which shows the change of the charge capacity of the charge storage area of the CCD image sensor which is Embodiment 1 of this invention. The plan view which shows the structure of a part of the CCD image sensor which is Embodiment 2 of this invention. FIG. 6 is a cross-sectional view taken from the cutting line DD of FIG. 7 of the CCD image sensor according to the second embodiment of the present invention. The schematic diagram which shows the saturation level of the charge capacity of each part of the CCD image sensor which is Embodiment 2 of this invention.

First, the configuration of the CCD image sensor of the present invention will be described with reference to the drawings. The figure is schematic and conceptually explains the function or structure. Further, the present invention is not limited to the embodiments shown below. Unless otherwise specified, the basic configuration of the CCD image sensor is common to all embodiments. Further, those having the same reference numerals are the same or equivalent thereof, and this is common to the whole text of the specification.

Here, in the description of each embodiment, the vertical direction is defined as the vertical direction which is the first direction when the plan view is viewed, and the direction orthogonal to the vertical direction which is the first direction, that is, the left and right directions when the plan view is viewed. The description will be given with the direction as the horizontal direction, which is the second direction.

Embodiment 1.
FIG. 1 is a plan view showing the overall configuration of the CCD image sensor according to the first embodiment of the present invention.

As shown in FIG. 1, the CCD image sensor according to the present embodiment includes a pixel region 10, a drive circuit 20, a charge storage unit 30, and an output circuit 40.

As shown in FIG. 1, the pixel region 10 is a region in which pixels 12, which are photoelectric conversion units that generate signal charges in response to light incident, are arranged in a two-dimensional array. Here, although FIG. 1 shows an example in which the pixels 12 are arranged in a two-dimensional array, the pixels 12 may be arranged one-dimensionally.

The drive circuit 20 is adjacent to and connected to one end of the pixel region 10 in the horizontal direction. The drive circuit 20 is a circuit that drives the transfer electrode 16 described later in order to transfer the signal charge generated in the pixel 12 to the charge storage unit 30 in the vertical direction.

The charge storage unit 30 is a region for storing signal charges transferred in the vertical direction by the transfer electrode 16 which is driven and controlled by the drive circuit 20. The charge storage unit 30 is provided at one end of the pixel region 10 in the vertical direction in which the signal charge is transferred, and can store the signal charge transferred for each row of the pixels 12 in the pixel region 10.

Further, the charge storage unit 30 includes an external terminal EXT for controlling the voltage of the overflow gate electrode 35 of the charge storage unit 30, which will be described later. The external terminal EXT can control the voltage of the overflow gate electrode 35 from the outside.

Here, controlling from the outside means controlling from outside the chip provided with the CCD image sensor according to the present embodiment. For example, an external voltage is input to the external terminal EXT from a power supply circuit provided outside the chip. , The voltage of the overflow gate electrode 35 is controlled.

The output circuit 40 is a circuit that converts the signal charge of the pixel 12 stored in the charge storage unit 30 into a voltage, performs analog-digital conversion, and outputs a signal of an image of the subject as a digital signal. The output circuit 40 includes, for example, a horizontal CCD 42, an FD (Floating Diffusion) amplifier 44, an output amplifier 46, and an ADC (Analog to Digital Converter) 48.

The horizontal CCD 42 horizontally transfers the signal charge accumulated in the charge storage unit 30 for each row of the pixels 12 in the pixel region 10, and the transferred signal charge is output to the FD amplifier 44.

The FD amplifier 44 converts the signal charge transferred from the horizontal CCD 42 into a voltage, and the voltage-converted signal charge is output to the output amplifier 46.

The output amplifier 46 amplifies the voltage corresponding to the signal charge converted by the FD amplifier 44, and the amplified voltage is output to the ADC 48.

The ADC 48 converts the voltage corresponding to the signal charge, which is voltage-converted by the FD amplifier 44 and amplified by the output amplifier 46, from an analog signal to a digital signal. The digital signal corresponding to the signal charge converted from analog to digital by the ADC 48 is output to, for example, a chip outside the chip provided with the CCD image sensor and input to a signal processing circuit (not shown) provided on another chip.

Here, the FD amplifier 44 has been described as an example of converting the signal charge transferred from the horizontal CCD 42 into a voltage, but the present invention is not limited to this, and the circuit that converts the signal charge transferred from the horizontal CCD 42 into a voltage. If so, a circuit other than the FD amplifier 44 may be used.

Further, the output amplifier 46 may be provided with a function of removing noise such as a CDS (Correlated Double Sampling) circuit.

Next, a detailed configuration of the CCD image sensor according to the present embodiment will be described.

FIG. 2 is a plan view showing a partial configuration of the CCD image sensor according to the present embodiment, and is a plan view near the boundary between the pixel region 10 and the charge storage unit 30 of the CCD image sensor according to the present embodiment. Is. FIG. 3 is a cross-sectional view taken from the cutting line AA of FIG. 2 of the CCD image sensor according to the present embodiment. FIG. 4 is a cross-sectional view taken from the cutting line BB of FIG. 2 of the CCD image sensor according to the present embodiment. FIG. 5 is a cross-sectional view taken from the cutting line CC of FIG. 2 of the CCD image sensor according to the present embodiment.

As shown in FIG. 2, in the pixel area 10 of the CCD image sensor according to the present embodiment, the area surrounded by bold letters is regarded as one pixel 12, and the transfer channel area 14, the transfer electrode 16, and the pixel separation area 50 are included. To prepare for. The pixel 12 shown in FIG. 2 is a pixel in which a plurality of pixels 12 shown in FIG. 1 are arranged in a column direction and are adjacent to a charge storage unit 30 provided at the end.

As shown in FIG. 2, the transfer channel region 14 extends vertically in the pixel region 10, passes through the transfer electrode 16, and generates a signal charge in response to light incident. As shown in FIG. 3, the transfer channel region 14 is formed on, for example, a semiconductor substrate 1 made of a P-type silicon substrate having a P-type impurity concentration which is the second conductive type, and is an N-type which is the first conductive type. It is an impurity region having an impurity concentration.

As shown in FIGS. 2 to 4, the transfer electrode 16 has lower transfer electrodes 16a and 16c and upper transfer electrodes 16b and 16d. The lower transfer electrodes 16a and 16c are made of, for example, polysilicon, are provided on the transfer channel region 14 via a gate insulating film 60 such as a silicon oxide film, and extend horizontally in the pixel region 10. There is. The upper transfer electrodes 16b and 16d are made of, for example, polysilicon, are provided on the transfer channel region 14 via a gate insulating film 62 such as a silicon oxide film, and extend horizontally in the pixel region 10. There is.

Here, FIG. 4 shows a cross-sectional view of the upper transfer electrode 16d in the horizontal direction, but the upper transfer electrode 16b also has a similar cross-sectional view. Further, the lower transfer electrodes 16a and 16c have the same cross-sectional view except that the gate insulating film 62 is replaced with the gate insulating film 60.

As shown in FIG. 2, control signals φ1 and φ3 are input from the drive circuit 20 to the lower transfer electrodes 16a and 16c, respectively, and control signals φ2 and φ4 from the drive circuit 20 are input to the upper transfer electrodes 16b and 16d, respectively. Entered. The lower transfer electrodes 16a and 16c and the upper transfer electrodes 16b and 16d control the control signals φ1 to φ4 by the drive circuit 20, so that the signal charges generated in the transfer channel region 14 in response to the light incident are transferred to the charge storage unit 30. Transfer vertically.

As shown in FIGS. 2 and 4, the pixel separation region 50 is a region that electrically separates the transfer channel region 14 and the transfer channel region 14 of the horizontally adjacent pixels 12. The pixel separation region 50 is horizontally adjacent to the transfer channel region 14 and extends vertically along the transfer channel region 14. The pixel separation region 50 is, for example, an impurity region formed on the semiconductor substrate 1 and having a P-type impurity concentration.

Here, in FIG. 2, the region shown by the thick line is described by taking as an example a configuration of one pixel 12, that is, a four-phase configuration in which control signals φ1 to φ4 control the lower transfer electrodes 16a and 16c and the upper transfer electrodes 16b and 16d. However, for example, a configuration in which the signal charge is transferred in the vertical direction with another number of phases such as two-phase or three-phase may be used.

Further, as shown in FIGS. 3 and 4, an insulating film 64 such as a silicon oxide film is provided above the transfer electrode 16 in order to flatten the surface.

Next, as shown in FIGS. 2 and 5, the charge storage unit 30 includes a charge storage region 31, a charge storage gate electrode 32, and a charge control gate electrode 33.

As shown in FIGS. 2, 3 and 5, the charge storage region 31 is provided at one end in the vertical direction of the transfer channel region 14 extending in the vertical direction, and receives the signal charge transferred from the transfer channel region 14. It is an area to accumulate. The charge storage region 31 extends vertically from one end adjacent to the transfer channel region 14 to the horizontal CCD 42. Further, as shown in FIG. 5, the charge storage region 31 is, for example, an impurity region provided on the semiconductor substrate 1 and having an N-type impurity concentration, and in the present embodiment, it is the impurity concentration of the transfer channel region 14. It has the same N-type impurity concentration.

The charge storage gate electrode 32 is made of the same polysilicon as the lower transfer electrodes 16a and 16c, and is charged at a position perpendicular to the upper transfer electrode 16d as shown in FIGS. 2, 3 and 5. It is provided on the region 31 via the gate insulating film 60. A control signal φST is input to the charge storage gate electrode 32.

The charge control gate electrode 33 is made of the same polysilicon as the upper transfer electrodes 16b and 16d, and is charged at a position perpendicular to the charge storage gate electrode 32 as shown in FIGS. 2, 3 and 5. It is provided on the storage region 31 via the gate insulating film 62. A control signal φSC is input to the charge control gate electrode 33.

The charge storage gate electrode 32 and the charge control gate electrode 33 are transferred from the transfer channel region 14 by the control signals φST and φSC input to each, and the signal charge stored in the charge storage region 31 is transferred to the horizontal CCD 42. Can be done.

Further, as shown in FIGS. 2 and 5, the charge storage unit 30 includes an overflow gate region 34, an overflow gate electrode 35, and an overflow drain region 36.

As shown in FIGS. 2 and 5, the overflow gate region 34 is provided at a position horizontally adjacent to the charge storage region 31. The overflow gate region 34 is, for example, an impurity region provided on the semiconductor substrate 1 and having an N-type impurity concentration. In the present embodiment, the overflow gate region 34 has the same N-type impurity concentration as the transfer channel region 14.

The overflow gate electrode 35 is made of the same polysilicon as the upper transfer electrodes 16b and 16d, and as shown in FIGS. 2 and 5, the overflow gate region 34 is located at a position horizontally adjacent to the charge storage gate electrode 32. It is provided on top via a gate insulating film 62. A control voltage VOFG that can be controlled by the external terminal EXT is input to the overflow gate electrode 35.

The overflow drain region 36 is provided at a position horizontally adjacent to the overflow gate region 34. The overflow / drain region 36 is, for example, an impurity region provided on the semiconductor substrate 1 and having an N-type impurity concentration. In the present embodiment, the overflow / drain region 36 has the same N-type impurity concentration as the transfer channel region 14. Further, a control voltage VOFD is applied to the overflow / drain region 36.

In the present embodiment, the control voltage VOFG is applied to the overflow gate electrode 35 to control the overflow gate electrode 35, so that the excess signal charge accumulated in the charge storage region 31 overflows through the overflow gate region 34. It can be discharged to the drain region 36. Details will be described later.

As shown in FIGS. 2 and 5, a pixel separation region 50 extending from the pixel region 10 is provided at an adjacent position of the charge storage unit 30 configured as described above, and a row of adjacent pixels 12 is provided. It is electrically separated from the charge storage unit 30 corresponding to the above in the horizontal direction.

Further, as shown in FIG. 5, an insulating film 64 for flattening the surface is provided above the charge storage gate electrode 32 and the overflow gate electrode 35.

From the above, the CCD image sensor according to the present embodiment is configured.

Here, in the present embodiment, the transfer channel region 14, the charge storage region 31, the overflow gate region 34, and the overflow drain region 36 have been described as N-type impurity regions having the same impurity concentration, but the conductive type of each impurity region has been described. And the impurity concentration can be appropriately changed without departing from the present invention.

Next, the operation of the CCD image sensor according to the present embodiment will be described.

When light is incident on the CCD image sensor according to the present embodiment, a signal charge corresponding to the incident light is generated in the transfer channel region 14. After that, by controlling the control signals φ1 to φ4 input from the drive circuit 20 to the transfer electrodes 16a to 16d, the signal charges generated in the transfer channel region 14 are transferred to the charge storage unit 30 in the vertical direction line by line.

Then, the signal charge transferred from the transfer channel region 14 is stored in the charge storage region 31 of the charge storage unit 30. After that, by controlling the control signals φST and φSC, the charge storage gate electrode 32 and the charge control gate electrode 33 are driven, and the signal charge stored in the charge storage region 31 is transferred to the horizontal CCD 42.

At this time, as described above, the CCD image sensor of the present embodiment includes the overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 in the charge storage unit 30, so that the signal stored in the charge storage region 31 is provided. Of the charges, the excess signal charge can be discharged to the overflow drain region 36 via the overflow gate region 34 by controlling the overflow gate electrode 35.

Further, since the overflow gate electrode 35 is controlled by the control voltage VOFG and the control voltage VOFG can be controlled from the external terminal EXT, the charge capacity that can be stored in the charge storage region 31 is changed by the voltage value of the control voltage VOFG, resulting in excess. The amount of signal charge emitted can be adjusted. Details will be described later.

Then, the signal charge transferred to the horizontal CCD 42 is transferred in the horizontal direction by the horizontal CCD 42, the signal charge transferred from the horizontal CCD 42 by the FD amplifier 44 is converted into a voltage, and the signal charge is converted into a signal charge by the ADC 48 via the output amplifier 46. The corresponding voltage is analog-digitally converted, and as a digital signal, the signal of the image of the subject is output from the ADC 48 to the outside of the chip provided with the CCD image sensor. The digital signal output to the outside of the chip of the CCD image sensor is input to, for example, a signal processing circuit (not shown) provided on another chip, and signal processing is performed.

Next, the detailed operation of the CCD image sensor according to the present embodiment will be described. FIG. 6 is a schematic diagram showing a change in the charge capacity that can be stored in the charge storage region 31 of the CCD image sensor according to the present embodiment, in which the control signal φST of the charge storage gate electrode 32 is controlled to 10 V and the overflow drain region 36 is controlled. The charge capacity that can be stored in the charge storage region 31 when a voltage of 15 V is applied and the voltage applied to the control voltage VOFG of the overflow gate electrode 35 is changed to (a) 0 V, (b) 3 V, and (c) 7 V is shown. ing.

As shown in FIG. 6, since the pixel separation region 50 is a P-type impurity region and has a higher potential barrier than the charge storage region 31, the charge capacity stored in the charge storage region 31 is the control signal φST. It is determined by the potential barrier corresponding to the potential difference with the control voltage VOFG, and the signal charge can be accumulated up to the upper part of the shaded area. Excessive signal charge exceeding the charge capacity that can be stored in the charge storage region 31 is discharged to the overflow drain region 36 via the overflow gate region 34.

Therefore, when the control voltage VOFG = 0V in FIG. 6A, the charge capacity that can be stored in the charge storage region 31 has the maximum charge capacity in FIGS. 6A to 6C. When the control voltage VOFG = 3V in FIG. 6B has an intermediate charge capacity in FIGS. 6A to 6C, and when the control voltage VOFG in FIG. 6C is 7V. , Has the smallest charge capacity among (a) to (c) of FIG.

Therefore, the CCD image sensor of the present embodiment can control the charge capacity that can be stored in the charge storage region 31 by controlling the voltage value of the control voltage VOFG of the overflow gate electrode 35, and the charge storage region can be controlled. It is possible to control the amount of excess signal charge emitted from 31.

Further, in the CCD image sensor of the present embodiment, the external terminal EXT is directly connected to the overflow gate electrode 35 via the internal wiring. Therefore, the voltage value of the control voltage VOFG can be directly controlled by inputting the external voltage generated by the external power supply circuit from the external terminal EXT. In the present embodiment, an external voltage in an arbitrary range generated by an external power supply circuit, for example, an external voltage of 0V to 7V is input to the external terminal EXT, and the overflow gate electrode 35 can be directly controlled. ..

Here, the external voltage is not limited to the case where it can be set within a predetermined range, but a plurality of predetermined voltage values, for example, as shown in FIG. 6, only three voltage values can be input and can be arbitrarily input from the outside. You may select and change the voltage value. If the power supply circuit is located in the same chip of the CCD image sensor, a control signal for determining the voltage value input to the overflow gate electrode 35 is input from the external terminal EXT, and the inside is based on the control signal. The voltage input to the overflow gate electrode 35 may be generated by the power supply circuit of.

Further, in the present embodiment, the control voltage VOFD applied to the overflow / drain region 36 has been described as 15V, but a deep potential level is provided so that an excessive signal charge is discharged to the overflow / drain region 36. The voltage value of the control voltage VOFD is not limited to 15V and can be set as appropriate.

Next, the effect of the CCD image sensor according to this embodiment will be described.

As described above, since the CCD image sensor of the present embodiment includes the overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 in the charge storage unit 30, the signal stored in the charge storage region 31 is provided. Of the charges, the excess signal charge can be discharged to the overflow drain region 36 via the overflow gate region 34 by controlling the overflow gate electrode 35. Since the overflow gate electrode 35 is controlled by the control voltage VOFG and the control voltage VOFG can be controlled from the external terminal EXT, the charge capacity that can be stored in the charge storage region 31 is changed by the voltage value of the control voltage VOFG, resulting in an excessive signal. The amount of charge emitted can be adjusted.

Therefore, in the past, an overflow gate region and an overflow drain region were provided in the pixel region, and the amount of excess signal charge discharged was controlled by the transfer electrode. Therefore, it depends on the signal charge transfer operation and the excess signal charge is discharged. Although it was difficult to control the amount, the CCD image sensor of the present embodiment controls the voltage of the overflow gate electrode 35 to reduce the excess signal charge accumulated in the charge storage region 31 to the overflow drain region 36. It can be discharged to, and it becomes easy to control the amount of excess signal charge discharged. That is, in the CCD image sensor of the present embodiment, the emission amount of the excessive signal charge can be controlled by the control voltage VOFG without depending on the operation of the transfer electrode. Therefore, since the optimum signal charge emission amount can be set by controlling the voltage of the overflow gate electrode 35, noise such as blooming can be further removed as compared with the conventional case, and a highly sensitive CCD image sensor is provided. can do.

Further, the control voltage VOFG can be controlled from the external terminal EXT, and the charge capacity that can be stored in the charge storage region 31 can be changed by the voltage value of the control voltage VOFG. It is possible to control the amount of signal charge emitted, and it is possible to provide a highly sensitive CCD image sensor with reduced noise such as blooming.

Further, since the control voltage VOFG can be controlled from the external terminal EXT, even if the specifications of the output circuit 40 such as the ADC 48 are changed, the charge capacity that can be stored in the charge storage region 31 is changed according to the voltage value of the control voltage VOFG. The amount of signal charge to be transferred to the horizontal CCD 42 can be adjusted according to the specifications of the output circuit 40 such as the ADC 48. Therefore, it is not necessary to review the design of the pixel region 10 according to the specifications of the output circuit 40 such as the ADC 48, and the CCD image sensor can be easily designed.

Further, in the conventional CCD image sensor, it is necessary to determine the charge capacity of the signal charge that can be stored in the output circuit such as the horizontal CCD according to the charge capacity of the signal charge transferred from the pixel region, which depends on the semiconductor manufacturing process. Although high build-in accuracy was required, the CCD image sensor according to the present embodiment can change the charge capacity that can be stored in the charge storage region 31 depending on the voltage value of the control voltage VOFG. It is possible to relax the manufacturing accuracy by the semiconductor manufacturing process with the output circuit 40 such as the horizontal CCD 42, facilitate the manufacturing and improve the yield, and reduce the manufacturing cost.

Further, in the conventional CCD image sensor, since the overflow gate region and the overflow drain region are provided in the pixel region, the region in which the signal charge is generated according to the light incident in the pixel region is reduced. Since the CCD image sensor of the embodiment provides the overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 in the charge storage unit 30, signal charges are generated according to the light incident in the pixel region 10. The area to be used can be widened as compared with the conventional case, and a highly sensitive CCD image sensor can be provided.

From the above, in the CCD image sensor of the present embodiment, a first overflow drain region for discharging the excess signal charge accumulated in the charge storage region and a control voltage for controlling the discharge amount of the excess signal charge are applied. By providing the overflow gate electrode, the excess signal charge accumulated in the charge storage region can be discharged to the overflow drain region, so that it is easy to control the discharge amount of the excess signal charge and the sensitivity is high. A CCD image sensor can be provided.

Here, in the CCD image sensor according to the present embodiment, the output circuit 40 using the horizontal CCD 42 and the FD amplifier 44 has been described as an example, but the electric charge of the FD amplifier or the like is described for each row of the pixels 12 in the pixel region 10. -A configuration in which an output circuit such as a voltage conversion unit is provided and a signal charge is output for each row of pixels 12 may be used.

Embodiment 2.
Unlike the first embodiment, the CCD image sensor according to the second embodiment of the present invention includes an overflow gate region and an overflow drain region extending in the vertical direction between the transfer channel region and the pixel separation region. Since the other parts with the same reference numerals are configured in the same manner as the CCD image sensor according to the first embodiment, the description thereof will be omitted.

FIG. 7 is a plan view showing a partial configuration of the CCD image sensor according to the present embodiment, and is a plan view near the boundary between the pixel region 10 and the charge storage unit 30 of the CCD image sensor according to the present embodiment. Is. FIG. 8 is a cross-sectional view taken from the cutting line DD of FIG. 7 of the CCD image sensor according to the present embodiment.

As shown in FIGS. 7 and 8, the CCD image sensor according to the present embodiment has an overflow gate region 70 extending in the vertical direction between the transfer channel region 14 and the pixel separation region 50 in the pixel region 10 and the overflow gate region 70. An overflow / drain region 72 is provided.

As shown in FIG. 7, the overflow gate region 70 is provided at a position horizontally adjacent to the transfer channel region 14, and extends vertically along the transfer channel region 14. As shown in FIG. 8, the overflow gate region 70 is, for example, an impurity region provided at a position adjacent to the transfer channel region 14 of the semiconductor substrate 1 and having a P-type impurity concentration. The P-type impurity concentration in the overflow gate region 70 is lower than the P-type impurity concentration in the pixel separation region 50.

As shown in FIG. 7, the overflow drain region 72 is provided adjacent to the overflow gate region 70 and the pixel separation region 50, and extends vertically along the overflow gate region 70. As shown in FIG. 8, the overflow / drain region 72 is, for example, an impurity region provided at a position adjacent to the overflow gate region 70 of the semiconductor substrate 1 and having an N-type impurity concentration. Since the overflow / drain region 72 discharges the excess signal charge generated in the transfer channel region 14, the overflow / drain region 72 has an N-type impurity concentration higher than the N-type impurity concentration in the transfer channel region 14.

Next, the operation of the CCD image sensor according to the present embodiment will be described.

When light is incident on the CCD image sensor according to the present embodiment, a signal charge corresponding to the incident light is generated in the transfer channel region 14. At this time, for example, when strong light exceeding the charge capacity of the transfer channel region 14 is incident, the CCD image sensor according to the present embodiment includes the overflow gate region 70 and the overflow drain region 72 in the pixel region 10. Excess signal charge exceeding the charge capacity of the transfer channel region 14 is discharged to the overflow drain region 72 via the overflow gate region 70 by controlling the transfer electrode 16.

At the same time, the remaining signal charge from which the excess signal charge is discharged is vertically transferred from the transfer channel region 14 to the charge storage unit 30 as in the first embodiment. Since the subsequent operations are the same as those in the first embodiment, the description thereof will be omitted.

That is, in the CCD image sensor of the present embodiment, noise such as blooming when strong light exceeding the charge capacity of the transfer channel region 14 is incident on the overflow gate region 70 and the overflow drain region 72 in the pixel region 10 is generated. The overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 in the charge storage unit 30 serve to remove the charge, and the control voltage of the overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 is controlled according to the charge capacity of the transfer channel region 14 and the charge capacity of the output circuit 40 in the subsequent stage. By controlling the VOFG, it functions to control the charge capacity that can be stored in the charge storage region 31.

Therefore, it is necessary to set the emission amount of the excess signal charge in the pixel region 10 to be larger, and the saturation level of the charge capacity of the transfer channel region 14 determined by the overflow gate region 70 and the overflow drain region 72 in the pixel region 10. Is larger than the saturation level of the charge capacity of the charge storage region 31 determined by the overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 in the charge storage unit 30. In other words, the saturation level of the charge capacity of the charge storage region 31 controlled by the overflow gate electrode 35 is smaller than the saturation level of the charge capacity of the transfer channel region 14 controlled by the overflow gate region 70.

Next, the effect of the CCD image sensor according to this embodiment will be described. FIG. 9 is a schematic diagram showing the saturation level of the charge capacitance of each part of the CCD image sensor according to the present embodiment.

As described above, the CCD image sensor according to the present embodiment includes the overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 in the charge storage unit 30, and also has a transfer channel region in the pixel region 10. An overflow gate region 70 and an overflow drain region 72 extending in the vertical direction between the 14 and the pixel separation region 50 are provided.

Therefore, the CCD image sensor according to the present embodiment can discharge the excess signal charge accumulated in the charge storage region 31 to the overflow drain region 36 as in the first embodiment, so that the excess signal charge can be discharged. The emission amount can be easily controlled, and the overflow gate region 70 and the overflow drain region 72 in the pixel region 10 can further remove noise such as blooming as compared with the first embodiment, and the CCD has higher sensitivity. An image sensor can be provided.

Further, conventionally, when strong light exceeding the charge capacity of the transfer channel region is incident by the overflow gate region and the overflow drain region in the pixel region, noise such as blooming can be removed, but after the charge storage portion. The charge capacity of each part must be designed according to the saturation level of the charge capacity in the transfer channel region, and high accuracy is required in the semiconductor manufacturing process.

However, the CCD image sensor according to the present embodiment causes noise such as blooming when strong light exceeding the charge capacity of the transfer channel region 14 is incident on the overflow gate region 70 and the overflow drain region 72 in the pixel region 10. The overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 in the charge storage unit 30 are removed, and the charge in the transfer channel region 14 is controlled by the control voltage VOFG without worrying about the removal of noise such as blooming. It is possible to easily control the charge capacity that can be stored in the charge storage region 31 according to the capacity and the charge capacity of the output circuit 40 in the subsequent stage.

Specifically, conventionally, since the charge capacity of the transfer channel region is determined by the overflow gate region and the overflow drain region in the pixel region, the charge capacity of each part after the charge storage unit is saturated with the charge capacity of the transfer channel region. In accordance with the level, the saturation level of the charge capacity of the charge storage unit must be larger than the saturation level of the charge capacity of the transfer channel region. Further, since the saturation level of the charge capacity in the transfer channel region varies depending on the fluctuation of the semiconductor manufacturing process or the environmental conditions, the saturation level of the charge capacity of the charge storage unit is designed with a margin in consideration of these fluctuations. There is a need to. Therefore, the horizontal CCD, FD amplifier, output amplifier, and ADC, which are the output circuits after the charge storage unit, need to be designed in consideration of the above, which makes design and manufacturing difficult, and increases the manufacturing cost and the yield. I was invited.

However, in the CCD image sensor of the present embodiment, since the saturation level of the charge capacity is determined by the overflow gate region 34, the overflow gate electrode 35, and the overflow drain region 36 of the charge storage unit 30, the charge is as shown in FIG. The saturation level of the charge capacity of the storage unit 30 can be set to be smaller than the saturation level of the charge capacity of the transfer channel region 14. Therefore, the saturation level of the charge capacity of the horizontal CCD 42, the FD amplifier 44, the output amplifier 46, and the ADC 48, which are the output circuits 40 after the charge storage unit 30, is smaller than the saturation level of the charge capacity of the transfer channel region 14. It is possible to design based on the saturation level of the charge capacity of 30. Further, since the control voltage VOFG can be controlled by the voltage input from the external terminal EXT, the saturation level of the charge capacity of the charge storage unit 30 can be adjusted. Therefore, even if the specifications of the output circuit 40 such as the ADC 48 are changed and the saturation level is changed, the saturation level of the charge capacity of the charge storage region 31 is changed by the voltage value of the control voltage VOFG, and the output circuit 40 such as the ADC 48 is changed. The saturation level of the charge capacity of the charge storage region 31 can be adjusted according to the specifications.

Therefore, it is not necessary to review the design of the pixel region 10 according to the specifications of the output circuit 40 such as the ADC 48, and the CCD image sensor can be easily designed. Further, since the saturation level of the charge capacity of the charge storage region 31 can be changed by the voltage value of the control voltage VOFG, the built-in accuracy by the semiconductor manufacturing process between the pixel region 10 and the output circuit 40 such as the horizontal CCD 42 can be improved. It can be relaxed, the manufacturing can be facilitated and the yield can be improved, and the manufacturing cost can be reduced. Further, since the saturation level of the allowable charge capacity of the output circuit 40 such as the horizontal CCD 42 can be reduced, the chip size can be reduced and the power consumption can be reduced.

In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention. Furthermore, the present invention is not limited to the above-described embodiment, and can be variously modified at the implementation stage without departing from the gist thereof. Further, the above-described embodiment includes inventions at various stages, and various inventions can be extracted by an appropriate combination of the plurality of disclosed constituent requirements.

10 pixel area, 12 pixels, 14 transfer channel area, 16 transfer electrode, 30 charge storage part, 31 charge storage area, 32 charge storage gate electrode, 33 charge control gate electrode, 34, 70 overflow gate area, 35 overflow gate electrode, 36, 72 Overflow drain area, 50 pixel separation area, EXT external terminal

Claims (3)

A transfer channel region extending in the first direction and generating a signal charge in response to light incident, and a second direction provided above the transfer channel region and orthogonal to the first direction. A pixel region comprising a transfer electrode that transfers the signal charge in the first direction,
A charge storage region provided at one end of the pixel region in the direction in which the signal charge is transferred and accumulating the signal charge transferred from the pixel region, and a charge storage region.
Of the signal charges accumulated in the charge storage region, a first overflow drain region for discharging the excess signal charge accumulated in the charge storage region, and
An overflow gate electrode provided between the charge storage region and the first overflow drain region and to which a control voltage for controlling the amount of excess signal charge is applied is applied .
A first overflow gate region that extends in the first direction and is adjacent to the transfer channel region in the second direction.
Extends in the first direction, adjacent to the first overflow gate region in the second direction, and ejects excess signal charge in the transfer channel region through the first overflow gate region. With the second overflow drain area
Equipped with
The CCD image characterized in that the saturation level of the charge capacity of the charge storage region controlled by the overflow gate electrode is smaller than the saturation level of the charge capacity of the transfer channel region controlled by the first overflow gate region. Sensor. The overflow gate electrode is provided at a position adjacent to the charge storage region in the second direction.
The CCD image sensor according to claim 1, wherein the first overflow / drain region is provided at a position adjacent to the overflow gate electrode in the second direction. The CCD image sensor according to claim 1 or 2, further comprising an external terminal for controlling the control voltage.

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