JP6991873B2 - Display device and inspection method - Google Patents

Description

The present invention relates to a display device and an inspection method.

In recent years, in a display device using a liquid crystal display panel or an organic EL display panel (OLED: Organic Electro-Luminescence Display) using organic electroluminescence light emission, high density (high definition) of pixels is required. With the increase in definition of such display devices, the number of video signal lines and scanning lines has also increased, and the number of pins of the driver IC for driving these video signal lines and scanning lines has also increased. For example, in a semiconductor test device for testing an LCD driver, a high-speed technique for performing a contact test or a pin-to-pin short-circuit test before testing various items to see if the LCD driver meets the specifications is disclosed. (For example, Patent Document 1).

Japanese Patent Application Laid-Open No. 2003-57284

In mobile terminal devices such as smartphones, there is a demand for a display panel capable of narrowing the frame as well as high definition. Along with this, the number of cases where the driver IC is mounted on the flexible substrate by COF (Chip On Film) is increasing. The flexible substrate on which the driver IC is mounted is mounted on the glass substrate constituting the display panel by FOG (Film On Glass).

As the definition of the display device becomes higher, the wiring between the flexible board on which the driver IC is mounted and the glass board constituting the display panel increases, and the distance between the connection terminals connecting the wiring of both boards becomes narrower. ing. When the distance between the connection terminals is narrowed, there is a high possibility that a short circuit will occur between the adjacent connection terminals due to the conductive foreign matter caught between the glass substrate and the flexible substrate. Further, depending on the resistance value of the conductive foreign matter, the abnormality cannot be visually recognized in the display inspection, and the shipping quality of the display device may deteriorate.

An object of the present invention is to provide a display device capable of improving quality.

The display device according to one aspect of the present invention includes a first substrate provided with a display unit in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction, and a drive circuit for driving the display unit. A signal selection circuit provided between the display unit and the driver IC, a signal selection circuit provided between the driver IC, a second board provided with the driver IC, and the first board. A plurality of first wirings that are wired to the board and one end of which is electrically connected to the signal selection circuit, and a plurality of second wirings that are wired to the second board and one end of which is electrically connected to the driver IC. And a plurality of connection terminals in which the other end of the first wiring and the other end of the second wiring are electrically connected, and the signal selection circuit is a control state that the driver IC can take. It includes a first control state in which open control is performed and a potential difference is not applied between the adjacent connection terminals, and a second control state in which the signal selection circuit is open-controlled and a potential difference is applied between the adjacent connection terminals. ..

The inspection method of the display device according to one aspect of the present invention drives a first substrate provided with a display unit in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction, and the display unit. A driver IC in which a driving circuit is integrated, a second board provided with the driver IC, a signal selection circuit provided between the display unit and the driver IC, and arranged on the first board. A plurality of first wires that are wired to the first board and one end of which is electrically connected to the signal selection circuit, and a plurality of first wires that are wired to the second board and one end of which is electrically connected to the driver IC. In an inspection method for a display device having a second wiring and a plurality of connection terminals in which the other end of the first wiring and the other end of the second wiring are electrically connected, the connection terminal and the display unit. The first step of cutting off between the two, the second step of acquiring the first current value flowing through the driver IC in a state where no potential difference is applied between the adjacent connection terminals, and the adjacent connection terminals. The third step of acquiring the second current value flowing through the driver IC while the potential difference is applied to the driver IC, and the third step of comparing the difference between the first current value and the second current value with a predetermined current threshold value. It has 4 steps and a 5th step in which it is determined that a short circuit has occurred between the adjacent connection terminals when the difference is larger than the current threshold value.

The inspection method of the display device according to one aspect of the present invention drives a first substrate provided with a display unit in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction, and the display unit. A driver IC in which a driving circuit is integrated, a second board provided with the driver IC, a signal selection circuit provided between the display unit and the driver IC, and arranged on the first board. A plurality of first wires wired to the first board and one end electrically connected to the signal selection circuit, and a plurality of first wires wired to the second board and one end electrically connected to the driver IC. In an inspection method for a display device having a second wiring, a plurality of connection terminals to which the other end of the first wiring and the other end of the second wiring are electrically connected, the connection terminal and the display unit. The first step of cutting off between the two, the second step of supplying different voltages from the drive circuit to the adjacent connection terminals, the first voltage value of one of the adjacent connection terminals, and the adjacent connection terminals. The third step of detecting the other second voltage value, the fourth step of comparing the difference between the first voltage value and the second voltage value with a predetermined voltage threshold, and the difference from the voltage threshold. It also has a fifth step of determining that a short circuit has occurred between the adjacent connection terminals when the voltage is large.

FIG. 1 is a schematic diagram showing a schematic configuration of a display device according to the first embodiment. FIG. 2 is a circuit diagram showing a pixel arrangement of a display unit according to an embodiment. FIG. 3 is a diagram showing an example of a FOG mounting unit of a display board and a circuit board. FIG. 4 is a diagram showing a schematic configuration of a display device and an inspection jig according to the first embodiment. FIG. 5 is a diagram showing an example of the short circuit determination processing procedure according to the first embodiment. FIG. 6 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the first embodiment. FIG. 7 is a diagram showing an example of the short-circuit determination processing procedure according to the first modification of the first embodiment. FIG. 8 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the first modification of the first embodiment. FIG. 9 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modification 2 of the first embodiment. FIG. 10A is a diagram showing a schematic configuration of a display device and an inspection jig according to the second embodiment. FIG. 10B is a diagram showing a first modification in the schematic configuration of the display device and the inspection jig according to the second embodiment. FIG. 10C is a diagram showing a second modification in the schematic configuration of the display device and the inspection jig according to the second embodiment. FIG. 10D is a diagram showing a third modification in the schematic configuration of the display device and the inspection jig according to the second embodiment. FIG. 11 is a diagram showing an example of the short circuit determination processing procedure according to the second embodiment. FIG. 12 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the second embodiment. FIG. 13 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modified example of the second embodiment. FIG. 14 is a diagram showing a schematic configuration of a display device and an inspection jig according to the third embodiment. FIG. 15 is a diagram showing an example of the short circuit determination processing procedure according to the third embodiment. FIG. 16 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the third embodiment. FIG. 17 is a diagram showing a schematic configuration of a display device and an inspection jig according to the fourth embodiment. FIG. 18 is a diagram showing an example of the short circuit determination processing procedure according to the fourth embodiment. FIG. 19 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the fourth embodiment. FIG. 20 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modified example of the fourth embodiment. FIG. 21 is a diagram showing a schematic configuration of a display device and an inspection jig according to the fifth embodiment. FIG. 22 is a diagram showing an example of the short circuit determination processing procedure according to the fifth embodiment. FIG. 23 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the fifth embodiment. FIG. 24 is a diagram showing an example of the short-circuit determination processing procedure according to the first modification of the fifth embodiment. FIG. 25 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the first modification of the fifth embodiment. FIG. 26 is a diagram showing a schematic configuration of a display device and an inspection jig according to the second modification of the fifth embodiment. FIG. 27 is a schematic diagram showing a schematic configuration of the display device according to the sixth embodiment. FIG. 28 is a diagram showing a schematic configuration of a display device and an inspection jig according to the sixth embodiment. FIG. 29 is a diagram showing an example of the short circuit determination processing procedure according to the sixth embodiment. FIG. 30 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the sixth embodiment. FIG. 31 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modified example of the sixth embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention, which are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited. Further, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

(Embodiment 1)
FIG. 1 is a schematic diagram showing a schematic configuration of a display device according to the first embodiment. As shown in FIG. 1, the display device 100 according to the present embodiment includes a display board 1, a first circuit board 3, and a second circuit board 4.

In the present embodiment, the display substrate 1 is composed of a glass substrate. The display board 1 is provided with a display unit 11 in which pixels Pix (see FIG. 2) are arranged in the X direction and the Y direction in the drawing.

The display unit 11 may be configured to include, for example, a liquid crystal display element as a display element. Further, the display unit 11 may be configured to include, for example, an organic EL element (organic light emitting diode) as a light emitting element. The present disclosure is not limited by the aspect of the display unit 11.

The display board 1 is provided with a scanning signal line for supplying a scanning signal to the pixel circuit of the display unit 11 and a video signal line for supplying a video signal to the pixel circuit of the display unit 11.

As a control unit that controls the operation of the display unit 11, a drive circuit that supplies various signals to the pixel circuit, a controller that generates timing signals to be supplied to the drive circuit, and the like are provided.

For example, a scanning line drive circuit or the like that supplies a scanning signal to the scanning signal line of the display unit 11 can be arranged on the display board 1.

In the present embodiment, the first circuit board 3 is composed of a flexible wiring board (FPC: Flexible Printed Circuits). The driver IC 6 is mounted on the first circuit board 3. The driver IC 6 is, for example, a semiconductor chip in which a video line drive circuit for supplying a video signal to the video signal line of the display unit 11 is integrated. The driver IC 6 is mounted on the first circuit board 3 by a COF (Chip On Film) using, for example, an anisotropic conductive film (ACF) (hereinafter referred to as “COF mounting”).

In the present embodiment, the second circuit board 4 is composed of a flexible wiring board. Circuit elements such as a power supply circuit that generates various reference potentials, a signal processing circuit that processes a video signal, and a frame memory can be arranged on the second circuit board 4.

At the end of the display board 1, terminals (pads) for connecting to each wiring on the first circuit board 3 side are provided. Further, at one end of the first circuit board 3, a terminal (pad) for connecting to each wiring on the display board 1 side is provided. The first circuit board 3 is adhered to the display board 1 by, for example, FOG (Film On Glass) using ACF (hereinafter, referred to as “FOG mounting”). As a result, each wiring on the display board 1 side and each wiring on the first circuit board 3 side corresponding to each wiring on the display board 1 side are electrically connected.

At the end of the second circuit board 4, terminals (pads) for connecting to each wiring on the first circuit board 3 side are provided. Further, at the other end of the first circuit board 3, a terminal (pad) for connecting to each wiring on the second circuit board 4 side is provided. The first circuit board 3 is adhered to the second circuit board 4 by, for example, FOF (Film On Film) using ACF (hereinafter, referred to as “FOF mounting”). As a result, each wiring on the second circuit board 4 side and each wiring on the first circuit board 3 side corresponding to each wiring on the second circuit board 4 side are electrically connected.

The first circuit board 3 and the second circuit board 4 may be composed of one flexible wiring board. In this case, circuit elements other than the driver IC 6 may be mounted on the flexible wiring board, or circuit elements other than the driver IC 6 may not be mounted. Hereinafter, when it is not necessary to distinguish between the first circuit board 3 and the second circuit board 4, the first circuit board 3 and the second circuit board 4 are regarded as the circuit board 2 composed of one flexible wiring board. explain.

The display board 1 corresponds to the "first board" in the present disclosure. Further, the circuit board 2 corresponds to the "second board" in the present disclosure.

FIG. 2 is a circuit diagram showing a pixel arrangement of a display unit according to an embodiment. FIG. 2 illustrates a pixel configuration when a liquid crystal display panel is used as the display device 100. In the present embodiment, the pixel Pix includes three sub-pixel SPix corresponding to the color filters 12R, 12G, and 12B colored in three colors of red (R), green (G), and blue (B), respectively. The pixel Pix may be configured to include four or more sub-pixel SPix corresponding to each of the color filters colored in four or more colors.

The display board 1 is formed with a switching element Tr of each sub-pixel SPix, a video signal line SGL, a scanning signal line GCL, and the like. The video signal line SGL is wiring for supplying the pixel signal Vpix to each switching element Tr. The scanning signal line GCL is wiring for supplying a drive signal for driving each switching element Tr. The video signal line SGL and the scanning signal line GCL extend on a plane parallel to the surface of the display substrate 1. In the present embodiment, the scanning signal line GCL is provided so as to extend in the X direction in the figure. Further, in the present embodiment, the video signal line SGL is provided so as to extend in the Y direction in the drawing.

The video signal line SGL and the scanning signal line GCL are electrically connected to the switching element Tr. The switching element Tr is provided at the intersection of the video signal line SGL and the scanning signal line GCL.

The display unit 11 has a plurality of sub-pixel SPix arranged in a matrix. The sub-pixel SPix includes a switching element Tr and a liquid crystal element 13a, respectively. The switching element Tr is composed of a thin film transistor, and is composed of, for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT. A pixel electrode is configured on the drain of the switching element Tr. An insulating layer is provided between the pixel electrode and the first electrode COML, and a holding capacity 13b is formed.

In the display unit 11, the scan signal line GCL is sequentially selected by the scan line drive circuit, and the scan signal Vscan is applied from the scan line drive circuit to the gate of the switching element Tr of the sub-pixel SPix via the scan signal line GCL. As a result, the sub-pixel SPix (1 horizontal line) arranged in the X direction is sequentially selected as the display drive target. Further, the display unit 11 supplies the pixel signal Vpix from the video line drive circuit to the source of the switching element Tr of the sub-pixel SPix of one horizontal line selected by the scanning line drive circuit via the video signal line SGL. .. As a result, the display unit 11 displays one horizontal line at a time according to the pixel signal Vpix supplied from the video line drive circuit.

When performing this display operation, a drive voltage Vcomdc, which is a common potential for a plurality of sub-pixel SPix, is applied to the electrode COML from the driver IC 6. As a result, each electrode COML functions as a common electrode for the pixel electrode. In this embodiment, a common drive voltage Vcomdc is applied to all the electrodes COML of the display unit 11.

FIG. 3 is a diagram showing an example of a FOG mounting unit of a display board and a circuit board. FIG. 3 shows an example in which the connection terminals 53 to which the first wiring 51 of the display board 1 and the second wiring 52 of the circuit board 2 are connected are arranged and arranged in the X direction in the FOG mounting unit 5.

One end of the first wiring 51 is electrically connected to the signal selection circuit 14 (see FIG. 4). One end of the second wiring 52 is electrically connected to the driver IC 6. In the example shown in FIG. 3, the FOG mounting unit 5 is configured such that the other end of the first wiring 51 and the other end of the second wiring 52 are electrically connected, and a plurality of connection terminals 53 are arranged in a row.

When the circuit board 2 is FOG mounted on the display board 1, a conductive foreign substance 54 may be caught between the display board 1 and the circuit board 2, and a short circuit may occur between the adjacent connection terminals 53 in the FOG mounting section 5. There is sex. As the definition of the display unit 11 becomes higher, the distance between the connection terminals 53 in the FOG mounting unit 5 tends to become narrower, and a short circuit may occur between the adjacent connection terminals 53 in the FOG mounting unit 5 due to the conductive foreign matter 54. The sex becomes high. Further, when the short circuit due to the conductive foreign matter 54 becomes high resistance, it is difficult to remove it by a normal inspection, so that the shipping quality of the display device 100 may deteriorate. In addition, the normal inspection includes an inspection (visual inspection) in which the display state is visually inspected.

In the present embodiment, in the shipping inspection of the display device 100, a short-circuit defect between adjacent connection terminals 53 is detected in the FOG mounting unit 5 by using an electric method. Hereinafter, a configuration for detecting a short-circuit defect between adjacent connection terminals 53 in the FOG mounting unit 5 will be described.

FIG. 4 is a diagram showing a schematic configuration of a display device and an inspection jig according to the first embodiment. As shown in FIG. 4, the inspection jig 200 is connected to the circuit board 2 in the shipping inspection of the display device 100.

The driver IC 6 FOG mounted on the circuit board 2 includes a video line drive circuit 61, a switch control unit 62, and an output control circuit 63. The video line drive circuit 61 corresponds to the "drive circuit" in the present disclosure.

The video line drive circuit 61 generates an image signal Vsig in which the pixel signal Vpix supplied to the sub-pixel SPix of R (red), G (green) and B (blue) is time-division-multiplexed when the display operation is performed. And output. The video line drive circuit 61 includes n amplifier circuits 611, ..., 61n corresponding to n rows of pixels (n is a positive integer). In the video line drive circuit 61, the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201 of the inspection jig 200.

The output control circuit 63 switches between connection and disconnection between the amplifier circuits 611, ..., 61n of the video line drive circuit 61 and the connection terminals 53 of the FOG mounting unit 5. The output control circuit 63 includes switches 631, ..., 63n corresponding to the amplifier circuits 611, ..., 61n of the video line drive circuit 61, respectively. In this embodiment, the connection terminals 53 connected to the amplifier circuits 611, ..., 61n of the video line drive circuit 61 via the output control circuit 63 are targeted for detecting a short circuit defect. Hereinafter, the connection terminal 53 for which a short circuit defect is detected in the present embodiment is referred to as a “short circuit detection target connection terminal 53a”.

The switch control unit 62 controls each switch of the output control circuit 63 and each switch of the signal selection circuit 14 provided on the display board 1.

The display board 1 includes a signal selection circuit 14 that separates R (red), G (green), and B (blue) pixel signals Vpix that are time-division-multiplexed on the image signal Vsig. The signal selection circuit 14 is configured by using, for example, a multiplexer (MPX).

The inspection jig 200 is connected to the circuit board 2 in the shipping inspection of the display device 100. The inspection jig 200 includes a power supply unit 201, a processing unit 202, a register unit 203, and a current detection unit 204.

The power supply unit 201 generates a first positive power supply voltage A VDD1 and a first negative power supply voltage AVEE1 to be supplied to the driver IC 6. The first positive electrode power supply voltage A VDD1 has a potential difference of, for example, +5.5 V with respect to the reference potential GND. The first negative electrode power supply voltage AVEE1 has a potential difference of, for example, −5.5 V with respect to the reference potential GND.

A first positive electrode power supply voltage A VDD1, a reference potential GND, and a first negative electrode power supply voltage AVEE1 are supplied to each of the amplifier circuits 611, ..., 61n of the video line drive circuit 61. Each amplifier circuit 611, ..., 61n of the video line drive circuit 61 operates by the potential difference between the first positive electrode power supply voltage A VDD1 and the reference potential GND when outputting the positive voltage, and outputs the negative voltage. When outputting, it operates by the potential difference between the reference potential GND and the first negative electrode power supply voltage AVEE1. The present disclosure is not limited by the potential difference between the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 with respect to the reference potential GND. Further, in the present embodiment, the reference potential is set to the GND potential, but the present invention is not limited to this.

The processing unit 202 controls the driver IC 6 and performs short-circuit determination processing in the FOG mounting unit 5 in the shipping inspection of the display device 100. The short-circuit determination process in this embodiment will be described later.

The register unit 203 stores various data in the short-circuit determination process of the FOG mounting unit 5 by the processing unit 202. The various data stored in the register unit 203 include, for example, a current threshold value in the short-circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 203 may be numerical data or discrete values such as digital data.

The current detection unit 204 detects the current flowing through the power supply unit 201. Note that FIG. 4 shows a configuration in which current detectors are provided in both the supply path of the first positive power supply voltage A VDD1 and the supply path of the first negative electrode power supply voltage AVEE1, but the first positive electrode power supply voltage A VDD1 is shown. The configuration may be such that the current flowing in at least one of the supply path and the supply path of the first negative electrode power supply voltage AVEE1 is detected.

Hereinafter, in the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5 will be described. FIG. 5 is a diagram showing an example of the short circuit determination processing procedure according to the first embodiment. FIG. 6 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the first embodiment.

The short-circuit determination process shown in FIG. 5 is started in a state where the inspection jig 200 is connected to the circuit board 2 in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. .. It is assumed that the determination flag indicating the determination result in this short-circuit determination process is set to "0" and stored in the register unit 203. Here, the determination flag "0" indicates that no short circuit has occurred between any of the short-circuit detection target connection terminals 53a of the FOG mounting unit 5, and the determination flag "1" is 1 or more of the FOG mounting unit 5. It is assumed that a short circuit has occurred between the connection terminals 53a to be detected.

When the short-circuit determination processing start command is input, the processing unit 202 outputs a closing control command for all the switches of the output control circuit 63 and an open control command for all the switches of the signal selection circuit 14 to the switch control unit 62. (Step S101). As a result, the wiring between the video line drive circuit 61 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 is connected, and the video signal line SGL of the display unit 11 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 are connected. The wiring between them is cut off. The states of the switches of the signal selection circuit 14 and the video line drive circuit 61 in FIG. 4 indicate the state in which the process of step S101 has been performed.

Subsequently, the processing unit 202 controls the video line drive circuit 61 so that the potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 becomes substantially zero (step S102). Specifically, each amplifier circuit corresponding to the short-circuit detection target connection terminal 53a in the odd row is controlled so that a DC voltage of, for example, 0V is output, and each amplifier corresponding to the short-circuit detection target connection terminal 53a in the even row is controlled. It is controlled so that a DC voltage of, for example, 0 V is output from the circuit. At this time, the potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 becomes 0V. The control state of the driver IC 6 at this time corresponds to the "first control state" in the present disclosure. The processing unit 202 acquires the current value at this time as the first current value I1 from the current detection unit 204, and stores it in the register unit 203 as the first current value information (step S103).

Further, the processing unit 202 controls the video line drive circuit 61 to apply a predetermined potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 (step S104). Specifically, each amplifier that supplies an image signal Vsig to an odd-row pixel Pix is controlled so that a DC voltage of, for example, + 5V is output, and an image signal Vsig is supplied to an even-row pixel Pix. It is controlled so that a DC voltage of, for example, -5V is output from the circuit. At this time, the potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 is 10V. The control state of the driver IC 6 at this time corresponds to the "second control state" in the present disclosure. The processing unit 202 acquires the current value at this time as the second current value I2 from the current detection unit 204, and stores it in the register unit 203 as the second current value information (step S105).

In the example shown in FIG. 6, the first current value information and the second current value information are stored only, respectively, but as shown in FIG. 4, the supply path of the first positive power supply voltage A VDD1 and the second current value information are stored. 1 When a current detector is provided in both the supply path of the negative power supply voltage AVEE1, the current flowing in the supply path of the first positive power supply voltage A VDD1 and the current flowing in the supply path of the first negative power supply voltage AVEE1. The first current value I1 and the second current value I2 corresponding to each of the above may be acquired and the first current value information and the second current value information may be stored.

The above-mentioned processes of steps S102 and S103 and the processes of steps S104 and S105 can be interchanged. That is, there may be an embodiment in which the processing of step S104 and step S105 is performed, and then the processing of step S102 and step S103 is performed. The present disclosure is not limited by the order of implementation of the processes of steps S102 and S103 and the processes of steps S104 and S105.

Subsequently, the processing unit 202 reads out the first current value information and the second current value information from the register unit 203, and sets the difference | I1-I2 | between the first current value I1 and the second current value I2 as the current threshold value ΔIth. (| I1-I2 |> ΔIt) (step S106). Here, when the first current value I1 and the second current value I2 corresponding to the current flowing in the supply path of the first positive power supply voltage A VDD1 and the current flowing in the supply path of the first negative power supply voltage AVEE1 are acquired. In, the process of step S106 is performed for each of the current flowing in the supply path of the first positive power supply voltage A VDD1 and the current flowing in the supply path of the first negative power supply voltage AVEE1.

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is larger than the current threshold value ΔIt (step S106; Yes), the processing unit 202 is targeted for short-circuit detection of one or more of the FOG mounting unit 5. It is determined that a short circuit has occurred between the connection terminals 53a, the determination flag of the register unit 203 is rewritten from "0" to "1" (step S107), and the short circuit determination process according to the first embodiment is completed. FIG. 6 shows an example in which a short circuit occurs between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5. When the first current value I1 and the second current value I2 corresponding to the current flowing in the supply path of the first positive power supply voltage A VDD1 and the current flowing in the supply path of the first negative electrode power supply voltage AVEE1 are acquired. In the process of step S106, when at least one of the processing results is larger than the current threshold value, the processing unit 202 causes a short circuit between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5. It may be in the mode of determining.

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is equal to or less than the current threshold value ΔIth (step S106; No), the processing unit 202 is connected to any of the FOG mounting units 5 for short-circuit detection. It is determined that no short circuit has occurred between the terminals 53a, and the short circuit determination process according to the first embodiment is terminated.

In the configuration according to the first embodiment described above, by carrying out the short circuit determination processing procedure according to the first embodiment, it is detected that a short circuit has occurred between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5. be able to. Then, by reading the determination flag of the register unit 203 from the outside via the processing unit 202, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53a of the FOG mounting unit 5. can.

(Modification 1 of Embodiment 1)
FIG. 7 is a diagram showing an example of the short-circuit determination processing procedure according to the first modification of the first embodiment. FIG. 8 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the first modification of the first embodiment.

The short-circuit determination process shown in FIG. 7 is started in a state where the inspection jig 200 is connected to the circuit board 2 in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. ..

When the short-circuit determination processing start command is input, the processing unit 202 outputs a closing control command for all the switches of the output control circuit 63 and an open control command for all the switches of the signal selection circuit 14 to the switch control unit 62. (Step S201). As a result, the wiring between the video line drive circuit 61 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 is connected, and the video signal line SGL of the display unit 11 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 are connected. The wiring between them is cut off. The states of the switches of the signal selection circuit 14 and the video line drive circuit 61 in FIG. 4 indicate the state in which the process of step S201 has been performed.

Subsequently, the processing unit 202 controls the video line drive circuit 61 so that the potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 becomes substantially zero (step S202). Specifically, each amplifier circuit corresponding to the short-circuit detection target connection terminal 53a in the odd row is controlled so that a DC voltage of, for example, 0V is output, and each amplifier corresponding to the short-circuit detection target connection terminal 53a in the even row is controlled. It is controlled so that a DC voltage of, for example, 0 V is output from the circuit. At this time, the potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 becomes 0V. The control state of the driver IC 6 at this time corresponds to the "first control state" in the present disclosure. The processing unit 202 acquires the current value at this time as the first current value I1 from the current detection unit 204, and stores it in the register unit 203 as the first current value information (step S203).

Subsequently, the processing unit 202 selects between any short-circuit detection target connection terminals 53a among the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 (step S204). When the number of pixel rows is n, there are n-1 combinations of adjacent short-circuit detection target connection terminals 53a.

The processing unit 202 controls the video line drive circuit 61 to apply a predetermined potential difference between the selected short-circuit detection target connection terminals 53a (step S205). Specifically, it is controlled so that a DC voltage of, for example, + 5V is output from an amplifier circuit that supplies an image signal Vsig to pixels Pix in an odd row between the selected short-circuit detection target connection terminals 53a, and the selected short-circuit detection is detected. Between the target connection terminals 53a, control is performed so that, for example, a DC voltage of -5V is output from an amplifier circuit that supplies an image signal Vsig to even-row pixels Pix. At this time, the potential difference between the selected short-circuit detection target connection terminals 53a is 10V. The control state of the driver IC 6 at this time corresponds to the "second control state" in the present disclosure. The processing unit 202 acquires the current value at this time as the second current value I2 from the current detection unit 204, and stores it in the register unit 203 as the second current value information (step S206).

Subsequently, the processing unit 202 reads out the first current value information and the second current value information between the selected short-circuit detection target connection terminals 53a from the register unit 203, and sets the first current value I1 and the second current value I2. The difference | I1-I2 | is compared with the current threshold ΔIt (| I1-I2 |> ΔIt) (step S207).

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is larger than the current threshold value ΔIt (step S207; Yes), the processing unit 202 short-circuits between the selected short-circuit detection target connection terminals 53a. Is determined to have occurred, and the determination flag of the register unit 203 is rewritten from "0" to "1" (step S208). FIG. 8 shows an example in which a short circuit occurs between the connection terminals 53a (3, 4) to be detected as a short circuit.

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is equal to or less than the current threshold value ΔIth (step S207; No), the processing unit 202 short-circuits between the selected short-circuit detection target connection terminals 53a. Is determined not to occur.

Subsequently, the processing unit 202 determines a short circuit between all the adjacent short circuit detection target connection terminals 53a (1,2), (2,3), (3,4), ... (N-1, n). It is determined whether or not it has been completed (step S209).

If there is a short-circuit detection target connection terminal 53a that has not been determined to be short-circuited (step S209; No), the process returns to step S204 and the processes up to step S209 are repeated.

If the short-circuit determination has been completed between all the short-circuit detection target connection terminals 53a (step S209; Yes), the short-circuit determination process according to the first modification of the first embodiment is terminated.

In the configuration according to the first embodiment described above, by carrying out the short-circuit determination processing procedure according to the first modification of the first embodiment, the short-circuit detection target connection terminal 53a in which the short-circuit occurs in the FOG mounting unit 5 is specified. be able to. Then, by reading the information of the register unit 203 from the outside via the processing unit 202, it is possible to identify between the short circuit detection target connection terminals 53a in which the short circuit has occurred in the FOG mounting unit 5.

In this embodiment, in the second control state, control is performed so that, for example, a DC voltage of + 5V is output from each amplifier circuit that supplies the image signal Vsig to the pixel Pix in the odd row, and the pixel Pix in the even row is used. An example of controlling so that a DC voltage of, for example, -5V is output from each amplifier circuit that supplies the image signal Vsig is shown, but the following aspects are also possible.

For example, in the second control state, control is performed so that, for example, a DC voltage of -5V is output from each amplifier circuit that supplies the image signal Vsig to the pixel Pix in the odd row, and the image signal Vsig is output to the pixel Pix in the even row. A mode may be used in which control is performed so that, for example, a DC voltage of + 5 V is output from each of the supplied amplifier circuits.

For example, in the second control state, each amplifier circuit that supplies the image signal Vsig to the odd-row pixels Pix is controlled so that a DC voltage of, for example, + 5V is output, and the image signal Vsig is supplied to the even-row pixels Pix. A mode may be used in which control is performed so that, for example, a DC voltage of 0 V is output from each of the amplifier circuits.

Further, for example, in the second control state, control is performed so that, for example, a DC voltage of 0 V is output from each amplifier circuit that supplies the image signal Vsig to the pixel Pix in the odd row, and the image signal Vsig is output to the pixel Pix in the even row. The amplifier circuit may be controlled so that a DC voltage of, for example, -5V is output from each amplifier circuit.

That is, in the second control state, different voltages may be supplied to the adjacent short-circuit detection target connection terminals 53a.

(Modification 2 of Embodiment 1)
FIG. 9 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modification 2 of the first embodiment. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 9, the inspection jig 200a is connected to the circuit board 2a in the shipping inspection of the display device 100a.

The driver IC 6a FOG mounted on the circuit board 2a includes a video line drive circuit 61, a switch control unit 62, an output control circuit 63, a processing unit 65, a register unit 66, and a current detection unit 67.

The processing unit 65 is a component unit corresponding to the processing unit 202 in the inspection jig 200 of the first embodiment, and controls the driver IC 6a and performs a short-circuit determination process in the FOG mounting unit 5 in the shipping inspection of the display device 100a.

The register unit 66 is a component unit corresponding to the register unit 203 in the inspection jig 200 of the first embodiment, and stores various data in the short-circuit determination process of the FOG mounting unit 5 by the processing unit 65. The various data stored in the register unit 66 include, for example, a threshold value in the short-circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 66 may be numerical data or discrete values such as digital data.

The current detection unit 67 is a component corresponding to the current detection unit 204 in the inspection jig 200 of the first embodiment.

The inspection jig 200a is connected to the circuit board 2a in the shipping inspection of the display device 100a. The inspection jig 200a includes a power supply unit 201.

In the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5 is the same as the short-circuit determination process procedure according to the first embodiment and the short-circuit determination process procedure according to the modified example 1 of the first embodiment. Specifically, in the short-circuit determination processing procedure according to the first embodiment and the short-circuit determination processing procedure according to the modified example 1 of the first embodiment, the processing unit 202 is read as the processing unit 65, and the register unit 203 is read as the register unit 66. By replacing the current detection unit 204 with the current detection unit 67, it is possible to realize the same processing procedure as the short-circuit determination processing procedure according to the first embodiment or the short-circuit determination processing procedure according to the modified example 1 of the first embodiment.

In the configuration according to the second modification of the first embodiment described above, by carrying out the short circuit determination processing procedure according to the first embodiment, a short circuit occurs between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5. It can be detected that it is present. Then, by reading the determination flag of the register unit 66 from the outside via the processing unit 65, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53a of the FOG mounting unit 5. can.

Further, in the configuration according to the modification 2 of the embodiment 1 described above, by carrying out the short circuit determination processing procedure according to the modification 1 of the embodiment 1, a short circuit detection target connection in which a short circuit occurs in the FOG mounting unit 5 is performed. It is possible to specify between the terminals 53a. Then, by reading the information of the register unit 66 from the outside via the processing unit 65, it is possible to identify between the short circuit detection target connection terminals 53a in which the short circuit has occurred in the FOG mounting unit 5.

According to this embodiment, it is possible to provide display devices 100, 100a capable of improving quality.

(Embodiment 2)
FIG. 10A is a diagram showing a schematic configuration of a display device and an inspection jig according to the second embodiment. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 10A, the inspection jig 200b is connected to the circuit board 2b in the shipping inspection of the display device 100b.

The driver IC 6b FOG-mounted on the circuit board 2b includes a video line drive circuit 61, a switch control unit 62a, an output control circuit 63, and a voltage application circuit 64.

The voltage application circuit 64 includes switches 641, ..., 64n corresponding to the amplifier circuits 611, ..., 61n of the video line drive circuit 61, respectively. The voltage application circuit 64 is connected to the short-circuit detection target connection terminal 53a connected to the amplifier circuit that supplies the image signal Vsig to the pixels Pix of the odd row among the amplifier circuits 611, ..., 61n of the video line drive circuit 61. On the other hand, a short-circuit detection target connection connected to a switch 64p (p is a positive odd number of n or less) that individually applies the first positive voltage A VDD1 and an amplifier circuit that supplies an image signal Vsig to pixels Pix in an even row. It includes a switch 64q (q is a positive even number of n or less) that individually applies a first negative voltage AVEE1 to the terminal 53a.

The switch control unit 62a controls each switch of the output control circuit 63, each switch of the signal selection circuit 14 provided on the display board 1, and each switch 64p and each switch 64q of the voltage application circuit 64.

The inspection jig 200b is connected to the circuit board 2b in the shipping inspection of the display device 100b. The inspection jig 200b includes a power supply unit 201, a processing unit 202a, a register unit 203a, and a current detection unit 204.

The processing unit 202a controls the driver IC 6b and performs short-circuit determination processing in the FOG mounting unit 5 in the shipping inspection of the display device 100b. The short-circuit determination process in this embodiment will be described later.

The register unit 203a stores various data in the short-circuit determination process of the FOG mounting unit 5 by the processing unit 202a. The various data stored in the register unit 203a include, for example, a current threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 203a may be numerical data or discrete values such as digital data.

Hereinafter, in the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5 will be described. FIG. 11 is a diagram showing an example of the short circuit determination processing procedure according to the second embodiment. FIG. 12 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the second embodiment.

The short-circuit determination process shown in FIG. 11 is started in a state where the inspection jig 200b is connected to the circuit board 2b in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. .. At this time, all the switches of the voltage application circuit 64 are open-controlled, and the first positive power supply voltage A VDD1 or the first negative power supply voltage AVEE1 is supplied to all the short-circuit detection target connection terminals 53a of the FOG mounting unit 5. It shall be blocked.

When the short-circuit determination processing start command is input, the processing unit 202a outputs an open control command for all the switches of the output control circuit 63 and an open control command for all the switches of the signal selection circuit 14 to the switch control unit 62a. (Step S301). As a result, the wiring between the video line drive circuit 61 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 is cut off, and the video signal line SGL of the display unit 11 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 The wiring between them is cut off. The control state of the driver IC 6b at this time corresponds to the "first control state" in the present disclosure. The processing unit 202a acquires the current value at this time as the first current value I1 from the current detection unit 204, and stores it in the register unit 203a as the first current value information (step S302).

Subsequently, the processing unit 202a selects between any short-circuit detection target connection terminals 53a among the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 (step S303). When the number of pixel rows is n, there are n-1 combinations of adjacent short-circuit detection target connection terminals 53a.

The processing unit 202a of the voltage application circuit 64 so that the first positive power supply voltage A VDD1 is applied to one of the selected adjacent short-circuit detection target connection terminals 53a and the first negative power supply voltage AVEE1 is applied to the other. The switch 64p and the switch 64q are closed and controlled (step S304). At this time, when the first positive power supply voltage A VDD1 is, for example, +5.5V and the first negative power supply voltage AVEE1 is, for example, -5.5V, the potential difference applied between the adjacent short-circuit detection target connection terminals 53a is It is 11V. The states of the switches of the signal selection circuit 14, the video line drive circuit 61, and the voltage application circuit 64 in FIG. 10A indicate the state in which the process of step S304 has been performed. In the example shown in FIG. 10A, an example is shown in which the short-circuit detection target connection terminal 53a (1,2) shown in FIG. 11 is selected and the switch 641 and the switch 642 of the voltage application circuit 64 are closed-controlled. The control state of the driver IC 6b at this time corresponds to the "second control state" in the present disclosure. The processing unit 202a acquires the current value at this time as the second current value I2 from the current detection unit 204, and stores it in the register unit 203a as the second current value information (step S305).

Subsequently, the processing unit 202a reads out the first current value information and the second current value information between the selected short-circuit detection target connection terminals 53a from the register unit 203a, and sets the first current value I1 and the second current value I2. The difference | I1-I2 | is compared with the current threshold ΔIt (| I1-I2 |> ΔTh) (step S306).

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is larger than the current threshold value ΔIt (step S306; Yes), the processing unit 202a short-circuits between the selected short-circuit detection target connection terminals 53a. Is determined to have occurred, and the determination flag of the register unit 203a between the short-circuit detection target connection terminals 53a is rewritten from "0" to "1" (step S307). FIG. 12 shows an example in which a short circuit occurs between the connection terminals 53a (3, 4) to be detected as a short circuit.

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is equal to or less than the current threshold value ΔIth (step S306; No), the processing unit 202a short-circuits between the selected short-circuit detection target connection terminals 53a. Is determined not to occur.

Subsequently, the processing unit 202a determines a short circuit between all adjacent short circuit detection target connection terminals 53a (1,2), (2,3), (3,4), ... (N-1, n). It is determined whether or not it has been completed (step S308).

If there is a short-circuit detection target connection terminal 53a that has not been determined to be short-circuited (step S308; No), the process returns to step S303 and the processes up to step S308 are repeated.

If the short-circuit determination has been completed between all the short-circuit detection target connection terminals 53a (step S308; Yes), the short-circuit determination process according to the second embodiment is terminated.

In the configuration according to the second embodiment described above, by carrying out the short circuit determination processing procedure according to the second embodiment, a short circuit detection target in which a short circuit occurs in the FOG mounting unit 5 is performed as in the first modification of the first embodiment. It is possible to specify between the connection terminals 53a. Then, by reading the information of the register unit 203a from the outside via the processing unit 202a, it is possible to identify between the short-circuit detection target connection terminals 53a in which the short-circuit occurs in the FOG mounting unit 5.

Further, since the operation of each of the amplifier circuits 611, ..., 61n of the video line drive circuit 61 can be stopped, the steady circuit current included in the first current value I1 and the second current value I2 is reduced. This makes it possible to improve the accuracy of the threshold value determination when performing the short circuit determination.

In the present embodiment, the switch 64p (p is a positive odd number of n or less) of the voltage application circuit 64 is connected to the amplifier circuit that supplies the image signal Vsig to the pixel Pix in the odd row, and the short circuit detection target connection terminal 53a is connected. The first positive voltage A VDD1 is individually applied to the voltage applied circuit 64, and the switch 64q (q is a positive even number of n or less) of the voltage application circuit 64 is connected to an amplifier circuit that supplies the image signal Vsig to the pixel Pix in the even row. Although an example in which the first negative voltage AVEE1 is individually applied to the short-circuit detection target connection terminal 53a is shown, the following aspects can also be used.

FIG. 10B is a diagram showing a first modification in the schematic configuration of the display device and the inspection jig according to the second embodiment. As shown in FIG. 10B, for example, a short-circuit detection target connection in which a switch 64p (p is a positive odd number of n or less) of the voltage application circuit 64 is connected to an amplifier circuit that supplies an image signal Vsig to a pixel Pix in an odd row. An amplifier circuit in which the first negative voltage AVEE1 is individually applied to the terminals 53a, and the switch 64q (q is a positive even number of n or less) of the voltage application circuit 64 supplies the image signal Vsig to the pixels Pix in the even row. The first positive voltage A VDD1 may be individually applied to the short circuit detection target connection terminal 53a connected to the above.

FIG. 10C is a diagram showing a second modification in the schematic configuration of the display device and the inspection jig according to the second embodiment. As shown in FIG. 10C, for example, a short-circuit detection target connection in which a switch 64p (p is a positive odd number of n or less) of the voltage application circuit 64 is connected to an amplifier circuit that supplies an image signal Vsig to a pixel Pix in an odd row. An amplifier circuit in which the first positive voltage A VDD1 is individually applied to the terminals 53a, and the switch 64q (q is a positive even number of n or less) of the voltage application circuit 64 supplies the image signal Vsig to the pixels Pix in the even row. The reference potential GND may be individually applied to the short-circuit detection target connection terminal 53a connected to the above.

FIG. 10D is a diagram showing a third modification in the schematic configuration of the display device and the inspection jig according to the second embodiment. As shown in FIG. 10D, for example, a short-circuit detection target connection in which a switch 64p (p is a positive odd number of n or less) of the voltage application circuit 64 is connected to an amplifier circuit that supplies an image signal Vsig to a pixel Pix in an odd row. A reference potential GND is individually applied to the terminal 53a, and the switch 64q (q is a positive even number of n or less) of the voltage application circuit 64 is connected to an amplifier circuit that supplies the image signal Vsig to the pixel Pix in the even row. The first negative voltage AVEE1 may be individually applied to the short circuit detection target connection terminal 53a.

That is, in the second control state, different voltages may be supplied to the adjacent short-circuit detection target connection terminals 53a.

(Modified Example of Embodiment 2)
FIG. 13 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modified example of the second embodiment. The same components as those in the second embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 13, the inspection jig 200a is connected to the circuit board 2c in the shipping inspection of the display device 100c.

The driver IC 6c mounted on the circuit board 2c by FOG includes a video line drive circuit 61, a switch control unit 62a, an output control circuit 63, a voltage application circuit 64, a processing unit 65a, a register unit 66a, and a current detection unit. 67 and.

The processing unit 65a is a component corresponding to the processing unit 202a in the inspection jig 200b of the second embodiment, and controls the driver IC 6c and performs a short-circuit determination process in the FOG mounting unit 5 in the shipping inspection of the display device 100c.

The register unit 66a is a component unit corresponding to the register unit 203a in the inspection jig 200b of the second embodiment, and stores various data in the short-circuit determination process of the FOG mounting unit 5 by the processing unit 65a. The various data stored in the register unit 66a include, for example, a current threshold value in the short-circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 66a may be numerical data or discrete values such as digital data.

The current detection unit 67 is a component corresponding to the current detection unit 204 in the inspection jig 200b of the second embodiment.

The inspection jig 200a is connected to the circuit board 2c in the shipping inspection of the display device 100c. The inspection jig 200a includes a power supply unit 201.

In the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5 is the same as the short-circuit determination process procedure according to the second embodiment. Specifically, in the short-circuit determination processing procedure according to the second embodiment, the processing unit 202a is read as the processing unit 65a, the register unit 203a is read as the register unit 66a, and the current detection unit 204 is read as the current detection unit 67. It is possible to realize the same processing procedure as the short-circuit determination processing procedure according to the second embodiment.

In the configuration according to the modification of the second embodiment described above, by carrying out the short circuit determination processing procedure according to the second embodiment, the short circuit detection target connection terminal 53a where the short circuit has occurred in the FOG mounting unit 5 is specified. Can be done. Then, by reading the information of the register unit 66a from the outside via the processing unit 65a, it is possible to identify between the short circuit detection target connection terminals 53a in which the short circuit has occurred in the FOG mounting unit 5.

Further, as in the second embodiment, since the operations of the amplifier circuits 611, ..., 61n of the video line drive circuit 61 can be stopped, the steady state included in the first current value I1 and the second current value I2. The circuit current can be reduced, and the accuracy of the threshold value determination when performing the short circuit determination is improved.

According to this embodiment, it is possible to provide display devices 100b and 100c capable of improving quality.

(Embodiment 3)
FIG. 14 is a diagram showing a schematic configuration of a display device and an inspection jig according to the third embodiment. The same components as those in the first embodiment or the second embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 14, the inspection jig 200a is connected to the circuit board 2d in the shipping inspection of the display device 100d.

The driver IC 6d mounted on the circuit board 2d by FOG includes a video line drive circuit 61, a switch control unit 62b, an output control circuit 63, a voltage application circuit 64, a processing unit 65b, a register unit 66b, and a current detection unit. 67, a first booster circuit 68-1, a second booster circuit 68-2, and a voltage switching circuit 69 are included.

The first booster circuit 68-1 boosts the first positive electrode power supply voltage A VDD1 supplied from the power supply unit 201 of the inspection jig 200a to generate the second positive electrode voltage A VDD2. The second positive electrode voltage A VDD2 is, for example, + 10V.

The second booster circuit 68-2 boosts the first negative electrode power supply voltage AVEE1 supplied from the power supply unit 201 of the inspection jig 200a to generate the second negative electrode voltage AVEE2. The second negative electrode voltage AVEE2 is, for example, −10 V.

In the present embodiment, in the second control state of the short-circuit determination process described later, the potential difference between the first positive power supply voltage A VDD1 and the first negative power supply voltage AVEE1 between the selected adjacent short-circuit detection target connection terminals 53a. When 1 potential difference is applied and it is detected that a short circuit has occurred between the short circuit detection target connection terminals 53a, the second positive voltage is larger than the first potential difference between the short circuit detection target connection terminals 53a. By applying the second potential difference, which is the potential difference between the power supply voltage A VDD2 and the second negative power supply voltage AVEE2, the conductive foreign matter 54 (FIG. 3) between the adjacent short-circuit detection target connection terminals 53a is removed, and a short circuit is caused. Eliminate. The present disclosure is not limited by the voltages of the second positive electrode power supply voltage A VDD2 and the second negative electrode power supply voltage AVEE2, that is, the magnitude of the second potential difference.

The voltage switching circuit 69 switches the power supply voltage supplied to the voltage application circuit 64. Specifically, the voltage switching circuit 69 is provided for the switch 691-1 for switching between the supply and cutoff of the first positive power supply voltage A VDD1 to each switch 64p of the voltage application circuit 64, and to each switch 64q of the voltage application circuit 64. A switch 691-2 that switches between supply and cutoff of the first negative power supply voltage AVEE1, and a switch 692-1 that switches between supply and cutoff of the second positive power supply voltage A VDD2 to each switch 64p of the voltage application circuit 64. It is provided with a switch 692-2 for switching between supply and cutoff of the second negative power supply voltage AVEE2 to each switch 64q of the voltage application circuit 64.

The switch control unit 62b includes each switch of the output control circuit 63, each switch of the signal selection circuit 14 provided on the display board 1, each switch 64p of the voltage application circuit 64 and each switch 64q, and each switch of the voltage changeover circuit 69. It controls 691-1,691-2,692-1,692-2.

Specifically, when the first positive power supply voltage A VDD1 is supplied to each switch 64p of the voltage application circuit 64 and the first negative power supply voltage AVEE1 is supplied to each switch 64q of the voltage application circuit 64, the switch control unit 62b closes and controls each switch 691-1,691-2 of the voltage switching circuit 69, and opens and controls each switch 692-1,692-2 of the voltage switching circuit 69.

Further, when the second positive power supply voltage A00572 is supplied to each switch 64p of the voltage application circuit 64 and the second negative power supply voltage AVEE2 is supplied to each switch 64q of the voltage application circuit 64, the switch control unit 62b , Each switch 691-1,691-2 of the voltage switching circuit 69 is open-controlled, and each switch 692-1,692-2 of the voltage switching circuit 69 is closed-controlled.

The processing unit 65b controls the driver IC 6d and performs short-circuit determination processing in the FOG mounting unit 5 in the shipping inspection of the display device 100d. The short-circuit determination process in this embodiment will be described later.

The register unit 66b stores various data in the short-circuit determination process of the FOG mounting unit 5 by the processing unit 65b. The various data stored in the register unit 66b include, for example, a current threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 66b may be numerical data or discrete values such as digital data.

Hereinafter, in the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5 will be described. FIG. 15 is a diagram showing an example of the short circuit determination processing procedure according to the third embodiment. FIG. 16 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the third embodiment.

In the present embodiment, the determination flag is "1", that is, between the short-circuit detection target connection terminals 53a in which the determination flag is "1" when there is a short-circuit detection target connection terminal 53a in which a short circuit has occurred. By performing a process of applying a second potential difference higher than the first potential, the short circuit between the short circuit detection target connection terminals 53a in which the determination flag is "1" is eliminated. This process is also referred to as "repair process" below.

The short-circuit determination process shown in FIG. 15 is started in a state where the inspection jig 200a is connected to the circuit board 2d in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. .. Further, at this time, it is assumed that all the switches of the voltage application circuit 64 are open-controlled, and the supply of the positive voltage or the negative voltage to all the short-circuit detection target connection terminals 53a of the FOG mounting unit 5 is cut off. Further, it is assumed that the switches 691-1 and 691-2 of the voltage switching circuit 69 are closed controlled and the switches 692-1 and 692-2 of the voltage switching circuit 69 are open controlled.

When the short-circuit determination processing start command is input, the processing unit 65b outputs the open control command for all the switches of the output control circuit 63 and the open control command for all the switches of the signal selection circuit 14 to the switch control unit 62b. (Step S401). As a result, the wiring between the video line drive circuit 61 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 is cut off, and the video signal line SGL of the display unit 11 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5 The wiring between them is cut off. The control state of the driver IC 6d at this time corresponds to the "first control state" in the present disclosure. The processing unit 65b acquires the current value at this time as the first current value I1 from the current detection unit 67, and stores it in the register unit 66b as the first current value information (step S402).

Subsequently, the processing unit 65b selects between any short-circuit detection target connection terminals 53a among the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5 (step S403). When the number of pixel rows is n, there are n-1 combinations of adjacent short-circuit detection target connection terminals 53a.

The processing unit 65b of the voltage application circuit 64 so that the first positive power supply voltage A VDD1 is applied to one of the selected adjacent short-circuit detection target connection terminals 53a and the first negative power supply voltage AVEE1 is applied to the other. The switch 64p and the switch 64q are closed and controlled (step S404). At this time, when the first positive power supply voltage A VDD1 is, for example, +5.5 V and the first negative power supply voltage AVEE1 is, for example, −5.5 V, the first applied between the adjacent short-circuit detection target connection terminals 53a. The potential difference is 11V. The states of the switches of the signal selection circuit 14, the video line drive circuit 61, the voltage application circuit 64, and the voltage switching circuit 69 in FIG. 14 indicate the state in which the process of step S404 has been performed. In the example shown in FIG. 14, an example is shown in which the short-circuit detection target connection terminal 53a (1, 2) shown in FIG. 16 is selected and the switch 641 and the switch 642 of the voltage application circuit 64 are closed-controlled. The control state of the driver IC 6d at this time corresponds to the "second control state" in the present disclosure. The processing unit 65b acquires the current value at this time as the second current value I2 from the current detection unit 67, and stores it in the register unit 66b as the second current value information (step S405).

Subsequently, the processing unit 65b reads the first current value information and the second current value information from the register unit 66b, and sets the difference | I1-I2 | between the first current value I1 and the second current value I2 as the current threshold value ΔIth. (| I1-I2 |> ΔIt) (step S406).

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is larger than the current threshold value ΔIt (step S406; Yes), the processing unit 65b short-circuits between the selected short-circuit detection target connection terminals 53a. Is determined to have occurred, and the determination flag of the register unit 66b between the short-circuit detection target connection terminals 53a is rewritten from "0" to "1" (step S407a). FIG. 16 shows an example in which a short circuit occurs between the connection terminals 53a (3, 4) to be detected as a short circuit.

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is equal to or less than the current threshold value ΔIth (step S406; No), the processing unit 65b short-circuits between the selected short-circuit detection target connection terminals 53a. If the determination flag of the register unit 66b between the short-circuit detection target connection terminals 53a is "1", the determination flag is rewritten from "1" to "0" (step). S407b).

Subsequently, the processing unit 65b determines a short circuit between all the adjacent connection terminals 53a for short circuit detection (1, 2, 3), (3, 4), ... (N-1, n). It is determined whether or not it has been completed (step S408).

If there is a short-circuit detection target connection terminal 53a that has not been determined to be short-circuited (step S408; No), the process returns to step S403 and the processes up to step S408 are repeated.

When the short-circuit determination has been completed between all the short-circuit detection target connection terminals 53a (step S408; Yes), the processing unit 65b refers to the information stored in the register unit 66b, and the determination flag is "1", that is, the short circuit is set. It is determined whether or not there is a short circuit detection target connection terminal 53a that has occurred (step S409).

If there is no short-circuit detection target connection terminal 53a where a short-circuit has occurred (step S409; Yes), the short-circuit determination process according to the third embodiment is terminated.

When there is a short-circuit detection target connection terminal 53a between the short-circuit detection target terminals 53a (step S409; No), the processing unit 65b determines whether or not the repaired flag is “0” (step S410). FIG. 16 shows an example in which the repaired flag is “0”.

When the repaired flag is "1" (step S410; No), the short-circuit determination process according to the third embodiment is terminated.

When the repaired flag is "0" (step S410; Yes), the processing unit 65b opens and controls each switch 691-1, 691-2 of the voltage switching circuit 69, and opens and controls each switch 692 of the voltage switching circuit 69. -1,692-2 is closed and controlled. As a result, the second positive power supply voltage A VDD2 is supplied to each switch 64p of the voltage application circuit 64, and the second negative power supply voltage AVEE2 is supplied to each switch 64q of the voltage application circuit 64. At this time, when the second positive electrode power supply voltage A VDD2 is, for example, + 10V and the second negative electrode power supply voltage AVEE2 is, for example, −10V, the second potential difference applied between the switch 64p and the switch 64q is 20V. ..

The processing unit 65b controls each switch 64p and each switch 64q of the voltage application circuit 64 so that the second potential difference is applied between the short-circuit detection target connection terminals 53a whose determination flag is “1” (step S411). .. The process in step S411 corresponds to the repair process described above.

After a lapse of a predetermined time, the processing unit 65b opens and controls all the switches of the voltage application circuit 64, closes and controls each of the switches 691-1 and 691-2 of the voltage switching circuit 69, and controls each of the voltage switching circuits 69. The switches 692-1,692-2 are open-controlled. After that, the processing unit 65b changes the repaired flag from "0" to "1" (step S412), returns to step S403, and performs the processing up to step S410 again.

In the configuration according to the third embodiment described above, by carrying out the short circuit determination processing procedure according to the third embodiment, it is detected that a short circuit has occurred between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5. be able to. Then, by reading the determination flag of the register unit 66b from the outside via the processing unit 65b, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53a of the FOG mounting unit 5. can.

Further, in the short-circuit determination process according to the third embodiment described above, the repair process is performed between the short-circuit detection target connection terminals 53a in which the short-circuit is generated in the FOG mounting unit 5. This makes it possible to reduce short-circuit defects in the FOG mounting unit 5 in the short-circuit determination process. Further, by reading the information of the register unit 66b from the outside via the processing unit 65b, the history of the repair process can be referred to.

In the present embodiment, even if the processes from step S403 to step S410 are re-executed, if there is a short-circuit detection target connection terminal 53a between the short-circuit detection target connection terminals 53a (step S409; No), in step S410. The repaired flag is determined to be "1" (step S410; No), and the short-circuit determination process according to the third embodiment is terminated. This makes it possible to exclude individuals whose short circuit is not resolved even if the repair process (step S411) is performed, but the present invention is not limited to this. For example, the repair process may be repeated until the short circuit between the short circuit detection target connection terminals 53a is resolved without providing the repaired flag, or the short circuit detection target connection terminal 53a may be performed even if the repair process is performed a plurality of times. When the short circuit between the two is not resolved, the short circuit determination process may be terminated.

According to this embodiment, it is possible to provide a display device 100d capable of improving quality.

(Embodiment 4)
FIG. 17 is a diagram showing a schematic configuration of a display device and an inspection jig according to the fourth embodiment. The same components as those in the first to third embodiments are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 17, an inspection jig 200c is connected to the circuit board 2e in the shipping inspection of the display device 100e.

The driver IC 6e FOG mounted on the circuit board 2e includes a video line drive circuit 61, a switch control unit 62c, an output control circuit 63, a first booster circuit 68-1, a second booster circuit 68-2, and a voltage. The generation unit 70 and the like are included.

The switch control unit 62c controls each switch of the output control circuit 63, each switch of the signal selection circuit 14 provided on the display board 1a, and each switch of the voltage supply circuit 15 provided on the display board 1a.

The voltage generation unit 70 includes a first voltage generation circuit 701 and a second voltage generation circuit 702. The second booster voltage A VDD2 is supplied from the first booster circuit 68-1 to the voltage generation unit 70, and the second negative electrode voltage AVEE2 is supplied from the second booster circuit 68-2.

The first voltage generation circuit 701 generates a positive voltage of 0 V or more supplied to the display board 1a.

The second voltage generation circuit 702 generates a negative voltage of 0 V or less supplied to the display board 1a.

The display board 1a includes a voltage supply circuit 15 in addition to the signal selection circuit 14.

The voltage supply circuit 15 includes switches 151, ..., 15n corresponding to the amplifier circuits 611, ..., 61n of the video line drive circuit 61, respectively. The voltage supply circuit 15 is connected to the short-circuit detection target connection terminal 53a connected to the amplifier circuit that supplies the image signal Vsig to the pixels Pix in the odd row among the amplifier circuits 611, ..., 61n of the video line drive circuit 61. On the other hand, the image signal Vsig is supplied to the switch 15p (p is a positive odd number of n or less) for applying the positive voltage supplied from the first voltage generation circuit 701 of the voltage generation unit 70, and the pixel Pix in the even row. A switch 15q (q is a positive even number of n or less) that applies a negative voltage supplied from the second voltage generation circuit 702 of the voltage generation unit 70 to the short circuit detection target connection terminal 53a connected to the amplifier circuit. ,including.

The inspection jig 200c is connected to the circuit board 2e in the shipping inspection of the display device 100e. The inspection jig 200c includes a power supply unit 201, a processing unit 202b, a register unit 203b, and a current detection unit 204.

The processing unit 202b controls the driver IC 6e and performs a short-circuit determination process in the FOG mounting unit 5a in the shipping inspection of the display device 100e. The short-circuit determination process in this embodiment will be described later.

The register unit 203b stores various data in the short-circuit determination process of the FOG mounting unit 5a by the processing unit 202b. The various data stored in the register unit 203b include, for example, a current threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 203b may be numerical data or discrete values such as digital data.

Hereinafter, in the above-described configuration, a procedure for performing a short-circuit determination process in the FOG mounting unit 5a will be described. FIG. 18 is a diagram showing an example of the short circuit determination processing procedure according to the fourth embodiment. FIG. 19 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the fourth embodiment.

In the present embodiment, when the determination flag is "1", that is, when a short circuit occurs between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a, a second potential difference higher than the first potential is applied. The short circuit between the short circuit detection target connection terminals 53a in the FOG mounting unit 5a is eliminated by carrying out the processing. This process is hereinafter referred to as "repair process".

The short-circuit determination process shown in FIG. 18 is started in a state where the inspection jig 200c is connected to the circuit board 2e in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. .. Further, it is assumed that the voltage generation unit 70 is controlled in the FOG mounting unit 5a so as to apply a predetermined first potential difference between the adjacent short-circuit detection target connection terminals 53a. Specifically, the first voltage generation circuit 701 is controlled to output a DC voltage of, for example, + 5V, and the second voltage generation circuit 702 is controlled to output a DC voltage of, for example, -5V. .. At this time, it is assumed that all the switches of the voltage supply circuit 15 are open-controlled and the supply of the positive voltage or the negative voltage to all the short-circuit detection target connection terminals 53a of the FOG mounting unit 5a is cut off.

When the short-circuit determination processing start command is input, the processing unit 202b outputs an open control command for all the switches of the output control circuit 63 and an open control command for all the switches of the signal selection circuit 14 to the switch control unit 62c. (Step S501). As a result, the wiring between the video line drive circuit 61 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a is cut off, and the video signal line SGL of the display unit 11 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a The wiring between them is cut off. The control state of the driver IC6e at this time corresponds to the "first control state" in the present disclosure.

The processing unit 202b acquires the current value at this time as the first current value I1 from the current detection unit 204, and stores it in the register unit 203b as the first current value information (step S502).

Subsequently, the processing unit 202b outputs a closing control command for all the switches of the voltage supply circuit 15 to the switch control unit 62c (step S503). As a result, the wiring between the voltage generation unit 70 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a is connected. The states of the switches of the signal selection circuit 14, the video line drive circuit 61, and the voltage supply circuit 15 in FIG. 17 indicate the state in which the process of step S503 has been performed. The control state of the driver IC6e at this time corresponds to the "second control state" in the present disclosure. At this time, the first potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5a is 10V. The processing unit 202b acquires the current value at this time as the second current value I2 from the current detection unit 204, and stores it in the register unit 203b as the second current value information (step S504).

Subsequently, the processing unit 202b reads the first current value information and the second current value information from the register unit 203b, and sets the difference | I1-I2 | between the first current value I1 and the second current value I2 as the current threshold value ΔIth. (| I1-I2 |> ΔIt) (step S505).

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is larger than the current threshold value ΔIt (step S505; Yes), the processing unit 202b is the target for short-circuit detection of one or more of the FOG mounting unit 5a. It is determined that a short circuit has occurred between the connection terminals 53a, and the determination flag of the register unit 203b is rewritten from "0" to "1" (step S506a). FIG. 19 shows an example in which a short circuit occurs between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a.

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is equal to or less than the current threshold value ΔIth (step S505; No), the processing unit 202b is connected to any of the FOG mounting units 5a for short-circuit detection. If it is determined that no short circuit has occurred between the terminals 53a and the determination flag of the register unit 203b is "1", the determination flag is rewritten from "1" to "0" (step S506b).

Subsequently, the processing unit 202b refers to the information stored in the register unit 203b, and the determination flag is "0", that is, a short circuit has occurred between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a. It is determined whether or not there is any (step S507).

If no short circuit has occurred between one or more short-circuit detection target connection terminals 53a of the FOG mounting unit 5a (step S507; Yes), the short-circuit determination process according to the fourth embodiment is terminated.

When a short circuit has occurred between one or more short-circuit detection target connection terminals 53a of the FOG mounting unit 5a (step S507; No), the processing unit 202b determines whether or not the repaired flag is "0". Determination (step S508). FIG. 19 shows an example in which the repaired flag is “0”.

When the repaired flag is "1" (step S508; No), the short-circuit determination process according to the fourth embodiment is terminated.

When the repaired flag is "0" (step S508; Yes), the processing unit 202b is larger than the first potential difference between the short-circuit detection target connection terminals 53a adjacent to each other in the FOG mounting unit 5a with respect to the voltage generation unit 70. The second potential difference is controlled to be applied (step S509). Specifically, the first voltage generation circuit 701 controls to output a DC voltage of, for example, + 8V, and the second voltage generation circuit 702 controls to output a DC voltage of, for example, −8V. At this time, the second potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting portion 5a is 16V.

After a lapse of a predetermined time, the processing unit 202b applies the first potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5a, and rewrites the repaired flag from "0" to "1" (step S510). ), An open control command for all switches of the voltage supply circuit 15 is output to the switch control unit 62c (step S511). After that, the process returns to step S502 and the processes up to step S508 are performed again.

In the configuration according to the fourth embodiment described above, by carrying out the short circuit determination processing procedure according to the fourth embodiment, it is detected that a short circuit has occurred between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a. be able to. Then, by reading the determination flag of the register unit 203b from the outside via the processing unit 202b, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53a of the FOG mounting unit 5a. can.

Further, in the short-circuit determination process according to the fourth embodiment described above, the repair process is performed when a short circuit occurs between one or more short-circuit detection target connection terminals 53a of the FOG mounting unit 5a. This makes it possible to reduce short-circuit defects in the FOG mounting unit 5a in the short-circuit determination process. Further, by reading the information of the register unit 203b from the outside via the processing unit 202b, the history of the repair process can be referred to.

Further, as in the second embodiment, since the operations of the amplifier circuits 611, ..., 61n of the video line drive circuit 61 can be stopped, the steady state included in the first current value I1 and the second current value I2. The circuit current can be reduced, and the accuracy of the threshold value determination when performing the short circuit determination is improved.

In the present embodiment, even if the processes from step S502 to step S508 are re-executed, if a short circuit occurs (step S507; No), the repaired flag is determined to be "1" in step S508. (Step S508; No), and the short-circuit determination process according to the fourth embodiment is terminated. This makes it possible to exclude individuals whose short circuit is not resolved even if the repair process (step S509) is performed, but the present invention is not limited to this. For example, the repair process may be repeated until the short circuit between the short circuit detection target connection terminals 53a is resolved without providing the repaired flag, or the short circuit detection target connection terminal 53a may be performed even if the repair process is performed a plurality of times. When the short circuit between the two is not resolved, the short circuit determination process may be terminated.

(Modified Example of Embodiment 4)
FIG. 20 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modified example of the fourth embodiment. The same components as those in the fourth embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 20, the inspection jig 200a is connected to the circuit board 2f in the shipping inspection of the display device 100f.

The driver IC 6f mounted on the circuit board 2f by FOG includes a video line drive circuit 61, a switch control unit 62c, an output control circuit 63, a processing unit 65c, a register unit 66c, a current detection unit 67, and a first step-up. It includes a circuit 68-1, a second booster circuit 68-2, and a voltage generation unit 70.

The processing unit 65c is a component corresponding to the processing unit 202b in the inspection jig 200c of the fourth embodiment, and controls the driver IC 6f and performs a short-circuit determination process in the FOG mounting unit 5a in the shipping inspection of the display device 100f.

The register unit 66c is a component unit corresponding to the register unit 203b in the inspection jig 200c of the fourth embodiment, and stores various data in the short-circuit determination process of the FOG mounting unit 5a by the processing unit 65c. The various data stored in the register unit 66c include, for example, a current threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 66c may be numerical data or discrete values such as digital data.

The inspection jig 200a is connected to the circuit board 2f in the shipping inspection of the display device 100f. The inspection jig 200a includes a power supply unit 201.

In the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5a is the same as the short-circuit determination process procedure according to the fourth embodiment. Specifically, in the short-circuit determination processing procedure according to the fourth embodiment, the processing unit 202b is read as the processing unit 65c, the register unit 203b is read as the register unit 66c, and the current detection unit 204 is read as the current detection unit 67. It is possible to realize the same processing procedure as the short-circuit determination processing procedure according to the fourth embodiment.

In the configuration according to the modification of the fourth embodiment described above, a short circuit is generated between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a by carrying out the short circuit determination processing procedure according to the fourth embodiment. Can be detected. Then, by reading the determination flag of the register unit 66c from the outside via the processing unit 65c, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53a of the FOG mounting unit 5a. can.

Further, in the short-circuit determination process according to the fourth embodiment described above, the repair process is performed between the short-circuit detection target connection terminals 53a in which the short-circuit is generated in the FOG mounting unit 5a. This makes it possible to reduce short-circuit defects in the FOG mounting unit 5a in the short-circuit determination process. Further, by reading the information of the register unit 66c from the outside via the processing unit 65c, the history of the repair process can be referred to.

Further, as in the fourth embodiment, since the operations of the amplifier circuits 611, ..., 61n of the video line drive circuit 61 can be stopped, the steady state included in the first current value I1 and the second current value I2. The circuit current can be reduced, and the accuracy of the threshold value determination when performing the short circuit determination is improved.

According to this embodiment, it is possible to provide display devices 100e and 100f that can improve the quality.

(Embodiment 5)
FIG. 21 is a diagram showing a schematic configuration of a display device and an inspection jig according to the fifth embodiment. The same components as those in the first to fourth embodiments are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 21, an inspection jig 200d is connected to the circuit board 2g in the shipping inspection of the display device 100g.

The driver IC 6g mounted on the circuit board 2g by FOG includes a video line drive circuit 61, a switch control unit 62c, and an output control circuit 63.

The configuration of the voltage readout circuit 15a is the same as that of the voltage supply circuit 15 of the fourth embodiment described above. In the present embodiment, each switch 15p is a short-circuit detection target connected to an amplifier circuit that supplies an image signal Vsig to an odd-row pixel Pix among the amplifier circuits 611, ..., 61n of the video line drive circuit 61. This is a switch for detecting the voltage of the connection terminal 53a by the processing unit 202c of the inspection jig 200d described later. Further, each switch 15q is for detecting the voltage of the short-circuit detection target connection terminal 53a connected to the amplifier circuit that supplies the image signal Vsig to the even-numbered pixels Pix by the processing unit 202c of the inspection jig 200d described later. It is a switch.

The inspection jig 200d is connected to the circuit board 2g in the shipping inspection of the display device 100g. The inspection jig 200d includes a power supply unit 201, a processing unit 202c, and a register unit 203c.

The processing unit 202c controls the driver IC 6g and performs a short-circuit determination process in the FOG mounting unit 5a in the shipping inspection of the display device 100g. The short-circuit determination process in this embodiment will be described later.

The register unit 203c stores various data in the short-circuit determination process of the FOG mounting unit 5a by the processing unit 202c. The various data stored in the register unit 203c include, for example, a voltage threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 203c may be numerical data or discrete values such as digital data.

Hereinafter, in the above-described configuration, a procedure for performing a short-circuit determination process in the FOG mounting unit 5a will be described. FIG. 22 is a diagram showing an example of the short circuit determination processing procedure according to the fifth embodiment. FIG. 23 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the fifth embodiment.

The short-circuit determination process shown in FIG. 22 is started in a state where the inspection jig 200d is connected to the circuit board 2g in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. ..

When the short-circuit determination processing start command is input, the processing unit 202c gives the switch control unit 62c a closing control command for all the switches of the output control circuit 63, an open control command for all the switches of the signal selection circuit 14, and a voltage read-out. A close control command for all switches in the circuit 15a is output (step S601). As a result, the wiring between the video line drive circuit 61 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a is connected, and the video signal line SGL of the display unit 11 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a are connected. The wiring between them is cut off, and the wiring between the voltage generation unit 70 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a is connected. The control state of the driver IC 6g at this time corresponds to the "first control state" in the present disclosure. The states of the switches of the signal selection circuit 14, the video line drive circuit 61, and the voltage readout circuit 15a in FIG. 21 indicate the state in which the process of step S601 has been performed.

Subsequently, the processing unit 202c controls the video line drive circuit 61 to apply a predetermined potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5a (step S602). Specifically, each amplifier that supplies an image signal Vsig to an odd-row pixel Pix is controlled so that a DC voltage of, for example, + 5V is output, and an image signal Vsig is supplied to an even-row pixel Pix. It is controlled so that a DC voltage of, for example, -5V is output from the circuit. At this time, the potential difference between the adjacent short-circuit detection target connection terminals 53a in the FOG mounting portion 5a is 10V. The control state of the driver IC 6g at this time corresponds to the "second control state" in the present disclosure.

The processing unit 202c inputs a first voltage value V1 which is a voltage value of a short-circuit detection target connection terminal 53a connected to an amplifier circuit that supplies an image signal Vsig to an odd-row pixel Pix, which is input via each switch 15p. A short-circuit detection target connection terminal that is detected and stored in the register unit 203c as the first voltage value information, and is connected to an amplifier circuit that supplies an image signal Vsig to an even-row pixel Pix, which is input via each switch 15q. The second voltage value V2, which is the voltage value of 53a, is detected and stored in the register unit 203c as the second voltage value information (step S603).

Subsequently, the processing unit 202c reads the first voltage value information and the second voltage value information from the register unit 203c, and sets the difference | V1-V2 | between the first voltage value V1 and the second voltage value V2 as the voltage threshold value ΔVth. (| V1-V2 | <ΔVth) (step S604).

When the difference | V1-V2 | between the first voltage value V1 and the second voltage value V2 is smaller than the voltage threshold value ΔVth (step S604; Yes), the processing unit 202c is the target for short-circuit detection of one or more of the FOG mounting unit 5a. It is determined that a short circuit has occurred between the connection terminals 53a, the determination flag of the register unit 203c is rewritten from "0" to "1" (step S605), and the short circuit determination process according to the fifth embodiment is completed. FIG. 23 shows an example in which a short circuit occurs between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a.

When the difference | V1-V2 | between the first voltage value V1 and the second voltage value V2 is equal to or greater than the voltage threshold value ΔVth (step S604; No), the processing unit 202c is connected to any of the FOG mounting units 5a for short-circuit detection. It is determined that no short circuit has occurred between the terminals 53a, and the short circuit determination process according to the fifth embodiment is terminated.

In the configuration according to the fifth embodiment described above, by carrying out the short circuit determination processing procedure according to the fifth embodiment, it is detected that a short circuit has occurred between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a. be able to. Then, by reading the determination flag of the register unit 203c from the outside via the processing unit 202c, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53a of the FOG mounting unit 5a. can.

(Modification 1 of Embodiment 5)
FIG. 24 is a diagram showing an example of the short-circuit determination processing procedure according to the first modification of the fifth embodiment. FIG. 25 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the first modification of the fifth embodiment.

The short-circuit determination process shown in FIG. 24 is started in a state where the inspection jig 200d is connected to the circuit board 2g in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. ..

When the short-circuit determination processing start command is input, the processing unit 202c gives the switch control unit 62c a closing control command for all the switches of the output control circuit 63, an open control command for all the switches of the signal selection circuit 14, and a voltage read-out. A close control command for all switches in the circuit 15a is output (step S701). As a result, the wiring between the video line drive circuit 61 and the short-circuit detection target connection terminal 53 of the FOG mounting unit 5a is connected, and the video signal line SGL of the display unit 11 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a are connected. The wiring between them is cut off, and the wiring between the voltage generation unit 70 and the short-circuit detection target connection terminal 53a of the FOG mounting unit 5a is connected. The control state of the driver IC 6g at this time corresponds to the "first control state" in the present disclosure. The states of the switches of the signal selection circuit 14, the video line drive circuit 61, and the voltage readout circuit 15a in FIG. 21 indicate the state in which the process of step S701 has been performed.

Subsequently, the processing unit 202c selects between any short-circuit detection target connection terminals 53a among the adjacent short-circuit detection target connection terminals 53a in the FOG mounting unit 5a (step S702). When the number of pixel rows is n, there are n-1 combinations of adjacent short-circuit detection target connection terminals 53a.

Subsequently, the processing unit 202c controls to apply a predetermined potential difference between the selected short-circuit detection target connection terminals 53a (step S703). Specifically, it is controlled so that a DC voltage of, for example, + 5V is output from an amplifier circuit that supplies an image signal Vsig to pixels Pix in an odd row between the selected short-circuit detection target connection terminals 53a, and the selected short-circuit detection is detected. Between the target connection terminals 53a, control is performed so that, for example, a DC voltage of -5V is output from an amplifier circuit that supplies an image signal Vsig to even-row pixels Pix. At this time, the potential difference between the selected short-circuit detection target connection terminals 53a is 10V. The control state of the driver IC 6g at this time corresponds to the "second control state" in the present disclosure.

The processing unit 202c detects the first voltage value V1, which is the voltage value of one of the selected adjacent short-circuit detection target connection terminals 53a, which is input via the switch 15p, and is used in the register unit 203c as the first voltage value information. Along with storing, the second voltage value V2, which is the other voltage value of the selected adjacent short-circuit detection target connection terminals 53a input via the switch 15q, is detected and stored in the register unit 203c as the second voltage value information. (Step S704).

Subsequently, the processing unit 202c reads out the first voltage value information and the second voltage value information between the selected short-circuit detection target connection terminals 53a from the register unit 203c, and sets the first voltage value V1 and the second voltage value V2. The difference | V1-V2 | is compared with the voltage threshold ΔVth (| V1-V2 | <ΔVth) (step S705).

When the difference | V1-V2 | between the first voltage value V1 and the second voltage value V2 is smaller than the voltage threshold value ΔVth (step S705; Yes), the processing unit 202c short-circuits between the selected short-circuit detection target connection terminals 53a. Is determined to have occurred, and the determination flag of the register unit 203c is rewritten from "0" to "1" (step S706). FIG. 25 shows an example in which a short circuit occurs between the connection terminals 53a (3, 4) to be detected as a short circuit.

When the difference | V1-V2 | between the first voltage value V1 and the second voltage value V2 is equal to or greater than the voltage threshold value ΔVth (step S705; No), the processing unit 202c short-circuits between the selected short-circuit detection target connection terminals 53a. Is determined not to occur.

Subsequently, the processing unit 202c determines a short circuit between all the adjacent short circuit detection target connection terminals 53a (1,2), (2,3), (3,4), ... (N-1, n). It is determined whether or not it has been completed (step S707).

If there is a short-circuit detection target connection terminal 53a that has not been determined to be short-circuited (step S707; No), the process returns to step S702 and the processes up to step S707 are repeated.

If the short-circuit determination has been completed between all the short-circuit detection target connection terminals 53a (step S707; Yes), the short-circuit determination process according to the first modification of the fifth embodiment is terminated.

In the configuration according to the above-described fifth embodiment, by carrying out the short-circuit determination processing procedure according to the first modification of the fifth embodiment, the short-circuit detection target connection terminal 53a where the short-circuit has occurred in the FOG mounting unit 5a is specified. be able to. Then, by reading the information of the register unit 203c from the outside via the processing unit 202c, it is possible to identify between the short circuit detection target connection terminals 53a in which the short circuit has occurred in the FOG mounting unit 5a.

(Modification 2 of Embodiment 5)
FIG. 26 is a diagram showing a schematic configuration of a display device and an inspection jig according to the second modification of the fifth embodiment. The same components as those in the fifth embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 26, the inspection jig 200a is connected to the circuit board 2h in the shipping inspection of the display device 100h.

The driver IC 6h mounted on the circuit board 2h by FOG includes a video line drive circuit 61, a switch control unit 62c, an output control circuit 63, a processing unit 65d, and a register unit 66d.

The processing unit 65d is a component corresponding to the processing unit 202c in the inspection jig 200d of the fifth embodiment, and controls the driver IC 6h and performs a short-circuit determination process in the FOG mounting unit 5a in the shipping inspection of the display device 100h.

The register unit 66d is a component unit corresponding to the register unit 203c in the inspection jig 200d of the fifth embodiment, and stores various data in the short-circuit determination process of the FOG mounting unit 5a by the processing unit 65d. The various data stored in the register unit 66d include, for example, a voltage threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 66d may be numerical data or discrete values such as digital data.

The inspection jig 200a is connected to the circuit board 2h in the shipping inspection of the display device 100h. The inspection jig 200a includes a power supply unit 201.

In the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5a is the same as the short-circuit determination process procedure according to the fifth embodiment and the short-circuit determination process procedure according to the first modification of the fifth embodiment. Specifically, in the short-circuit determination processing procedure according to the fifth embodiment and the short-circuit determination processing procedure according to the modified example 1 of the fifth embodiment, the processing unit 202c is read as the processing unit 65d, and the register unit 203c is read as the register unit 66d. Therefore, the same processing procedure as the short-circuit determination processing procedure according to the fifth embodiment or the short-circuit determination processing procedure according to the modified example 1 of the fifth embodiment can be realized.

In the configuration according to the second modification of the fifth embodiment described above, by carrying out the short circuit determination processing procedure according to the fifth embodiment, a short circuit occurs between one or more short circuit detection target connection terminals 53a of the FOG mounting unit 5a. It can be detected that it is present. Then, by reading the determination flag of the register unit 66d from the outside via the processing unit 65d, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53a of the FOG mounting unit 5a. can.

Further, in the configuration according to the modification 2 of the embodiment 5 described above, by carrying out the short circuit determination processing procedure according to the modification 1 of the embodiment 5, a short circuit detection target connection in which a short circuit occurs in the FOG mounting unit 5a is performed. It is possible to specify between the terminals 53a. Then, by reading the information of the register unit 66d from the outside via the processing unit 65d, it is possible to identify between the short-circuit detection target connection terminals 53a in which the short circuit has occurred in the FOG mounting unit 5a.

According to this embodiment, it is possible to provide display devices 100g and 100h that can improve the quality.

(Embodiment 6)
FIG. 27 is a schematic diagram showing a schematic configuration of the display device according to the sixth embodiment.

The display device 100i includes a display board 1b, a first circuit board 3a, and a second circuit board 4a.

In the present embodiment, the display substrate 1b is composed of a glass substrate. The display board 1b is provided with a display unit 11 in which pixels Pix (see FIG. 2) are arranged in the X direction and the Y direction in the drawing.

In the present embodiment, the display device 100i is a display device in which the display unit 11 and the touch sensor 16 are integrated. Specifically, a part of the members such as the electrode and the substrate of the display unit 11 is also used as the electrode and the substrate of the touch sensor 16.

The display unit 11 may be configured to include, for example, a liquid crystal display element as a display element. Further, the display unit 11 may be configured to include, for example, an organic EL element (organic light emitting diode) as a light emitting element. The present disclosure is not limited by the aspect of the display unit 11.

The display board 1b is provided with a scanning signal line for supplying a scanning signal to the pixel circuit of the display unit 11 and a video signal line for supplying a video signal to the pixel circuit of the display unit 11.

Further, the display board 1b is provided with an electrode COML to which a drive voltage Vcomdc for display is supplied at the time of display operation and a drive signal Vcom for touch detection is supplied at the time of touch detection. The electrode COML functions as a self-capacitance type touch detection electrode at the time of touch detection. Hereinafter, the electrode COML is also referred to as a “detection electrode COML”.

As a control unit that controls the operation of the display unit 11, a drive circuit that supplies various signals to the pixel circuit, a controller that generates timing signals to be supplied to the drive circuit, and the like are provided.

For example, a scanning line drive circuit or the like that supplies a scanning signal to the scanning signal line of the display unit 11 can be arranged on the display board 1b.

In the present embodiment, the first circuit board 3a is composed of a flexible wiring board. The driver IC 7 is mounted on the first circuit board 3a. The driver IC 7 is, for example, a video line drive circuit that supplies a video signal to the video signal line of the display unit 11, and a detection electrode drive circuit that supplies a drive voltage Vcomdc for display or a drive signal Vcom for touch detection to the detection electrode COML. It is a semiconductor chip in which etc. are integrated. The driver IC 7 is COF mounted on the first circuit board 3a.

In the present embodiment, the second circuit board 4a is composed of a flexible wiring board. Circuit elements such as a power supply circuit that generates various reference potentials, a signal processing circuit that processes a video signal, and a frame memory can be arranged on the second circuit board 4a.

At the end of the display board 1b, terminals (pads) for connecting to each wiring on the first circuit board 3a side are provided. Further, at one end of the first circuit board 3a, a terminal (pad) for connecting to each wiring on the display board 1b side is provided. The first circuit board 3a is FOG mounted on the display board 1b. As a result, each wiring on the display board 1b side and each wiring on the first circuit board 3a side corresponding to each wiring on the display board 1b side are electrically connected.

At the end of the second circuit board 4a, terminals (pads) for connecting to each wiring on the first circuit board 3a side are provided. Further, at the other end of the first circuit board 3a, terminals (pads) for connecting to each wiring on the second circuit board 4a side are provided. The first circuit board 3a is FOF-mounted on the second circuit board 4a. As a result, each wiring on the second circuit board 4a side and each wiring on the first circuit board 3a side corresponding to each wiring on the second circuit board 4a side are electrically connected.

The first circuit board 3a and the second circuit board 4a may be configured by one flexible wiring board. In this case, circuit elements other than the driver IC 7 may be mounted on the flexible wiring board, or circuit elements other than the driver IC 7 may not be mounted. Hereinafter, when it is not necessary to distinguish between the first circuit board 3a and the second circuit board 4a, the first circuit board 3a and the second circuit board 4a are regarded as a circuit board 2i composed of one flexible wiring board. explain.

The display board 1b corresponds to the "first board" in the present disclosure. Further, the circuit board 2i corresponds to the "second board" in the present disclosure.

FIG. 28 is a diagram showing a schematic configuration of a display device and an inspection jig according to the sixth embodiment. The same components as those in the first to fifth embodiments are designated by the same reference numerals, and the description thereof will be omitted. As shown in FIG. 28, the inspection jig 200e is connected to the circuit board 2i in the shipping inspection of the display device 100i.

The driver IC 7 FOG mounted on the circuit board 2i includes a detection electrode drive circuit 71, a switch control unit 72, an output control circuit 73, a first booster circuit 74-1 and a second booster circuit 74-2, and a voltage. The generation unit 75 and the like are included. The detection electrode drive circuit 71 corresponds to the "drive circuit" in the present disclosure.

When touch detection is performed, the detection electrode drive circuit 71 generates and outputs individual drive signals Vcom for touch detection to a plurality of detection electrodes COML provided on the display board 1b. The detection electrode drive circuit 71 includes m amplifier circuits 711, ..., 71m corresponding to the detection electrode COML in the m row (m is a positive integer). In the detection electrode drive circuit 71, the first positive power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201 of the inspection jig 200e.

The output control circuit 73 switches between connection and disconnection between each amplifier circuit 711, ..., 71m of the detection electrode drive circuit 71 and each connection terminal 53 of the FOG mounting unit 5b. The output control circuit 73 includes switches 731, ..., 73m corresponding to the amplifier circuits 711, ..., 71m of the detection electrode drive circuit 71, respectively. In the present embodiment, the connection terminals 53 connected to the amplifier circuits 711, ..., 71m of the detection electrode drive circuit 71 via the output control circuit 73 are targeted for detecting short-circuit defects. Hereinafter, the connection terminal 53 for which a short circuit defect is detected in the present embodiment is referred to as a “short circuit detection target connection terminal 53b”.

The switch control unit 72 controls each switch of the output control circuit 73 and each switch of the voltage supply circuit 17 provided on the display board 1b.

The first booster circuit 74-1 boosts the first positive electrode power supply voltage A VDD1 supplied from the power supply unit 201 of the inspection jig 200e to generate the second positive electrode voltage A VDD2. The second positive electrode voltage A VDD2 is, for example, + 10V.

The second booster circuit 74-2 boosts the first negative electrode power supply voltage AVEE1 supplied from the power supply unit 201 of the inspection jig 200e to generate the second negative electrode voltage AVEE2. The second negative electrode voltage AVEE2 is, for example, −10 V.

The present disclosure is not limited by the voltages of the second positive electrode power supply voltage A VDD2 and the second negative electrode power supply voltage AVEE2.

The voltage generation unit 75 includes a first voltage generation circuit 751 and a second voltage generation circuit 752. The second booster voltage A VDD2 is supplied from the first booster circuit 74-1 to the voltage generation unit 75, and the second negative electrode voltage AVEE2 is supplied from the second booster circuit 74-2.

The first voltage generation circuit 751 generates a positive voltage of 0 V or more supplied to the display board 1b.

The second voltage generation circuit 752 generates a negative voltage of 0 V or less supplied to the display board 1b.

The display board 1b includes a voltage supply circuit 17.

The voltage supply circuit 17 includes switches 171, ..., 17m corresponding to the amplifier circuits 711, ..., 71m of the detection electrode drive circuit 71, respectively. The voltage supply circuit 17 is an amplifier that supplies a drive voltage Vcomdc for display or a drive signal Vcom for touch detection to the detection electrode COML in an odd row among the amplifier circuits 711, ..., 71 m of the detection electrode drive circuit 71. A switch 17p (p is a positive odd number of m or less) that applies a positive voltage supplied from the first voltage generation circuit 751 of the voltage generation unit 75 to the short circuit detection target connection terminal 53b connected to the circuit. The second voltage generation circuit 752 of the voltage generation unit 75 with respect to the short circuit detection target connection terminal 53b connected to the amplifier circuit that supplies the drive voltage Vcomdc for display or the drive signal Vcom for touch detection to the detection electrodes COML in an even row. Includes a switch 17q (q is a positive even number of m or less) that applies a negative voltage supplied from.

The inspection jig 200e is connected to the circuit board 2i in the shipping inspection of the display device 100i. The inspection jig 200e includes a power supply unit 201, a processing unit 202d, a register unit 203d, and a current detection unit 204.

The processing unit 202d controls the driver IC 7 and performs short-circuit determination processing in the FOG mounting unit 5b in the shipping inspection of the display device 100i. The short-circuit determination process in this embodiment will be described later.

The register unit 203d stores various data in the short-circuit determination process of the FOG mounting unit 5b by the processing unit 202d. The various data stored in the register unit 203d include, for example, a current threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 203d may be numerical data or discrete values such as digital data.

Hereinafter, in the above-described configuration, a procedure for performing a short-circuit determination process in the FOG mounting unit 5b will be described. FIG. 29 is a diagram showing an example of the short circuit determination processing procedure according to the sixth embodiment. FIG. 30 is a diagram showing an example of information stored in the register unit in the short circuit determination process according to the sixth embodiment.

In the present embodiment, when the determination flag is "1", that is, when a short circuit occurs between one or more short-circuit detection target connection terminals 53b of the FOG mounting unit 5b, a second potential difference higher than the first potential is applied. This process is performed to eliminate the short circuit between the short circuit detection target connection terminals 53b in the FOG mounting unit 5b. This process is hereinafter referred to as "repair process".

The short-circuit determination process shown in FIG. 29 is started in a state where the inspection jig 200e is connected to the circuit board 2i in advance and the first positive electrode power supply voltage A VDD1 and the first negative electrode power supply voltage AVEE1 are supplied from the power supply unit 201. .. Further, at this time, it is assumed that all the switches of the voltage supply circuit 17 are open-controlled and the supply of the positive voltage or the negative voltage to all the short-circuit detection target connection terminals 53b of the FOG mounting unit 5b is cut off.

When the short-circuit determination processing start command is input, the processing unit 202d outputs the open control command for all the switches of the output control circuit 73 and the close control command for all the switches of the voltage supply circuit 17 to the switch control unit 72. (Step S801). As a result, the wiring between the detection electrode drive circuit 71 and the short-circuit detection target connection terminal 53b of the FOG mounting unit 5b is cut off, and the wiring between the voltage generation unit 75 and the short-circuit detection target connection terminal 53b of the FOG mounting unit 5b. Is connected. The states of the switches of the detection electrode drive circuit 71 and the voltage supply circuit 17 in FIG. 28 indicate the state in which the process of step S801 has been performed.

Subsequently, the processing unit 202d controls the voltage generation unit 75 so that the potential difference between the adjacent short-circuit detection target connection terminals 53b in the FOG mounting unit 5b becomes substantially zero (step S802). Specifically, the first voltage generation circuit 751 controls so that a DC voltage of, for example, 0 V is output, and the second voltage generation circuit 752 controls so that a DC voltage of, for example, 0 V is output. At this time, the potential difference between the adjacent short-circuit detection target connection terminals 53b in the FOG mounting portion 5b is 0V. The control state of the driver IC 7 at this time corresponds to the "first control state" in the present disclosure. The processing unit 202d acquires the current value at this time as the first current value I1 from the current detection unit 204, and stores it in the register unit 203d as the first current value information (step S803).

Further, the processing unit 202d controls the voltage generation unit 75 to apply a predetermined first potential difference between the adjacent short-circuit detection target connection terminals 53b in the FOG mounting unit 5b (step S804). Specifically, the first voltage generation circuit 751 is controlled to output a DC voltage of, for example, + 5V, and the second voltage generation circuit 752 is controlled to output a DC voltage of, for example, −5V. At this time, the first potential difference between the adjacent short-circuit detection target connection terminals 53b in the FOG mounting portion 5b is 10V. The control state of the driver IC 7 at this time corresponds to the "second control state" in the present disclosure. The processing unit 202d acquires the current value at this time as the second current value I2 from the current detection unit 204, and stores it in the register unit 203d as the second current value information (step S805).

The above-mentioned processes of steps S802 and S803 and the processes of steps S804 and S805 can be interchanged. That is, there may be an embodiment in which the processing of step S804 and step S805 is performed, and then the processing of step S802 and step S803 is performed. The present disclosure is not limited by the order of implementation of the processes of steps S802 and S803 and the processes of steps S804 and S805.

Subsequently, the processing unit 202d reads the first current value information and the second current value information from the register unit 203d, and sets the difference | I1-I2 | between the first current value I1 and the second current value I2 as the current threshold value ΔIth. (| I1-I2 |> ΔIt) (step S806).

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is larger than the current threshold value ΔIt (step S806; Yes), the processing unit 202d is the target for short-circuit detection of one or more of the FOG mounting unit 5b. It is determined that a short circuit has occurred between the connection terminals 53b, and the determination flag of the register unit 203d is rewritten from "0" to "1" (step S807a). FIG. 30 shows an example in which a short circuit occurs between one or more short circuit detection target connection terminals 53b of the FOG mounting unit 5b.

When the difference | I1-I2 | between the first current value I1 and the second current value I2 is equal to or less than the current threshold value ΔIth (step S806; No), the processing unit 202d is connected to any of the FOG mounting units 5b for short-circuit detection. If it is determined that no short circuit has occurred between the terminals 53b and the determination flag of the register unit 203d between the short circuit detection target connection terminals 53b is "1", the determination flag is changed from "1" to "1". Rewrite to "0" (step S807b).

Subsequently, the processing unit 202d refers to the information stored in the register unit 203d, and the determination flag is "0", that is, a short circuit has occurred between one or more short circuit detection target connection terminals 53b of the FOG mounting unit 5b. It is determined whether or not there is any (step S808).

If no short circuit has occurred between one or more short-circuit detection target connection terminals 53b of the FOG mounting unit 5b (step S808; Yes), the short-circuit determination process according to the sixth embodiment is terminated.

When a short circuit has occurred between one or more short-circuit detection target connection terminals 53b of the FOG mounting unit 5b (step S808; No), the processing unit 202d determines whether or not the repaired flag is "0". Determination (step S809). FIG. 30 shows an example in which the repaired flag is “0”.

When the repaired flag is "1" (step S809; No), the short-circuit determination process according to the sixth embodiment is terminated.

When the repaired flag is "0" (step S809; Yes), the processing unit 202d is larger than the first potential difference between the short-circuit detection target connection terminals 53b adjacent to each other in the FOG mounting unit 5b with respect to the voltage generation unit 75. The second potential difference is controlled to be applied (step S810). Specifically, the first voltage generation circuit 751 controls so that a DC voltage of, for example, + 8V is output, and the second voltage generation circuit 752 controls so that a DC voltage of, for example, −8V is output. At this time, the second potential difference between the adjacent short-circuit detection target connection terminals 53b in the FOG mounting portion 5b is 16V.

After the lapse of a predetermined time, the processing unit 202d rewrites the repaired flag from "0" to "1" (step S811), returns to step S802, and performs the processing up to step S809 again.

In the configuration according to the sixth embodiment described above, by carrying out the short circuit determination processing procedure according to the sixth embodiment, it is detected that a short circuit has occurred between one or more short circuit detection target connection terminals 53b of the FOG mounting unit 5b. can do. Then, by reading the determination flag of the register unit 203d from the outside via the processing unit 202d, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53b of the FOG mounting unit 5b. can.

Further, in the short-circuit determination process according to the sixth embodiment described above, the repair process is performed when a short circuit occurs between one or more short-circuit detection target connection terminals 53b of the FOG mounting unit 5b. This makes it possible to reduce short-circuit defects in the FOG mounting unit 5b in the short-circuit determination process. Further, by reading the information of the register unit 203d from the outside via the processing unit 202d, the history of the repair process can be referred to.

Further, since the operation of each amplifier circuit 711, ..., 71 m of the detection electrode drive circuit 71 can be stopped, the steady circuit current included in the first current value I1 and the second current value I2 is reduced. This makes it possible to improve the accuracy of the threshold value determination when performing the short circuit determination.

In the present embodiment, even if the processes from step S802 to step S809 are re-executed, if a short circuit occurs (step S808; No), it is determined that the repaired flag is "1" in step S809. (Step S809; No), and the short-circuit determination process according to the sixth embodiment is terminated. This makes it possible to exclude individuals whose short circuit is not resolved even if the repair process (step S810) is performed, but the present invention is not limited to this. For example, the repair process may be repeated until the short circuit between the short circuit detection target connection terminals 53b is resolved without providing the repaired flag, or the short circuit detection target connection terminal 53b may be performed even if the repair process is performed a plurality of times. When the short circuit between the two is not resolved, the short circuit determination process may be terminated.

(Modified Example of Embodiment 6)
FIG. 31 is a diagram showing a schematic configuration of a display device and an inspection jig according to a modified example of the sixth embodiment. The same components as those in the sixth embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 31, the inspection jig 200a is connected to the circuit board 2j in the shipping inspection of the display device 100j.

The driver IC 7a FOG mounted on the circuit board 2j includes a detection electrode drive circuit 71, a switch control unit 72, an output control circuit 73, a processing unit 65e, a register unit 66e, a current detection unit 67, and a first booster. A circuit 74-1, a second booster circuit 74-2, and a voltage generation unit 75 are included.

The processing unit 65e is a component corresponding to the processing unit 202d in the inspection jig 200e of the sixth embodiment, and controls the driver IC 7a and performs a short-circuit determination process in the FOG mounting unit 5b in the shipping inspection of the display device 100j.

The register unit 66e is a component unit corresponding to the register unit 203d in the inspection jig 200e of the sixth embodiment, and stores various data in the short-circuit determination process of the FOG mounting unit 5b by the processing unit 65e. The various data stored in the register unit 66e include, for example, a current threshold value in the short circuit determination process, intermediate process data, a determination flag, and the like. The various data stored in the register unit 66e may be numerical data or discrete values such as digital data.

The inspection jig 200a is connected to the circuit board 2j in the shipping inspection of the display device 100j. The inspection jig 200a includes a power supply unit 201.

In the above-described configuration, the procedure for performing the short-circuit determination process in the FOG mounting unit 5b is the same as the short-circuit determination process procedure according to the sixth embodiment. Specifically, in the short-circuit determination processing procedure according to the sixth embodiment, the processing unit 202d is read as the processing unit 65e, the register unit 203d is read as the register unit 66e, and the current detection unit 204 is read as the current detection unit 67. It is possible to realize the same processing procedure as the short-circuit determination processing procedure according to the sixth embodiment.

In the configuration according to the modification of the sixth embodiment described above, a short circuit is generated between one or more short circuit detection target connection terminals 53b of the FOG mounting unit 5b by carrying out the short circuit determination processing procedure according to the sixth embodiment. Can be detected. Then, by reading the determination flag of the register unit 66e from the outside via the processing unit 65e, it is possible to identify whether or not a short circuit has occurred between any of the short circuit detection target connection terminals 53b of the FOG mounting unit 5b. can.

Further, since the operation of each amplifier circuit 711, ..., 71 m of the detection electrode drive circuit 71 can be stopped, the steady circuit current included in the first current value I1 and the second current value I2 is reduced. This makes it possible to improve the accuracy of the threshold value determination when performing the short circuit determination.

According to this embodiment, it is possible to provide display devices 100i and 100j that can improve the quality.

In the above-described embodiment, each component can be appropriately combined. Further, it is naturally understood that the other effects brought about by the embodiments described in the present embodiment are apparent from the description of the present specification, or those which can be appropriately conceived by those skilled in the art are brought about by the present invention. ..

1,1a, 1b display board (first board)
2,2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j Circuit board (second board)
3,3a 1st circuit board 4,4a 2nd circuit board 5,5a, 5b FOG mounting unit 6,6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h Driver IC
7,7a driver IC
11 Display unit 12R, 12G, 12B Color filter 13a Liquid crystal element 13b Holding capacity 14 Signal selection circuit 15 Voltage supply circuit 15a Voltage readout circuit 16 Touch sensor 17 Voltage supply circuit 51 First wiring 52 Second wiring 53 Connection terminals 53a, 53b Short circuit Detection target connection terminal (connection terminal)
54 Foreign matter 61 Video line drive circuit 62, 62a, 62b, 62c Switch control unit 63 Output control circuit 64 Voltage application circuit 65, 65a, 65b, 65c, 65d, 65e Processing unit 66, 66a, 66b, 66c, 66d, 66e Register Section 67 Current detection section 68-1 First booster circuit 68-2 Second booster circuit 69 Voltage switching circuit 70 Voltage generation section 71 Detection electrode drive circuit 72 Switch control section 73 Output control circuit 74-1 First booster circuit 74-2 Second booster circuit 75 Voltage generator 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j Display device 200, 200a, 200b, 200c, 200d, 200e Inspection jig 201 Power supply unit 202, 202a, 202b, 202c, 202d Processing unit 203, 203a, 203b, 203c, 203d Register unit 204 Current detection unit 611, ..., 61n Amplifier circuit 641, ..., 64n, 64p, 64q Switch 701 First voltage generation Circuit 702 2nd voltage generation circuit 711, ..., 71m Amplifier circuit 751 1st voltage generation circuit 752 2nd voltage generation circuit A VDD1 1st positive voltage power supply voltage A VDD2 2nd positive power supply voltage AVEE1 1st negative voltage power supply voltage AVEE2 2nd negative power supply voltage GCL scanning signal line Pix pixel SGL video signal line SPix sub-pixel Tr switching element Vpix pixel signal Vsig image signal

Claims (13)

A first substrate provided with a display unit in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction.
A driver IC in which a drive circuit for driving the display unit is integrated,
The second board provided with the driver IC and
A signal selection circuit provided between the display unit and the driver IC and arranged on the first substrate, and a signal selection circuit.
A plurality of first wirings that are wired to the first board and one end of which is electrically connected to the signal selection circuit.
A plurality of second wirings that are wired to the second board and one end of which is electrically connected to the driver IC.
A plurality of connection terminals in which the other end of the first wiring and the other end of the second wiring are electrically connected,
Have,
As a control state that the driver IC can take,
The first control state in which the signal selection circuit is open-controlled and no potential difference is applied between the adjacent connection terminals.
A second control state in which the signal selection circuit is open-controlled and a potential difference is applied between the adjacent connection terminals.
Including
The driver IC is
An output control circuit provided between the drive circuit and the connection terminal,
A voltage application circuit that applies a predetermined potential difference to the adjacent connection terminals,
Equipped with
The output control circuit is open-controlled in the first control state and the second control state.
The voltage application circuit is closed and controlled in the second control state.
Display device. A first substrate provided with a display unit in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction.
A driver IC in which a drive circuit for driving the display unit is integrated,
The second board provided with the driver IC and
A signal selection circuit provided between the display unit and the driver IC and arranged on the first substrate, and a signal selection circuit.
A plurality of first wirings that are wired to the first board and one end of which is electrically connected to the signal selection circuit.
A plurality of second wirings that are wired to the second board and one end of which is electrically connected to the driver IC.
A plurality of connection terminals in which the other end of the first wiring and the other end of the second wiring are electrically connected,
Have,
As a control state that the driver IC can take,
The first control state in which the signal selection circuit is open-controlled and no potential difference is applied between the adjacent connection terminals.
A second control state in which the signal selection circuit is open-controlled and a potential difference is applied between the adjacent connection terminals.
Including
Further, a voltage supply circuit provided on the first substrate and applying a predetermined potential difference to the adjacent connection terminals is provided.
The driver IC is
An output control circuit provided between the drive circuit and the connection terminal is provided.
The output control circuit is open-controlled in the first control state and the second control state.
The voltage supply circuit is closed and controlled in the second control state.
Display device. The driver IC is
In the first control state, the same voltage is supplied from the drive circuit to both of the adjacent connection terminals.
The display device according to claim 1 or 2 , wherein in the second control state, different voltages are supplied from the drive circuit to the adjacent connection terminals. The driver IC is
In the first control state, the first current value flowing through the driver IC is acquired, and in the second control state, the second current value flowing through the driver IC is acquired, and the first current value and the second current value are obtained. The display device according to claim 3 , further comprising a processing unit that detects a short circuit between adjacent connection terminals based on a difference from the value. The driver IC is
In the first control state, the first current value flowing through the driver IC is acquired, and in the second control state, the second current value flowing through the driver IC is acquired, and the first current value and the second current value are obtained. The display device according to claim 1 or 2 , further comprising a processing unit that detects a short circuit between adjacent connection terminals based on a difference from the value. The driver IC is
The display device according to claim 5 , wherein when a short circuit between adjacent connection terminals is detected, the voltage is increased so that the potential difference applied to the adjacent connection terminals becomes large. Further, a voltage readout circuit provided on the first board and for detecting the voltage value of the adjacent connection terminal is provided.
The driver IC is
In the first control state, the same voltage is supplied from the drive circuit to both of the adjacent connection terminals.
The display device according to claim 1 or 2 , wherein in the second control state, different voltages are supplied from the drive circuit to the adjacent connection terminals. The driver IC is
In the second control state, the first voltage value of one of the adjacent connection terminals and the second voltage value of the other of the adjacent connection terminals are detected via the voltage readout circuit, and the first voltage is detected. The display device according to claim 7 , further comprising a processing unit that performs a short-circuit detection process between adjacent connection terminals based on a difference between the value and the second voltage value. The display device according to any one of claims 1 to 8 , wherein the driver IC is COF mounted on the second board. The display device according to any one of claims 1 to 9 , wherein the second board is FOG-mounted on the first board, and a connection terminal group in which a plurality of the connection terminals are lined up is configured. A first substrate provided with a display unit in which a plurality of pixels are arranged in a first direction and a second direction different from the first direction.
A driver IC in which a drive circuit for driving the display unit is integrated,
The second board provided with the driver IC and
A signal selection circuit provided between the display unit and the driver IC and arranged on the first substrate, and a signal selection circuit.
A plurality of first wirings that are wired to the first board and one end of which is electrically connected to the signal selection circuit.
A plurality of second wirings that are wired to the second board and one end of which is electrically connected to the driver IC.
A plurality of connection terminals in which the other end of the first wiring and the other end of the second wiring are electrically connected,
In the inspection method of the display device having
The first step of blocking between the connection terminal and the display unit,
In the second step of acquiring the first current value flowing through the driver IC in a state where no potential difference is applied between the adjacent connection terminals,
In the third step of acquiring the second current value flowing through the driver IC while the potential difference is applied between the adjacent connection terminals,
The fourth step of comparing the difference between the first current value and the second current value with a predetermined current threshold value,
The fifth step of determining that a short circuit has occurred between the adjacent connection terminals when the difference is larger than the current threshold value.
Have,
In the first step, the drive circuit and the connection terminal are cut off from each other.
In the third step, a predetermined potential difference is applied to the adjacent connection terminals.
In the fifth step, when it is determined that a short circuit has occurred between the adjacent connection terminals, the voltage is increased so that the potential difference applied to the adjacent connection terminals becomes large.
Display device inspection method. In the second step, the same voltage is supplied from the drive circuit to both of the adjacent connection terminals.
The method for inspecting a display device according to claim 11 , wherein in the third step, different voltages are supplied from the drive circuit to the adjacent connection terminals. A display unit in which a plurality of pixels are lined up in the first direction and a second direction different from the first direction.
A driver IC in which a drive circuit for driving the display unit is integrated,
The second board provided with the driver IC and
A signal selection circuit arranged between the display unit and the driver IC,
A plurality of first wires whose one end is electrically connected to the signal selection circuit,
A plurality of second wires whose one end is electrically connected to the driver IC,
A plurality of connection terminals in which the other end of the first wiring and the other end of the second wiring are electrically connected,
In the inspection method of the display device having
The first step of blocking between the connection terminal and the display unit,
In the second step of acquiring the first current value flowing through the driver IC in a state where no potential difference is applied between the adjacent connection terminals,
In the third step of acquiring the second current value flowing through the driver IC while the potential difference is applied between the adjacent connection terminals,
The fourth step of comparing the difference between the first current value and the second current value with a predetermined current threshold value,
The fifth step of determining that a short circuit has occurred between the adjacent connection terminals when the difference is larger than the current threshold value.
Have,
In the first step, the drive circuit and the connection terminal are cut off from each other.
In the third step, a predetermined potential difference is applied to the adjacent connection terminals.
In the fifth step, when it is determined that a short circuit has occurred between the adjacent connection terminals, the voltage is increased so that the potential difference applied to the adjacent connection terminals becomes large.
Display device inspection method.

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