JP6988300B2 - Three-phase inverter device - Google Patents

Description

The present invention relates to a three-phase inverter device that drives a motor.

The three-phase inverter device that drives the motor is provided with a current detection unit for detecting the three-phase current in order to control the drive of the motor based on the three-phase current supplied to the motor. The current detector not only directly detects the phase current with a current sensor, but also detects the element current, which is the current flowing through each arm composed of switching elements such as IGBTs and power MOSFETs, and detects the element current. There is also a configuration in which the phase current is estimated from the detected value.

As a conventional technique for detecting such a failure of the current detection unit, for example, the technique described in Patent Document 1 can be mentioned. In the following, the configuration described in Patent Document 1 will be referred to as a conventional configuration. In the conventional configuration, the failure determination of the current detection unit is performed from the determination result using the sum of the three-phase currents obtained by detection or estimation. Specifically, in the conventional configuration, the failure determination of the current detection unit is performed by comparing the total sum of the three-phase currents with 0, which is a predetermined threshold value.

Japanese Unexamined Patent Publication No. 2017-060276

With the conventional configuration, it is difficult to improve the sensitivity of failure detection and reduce the frequency of false detections at the same time. That is, in the conventional configuration, if the above threshold value is set to a relatively small value, the sensitivity of failure detection is increased, and it is possible to detect an abnormality with small fluctuations such as deterioration of durability of the current detection unit and the start of breakage, but noise and the like. Since the threshold value is likely to be exceeded due to the influence of the above, the frequency of false detection may increase. Further, in the conventional configuration, if the above threshold value is set to a relatively large value, the frequency of false detections can be suppressed to a low level, but the sensitivity of failure detection is lowered, and abnormalities such as durability deterioration and start of breakage are detected. I can't.

Therefore, in the conventional configuration, when the above threshold value is set to a relatively small value, the failure detection is not immediately determined when the total sum of the three-phase currents exceeds the threshold value, and such a state continues for a predetermined time. It is conceivable to make changes to confirm the failure detection for the first time. According to the configuration with such a change, it is possible to improve the detection sensitivity and reduce the frequency of false detections at the same time, but another problem such as a decrease in the responsiveness of the failure detection arises.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a three-phase inverter device capable of preventing erroneous detection of a failure detection of a current detection unit while enhancing the detection response. There is something in it.

The three-phase inverter device (1, 51, 61) according to claim 1 drives a motor (2), and has a three-phase half-bridge circuit (3u, 3v, 3w) and a current detection unit (4). -9, 19), a drive control unit (21) , a three- phase total calculation unit (22, 54), and a failure detection processing unit (23). The three-phase inverter device (1, 51, 61) according to claim 2 drives a motor (2), and has a three-phase half-bridge circuit (3u, 3v, 3w) and a current detection unit (4). -9, 19), a drive control unit (21), a three-phase current calculation unit (20, 53, 63), a three-phase total calculation unit (22, 54), and a failure detection processing unit (23). The three-phase half-bridge circuit produces a three-phase current to supply to the motor. Current detector of claim 1 detects the three-phase currents Ha Fuburijji circuit. The current detection unit according to claim 2 detects the element current flowing through the switching element constituting the half-bridge circuit. The drive control unit controls the drive of the motor by controlling the operation of the half-bridge circuit based on the current detection result by the current detection unit. The three-phase current calculation unit calculates the three-phase current supplied to the motor based on the current detection result by the current detection unit. The three-phase total calculation unit according to claim 1 calculates the total three-phase current of the half-bridge circuit detected by the current detection unit. The three-phase total calculation unit according to claim 2 calculates the total three-phase current calculated by the three-phase current calculation unit.

The failure detection processing unit executes a failure detection process for detecting a failure of the current detection unit. The failure detection process includes a first determination process, a count value addition process, and a second determination process. The first determination process is a process of determining whether or not the current detection unit is normal based on the total sum of the three-phase currents calculated by the three-phase total calculation unit. The count value addition process is a process of adding a predetermined value according to the determination result to the failure detection count value when the current detection unit is determined to be abnormal in the first determination process. The second determination process is a process of determining that the current detection unit has failed when the failure detection count value exceeds a predetermined failure determination value. In this case, the predetermined value added to the failure detection count value in the count value addition process is when the motor control method is the voltage phase control control method and the motor control method is the triangular wave comparison control method. It is set to a larger value than that .

As described above, in the failure detection process having the above configuration, the failure of the current detection unit is detected through two determination processes, the first determination process and the second determination process. Then, in the above configuration, the sensitivity of failure detection can be set to an arbitrary value according to the setting of the threshold value used for performing the determination based on the sum of the three-phase currents in the first determination process. Moreover, in the above configuration, even if the current detection unit is determined to be abnormal in the first determination process, the failure detection is not immediately confirmed, so that the frequency of erroneous detection due to noise or the like can be suppressed to a low level.

Further, in the above configuration, the detection responsiveness can be set to an arbitrary value according to the setting of the failure determination value used in the second determination process. Therefore, according to the above configuration, it is possible to obtain an excellent effect that the failure detection of the current detection unit can be prevented from being erroneously detected while improving the detection response.

The figure which shows typically the structure of the three-phase inverter apparatus which concerns on 1st Embodiment. The figure which shows typically the content of the process which concerns on the failure detection of the current detection part which concerns on 1st Embodiment. The figure which shows typically the content of the motor current estimation processing which concerns on 1st Embodiment The figure which shows typically the content of the failure detection process which concerns on 1st Embodiment The figure which shows typically the content of the failure detection process which concerns on 2nd Embodiment The figure which shows typically the content of the failure detection process which concerns on 3rd Embodiment The figure which shows typically the content of the failure detection process which concerns on 4th Embodiment It is a figure for demonstrating the problem to be solved by 5th Embodiment, and is the timing chart which shows an example of the waveform of a motor control waveform, the drive waveform, and the estimated three-phase current waveform. The figure which shows typically the structure of the three-phase inverter device which concerns on 5th Embodiment. The figure which shows typically the content of the process which concerns on the failure detection of the current detection part which concerns on 5th Embodiment. The figure which shows typically the content of the current detection processing for failure detection which concerns on 5th Embodiment. A timing chart schematically showing a motor control waveform and a drive waveform according to a fifth embodiment. The figure which shows an example of the association between the switching interval which concerns on 5th Embodiment, and the combination of the arm which enables current detection. It is a figure for demonstrating the effect obtained by 5th Embodiment, and is the timing chart which shows an example of the waveform of a motor control waveform, the drive waveform, and the estimated three-phase current waveform. The figure which shows typically the structure of the three-phase inverter device which concerns on 6th Embodiment. The figure which shows typically the content of the process which concerns on the failure detection of the current detection part which concerns on 6th Embodiment. The figure which shows typically the content of the current detection processing for failure detection which concerns on 6th Embodiment. The figure which shows typically the content of the combination selection process which concerns on 6th Embodiment The figure which shows typically the content of the arm selection process which concerns on 6th Embodiment It is a figure for demonstrating the effect obtained by 6th Embodiment, and is the timing chart which shows an example of the count value of a motor control waveform, a drive waveform, and a difference detection counter.

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In each embodiment, substantially the same configuration is designated by the same reference numeral, and the description thereof will be omitted.
(First Embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 4.

The three-phase inverter device 1 shown in FIG. 1 drives a motor 2, and includes an inverter main circuit 3, detection circuits 4 to 9, a controller 10, and the like. The motor 2 is, for example, a three-phase AC motor mounted on a vehicle. The inverter main circuit 3 converts, for example, a DC voltage supplied from a DC power supply 11 which is an in-vehicle battery through a pair of DC power supply lines L1 and L2 into three-phase AC voltages of U-phase, V-phase, and W-phase. Output.

The U-phase, V-phase, and W-phase, that is, the three-phase output terminals of the inverter main circuit 3 are connected to the three-phase terminals of the motor 2, respectively. As a result, the three-phase current, that is, the three-phase motor currents Iu, Iv, and Iw are supplied from the inverter main circuit 3 to the motor 2, and the motor 2 is driven. The inverter main circuit 3 includes three-phase half-bridge circuits 3u, 3v, and 3w connected between the DC power lines L1 and L2, respectively. The half-bridge circuits 3u, 3v, 3w generate three-phase motor currents Iu, Iv, Iw to supply to the motor 2. In the following, the motor current is also referred to as a phase current.

The half-bridge circuit 3u includes switching elements 12 and 13. The switching element 12 constituting the upper arm of the half-bridge circuit 3u is connected between the power supply line L1 on the high potential side and the node Nu which is the output terminal of the U phase of the inverter main circuit 3. The switching element 13 constituting the lower arm of the half-bridge circuit 3u is connected between the node Nu and the power line L2 on the low potential side.

The half-bridge circuit 3v includes switching elements 14 and 15. The switching element 14 constituting the upper arm of the half-bridge circuit 3v is connected between the power supply line L1 and the node Nv which is the output terminal of the V phase of the inverter main circuit 3. The switching element 15 constituting the lower arm of the half-bridge circuit 3v is connected between the node Nv and the power supply line L2.

The half-bridge circuit 3w includes switching elements 16 and 17. The switching element 16 constituting the upper arm of the half-bridge circuit 3w is connected between the power supply line L1 and the node Nw which is the output terminal of the W phase of the inverter main circuit 3. The switching element 17 constituting the lower arm of the half-bridge circuit 3w is connected between the node Nw and the power supply line L2.

The switching elements 12 to 17 are N-channel type power MOSFETs including the main cell 18 and the sense cell 19. The main cell 18 is interposed in a main energization path for energizing the motor 2 from the inverter main circuit 3. That is, the drain of the main cell 18 of the switching elements 12, 14, and 16 constituting the upper arm is connected to the power supply line L1, and the source thereof is connected to the nodes Nu, Nv, and Nw, respectively. The drains of the main cells 18 of the switching elements 13, 15 and 17 constituting the lower arm are connected to the nodes Nu, Nv and Nw, respectively, and their sources are connected to the power supply line L2.

The sense cell 19 is for detecting an arm current, that is, an element current flowing through the main cell 18, and a current corresponding to the current flowing through the main cell 18 flows at a predetermined diversion ratio. The diversion ratio is determined by the size ratio of the main cell 18 and the sense cell 19. According to such a configuration, even when a relatively large current flows through the main cell 18, the current can be easily detected.

The gates of the main cell 18 and the sense cell 19 are commonly connected, and a drive signal output from the controller 10 is given to the common gate. Specifically, drive signals G_up and G_un are given to the gates of the U-phase switching elements 12 and 13, respectively, and drive signals G_vp and G_vn are given to the V-phase switching elements 14 and 15, respectively. Drive signals G_wp and G_wn are given to the switching elements 16 and 17, respectively.

Each source of the main cell 18 and the sense cell 19 is connected to the input terminals of the detection circuits 4 to 9, respectively. The detection circuits 4 to 9 detect the element current flowing through the switching elements 12 to 17 based on the current flowing through the sense cell 19. Therefore, in the present embodiment, the sense cell 19 and the detection circuits 4 to 9 constitute a current detection unit.

The detection circuits 4 to 9 detect the current flowing through the sense cells 19 of the switching elements 12 to 17, and output a current detection signal representing the detected value. Specifically, the U-phase detection circuits 4 and 5 output current detection signals I_up and I_un representing the detected values of the current flowing through the sense cells 19 of the switching elements 12 and 13, respectively.

The V-phase detection circuits 6 and 7 output current detection signals I_vp and I_vn representing the detected values of the current flowing through the sense cells 19 of the switching elements 14 and 15, respectively. The W-phase detection circuits 8 and 9 output current detection signals I_wp and I_wn representing the detection values of the current flowing through the sense cells 19 of the switching elements 16 and 17, respectively.

The current detection signals I_up to I_wn output from the detection circuits 4 to 9 are given to the controller 10. Although not shown, specific configurations of the detection circuits 4 to 9 include, for example, an OP amplifier to which the source voltages of the main cell 18 and the sense cell 19 are input, an OP amplifier output terminal thereof, and the output terminal of the OP amplifier. It is possible to adopt a configuration including a resistor connected between the sources of the sense cell 19 and an A / D converter in which the voltage across the resistor is input.

According to the above configuration, the voltage across the resistor becomes a voltage corresponding to the current flowing through the sense cell 19, and a digital signal obtained by A / D converting such a voltage is transmitted to the controller 10 as a current detection signal. Further, in the above configuration, the source of the main cell 18 and the source of the sense cell 19 have the same potential due to the operation of the OP operational amplifier. Therefore, the controller 10 can accurately detect the element current flowing in the main cell 18 based on the current detection signal corresponding to the current flowing in the sense cell 19.

The controller 10 controls the drive of the motor 2, and includes a motor current estimation unit 20, a drive control unit 21, a three-phase total calculation unit 22, a failure detection processing unit 23, a failure detection counter 24, and the like. The motor current estimation unit 20 detects the element current flowing through the switching elements 12 to 17 based on the current detection signals I_up to I_wn given from the detection circuits 4 to 9, and the phase currents Iu and Iv from the detected element currents. , The process of estimating Iw and the execution of. In the present embodiment, the motor current estimation unit 20 corresponds to a three-phase current calculation unit that calculates the three-phase current supplied to the motor 2 based on the current detection result by the current detection unit.

The process for detecting the element current described above is performed at a normal detection timing corresponding to the control method of the motor 2. For example, when the control method of the motor 2 is a control method for comparing triangular waves, the timing at which the triangular wave signal as a carrier reaches the maximum value or the minimum value, that is, the apex corresponds to a normal detection timing.

The motor current estimation unit 20 may not be able to detect the element currents of the three phases at such a normal detection timing. The reason is as follows. That is, since the detection circuits 4 to 9 of the present embodiment have the above-described configuration, the element current cannot be correctly detected unless the switching elements 12 to 17 are driven on.

Depending on the control state of the motor 2, the normal detection timing may overlap with the period during which the drive signal given to the switching elements 12 to 17 is on-level for a short period of time, that is, the period during which the on-pulse width is short. The motor current estimation unit 20 cannot detect the element currents for three phases. In this case, the motor current estimation unit 20 estimates the element current of the remaining one phase that could not be detected from the element currents of the two phases that could be detected.

The motor current estimation unit 20 outputs a possibility signal indicating whether or not the failure detection process described later can be executed to the three-phase total calculation unit 22 and the failure detection processing unit 23. Although the details will be described later, when the motor current estimation unit 20 can detect the element currents of the three phases based on the current detection signals I_up to I_wn, the phase currents Iu and Iv are used from the element currents of the three phases. , Iw is obtained, and a pass / fail signal indicating that the execution of the failure detection process is “possible” is output.

Further, when the motor current estimation unit 20 can detect only the element currents of two phases based on the current detection signals I_up to I_wn, the motor current estimation unit 20 obtains the corresponding two-phase phase currents from the element currents of those two phases, and also obtains the corresponding two-phase phase currents. The phase current of the remaining one phase is estimated from the element currents of those two phases. The method for estimating the phase current will be described later. When only the element currents for two phases can be detected, the motor current estimation unit 20 estimates the phase currents Iu, Iv, and Iw as described above, and indicates that the execution of the failure detection process is "No". Outputs a pass / fail signal to represent.

The drive control unit 21 controls the operation of the half-bridge circuits 3u, 3v, and 3w based on the current detection result by the current detection unit. Specifically, the drive control unit 21 generates and outputs drive signals G_up to G_wn for driving the inverter main circuit 3 based on the phase currents Iu, Iv, and Iw estimated by the motor current estimation unit 20. This controls the current flowing through the motor 2.

The three-phase total calculation unit 22 calculates the absolute value of the phase currents Iu, Iv, Iw estimated by the motor current estimation unit 20, that is, the total sum of the three-phase currents, and outputs the calculation result to the failure detection processing unit 23. The sum calculation process can be executed. In this case, the three-phase total calculation unit 22 executes the total sum calculation process when the pass / fail signal given by the motor current estimation unit 20 is “possible”, but when the pass / fail signal is “no”, the sum is calculated. Do not execute the calculation process. The three-phase sum calculation unit 22 may be configured to always execute the sum calculation process regardless of the pass / fail signal.

The failure detection processing unit 23 can execute a failure detection process for detecting a failure of the current detection unit. The failure detection processing unit 23 executes the failure detection process when the pass / fail signal given by the motor current estimation unit 20 is "possible", but executes the failure detection process when the pass / fail signal is "no". do not do.

As described above, in the present embodiment, the current detection unit is composed of the sense cell 19 and the detection circuits 4 to 9. Therefore, in this case, the failure of the current detection unit includes not only the circuit failure of the detection circuits 4 to 9, but also the element failure of the switching elements 12 to 17 including the sense cell 19 and the wiring failure such as the disconnection of the wiring related to the sense cell 19. Is also included.

The failure detection process in the present embodiment includes a first determination process, a count value addition process, and a second determination process. The first determination process is a process of determining whether or not the current detection unit is normal based on the calculation result of the absolute value of the total sum of the three-phase currents given by the three-phase total calculation unit 22. The count value addition process is a process of adding a predetermined value according to the determination result to the failure detection count value when the current detection unit is determined to be abnormal in the first determination process. The second determination process is a process of determining that the current detection unit has failed when the failure detection count value exceeds a predetermined failure determination value.

The failure detection count value described above is counted using the failure detection counter 24. In the present embodiment, six failure detection counters 24 are provided corresponding to the respective arms of the three-phase half-bridge circuits 3u, 3v, and 3w. In this case, the failure detection processing unit 23 can identify the failed current detection unit by executing each of the above processes using each of the six failure detection counters 24.

Next, the operation of the above configuration will be described.
[1] Overall flow of processing related to failure detection of the current detection unit Among the processes by the controller 10, the processing related to failure detection of the current detection unit is the processing as shown in FIG. First, in step S100, the element current flowing through the switching elements 12 to 17 is detected based on the current detection signals I_up to I_wn. The detection timing in this case is a normal detection timing corresponding to the control method of the motor 2. For example, in the case of the triangle wave comparison control method, the timing at which the triangular wave signal as a carrier reaches the apex, that is, the maximum value or the minimum value corresponds to the normal detection timing.

In step S200, the motor current estimation process for estimating the phase currents Iu, Iv, and Iw from the element current detected in step S100 is executed. The details of the motor current estimation process will be described later. In step S300, the element currents for three phases can be detected based on the pass / fail signal, and it is determined whether or not the three-phase current is estimated from the detected values of the element currents. If the element currents for the three phases cannot be detected, the result is "NO" in step S300, and the process ends.

On the other hand, if the element currents for the three phases can be detected, the result is "YES" in step S300, and the process proceeds to step S400. In step S400, a sum calculation process for calculating the absolute value of the sum of the phase currents Iu, Iv, and Iw estimated in step S200 is executed. In the following, the absolute value of the sum of the phase currents Iu, Iv, and Iw is also referred to as "the sum of the three phases". In step S500, a failure detection process for detecting a failure of the current detection unit is executed using the sum of the three phases calculated in step S400. The details of the failure detection process will be described later.

[2] Contents of motor current estimation processing The motor current estimation processing of the present embodiment has the contents as shown in FIG. First, in step S201, it is determined whether or not the element current for three phases can be detected at the normal detection timing. If the element currents for three phases can be detected at the normal detection timing, the result is “YES” in step S201, and the process proceeds to step S202.

In step S202, the values of the phase currents Iu, Iv, and Iw are obtained from the detected values of the element currents. Specifically, the value of the phase current Iu is updated to the detected value of the element current of the U phase, the value of the phase current Iv is updated to the detected value of the element current of the V phase, and the value of the phase current Iw is the W phase. It is updated to the detected value of the element current.

The detected value of the element current of each phase described above is the detected value of the element current of the upper arm or the lower arm of each phase, and in FIG. 3 and the following description, the detected value I_u *, the detected value I_v *, and the detection. It is expressed as a value I_w *. After the execution of step S202, the process proceeds to step S203. In this case, the element current for three phases can be detected. Therefore, in step S203, the pass / fail signal is set to "possible".

If the element current for three phases cannot be detected at the normal detection timing, the result is "NO" in step S201, and the process proceeds to step S204. In step S204, it is determined whether or not the U-phase element current could be detected. If the U-phase element current cannot be detected, the result is "YES" in step S204, and the process proceeds to step S205.

In step S205, the values of the respective phase currents Iu, Iv, and Iw are obtained from the detected values I_v * and I_w *. Specifically, in step S205, the value of the phase current Iv is updated to the detected value I_v *, and the value of the phase current Iw is updated to the detected value I_w *. Further, the value of the phase current Iu is obtained by calculation using the detected values I_v * and I_w *.

That is, in the configuration of the present embodiment, if each circuit is normal, the sum of the phase currents Iu, Iv, and Iw becomes zero, that is, "Iu + Iv + Iv = 0" is established. Therefore, in step S205, the value of the phase current Iu is calculated based on the following equation (1) by utilizing the fact that the sum of the phase currents Iu, Iv, and Iw becomes zero.
Iu = -I_v * -I_w * ... (1)

On the other hand, if the element current of the U phase can be detected, the result becomes "NO" in step S204, and the process proceeds to step S206. In step S206, it is determined whether or not the V-phase element current could be detected. If the element current of the V phase cannot be detected, the result is "YES" in step S206, and the process proceeds to step S207.

In step S207, the values of the phase currents Iu, Iv, and Iw are obtained from the detected values I_u * and I_w *. Specifically, in step S207, the value of the phase current Iu is updated to the detected value I_u *, and the value of the phase current Iw is updated to the detected value I_w *. Further, the value of the phase current Iv is obtained by calculation using the detected values I_u * and I_w *. In this case, the value of the phase current Iv is calculated based on the following equation (2) by utilizing the fact that the sum of the phase currents Iu, Iv, and Iw becomes zero as in step S205.
Iv = -I_u * -I_w * ... (2)

On the other hand, if the element current of the V phase can be detected, the result becomes "NO" in step S206, and the process proceeds to step S208. In step S208, the values of the respective phase currents Iu, Iv, and Iw are obtained from the detected values I_u * and I_v *. Specifically, in step S208, the value of the phase current Iu is updated to the detected value I_u *, and the value of the phase current Iv is updated to the detected value I_v *. Further, the value of the phase current Iw is obtained by calculation using the detected values I_u * and I_v *. In this case, the value of the phase current Iw is calculated based on the following equation (3) by utilizing the fact that the sum of the phase currents Iu, Iv, and Iw becomes zero, as in steps S205 and S207.
Iw = -I_u * -I_v * ... (3)

After the execution of steps S205, S207 or S208, the process proceeds to step S209. In this case, the element currents for the three phases cannot be detected. Therefore, in step S209, the pass / fail signal is set to "no". The reason for doing this is as follows. That is, when the element current for three phases cannot be detected, the phase current of the phase for which the element current cannot be detected is calculated based on the above equations (1) to (3).

Therefore, in this case, the sum of the three phases is always zero. In the first determination process of the failure detection process described later, whether or not the current detection unit is normal is determined based on the sum of the three phases, and in a state where the sum of the three phases is always zero. , Cannot make an accurate judgment. For this reason, when the element currents for the three phases cannot be detected, the pass / fail signal is set to "No" so that the failure determination process is not executed. After the execution of step S203 or S209, the motor current estimation process ends.

As described above, in the motor current estimation process of the present embodiment, when the element currents for three phases cannot be detected, the phase in which the element currents could not be detected is U phase → V phase →. It is designed to be confirmed in the order of W phase. The order of processing for such confirmation is not necessarily limited to this order, and may be replaced. Further, such confirmation processing does not necessarily have to be sequential processing as shown in FIG. 3, and parallel processing may be performed.

[3] Contents of the failure detection process The failure detection process of the present embodiment has the contents as shown in FIG. In this failure detection process, the failure detection count value of the failure detection counter 24 is held and added, and the target failure detection counter 24 has the element currents of the three phases detected in step S100. There are three failure detection counters 24 provided corresponding to the flowing arm. Further, the initial value of the failure detection count value is zero.

First, in step S501, it is determined whether or not the sum of the three phases is less than the first threshold value Ith1. The first threshold value Ith1 is for determining whether or not the current detection unit is normal, that is, whether or not there is a possibility that the current detection unit has a failure. In the present embodiment, for example, " It is set to "10A". In addition, the first threshold value Ith1 can obtain a desired detection response for failure detection of the current detection unit and suppress the occurrence rate of erroneous detection to a desired degree in consideration of the current detection accuracy in the above configuration. You can set it to a value like this.

If the sum of the three phases is less than the first threshold value Ith1, the result is “YES” in step S501, and the process proceeds to step S502. In step S502, the failure detection count value is maintained at the current value. On the other hand, when the total sum of the three phases is equal to or higher than the first threshold value Ith1, the result is “NO” in step S501, and the process proceeds to step S503.

In step S503, a predetermined value A for adding to the failure detection count value is selected. Specifically, in step S503, "+2" is selected as the predetermined value A when the sum of the three phases is less than the second threshold value Ith2, and when the sum of the three phases is greater than or equal to the second threshold value Ith2. “+10” is selected as the predetermined value A.

The second threshold value Ith2 is set to a value larger than the first threshold value Itth1. Specifically, the second threshold value Ith2 is a value at which it can be clearly determined that some kind of failure has occurred in the current detection unit, and is set to, for example, "100A" in the present embodiment. Therefore, in step S503, when it can be clearly determined that some kind of failure has occurred in the current detection unit rather than the predetermined value A selected when it cannot be clearly determined that some kind of failure has occurred in the current detection unit. The predetermined value A selected for is larger.

After the execution of step S503, the process proceeds to step S504, and the predetermined value A selected in step S503 is added to the failure detection count value. After executing step S502 or S504, the process proceeds to step S505. In step S505, it is determined whether or not the failure detection count value exceeds the failure determination value Cth. In this embodiment, the failure determination value Cth is set to, for example, "100". In addition, the failure determination value Cth can obtain the desired detection response for the failure detection of the current detection unit and suppress the occurrence rate of erroneous detection to a desired degree in consideration of the current detection accuracy in the above configuration. You can set it to a value like this.

If the failure detection count value exceeds the failure determination value Cth, the result is “YES” in step S505, and the process proceeds to step S506. In step S506, it is determined that the current detection unit has a failure. On the other hand, when the failure detection count value is equal to or less than the failure determination value Cth, the result becomes "NO" in step S505, and the process proceeds to step S507. In step S507, it is determined that the current detection unit has not failed and the current detection unit is normal. After the execution of step S506 or S507, the failure detection process ends.

Of the processes shown in FIG. 4, step S501 corresponds to the first determination process, steps S503 and S504 correspond to the count value addition process, and steps S505 to S507 correspond to the second determination process.

According to the present embodiment described above, the following effects can be obtained.
In the failure detection process having the above configuration, the failure of the current detection unit is detected through two determination processes, the first determination process and the second determination process. Then, in the above configuration, the sensitivity of failure detection can be set to an arbitrary value according to the setting of the first threshold value Ith1 used for performing the determination based on the sum of the three-phase currents in the first determination process. .. Moreover, in the above configuration, even if the current detection unit is determined to be abnormal in the first determination process, the failure detection is not immediately confirmed, so that the frequency of erroneous detection due to noise or the like can be suppressed to a low level.

Further, in the above configuration, the detection responsiveness can be set to an arbitrary value according to the setting of the failure determination value Cth used in the second determination process. Therefore, according to the above configuration, it is possible to obtain an excellent effect that the failure detection of the current detection unit can be prevented from being erroneously detected while improving the detection response.

Further, in the count value addition process, the failure detection count is higher when the sum of the three phases is greater than or equal to the second threshold Ith2 than when the sum of the three phases is less than the second threshold Ith2, which is larger than the first threshold Ith1. The predetermined value A to be added to the value becomes a large value. That is, in the present embodiment, the farther the sum of the three phases is from zero, which is the original value, the larger the predetermined value A added to the failure detection count value in the count value addition process. By doing so, while keeping the frequency of false detections due to noise etc. low, it is possible to detect abnormalities such as the sense cell 19 and the detection circuits 4 to 9 in which the fluctuation of the total sum of the three phases is relatively small, such as deterioration of durability and start of breakage. At the same time, it is possible to detect an obvious failure in which the fluctuation of the sum of the three phases is relatively large in a relatively short time.

As described above, in the present embodiment, two threshold values, the first threshold value Ith1 and the second threshold value Ith2, are provided as the threshold values to be compared with the sum of the three phases. Then, according to the present embodiment, by setting the failure determination value Cth for comparison with these two threshold values and the failure detection count value in consideration of the current detection accuracy in the above configuration, the current detection unit can be used. With respect to failure detection, a desired detection response can be obtained, and the frequency of erroneous detection can be suppressed to a desired degree.

The switching elements 12 to 17 constituting the three-phase half-bridge circuits 3u, 3v, and 3w are configured to include a main cell 18 and a sense cell 19. The detection circuits 4 to 9 constituting the current detection unit of the present embodiment are configured to detect the element current flowing through the switching elements 12 to 17 based on the current flowing through the sense cell 19. According to such a configuration, the manufacturing cost of the apparatus can be kept low and the physique of the apparatus can be kept small as compared with the configuration provided with the current sensors for detecting the phase currents Iu, Iv, and Iw. Then, according to the failure detection process of the present embodiment, it is possible to detect a failure of the current detection unit having such an element current detection configuration, and it is possible to obtain the above-mentioned effect with respect to the failure detection.

The failure detection counter 24 is provided corresponding to each of the six arms constituting the three-phase half-bridge circuits 3u, 3v, and 3w. Further, in the failure detection process, among the six failure detection counters 24, the failure detection count 24 is targeted at the three failure detection counters 24 provided corresponding to the arms through which the element currents of the three phases detected in step S100 flow. Values are retained, added, etc. For example, when each element current of the U-phase upper arm, the V-phase lower arm, and the W-phase lower arm is detected in step S100, three failure detections corresponding to the U-phase upper arm, the V-phase lower arm, and the W-phase lower arm are detected. The counting operation is performed for the counter 24. Then, when it is determined that the failure detection count value exceeds the failure determination value Cth, a failure occurs in the current detection unit that detects the element current of the arm corresponding to the failure detection counter 24 that counts the failure detection count value. It can be judged that it was. Therefore, according to the above configuration, when a failure of the current detection unit is detected, it is possible to identify the failed current detection unit.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIG.
In the second embodiment, the content of the failure detection process is different from that in the first embodiment. The configuration of the three-phase inverter device 1 is the same as that of the first embodiment.

As shown in FIG. 5, in the failure detection process of the present embodiment, step S513 is provided instead of step S503 of the failure detection process of the first embodiment. In step S513, as in step S503, a predetermined value A for adding to the failure detection count value is selected. However, in this case, the predetermined value A is set to a value according to the control method of the motor 2.

Specifically, in step S513, when the sum of the three phases is less than the second threshold value Ith2 and the control method of the motor 2 is the control method for triangular wave comparison, "+2" is selected as the predetermined value A, and three When the sum of the phases is less than the second threshold value Ith2 and the control method of the motor 2 is the control method of voltage phase control, "+3" is selected as the predetermined value A.

Further, in step S513, when the sum of the three phases is the second threshold value Ith2 or more and the control method of the motor 2 is the control method of the triangular wave comparison, "+10" is selected as the predetermined value A, and the sum of the three phases is summed. Is equal to or higher than the second threshold value Ith2, and when the control method of the motor 2 is the control method of voltage phase control, "+15" is selected as the predetermined value A. That is, in step S513, the predetermined value A is set to 1.5 times that when the control method of the motor 2 is voltage phase control as compared with the case of triangular wave comparison. In this embodiment, steps S513 and S504 correspond to the count value addition process.

As described above, in the failure detection process of the present embodiment, the predetermined value A to be added to the failure detection count value in the count value addition process is set to a value corresponding to the control method of the motor 2. There is. By doing so, the following effects can be obtained. That is, in the case of triangular wave comparison, since the current is detected at the apex of the carrier, the current detection cycle does not depend on the rotation speed of the motor 2 or the like. On the other hand, in the case of voltage phase control, since the current is detected for each predetermined electric angle, the current detection cycle fluctuates depending on the rotation speed of the motor 2 and the like. Then, the time until the failure is detected is not stable, and the responsiveness of the failure detection may deteriorate. Therefore, by appropriately setting the value of the predetermined value A in consideration of the assumed rotation speed of the motor 2 and the like, it is possible to prevent such deterioration of the responsiveness of failure detection.

(Third Embodiment)
Hereinafter, the third embodiment will be described with reference to FIG.
In the third embodiment, the content of the failure detection process is different from that in the first embodiment. The configuration of the three-phase inverter device 1 is the same as that of the first embodiment.

As shown in FIG. 6, in the failure detection process of the present embodiment, step S522 is provided in place of step S502 of the failure detection process of the first embodiment. In step S522, a predetermined value A for adding to the failure detection count value is selected. Specifically, in step S522, when the sum of the three phases is less than the third threshold value Ith3, "-5" is selected as the predetermined value A, and when the sum of the three phases is the third threshold value Ith3 or more. As a predetermined value A, "-1" is selected.

The third threshold value Ith3 is set to a value smaller than the first threshold value Itth1. Specifically, the third threshold value Ith3 is a value that can be clearly determined to be normal without any failure in the current detection unit, and is set to, for example, "1A" in the present embodiment. Therefore, in step S522, the predetermined value A selected when the current detection unit can be clearly determined to be normal is higher than the predetermined value A selected when the current detection unit cannot be clearly determined to be normal. The value is larger in the negative direction.

After the execution of step S522, the process proceeds to step S504, and the predetermined value A selected in step S522 is added to the failure detection count value. However, in this case, since the predetermined value A is a negative value, subtraction from the failure detection count value is performed in step S504. Therefore, in the present embodiment, steps S522 and S504 correspond to the count value subtraction process of subtracting the failure detection count value on condition that the current detection unit is determined to be normal in the first determination process.

As described above, in the failure detection process of the present embodiment, a count value subtraction process for subtracting the failure detection count value is provided on condition that the current detection unit is determined to be normal in the first determination process. There is. By doing so, the following effects can be obtained. That is, it is conceivable that, for example, due to the influence of noise or the like, a state in which the sum of the three phases temporarily exceeds the first threshold value Ith1 may occur. Then, every time such a state occurs, the failure detection count value is added, and eventually the failure detection count value exceeds the failure determination value Cth, which may cause erroneous detection. However, if the failure detection count value is subtracted when the sum of the three phases is within the normal range as in the present embodiment, it is possible to prevent the occurrence of erroneous detection due to the influence of such noise. Can be done.

Further, in the count value subtraction process, the failure detection count is higher when the total sum of the three phases is less than the third threshold Ith3 than when the sum of the three phases is the third threshold Ith3 or more, which is smaller than the first threshold Ith1. The value subtracted from the value becomes larger. That is, in the present embodiment, the closer the sum of the three phases is to zero, which is the original value, the larger the value subtracted from the failure detection count value in the count value subtraction process. By doing so, even if the failure detection count value is cumulatively added due to the influence of noise or the like, if the current detection unit is normal, the failure detection count value is immediately greatly subtracted, so that the influence of noise or the like is obtained. It is possible to more reliably prevent the occurrence of false detection due to the above.

(Fourth Embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIG. 7.
In the fourth embodiment, the content of the failure detection process is different from that in the first embodiment. The configuration of the three-phase inverter device 1 is the same as that of the first embodiment.

As shown in FIG. 7, in the failure detection process of the present embodiment, step S513 is provided in place of step S503 of the failure detection process of the first embodiment, and step S502 of the failure detection process of the first embodiment is provided. Step S522 is provided instead of the above. That is, the failure detection process of the present embodiment is a combination of the failure detection process of the second embodiment and the failure detection process of the third embodiment. Therefore, according to the present embodiment, both the effect obtained by the second embodiment and the effect obtained by the third embodiment can be obtained.

(Fifth Embodiment)
Hereinafter, the fifth embodiment will be described with reference to FIGS. 8 to 14.
As described above, when the device current detection configuration is adopted as the current detection unit, the device current for three phases may not be detected at the normal detection timing. In particular, in the control method for triangle wave comparison, when the motor 2 is controlled at high output or high rotation, the carrier apex and the period when the on-pulse width of the drive signal is short may continuously overlap, and the element current for three phases may overlap. May continue for a period in which the failure determination process cannot be executed without being able to detect.

FIG. 8 shows an example of a state in which the element currents for three phases cannot be continuously detected. In FIG. 8, the upper row shows a motor control waveform, specifically, a triangular wave signal, a U-phase modulated wave signal, a V-phase modulated wave signal, and a W-phase modulated wave signal, which are carriers, and the middle row shows a drive waveform, specifically, a drive waveform. Indicates a U-phase drive signal, a V-phase drive signal, and a W-phase drive signal, and the lower row shows the waveform of the estimated three-phase current.

In the case of the example shown in FIG. 8, it is not possible to detect the element currents for three phases six times in a row at time t1, t2, t3, t4, t5, and t6, which are normal detection timings, and the result is , The failure determination process cannot be executed continuously for 6 cycles. If the period during which the failure determination process cannot be executed is prolonged, the detection may be delayed when a failure occurs in the current detection unit. Therefore, in the present embodiment, a device for solving such a problem is added.

As shown in FIG. 9, the three-phase inverter device 51 of the present embodiment is different from the three-phase inverter device 1 of the first embodiment in that the controller 52 is provided in place of the controller 10. The controller 52 includes a motor current estimation unit 53 instead of the motor current estimation unit 20 and a three-phase total calculation unit 54 instead of the three-phase total calculation unit 22 with respect to the controller 10. different.

When the motor current estimation unit 53 corresponding to the three-phase current calculation unit can detect the element currents of the three phases at the normal detection timing, the motor current estimation unit 53 obtains the three-phase currents from the element currents of the three phases. The three-phase current thus obtained is given to the drive control unit 21 as phase currents Iu, Iv, and Iw for drive control of the motor 2, and three-phase summation as phase currents Iu_err, Iv_err, and Iw_err for failure detection. It is given to the calculation unit 54.

Further, when the motor current estimation unit 53 can detect only the element currents of the two phases at the normal detection timing, the motor current estimation unit 53 obtains the corresponding two-phase phase currents from the element currents of the two phases and the two-phase components. Estimate the phase current of the remaining one phase from the element current of. The three-phase current thus obtained is given to the drive control unit 21 as phase currents Iu, Iv, and Iw for drive control of the motor 2.

Further, in this case, the motor current estimation unit 53 calculates the three-phase current based on the current detection result by the current detection unit at the detection timing for failure detection in which the detection results for the three phases are obtained. The three-phase current calculated in this way is given to the three-phase total calculation unit 54 as the phase currents Iu_err, Iv_err, and Iw_err for fault detection.

The three-phase sum calculation unit 54 can execute the same sum calculation process as the three-phase sum calculation unit 22. However, in this case, the calculation target in the total calculation process is not the phase currents Iu, Iv, and Iw, but the phase currents Iu_err, Iv_err, and Iw_err.

As described above, in the configuration of the present embodiment, when the element currents for three phases cannot be detected at the normal detection timing, the three phases are at the failure detection timing, which is another timing at which the detection results for the three phases are obtained. The element current for each minute is detected, and the failure detection process is performed using the three-phase current calculated from those detected values.

Next, the operation of the above configuration will be described.
[1] Overall flow of processing related to failure detection of the current detection unit Among the processes by the controller 52, the processing related to failure detection of the current detection unit is the processing as shown in FIG. In the process related to the failure detection of the present embodiment, step S350 is added to the process related to the failure detection of the first embodiment. Step S350 is executed when the element currents of the three phases cannot be detected at the normal detection timing, that is, when "NO" in step S300.

In step S350, the element currents for three phases are detected at the failure detection timing, and the failure detection current detection process for calculating the failure detection phase currents Iu_err, Iv_err, and Iw_err from the detected element currents is executed. To. In the following description, the phase currents Iu_err, Iv_err, and Iw_err for failure detection are also simply expressed as phase currents Iu, Iv, and Iw. After the execution of step S350, the process proceeds to step S400, and the total calculation process is executed.

[2] Contents of current detection processing for failure detection The current detection processing for failure detection of the present embodiment has the contents as shown in FIG. First, in step S351, the switching interval of each phase is calculated based on the modulated wave signal of each phase, and the switching interval is associated with the combination of the arms capable of detecting the current.

For example, as shown in FIG. 12, when current detection is performed for each vertex of the triangular wave signal which is a carrier, three switching intervals T1_N + 1, T2_N + 1, between the Nth current detection and the N + 1th current detection, T3_N + 1 exists. Further, in this case, there are three switching intervals T1_N + 2, T2_N + 2, and T3_N + 2 between the N + 1th current detection and the N + 2nd current detection. In FIG. 12, the upper row shows the triangular wave signal, the U-phase modulated wave signal, the V-phase modulated wave signal, and the W-phase modulated wave signal which are carriers, and the lower row shows the drive signals G_up to G_wn.

The association in step S351 has the contents as shown in FIG. 13, for example. As is clear from FIG. 12, the combination A, which is a combination of arms capable of detecting current at the switching interval T1_N + 1, is a U-phase upper arm, a V-phase upper arm, and a W-phase upper arm.

As is clear from FIG. 12, the combination B, which is a combination of arms capable of detecting current at the switching interval T2_N + 1, is a U-phase lower arm, a V-phase upper arm, and a W-phase upper arm. As is clear from FIG. 12, the combination C, which is a combination of arms capable of detecting current at the switching interval T3_N + 1, is a U-phase lower arm, a V-phase lower arm, and a W-phase upper arm.

After the execution of step S351, the process proceeds to step S352. In step S352, one of the periods longer than Ton_NG during which the element currents of the three phases cannot be detected is selected from each switching interval. The reason why Ton_NG exists during such a period is as follows. That is, in the period Ton_NG from the start time of the switching interval to the elapse of a predetermined time, the element current cannot be normally detected by the detection circuits 4 to 9 due to the influence of noise generated by the switching of the switching elements 12 to 17. In FIG. 12, the period Ton_NG is represented by adding "NG" above the arrow.

Therefore, in step S351, as described above, a switching interval longer than the period Ton_NG is selected, and the element current of each phase is detected at an arbitrary timing after the period Ton_NG has elapsed from the start time of the switching interval. It should be noted that this arbitrary timing corresponds to the detection timing for failure detection in which the detection results for three phases can be obtained.

After the execution of step S351, the process proceeds to step S353. In step S353, the values of the phase currents Iu, Iv, and Iw are obtained from the values of the element currents detected in step S352. Specifically, the value of the phase current Iu is updated to the detected value of the element current of the U phase, the value of the phase current Iv is updated to the detected value of the element current of the V phase, and the value of the phase current Iw is the W phase. It is updated to the detected value of the element current.

The detected value of the element current of each phase described above is the detected value of the element current of the upper arm or the lower arm of each phase, and is referred to as the detected value Irr_u *, the detected value Irr_v *, and the detected value Irr_w * in FIG. show. After the execution of step S351, the current detection process for failure detection is completed.

As described above, in the configuration of the present embodiment, when the element currents for three phases cannot be detected at the normal detection timing, the failure detection timing is another timing at which the detection results for the three phases can be obtained. The element currents for the three phases are detected, and the failure detection process is performed using the three-phase currents calculated from those detected values. Therefore, even if the state in which the element currents for the three phases cannot be detected continues at the normal detection timing, the failure determination process can be executed.

For example, as shown in FIG. 14, even when the element currents of three phases cannot be detected continuously for 6 cycles at the normal detection timing, according to the configuration of the present embodiment, the failure detection is performed for each cycle. At the detection timings t1', t2', t3', t4', t5', and t6', the element currents for three phases are detected, and as a result, the failure determination process is executed every cycle. As described above, according to the present embodiment, it is not possible to detect the element currents of three phases at the normal detection timing, for example, when the motor 2 is controlled at high output or high rotation in the control method for triangle wave comparison. Even when the states are continuous, the period during which the failure determination process cannot be executed does not become long, so that when a failure occurs in the current detection unit, the failure can be quickly detected.

(Sixth Embodiment)
Hereinafter, the sixth embodiment will be described with reference to FIGS. 15 to 20.
In the fifth embodiment, as the detection timing for fault detection, an arbitrary timing at which the detection results for three phases are obtained is selected. In such a method, there is a possibility that the failure determination process is executed using only the detection result of the element current corresponding to the specific arm. That is, in the method of the fifth embodiment, there is a possibility that the number of failure determinations, which is the number of times used for failure determination for each arm, is biased. Therefore, in the present embodiment, a device for preventing such a bias is added.

As shown in FIG. 15, the controller 62 included in the three-phase inverter device 61 of the present embodiment includes the motor current estimation unit 63 instead of the motor current estimation unit 53 with respect to the controller 52 of the fifth embodiment. Is different. In the motor current estimation unit 63 corresponding to the three-phase current calculation unit, a number count unit 64 is added to the configuration provided in the motor current estimation unit 53.

For each of the six arms constituting the half-bridge circuits 3u, 3v, and 3w, the number-of-times counting unit 64 determines the number of times the element current detection result corresponding to each arm is used for calculating the three-phase current, and thus for failure determination. The number of failure determinations, which is the number of times used, is counted. The number-of-times counting unit 64 counts the number of failure determinations of each arm so that the number of failure determinations of the six arms is not biased. However, since the failure determination process is executed only when the element currents for the three phases can be detected, there is no bias in the number of failure determinations for each of the three phases. That is, the bias that becomes a problem here is the bias of the upper arm and the lower arm in each phase.

Therefore, the number-of-times counting unit 64 is provided with a counter for each of the three phases in order to detect the difference in the number of failure determinations of the upper and lower arms in each phase. Hereinafter, these three counters will be referred to as a difference detection counter. The difference detection counter increments the count value by "+1" when the detection result of the element current of the upper arm is used for failure determination for the corresponding phase, and the detection result of the element current of the lower arm is used for failure determination. If so, the count value is set to "-1". According to such a configuration, the count value of the difference detection counter becomes a value closer to zero as the deviation of the number of failure determinations of the upper and lower arms becomes smaller, and becomes a value farther from zero as the deviation becomes larger.

The motor current estimation unit 63 determines the detection timing for failure detection by giving priority to the timing at which the detection result of the element current corresponding to the arm having a small number of failure determinations is obtained. Although the details will be described later, the motor current estimation unit 63 determines the detection timing for failure detection so that the count values of the three difference detection counters included in the number count unit 64 approach zero.

Next, the operation of the above configuration will be described.
[1] Overall flow of processing related to failure detection of the current detection unit Among the processes by the controller 62, the processing related to failure detection of the current detection unit is the processing as shown in FIG. In the process related to the failure detection of the present embodiment, step S600 is added to the process related to the failure detection of the fifth embodiment. Step S600 is executed after the execution of step S500.

In step S600, the number of failure determinations is updated. Specifically, in step S600, when the detection result of the element current of the upper arm is used for failure determination, the count value of the difference detection counter is "+1" for each phase, and the element current of the lower arm is detected. When the result is used for failure determination, the count value of the difference detection counter is set to "-1".

[2] Contents of the current detection process for failure detection The current detection process for failure detection of the present embodiment has the contents as shown in FIG. In the current detection process for failure detection of the present embodiment, steps S354 to S357 are added to the current detection process for failure detection of the fifth embodiment. In this case, after the execution of step S351, step S354 is executed.

In step S354, a combination selection process for selecting a combination of arms to be used for failure determination is executed. The contents of the combination selection process will be described later. After the execution of step S354, the process proceeds to step S355, and it is determined whether or not the combination selected in step S354 exists in the combination associated with step S351.

If the selected combination is present in the associated combination, the result is "YES" in step S355, and the process proceeds to step S356. On the other hand, if the selected combination does not exist in the associated combination, the result is "NO" in step S355, and the process proceeds to step S352.

In step S356, it is determined whether or not the switching interval corresponding to the selected combination is longer than the period Ton_NG. If the switching interval corresponding to the selected combination is longer than the period Ton_NG, the result is "YES" in step S356, and the process proceeds to step S357. On the other hand, when the switching interval corresponding to the selected combination is a period of the period Ton_NG or less, the result is "NO" in step S356, and the process proceeds to step S352.

In step S357, the element current of each phase is detected at an arbitrary timing after the period Ton_NG has elapsed from the start time of the switching interval corresponding to the selected combination. It should be noted that this arbitrary timing corresponds to the detection timing for failure detection in which the detection results for three phases can be obtained. After the execution of step S357, step S353 is executed.

[3] Contents of the combination selection process The combination selection process has the contents as shown in FIG. That is, in the combination selection process, the arm selection process S700u for selecting the U-phase arm, the arm selection process S700v for selecting the V-phase arm, and the arm selection process S700w for selecting the W-phase arm are executed in this order. It has become. The execution order of the arm selection processes 700u, 700v, and 700w is not limited to this order, and may be replaced. Further, the arm selection processes 700u, 700v, and 700w do not necessarily have to be sequentially processed as shown in FIG. 18, and may be processed in parallel.

[4] Contents of arm selection process The arm selection processes S700u, 700v, and 700w all have the contents as shown in FIG. First, in step S701, it is determined whether or not the count value of the corresponding difference detection counter is larger than zero. In FIG. 19, the count value of the difference detection counter is abbreviated as "difference detection count value". If the count value of the difference detection counter is larger than zero, that is, if the count value is a positive value, the result is "YES" in step S701, and the process proceeds to step S702. In step S702, the "lower arm" is selected as the target for detecting the element current of the phase.

If the count value of the difference detection counter is zero or less, the result is "NO" in step S701, and the process proceeds to step S703. In step S703, it is determined whether or not the count value of the difference detection counter is zero. If the count value of the difference detection counter is zero, the result is "YES" in step S703, and the process proceeds to step S704. In step S704, "either the upper arm or the lower arm is acceptable" is selected as the target for detecting the element current of the phase. In this case, any one of the upper arm and the lower arm is selected as the target for detecting the element current of the phase.

If the count value of the difference detection counter is not zero, that is, if the count value of the difference detection counter is a negative value, the result becomes "NO" in step S703, and the process proceeds to step S705. In step S705, the upper arm is selected as the target for detecting the element current of the phase. After the execution of steps S702, S704 or S705, the arm selection process ends.

As described above, in the configuration of the present embodiment, the number counting unit 64 for counting the number of failure determinations of each arm is provided, and priority is given to the timing at which the detection result of the element current corresponding to the arm having a small number of failure determinations can be obtained. The detection timing for failure detection is determined. By doing so, the number of fault determinations of the six arms is not biased, and as a result, the current detection units corresponding to the six arms can be uniformly fault-determined.

When the detection timing for failure detection is arbitrarily selected, that is, at random, the number of failure determinations for each arm may be biased. For example, in the example shown in FIG. 20, the V phase is biased so that the state in which the upper arm is used for failure determination is continuous. In FIG. 20, the first stage from the top shows the motor control waveform, the second stage from the top shows the drive waveform, and the third stage from the top shows the count value of the difference detection counter when the arm is randomly selected. The fourth row from the top shows the count value of the difference detection counter when the arm is selected by the arm selection process of the present embodiment. As shown in FIG. 20, according to the present embodiment, it is possible to reduce the difference in the number of failure determinations between the upper arm and the lower arm for each phase, and as a result, a current detection unit corresponding to each of the upper and lower arms is provided. It can be seen that the failure can be determined evenly.

(Other embodiments)
It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, and can be arbitrarily modified, combined, or extended without departing from the gist thereof.
The numerical values and the like shown in each of the above embodiments are examples and are not limited thereto.

In each of the above embodiments, the absolute value of the total sum of the three-phase currents is obtained, and the absolute value is compared with the threshold values Ith1, Ith2, and It3, but the absolute value of the total sum of the three-phase currents is not obtained. It is also good. In this case, for steps S501, S503, S522, etc., whether or not the sum of the three-phase currents is included in the range from the negative threshold to the positive threshold is determined by setting each threshold as two thresholds, positive and negative. You can make changes to determine.

In steps S503 and S513 constituting the count value addition processing in the second to fourth embodiments, the predetermined value A is selected based on the result of comparing the sum of the three phases with the second threshold value Ith2 which is one threshold value. However, two or more threshold values to be compared with the sum of the three phases may be provided, and the predetermined value A may be selected in more detail based on the comparison result with each of the threshold values.

In step S513 constituting the count value addition processing in the third and fourth embodiments, the predetermined value A is selected in consideration of both the comparison result between the sum of the three phases and the second threshold value Ith2 and the control method of the motor 2. However, it may be changed so that the predetermined value A is selected in consideration of only the control method of the motor 2.

In step S522 constituting the count value subtraction process in the third embodiment, the predetermined value A is selected based on the result of comparing the sum of the three phases with the third threshold value Ith3, which is one threshold value. , Two or more threshold values to be compared with the sum of the three phases may be provided, and the predetermined value A may be selected in more detail based on the comparison result with each of the threshold values. Further, step S522 may be changed so as to select the predetermined value A in consideration of the control method of the motor 2 as in step S513 constituting the count value addition process in the second embodiment.

For the failure detection process, the count value clear process that forcibly clears the failure detection count value to zero based on an external command, etc., and the number of times the sum of the three phases is less than the first threshold value Ith1 exceeds a certain number of times. In such a case, a process of clearing the failure detection count value to zero may be added. As the above-mentioned external command, for example, a command for initialization given at the time when the driving of the motor 2 ends is assumed.

The detection circuits 4 to 9 may be configured to detect the element current flowing through the switching elements 12 to 17, and the specific configuration thereof can be appropriately changed. For example, when the current flowing through the half-bridge circuits 3u, 3v, and 3w is relatively small, a configuration without a sense cell 19 is used as the switching elements 12 to 17, and the element current flowing through the main cell 18 is directly detected by a shunt resistor or the like. It may be configured. In this case, the current detection unit is configured by the detection circuits 4 to 9 and the shunt resistor.

The current detection unit is not limited to the configuration of detecting the element current of the switching elements 12 to 17, and is configured by a hall type current sensor or the like that detects the three-phase current output from the half-bridge circuits 3u, 3v, and 3w. You may. When such a configuration is adopted, a configuration without a sense cell 19 as the switching elements 12 to 17 can be used, and the detection circuits 4 to 9 can be omitted. Further, in this case, the value detected by the current sensor becomes the value of the phase currents Iu, Iv, and Iw as it is, and there is no period during which the current cannot be detected as in the configuration of the element current detection. Therefore, when the above configuration is adopted, the processing of steps S200 and S300 in the processing related to the failure detection of the current detection unit shown in FIG. 2 and the like becomes unnecessary.

The switching element constituting the half-bridge circuit is not limited to the switching elements 12 to 17 which are power MOSFETs, and various power elements such as IGBTs, that is, power devices can be used.

The failure detection counter 24 does not necessarily have to be provided corresponding to each of the six arms constituting the three-phase half-bridge circuits 3u, 3v, and 3w. For example, one failure detection counter 24 may be provided for each phase, that is, a total of three failure detection counters 24 may be provided and used by the upper and lower arms of each phase, or one failure detection counter 24 may be provided as a whole and used by six arms. You may.
The number-of-times counting unit 64 of the sixth embodiment may be configured to provide a counter for each of the six arms and count the number of failure determinations for each of the six arms.

The present disclosure has been described in accordance with the examples, but it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various variations and variations within a uniform range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are within the scope and scope of the present disclosure.

1, 51, 61 ... Three-phase inverter device, 2 ... Motor, 3u, 3v, 3w ... Half bridge circuit, 4-9 ... Detection circuit, 12-17 ... Switching element, 18 ... Main cell, 19 ... Sense cell, 20, 53, 63 ... Motor current estimation unit, 22, 54 ... Three-phase total calculation unit, 23 ... Failure detection processing unit, 64 ... Number of times counting unit.

Claims (7)

A three-phase inverter device (1, 51, 61) that drives a motor (2).
A three-phase half-bridge circuit (3u, 3v, 3w) that generates a three-phase current to supply to the motor, and
A current detection unit for detecting a three-phase current before Symbol half-bridge circuit,
A drive control unit (21) that controls the drive of the motor by controlling the operation of the half-bridge circuit based on the current detection result of the current detection unit .
A three-phase total calculation unit (22, 54) that calculates the total of the three-phase currents of the half-bridge circuit detected by the current detection unit, and
A failure detection processing unit (23) that executes a failure detection process for detecting a failure of the current detection unit, and a failure detection processing unit (23).
Equipped with
For the failure detection process,
The first determination process for determining whether or not the current detection unit is normal based on the total sum of the three-phase currents calculated by the three-phase total calculation unit.
When the current detection unit is determined not to be normal in the first determination process, a count value addition process for adding a predetermined value according to the determination result to the failure detection count value, and
A second determination process for determining that the current detection unit has failed when the failure detection count value exceeds a predetermined failure determination value is included .
When the control method of the motor is a voltage phase control control method, the control method of the motor is a triangle wave comparison control method for the predetermined value to be added to the failure detection count value in the count value addition process. A three-phase inverter device that is set to a larger value than in the case. A three-phase inverter device (1, 51, 61) that drives a motor (2).
A three-phase half-bridge circuit (3u, 3v, 3w) that generates a three-phase current to supply to the motor, and
Current detector for detecting a device current flowing through the switching element (12 to 17) constituting the half bridge circuit and (4～9,19)
A drive control unit (21) that controls the drive of the motor by controlling the operation of the half-bridge circuit based on the current detection result of the current detection unit.
A three-phase current calculation unit (20, 53, 63) that calculates the three-phase current supplied to the motor based on the current detection result by the current detection unit, and
The three-phase total calculation unit (22, 54) for calculating the total sum of the three-phase currents calculated by the three-phase current calculation unit, and
A failure detection processing unit (23) that executes a failure detection process for detecting a failure of the current detection unit, and a failure detection processing unit (23).
Equipped with
For the failure detection process,
The first determination process for determining whether or not the current detection unit is normal based on the total sum of the three-phase currents calculated by the three-phase total calculation unit.
When the current detection unit is determined not to be normal in the first determination process, a count value addition process for adding a predetermined value according to the determination result to the failure detection count value, and
A second determination process for determining that the current detection unit has failed when the failure detection count value exceeds a predetermined failure determination value is included .
When the control method of the motor is a voltage phase control control method, the control method of the motor is a triangle wave comparison control method for the predetermined value to be added to the failure detection count value in the count value addition process. A three-phase inverter device that is set to a larger value than in the case. The switching element includes a main cell (18) and a sense cell (19).
The three-phase inverter device according to claim 2 , wherein the current detection unit detects the element current based on the current flowing through the sense cell. The drive control unit controls the drive of the motor based on the current detection result by the current detection unit at the normal detection timing corresponding to the control method of the motor.
When the three-phase current calculation unit (53, 63) cannot obtain the detection result of the element current for three phases at the normal detection timing, the detection for failure detection can obtain the detection result for the three phases. The three-phase inverter device according to claim 3 , wherein the three-phase current is calculated based on the current detection result by the current detection unit at the timing. Further, for each of the arms constituting the three-phase half-bridge circuit, the number of times the failure determination number is counted, which is the number of times the detection result of the element current corresponding to the arm is used for calculating the three-phase current. Equipped with a counting unit (64)
The three-phase current calculator (63), in claim 4 for determining the detection timing of the detection result of giving priority to timings obtained for the fault detection of the element current corresponding to the fault determination count is less the arm The described three-phase inverter device. For the failure detection process,
Further, any one of claims 1 to 5, further comprising a count value subtraction process for subtracting the failure detection count value on condition that the current detection unit is determined to be normal in the first determination process. The described three-phase inverter device. For the failure detection process,
The three-phase inverter device according to any one of claims 1 to 6, further comprising a count value clearing process for clearing the failure detection count value based on an external command.

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