JP2006296110A - Unit inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate the change, etc. of the number of installed units by enabling the communalization of a controller regardless of the number of installed inverters. <P>SOLUTION: A plurality of inverter units 2-4 are juxtaposed, and each phase currents, which are obtained by detecting each phase currents with detectors 11A-13A, via the resistors 14A-16A whose one end is connected in common, are added up to get an average value, whereupon the voltage across a resistor is equivalent to the amount of slippage from the average value, so based on it, variable ON delay circuits 26A-31A delay ON commands and transmit them to switching elements 5A-10A thereby balancing the currents. Since only the common connection part of the resistor is connected to the controller 32, it can be done regardless of the number of inverters. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a unit inverter device capable of maintaining a balance of output currents when a plurality of inverters are operated in parallel.

FIG. 3 shows a conventional apparatus configuration example. In FIG. 3, 101 is a DC power source, 102A, 102B, and 102C are drive circuits for generating dead time and driving the gates of the switching elements,
Reference numerals 103A, 103B, and 103C denote inverter main circuits, 104A to 106C denote current detectors, 107 denotes a PWM (pulse width modulation) waveform generation circuit, and 108 denotes a current balance circuit.

FIG. 3 shows a configuration in which a plurality of inverters are connected in parallel, in order to achieve the following objects 1) to 3).
1) When dealing with loads having different power capacities, it is unnecessary to design and manufacture inverters having different capacities by adjusting the capacities by the number of parallel inverters.
2) Facilitates capacity change after installation.
3) In the event of maintenance or failure, the power supply can be continued by stopping only the target inverter.

  In such a device, each inverter is driven by a PWM signal from a common control device, but current imbalance occurs due to variations in characteristics of switching elements in the inverter. If there is an imbalance, not only the capacity for the number of inverters can be secured, but also in extreme cases, current concentrates in one inverter and stops at overcurrent → Increase in current sharing of other inverter → Another inverter overcurrent In this case, the phenomenon of stopping → further increasing the current sharing may occur, which may cause the entire apparatus to stop.

The current balance control circuit 108 is provided to prevent the stop due to the overcurrent as described above, and a specific configuration example is shown in FIG. This is disclosed in Patent Document 1, for example. 201 is an adder, 202 is a divider, 203 to 205 are deviation detection circuits, 206 to 208 are deviation control amplifiers, and 209 is a pulse width adjustment circuit.
The average values of the phase currents IuA, IuB, and IuC of the three inverters are calculated by 201 and 202, and the difference from the current average value of each inverter is calculated by 203 to 205. This is amplified by 206 to 208 and then input to 209.

For example, when the current deviation of the inverter A is positive, the circuit 209 corrects the PWM signal transmitted to the inverter A so that the pulse width for outputting a positive voltage is shortened and the pulse width for outputting a negative voltage is lengthened. By doing so, current imbalance is suppressed. Although FIG. 4 shows only the U-phase current, a current balance control circuit is similarly provided for the other V and W phases.
Further, 102A, 102B, and 102C are added to the adjusted pulse, so-called dead time, that is, an off period for preventing a DC short-circuit due to simultaneous ON of the positive side switching element and the negative side switching element.

JP 09-331682 A

The method shown in FIG. 3 has the following problems.
1) A balance control circuit corresponding to the number of inverters is required inside the control device, but the number of inverters may range from a minimum of 1 to several tens depending on the capacity. For this reason, it is difficult to share a control device.
2) The number of inverters cannot be increased beyond the number of balance control circuits. In this case, it is necessary to replace the control device.
3) When the parallel number is large, the number of current detection signal lines connected from each inverter to the control device increases. When a large number of inverters are arranged in parallel, the number of signal lines increases, leading to an increase in the size of the apparatus.

  Accordingly, an object of the present invention is to make it possible to share a control device regardless of the number of inverters installed, and to easily change the number of installed devices.

In order to solve such a problem, in the present invention, a plurality of voltage-type inverter units each including a semiconductor switching element are provided, the AC output units of each unit are connected in parallel, and the unit in each unit is connected by a common control device. In a unit inverter device that gives a switching command to a semiconductor switching element,
Each unit is provided with a current detector for detecting the AC output current, a resistor connected to the output of the current detector, and a differential voltage detector for detecting a voltage across the resistor. One end is commonly connected to all units and introduced into the control device, and a variable on-delay circuit for delaying an on command by a time corresponding to the differential voltage and transmitting the command to the semiconductor switching element is provided. .

  According to the present invention, a control circuit can be shared regardless of the number of inverters in parallel. In addition, it is easy to change the number of units added or deleted.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, 1 is a DC power source, 2 to 4 are inverter units, 5A to 10A are semiconductor switching elements, 11A to 13A are current detectors, 14A to 16A are resistors, 17A to 19A are switches, and 20A to 22A are differentials. Amplifiers, 23A to 25A are sign inverters, and 26A to 31A are variable on-delay circuits (also simply referred to as variable on-delays). A gate drive circuit (not shown) is provided between the variable on-delay and the semiconductor switching element. A control device 32 is provided in common for the inverter units 2 to 4.

  The alternating current of each phase is detected by the detectors 11A to 13A and converted into a voltage proportional to the current value. This is connected to the same current detection line of other units via the resistors 14A to 16A by a common connection line. Since the common connection line is wired so as to cross each unit, the number connected to the control device 32 does not increase even if the number of units increases. Also, as indicated by the dotted line, the first unit and the last unit are connected by another common connection line, and a desired unit can be removed while maintaining the connection by creating a loop.

  If the resistance value of each unit is made the same, and a detector having a sufficiently large input impedance is used as a detector for detecting the voltage of the common connection line, the voltage of the common connection line becomes an average value of the voltage in each unit. FIG. 2 shows the principle. In this example, the average value of the voltages V1 to Vn is obtained with the input impedance Zi = ∞ of the detector D. As a result, the voltages at both ends of the resistors 14A to 16A are proportional to the deviation from the average value of the unit phase currents. Therefore, the voltages at both ends are measured by the differential amplifiers 20A to 22A and used as deviation signals.

  The variable on delays 26 </ b> A to 31 </ b> A increase the delay time as the input deviation signal increases. When the positive semiconductor switches 5A to 7A are turned on, a positive voltage is generated at the AC output terminal, and the current is increased in the positive direction. On the other hand, the negative-side semiconductor switches 8A to 10A generate a negative voltage at the AC output terminal when turned on, and increase the current in the negative direction. Therefore, the deviation signal is inputted as it is to the on delays 26A, 28A, 30A connected to the switches 5A to 7A, and when the deviation is positive, the turning on of 5A to 7A is delayed to suppress the current in the positive direction. Also, deviation signals are input to the on delays 27A, 29A, 31A connected to the switches 8A to 10A via the sign inverters 23A to 25A, and when the deviation is negative, the on-states of 8A to 10A are delayed, and the current in the negative direction Suppress.

  The AC current detection signal line connected to the control device 32 is only the common connection line (= current average value signal line) as described above, and performs control based on the average value of the unit current. The level of the input voltage is the same even if the number of units changes because the average value is transmitted. Therefore, the hardware of the control device can be the same regardless of the number of units.

  The switches 17A to 19A are used to select connection / disconnection of the in-unit current detection signal line to the common connection line. That is, when a certain unit is stopped due to failure or maintenance, the current detection value of that unit can be excluded from the average value calculation by turning off these switches. Further, by using a semiconductor switch (analog switch or the like) as a switch and giving an on / off command from the control device, the inverter can be operated / stopped and the switch can be turned on / off with a sufficiently small time difference. Thereby, for example, a certain unit can be stopped while another unit is operated, removed from the apparatus, reattached after maintenance, and restarted.

The control device 32 gives a signal including a dead time (fixed dead time) that should be secured in advance to each unit. Since there is a further delay (variable dead time) due to the on-delay in the unit, the dead time at the end of the semiconductor switch is (fixed dead time + variable dead time).
It should be noted that no delay with respect to the off timing is provided in order to avoid a DC power supply short circuit due to simultaneous turn-on of the positive and negative semiconductor switches.

Configuration diagram showing an embodiment of the present invention FIG. 1 is a diagram illustrating the principle of voltage detection of the common connection line Configuration diagram showing a conventional example Configuration diagram showing a specific example of the current balance control circuit of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2-4 ... Inverter unit, 5A-10A ... Semiconductor switching element, 11A-13A ... Current detector, 14A-16A ... Resistance, 17A-19A ... Switch, 20A-22A ... Differential amplifier, 23A- 25A: Sign inverter, 26A to 31A: Variable on-delay circuit, 32: Control device.

Claims (1)

In a unit inverter device comprising a plurality of voltage source inverter units constituted by semiconductor switching elements, connecting AC output units of each unit in parallel, and giving a switching command to the semiconductor switching elements in each unit by a common control device,
Each unit is provided with a current detector for detecting the AC output current, a resistor connected to the output of the current detector, and a differential voltage detector for detecting a voltage across the resistor. One end is commonly connected to all units and introduced into the control device, and a variable on-delay circuit for delaying an on command by a time corresponding to the differential voltage and transmitting the command to the semiconductor switching element is provided. Unit inverter device.

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