JP6984288B2 - Power converter - Google Patents

Description

The present invention relates to a power converter that drives a three-phase AC motor.

For example, an inverter, which is a power converter that drives a three-phase AC motor mounted on a vehicle, controls the drive of the motor based on the drive current flowing through the motor. It is equipped with. As a conventional technique for detecting such a failure of the current sensor, for example, the technique described in Patent Document 1 can be mentioned. In the following, the configuration described in Patent Document 1 will be referred to as a conventional configuration.

In the conventional configuration, the current of each phase of the motor is detected by using three current sensors. In the conventional configuration, the operation of measuring the amplitude of the monitor current detected by the remaining one while feedback-controlling the drive of the motor using the detection results of two of the three-phase current sensors is used for feedback control2. This is done while changing the combination of the two current sensors.

In the conventional configuration, an abnormality such as a gain failure of the current sensor is detected from the magnitude relationship of the amplitudes of the three monitor currents obtained by the above operation, and the current sensor having the gain failure is specified.

Japanese Unexamined Patent Publication No. 2016-123139

In the conventional configuration, even if one of the three current sensors fails, the failed current sensor can be identified. Therefore, after the identification, the other two current sensors are used to control the drive of the motor. That is, the motor control can be continued.

However, in the conventional configuration, when the motor control is continued using the other two current sensors in this way, the above-mentioned monitor current cannot be obtained, and abnormality detection and failure identification of the current sensor can be performed. I can't do it. That is, in the conventional configuration, if a failure of another current sensor occurs while the motor control is being continued using the normal current sensor after the abnormality is detected, the failure cannot be detected.

The present invention has been made in view of the above circumstances, and an object of the present invention is to detect a failure of a predetermined current detection unit among a plurality of current detection units, and then continue motor control while continuing another current detection unit. The purpose is to provide a power converter capable of detecting a failure of the electric current.

The power converter according to claim 1 drives a three-phase AC motor (2), and has a three-phase half-bridge circuit (4u, 4v, 4w), a current detection unit (5-10, 26), and a current detection unit (5-10, 26). It includes a drive control unit (28) and a failure detection processing unit (29). The current detection unit detects the current flowing through the upper arm and the lower arm of the half-bridge circuit. The drive control unit controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit. The failure detection processing unit detects a failure of the current detection unit based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Execute the process.

The failure detection process includes a test pattern determination process and a final failure determination process. In the test pattern judgment process, a predetermined judgment operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm is subjected to the judgment calculation result. This is a process for determining whether or not a failure has occurred in the corresponding current detection unit. The final failure determination process is a process of detecting a failure of the current detection unit based on the result when a failure determination is established for at least one test pattern as a result of executing the test pattern determination process. In this case, in the final failure determination process, when the failure determination is established for two or more test patterns as a result of executing the test pattern determination process, the failed current detection unit is specified based on the results. Processing is included.

According to the above configuration, if any of the plurality of current detection units provided corresponding to each of the six arms constituting the half-bridge circuit fails, the drive control unit drives the three-phase AC motor. The failure can be detected without being affected by the control. In the above configuration, when a failure determination is established for one test pattern, it can be specified that any of the current detection units provided corresponding to the arm selected in the test pattern has failed. Further, in the above configuration, when a failure determination is established for two or more test patterns, it is specified that one of the current detection units provided corresponding to the arms selected in all of the test patterns has failed. Can be done.

As described above, according to the above configuration, when a failure of the current detection unit is detected, the failed current detection unit can be identified. Therefore, even after the failure detection, the drive control unit can specify that the failure has occurred. The drive control of the three-phase AC motor can be continued by using the detection value of the current detection unit excluding the current detection unit. Further, according to the above configuration, even after the failure is detected, the test pattern determination process is executed by using the test pattern excluding the test pattern in which the arm corresponding to the current detection unit identified as the failure is selected. Further failures of the current detection unit can be detected. Therefore, according to the above configuration, it is possible to detect a failure of a predetermined current detection unit among a plurality of current detection units, and then detect a failure of another current detection unit while continuing motor control. The effect is obtained.

The figure which shows typically the structure of the motor control system which concerns on 1st Embodiment The figure which shows the specific structure of the control circuit which concerns on 1st Embodiment schematically. The figure in which the test pattern and the determination target which concerns on 1st Embodiment are associated with each other. The figure which shows an example of the test pattern judgment result table which shows the judgment result by the test pattern judgment processing which concerns on 1st Embodiment. The figure which shows an example of the failure information table which shows the determination result of the failure detection process which concerns on 1st Embodiment. The figure which shows typically the content of the failure detection process which concerns on 1st Embodiment The figure which shows typically the content of the test pattern determination process which concerns on 1st Embodiment FIG. 1 schematically showing the contents of the final failure determination process according to the first embodiment. FIG. 2 schematically showing the contents of the final failure determination process according to the first embodiment. The figure which shows typically the content of the failure detection process which concerns on 2nd Embodiment Timing chart for explaining the distribution of test patterns within one cycle of the voltage command value according to the third embodiment. The figure which shows typically the content of the failure detection process which concerns on 3rd Embodiment The figure in which the test pattern and the determination target which concerns on 4th Embodiment are associated with each other. The figure which shows an example of the test pattern judgment result table which shows the judgment result by the test pattern judgment processing which concerns on 4th Embodiment. The figure in which the combination of the on-driven arm according to the 4th embodiment and the test pattern which becomes feasible are associated with each other. The figure which shows typically the content of the test pattern determination process which concerns on 4th Embodiment The figure which shows typically the content of the test pattern determination process which concerns on 5th Embodiment The figure for demonstrating the operation of the queue which concerns on 5th Embodiment The figure for demonstrating the combination of the specific test pattern which includes all 6 arms which concerns on 6th Embodiment. The figure which shows typically the content of the failure detection processing which concerns on 6th Embodiment The figure which shows typically the content of the final failure determination process which concerns on 6th Embodiment

Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. In each embodiment, substantially the same configuration is designated by the same reference numeral, and the description thereof will be omitted.
(First Embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 9.

The motor control system 1 shown in FIG. 1 includes a motor 2 and a power converter 3 for driving the motor 2. The motor 2 is, for example, a three-phase AC motor mounted on a vehicle. The power converter 3 includes an inverter main circuit 4, detection circuits 5 to 10, drive circuits 11 to 16, control circuits 17, and the like.

The inverter main circuit 4 converts, for example, a DC voltage supplied from a DC power supply 18 which is an in-vehicle battery through a pair of DC power supply lines L1 and L2 into three-phase AC voltages of U-phase, V-phase, and W-phase. Output. The U-phase, V-phase, and W-phase, that is, the three-phase output terminals of the inverter main circuit 4 are connected to the three-phase terminals of the motor 2, respectively.

As a result, a three-phase current, that is, three phase currents iU, iV, and iW are supplied from the inverter main circuit 4 to the motor 2, and the motor 2 is driven. In this case, the sum of the three-phase currents, that is, the sum of the phase currents iU, iV, and iW is zero. That is, in the above configuration, "iU + iV + iW = 0" is established. The inverter main circuit 4 includes three-phase half-bridge circuits 4u, 4v, and 4w connected between the DC power lines L1 and L2, respectively. The half-bridge circuits 4u, 4v and 4w generate phase currents iU, iV and iW to supply to the motor 2.

The half-bridge circuit 4u includes power elements 19 and 20. The power element 19 constituting the upper arm of the half-bridge circuit 4u is connected between the power supply line L1 on the high potential side and the node Nu which is the output terminal of the U phase of the inverter main circuit 4. The power element 20 constituting the lower arm of the half-bridge circuit 4u is connected between the node Nu and the power line L2 on the low potential side.

The half-bridge circuit 4v includes power elements 21 and 22. The power element 21 constituting the upper arm of the half-bridge circuit 4v is connected between the power supply line L1 and the node Nv which is the output terminal of the V phase of the inverter main circuit 4. The power element 22 constituting the lower arm of the half-bridge circuit 4v is connected between the node Nv and the power supply line L2.

The half-bridge circuit 4w includes power elements 23 and 24. The power element 23 constituting the upper arm of the half-bridge circuit 4w is connected between the power supply line L1 and the node Nw which is the output terminal of the W phase of the inverter main circuit 4. The power element 24 constituting the lower arm of the half-bridge circuit 4w is connected between the node Nw and the power supply line L2.

The power elements 19 to 24 are switching elements constituting the half-bridge circuits 4u, 4v, and 4w, and all of them are N-channel type power MOSFETs including the main cell 25 and the sense cell 26. The main cell 25 is interposed in a main energization path for energizing the motor 2 from the inverter main circuit 4.

That is, the drain of the main cell 25 of the power elements 19, 21, and 23 constituting the upper arm is connected to the power supply line L1, and the source thereof is connected to the nodes Nu, Nv, and Nw, respectively. The drains of the main cells 25 of the power elements 20, 22, and 24 constituting the lower arm are connected to the nodes Nu, Nv, and Nw, respectively, and their sources are connected to the power supply line L2.

The sense cell 26 is for detecting the element current flowing in the main cell 25, and the current corresponding to the current flowing in the main cell 25 flows at a predetermined diversion ratio. The diversion ratio is determined by the size ratio of the main cell 25 and the sense cell 26 and the like. According to such a configuration, even when a relatively large current flows through the main cell 25, the current can be easily detected.

The gates of the main cell 25 and the sense cell 26 are commonly connected, and the output signals of the drive circuits 11 to 16 are given to the common gate. Each source of the main cell 25 and the sense cell 26 is connected to the input terminals of the detection circuits 5 to 10, respectively. The detection circuits 10 to 15 detect the element current flowing through the power elements 19 to 24 based on the current flowing through the sense cell 26. Therefore, in the present embodiment, the sense cell 26 and the detection circuits 5 to 10 constitute a current detection unit that detects the current flowing through the upper arm and the lower arm of the half-bridge circuits 4u, 4v, and 4w.

The detection circuits 5 to 10 detect the current flowing through the sense cells 26 of the power elements 19 to 24, and output a current detection signal Si representing the detected value. Each current detection signal Si output from the detection circuits 5 to 10 is given to the control circuit 17. The drive circuits 11 to 16 switch and drive the power elements 19 to 24 based on the gate signal Sg given from the control circuit 17.

The control circuit 17 includes a current detection signal Si output from the detection circuits 5 to 10, a position detection signal Sp output from the position sensor 27 that detects the rotation position of the rotor of the motor 2, and a higher-level controller (not shown). The given torque command signal St is input. The control circuit 17 controls the overall operation of the power converter 3, and has a function of controlling the drive of the inverter main circuit 4, a function of detecting a failure of the current detection unit, and the like. The specific configuration of the control circuit 17 is as shown in FIG.

As shown in FIG. 2, the control circuit 17 includes a drive control unit 28 and a failure detection processing unit 29. The drive control unit 28 controls the drive of the motor 2 by controlling the operation of the inverter main circuit 4 based on the detection value of the current detection unit. Further, the drive control unit 28 is configured to control the drive of the motor 2 based on the torque command signal St representing the torque command value that commands the torque of the motor 2.

Specifically, the drive control unit 28 generates and outputs a gate signal Sg for driving the inverter main circuit 4 based on the current detection signal Si, the position detection signal Sp, and the torque command signal St. As a result, the current flowing through the motor 2 and the torque generated by the motor 2 are feedback-controlled to desired values.

The failure detection processing unit 29 executes a failure detection process for detecting a failure of the current detection unit based on a plurality of test patterns and a current detection signal Si representing a detection value of the current detection unit. In the above-mentioned test pattern, one of the upper and lower arms is selected for each phase of the three-phase half-bridge circuits 4u, 4v, and 4w, and is as shown in FIG. 3, for example.

In this case, the test pattern No. Reference numeral 1 is a pattern in which the U-phase upper arm, the V-phase upper arm, and the W-phase upper arm are selected. Test pattern No. Reference numeral 2 is a pattern in which the U-phase upper arm, the V-phase lower arm, and the W-phase lower arm are selected. Test pattern No. Reference numeral 3 is a pattern in which the U-phase lower arm, the V-phase upper arm, and the W-phase lower arm are selected. Test pattern No. Reference numeral 4 is a pattern in which the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm are selected.

Test pattern No. Reference numeral 5 is a pattern in which the U-phase lower arm, the V-phase lower arm, and the W-phase lower arm are selected. Test pattern No. Reference numeral 6 is a pattern in which the U-phase lower arm, the V-phase upper arm, and the W-phase upper arm are selected. Test pattern No. Reference numeral 7 is a pattern in which the U-phase upper arm, the V-phase lower arm, and the W-phase upper arm are selected. Test pattern No. Reference numeral 8 is a pattern in which the U-phase upper arm, the V-phase upper arm, and the W-phase lower arm are selected.

As described above, the eight test pattern Nos. 1-No. Reference numeral 8 is set so that the combination of selectable arms is included in just proportion. In the following description, the test pattern No. 1-No. 8 is also referred to as test patterns 1 to 8, respectively.

In the failure detection process, a predetermined current detection signal Si representing a detection value of the current detection unit corresponding to the arm is used during a period in which the arm selected in the predetermined test pattern among the test patterns 1 to 8 is turned on. A test pattern determination process for executing a determination operation and determining whether or not a failure has occurred in the current detection unit corresponding to the arm based on the result of the determination operation is included.

In the determination calculation in this test pattern determination process, the absolute value of the sum of the detection values of the current detection units corresponding to the three arms selected in the predetermined test pattern is calculated during the period when the three arms are turned on. Then, in the test pattern determination process, the absolute value calculated by the determination operation is compared with the predetermined determination threshold value, and based on the comparison result, whether or not the current detection unit corresponding to the above three arms has a failure. Is determined.

As described above, in the present embodiment, the total sum of the three-phase currents is zero. Therefore, if the current detection unit is normal, the absolute value of the sum of the detection values of the current detection units corresponding to the three arms selected in each test pattern during the period when the three arms are turned on is zero. .. Therefore, it is possible to determine whether or not a failure has occurred in the current detection unit based on whether or not the absolute value calculated by the determination calculation is zero.

However, due to the influence of various errors in the configuration related to current detection, it is conceivable that the absolute value of the sum of the detected values may not be completely zero even when the current detection unit is normal. Therefore, in the present embodiment, the determination threshold value is set to a value at which erroneous determination does not occur due to the influence of such an error, for example, a value larger than zero by a predetermined margin.

In FIG. 3, each test pattern 1 to 8 is associated with a determination target in the test pattern determination process. That is, in the test pattern determination process using the test pattern 1, the failure determination (evaluation) of the current detection unit corresponding to the U phase upper arm, the V phase upper arm, and the W phase upper arm is performed. In the test pattern determination process using the test pattern 2, the failure determination of the current detection unit corresponding to the U-phase upper arm, the V-phase lower arm, and the W-phase lower arm is performed.

In the test pattern determination process using the test pattern 3, the failure determination of the current detection unit corresponding to the U-phase lower arm, the V-phase upper arm, and the W-phase lower arm is performed. In the test pattern determination process using the test pattern 4, the failure determination of the current detection unit corresponding to the U-phase lower arm, the V-phase lower arm, and the W-phase upper arm is performed. In the test pattern determination process using the test pattern 5, the failure determination of the current detection unit corresponding to the U-phase lower arm, the V-phase lower arm, and the W-phase lower arm is performed.

In the test pattern determination process using the test pattern 6, the failure determination of the current detection unit corresponding to the U-phase lower arm, the V-phase upper arm, and the W-phase upper arm is performed. In the test pattern determination process using the test pattern 7, a failure determination of the current detection unit corresponding to the U-phase upper arm, the V-phase lower arm, and the W-phase upper arm is performed. In the test pattern determination process using the test pattern 8, the failure determination of the current detection unit corresponding to the U-phase upper arm, the V-phase upper arm, and the W-phase lower arm is performed.

The determination result by the test pattern determination process as described above is stored as, for example, a table as shown in FIG. 4 (hereinafter, also referred to as a TP determination result table). The table shown in FIG. 4 is stored in, for example, a storage area secured on a memory included in the control circuit 17. In the table shown in FIG. 4, "normal", "failure", or "unevaluated" is stored as a determination result corresponding to each of the test patterns 1 to 8.

Here, "normal" means that the failure determination is unsuccessful in the test pattern determination process performed using the corresponding test pattern, and is represented by, for example, "1". The failure means that the failure determination is established in the test pattern determination process performed using the corresponding test pattern, and is represented by, for example, "-1". Not evaluated means that the test pattern determination process using the corresponding test pattern has not been performed, and is represented by, for example, "0".

In the example shown in FIG. 4, the failure determination is unsuccessful in the test pattern determination process performed using the test patterns 1 and 2, and the failure determination is performed in the test pattern determination process performed using the test patterns 3 to 6. The contents indicate that the above is satisfied and that the test pattern determination process using the test patterns 7 and 8 has not been performed.

Further, the failure detection process includes a final failure determination process for detecting a failure of the current detection unit based on the result when a failure determination is established for at least one test pattern as a result of executing the test pattern determination process. It has been. Then, in this final failure determination process, when the failure determination is established for two or more test patterns as a result of executing the test pattern determination process, the failed current detection unit is specified based on the results. Processing is included. Further, in the final failure determination process, when the failure determination is unsuccessful for two or more test patterns as a result of executing the test pattern determination process, a normal current detection unit is specified based on the results. Processing is included.

The failure detection processing unit 29 determines the failure of the current detection unit by executing the failure detection process having the contents described above, and outputs the failure information indicating the determination result to the drive control unit 28 and a higher-level controller (not shown). Output to. This failure information is configured as, for example, a table as shown in FIG. 5 (hereinafter, also referred to as a failure information table). The table shown in FIG. 5 is stored in, for example, a storage area secured on a memory included in the control circuit 17.

In the table shown in FIG. 5, "normal", "failure", or "unevaluated" is stored as failure information for the six current detectors corresponding to the upper and lower arms of the U phase, the V phase, and the W phase. .. Here, "normal" means that the corresponding current detection unit has been identified as normal, and is represented by, for example, "1".

The failure means that the corresponding current detection unit has been identified as a failure, and is represented by, for example, "-1". Not evaluated means that the corresponding current detector has not been identified as normal or faulty, and is represented by, for example, "0". In the example shown in FIG. 5, each current detection unit corresponding to the U-phase upper arm, the V-phase upper arm, the V-phase lower arm, the W-phase upper arm, and the W-phase lower arm is "normal", and the U-phase lower arm is used. It is failure information indicating that the corresponding current detection unit is a "failure".

Next, the operation of the above configuration will be described.
[1] Overall flow of failure detection processing The failure detection processing unit 29 executes failure detection processing as shown in FIG. 6 at the timing when the gate signal Sg is inverted. However, immediately after the inversion of the gate signal Sg, the current detection signal Si may not be stable due to the influence of noise or the like generated because the power elements 19 to 24 are in the switching transient state, and the accuracy of current detection may decrease. Therefore, the failure detection processing unit 29 may execute the failure detection processing at a timing after a predetermined time such as several microseconds has elapsed from the timing at which the gate signal Sg is inverted.

As shown in FIG. 6, in step S100, which is first executed after the failure detection process is started, the power elements 19 to 24 constituting the arms of the half-bridge circuits 4u, 4v, and 4w are driven according to the driving conditions. The test pattern to be judged (evaluation target) is determined. Specifically, in step S100, among the upper and lower arms of each phase, a test pattern in which the combination of the arm whose gate is ON, that is, the arm which is driven ON and the combination of the selected arm match is the determination target. It is determined as a test pattern.

After the execution of step S100, the process proceeds to step S200, and it is determined whether or not the determined test pattern can be used. In this case, a test pattern that is not set to "evaluation prohibited" becomes a usable test pattern. Note that "evaluation prohibition" means prohibition of execution of the test pattern determination process using the test pattern. Although the details will be described later, in the final failure determination process, the test pattern including the arm corresponding to the current detection unit in which the failure is confirmed is set to "evaluation prohibited".

As described above, in the present embodiment, when a failure of a predetermined current detection unit is detected as a result of executing the final failure determination process, the failure is detected in the test pattern determination process executed thereafter. The arm corresponding to the current detection unit is excluded from the determination target for the selected test pattern.

Here, if the determined test pattern is set to "evaluation prohibited", the result is "NO" in step S200, and the process ends as it is. On the other hand, if the determined test pattern is not set to "evaluation prohibited", the result is "YES" in step S200, and the process proceeds to step S300. In step S300, the current detection signal Si output from the current detection unit corresponding to the three arms selected by the determined test pattern, that is, the current detection value by the current detection unit is read.

After the execution of step S300, the process proceeds to step S400, and the test pattern determination process described above is executed. The specific contents of the test pattern determination process will be described later. After the execution of step S400, the process proceeds to step S500. In step S500, it is determined whether or not the evaluation of all the test patterns is completed, that is, whether or not the test pattern determination process is executed for all of the test patterns 1 to 8. This determination is made based on the TP determination result table.

If at least one of the test patterns 1 to 8 has not been evaluated, that is, if there is at least one place where "unevaluated" is stored in the TP determination result table, the result is "NO" in step S500, and the process is performed as it is. It will be the end. On the other hand, if all of the test patterns 1 to 8 have been evaluated, that is, if there is no place where "unevaluated" is stored in the TP determination result table, the result is "YES" in step S500, and the process proceeds to step S600.

In step S600, the final failure determination process described above is executed. As described above, in the present embodiment, the final failure determination process is executed after the test pattern determination process is executed for all of the eight test patterns 1 to 8. The specific contents of the final failure determination process will be described later.

After the execution of step S600, the process proceeds to step S700. In step S700, the failure determination of the usable test pattern, that is, the evaluable test pattern is initialized. Specifically, in step S700, initialization is performed so that each value in the TP determination result table becomes “unevaluated”. However, the value of the test pattern set to "evaluation prohibited" is not initialized, and the value as it is, that is, "failure" is maintained.

[2] Contents of the test pattern determination process The test pattern determination process of the present embodiment has the contents as shown in FIG. 7. First, in step S401, it is determined whether or not the sum of the three current detection values read in step S300 is equal to or less than the determination threshold value. That is, in step S401, the sum of the detection values of the current detection units corresponding to the three arms selected in the test pattern (hereinafter referred to as the current test pattern) to be determined in the test pattern determination process, that is, 3. It is determined whether or not the absolute value of the sum of the phase currents is equal to or less than the determination threshold value.

If the absolute value of the total sum of the three-phase currents is equal to or less than the determination threshold value, the result is “YES” in step S401, and the process proceeds to step S402. In step S402, "normal" is stored as the determination result of the current test pattern in the TP determination result table. On the other hand, if the absolute value of the total sum of the three-phase currents is larger than the determination threshold value, the result becomes “NO” in step S401, and the process proceeds to step S403. In step S403, "failure" is stored as the determination result of the current test pattern in the TP determination result table. After the execution of step S402 or S403, the test pattern determination process ends.

[3] Contents of the final failure determination process The final failure determination process of the present embodiment has the contents as shown in FIGS. 8 and 9. In this case, the portion marked with "1" in the circle in FIG. 8 is connected to the portion marked with "1" in the circle in FIG.

First, in step S601, it is determined whether or not all the available test patterns are normal determinations. That is, in step S601, it is determined whether or not "normal" is stored in all the available test patterns in the TP determination result table. Here, if "normal" is stored in all the test patterns except the test pattern set to "evaluation prohibited", "YES" is set in step S601, and the process proceeds to step S602.

In step S602, "normal" is stored for all the arms that are not stored as "failure" in the failure information table. In the present embodiment, in steps S601 and S602, when the failure determination is unsuccessful for all the test patterns as a result of executing the test pattern determination process, it is detected that all the current detection units are normal. Corresponds to processing. On the other hand, if a value other than "normal" is stored in at least one of the test patterns excluding the test pattern set to "evaluation prohibited", the result becomes "NO" in step S601, and the process proceeds to step S603.

Steps S603 to S607 are processes for determining whether or not the current detection unit corresponding to the U-phase upper arm is out of order. Therefore, here, based on the evaluation results of the test patterns 1, 2, 7, and 8 in which the U-phase upper arm is selected, whether the current detector corresponding to the U-phase upper arm is defective or normal. Is determined. As shown in FIG. 3, the test patterns 1, 2, 7, and 8 are all patterns in which the "U phase upper arm" is selected.

First, in step S603, it is determined whether or not all of the test patterns 1, 2, 7, and 8 are failure determinations. That is, in step S603, it is determined whether or not "failure" is stored in all of the test patterns 1, 2, 7 and 8 in the TP determination result table.

Here, if "failure" is stored in all of the test patterns 1, 2, 7, and 8, the result is "YES" in step S603, and the process proceeds to step S604. In step S604, "failure" is stored in the U-phase upper arm in the failure information table. After the execution of step S604, the process proceeds to step S605, and test patterns 1, 2, 7, and 8 are set to prohibit evaluation.

On the other hand, when a value other than "failure" is stored in at least one of the test patterns 1, 2, 7, and 8, the result is "NO" in step S603, and the process proceeds to step S606. In step S606, it is determined whether or not all of the test patterns 1, 2, 7 and 8 are normal determinations. That is, in step S606, it is determined whether or not "normal" is stored in all of the test patterns 1, 2, 7 and 8 in the TP determination result table.

Here, when "normal" is stored in all of the test patterns 1, 2, 7, and 8, the result is "YES" in step S606, and the process proceeds to step S607. In step S607, "normal" is stored in the U-phase upper arm in the failure information table. On the other hand, when a value other than "normal" is stored in at least one of the test patterns 1, 2, 7, and 8, the result is "NO" in step S606, and the process proceeds to step S608. Even after the execution of step S605 or S607, the process proceeds to step S608.

Steps S608 to S612 are processes for determining whether or not the current detection unit corresponding to the U-phase lower arm is out of order. Therefore, here, based on the evaluation results of the test patterns 3, 4, 5 and 6 in which the U-phase lower arm is selected, whether the current detector corresponding to the U-phase lower arm is defective or normal. Is determined. As shown in FIG. 3, the test patterns 3, 4, 5 and 6 are all patterns in which the "U-phase lower arm" is selected.

First, in step S608, it is determined whether or not all of the test patterns 3, 4, 5 and 6 are failure determinations. That is, in step S608, it is determined whether or not "failure" is stored in all of the test patterns 3, 4, 5 and 6 in the TP determination result table.

Here, if "failure" is stored in all of the test patterns 3, 4, 5 and 6, the result is "YES" in step S608, and the process proceeds to step S609. In step S609, "failure" is stored in the U-phase lower arm in the failure information table. After the execution of step S609, the process proceeds to step S610, and the test patterns 3, 4, 5 and 6 are set to prohibit evaluation.

On the other hand, when a value other than "failure" is stored in at least one of the test patterns 3, 4, 5 and 6, the result is "NO" in step S608, and the process proceeds to step S611. In step S611, it is determined whether or not all of the test patterns 3, 4, 5 and 6 are normal determinations. That is, in step S611, it is determined whether or not "normal" is stored in all of the test patterns 3, 4, 5 and 6 in the TP determination result table.

Here, when "normal" is stored in all of the test patterns 3, 4, 5 and 6, the result is "YES" in step S611, and the process proceeds to step S612. In step S612, "normal" is stored in the U-phase lower arm in the failure information table. On the other hand, when a value other than "normal" is stored in at least one of the test patterns 3, 4, 5 and 6, the result is "NO" in step S611, and the process proceeds to step S613. Even after the execution of step S610 or S612, the process proceeds to step S613.

Steps S613 to S617 are processes for determining whether or not the current detection unit corresponding to the V-phase upper arm is out of order. Therefore, here, based on the evaluation results of the test patterns 1, 3, 6 and 8 in which the V-phase upper arm is selected, whether the current detector corresponding to the V-phase upper arm is defective or normal. Is determined. As shown in FIG. 3, the test patterns 1, 3, 6 and 8 are all patterns in which the "V-phase upper arm" is selected.

First, in step S613, it is determined whether or not all of the test patterns 1, 3, 6 and 8 are failure determinations. That is, in step S613, it is determined whether or not "failure" is stored in all of the test patterns 1, 3, 6 and 8 in the TP determination result table.

Here, if "failure" is stored in all of the test patterns 1, 3, 6 and 8, the result is "YES" in step S613, and the process proceeds to step S614. In step S614, "failure" is stored in the V-phase upper arm in the failure information table. After the execution of step S614, the process proceeds to step S615, and test patterns 1, 3, 6 and 8 are set to prohibit evaluation.

On the other hand, when a value other than "failure" is stored in at least one of the test patterns 1, 3, 6 and 8, the result is "NO" in step S613, and the process proceeds to step S616. In step S616, it is determined whether or not all of the test patterns 1, 3, 6 and 8 are normal determinations. That is, in step S616, it is determined whether or not "normal" is stored in all of the test patterns 1, 3, 6 and 8 in the TP determination result table.

Here, if "normal" is stored in all of the test patterns 1, 3, 6 and 8, the result is "YES" in step S616, and the process proceeds to step S617. In step S617, "normal" is stored in the V-phase upper arm in the failure information table. On the other hand, when a value other than "normal" is stored in at least one of the test patterns 1, 3, 6 and 8, the result is "NO" in step S616, and the process proceeds to step S618. Even after the execution of step S615 or S617, the process proceeds to step S608.

Steps S618 to S622 are processes for determining whether or not the current detection unit corresponding to the V-phase lower arm is out of order. Therefore, here, based on the evaluation results of the test patterns 2, 4, 5 and 7 in which the V-phase lower arm is selected, whether the current detector corresponding to the V-phase lower arm is defective or normal. Is determined. As shown in FIG. 3, the test patterns 2, 4, 5 and 7 are all patterns in which the "V-phase lower arm" is selected.

First, in step S618, it is determined whether or not all of the test patterns 2, 4, 5 and 7 are failure determinations. That is, in step S618, it is determined whether or not "failure" is stored in all of the test patterns 2, 4, 5 and 7 in the TP determination result table.

Here, if "failure" is stored in all of the test patterns 2, 4, 5 and 7, the result is "YES" in step S618, and the process proceeds to step S619. In step S619, the "failure" is stored in the V-phase lower arm in the failure information table. After the execution of step S619, the process proceeds to step S620, and the test patterns 2, 4, 5 and 7 are set to prohibit evaluation.

On the other hand, when a value other than "failure" is stored in at least one of the test patterns 2, 4, 5 and 7, the result is "NO" in step S618, and the process proceeds to step S621. In step S621, it is determined whether or not all of the test patterns 2, 4, 5 and 7 are normal determinations. That is, in step S621, it is determined whether or not "normal" is stored in all of the test patterns 2, 4, 5 and 7 in the TP determination result table.

Here, when "normal" is stored in all of the test patterns 2, 4, 5 and 7, the result is "YES" in step S621, and the process proceeds to step S622. In step S622, "normal" is stored in the V-phase lower arm in the failure information table. On the other hand, when a value other than "normal" is stored in at least one of the test patterns 2, 4, 5, and 7, the result is "NO" in step S621, and the process proceeds to step S623. Even after the execution of step S620 or S622, the process proceeds to step S623.

Steps S623 to S627 are processes for determining whether or not the current detection unit corresponding to the W phase upper arm is out of order. Therefore, here, based on the evaluation results of the test patterns 1, 4, 6 and 7 in which the W phase upper arm is selected, whether the current detector corresponding to the W phase upper arm is defective or normal. Is determined. As shown in FIG. 3, the test patterns 1, 4, 6 and 7 are all patterns in which the "V-phase upper arm" is selected.

First, in step S623, it is determined whether or not all of the test patterns 1, 4, 6 and 7 are failure determinations. That is, in step S623, it is determined whether or not "failure" is stored in all of the test patterns 1, 4, 6 and 7 in the TP determination result table.

Here, if "failure" is stored in all of the test patterns 1, 4, 6 and 7, the result is "YES" in step S623, and the process proceeds to step S624. In step S624, "failure" is stored in the W phase upper arm in the failure information table. After the execution of step S624, the process proceeds to step S625, and test patterns 1, 4, 6 and 7 are set to prohibit evaluation.

On the other hand, when a value other than "failure" is stored in at least one of the test patterns 1, 4, 6 and 7, the result is "NO" in step S623, and the process proceeds to step S626. In step S626, it is determined whether or not all of the test patterns 1, 4, 6 and 7 are normal determinations. That is, in step S626, it is determined whether or not "normal" is stored in all of the test patterns 1, 4, 6 and 7 in the TP determination result table.

Here, when "normal" is stored in all of the test patterns 1, 4, 6 and 7, the result is "YES" in step S626, and the process proceeds to step S627. In step S627, "normal" is stored in the W phase upper arm in the failure information table. On the other hand, when a value other than "normal" is stored in at least one of the test patterns 1, 4, 6 and 7, the result is "NO" in step S626, and the process proceeds to step S628. Even after the execution of step S625 or S627, the process proceeds to step S628.

Steps S628 to S632 are processes for determining whether or not the current detection unit corresponding to the W phase lower arm is out of order. Therefore, here, based on the evaluation results of the test patterns 2, 3, 5, and 8 in which the W phase lower arm is selected, whether the current detector corresponding to the W phase lower arm is defective or normal. Is determined. As shown in FIG. 3, the test patterns 2, 3, 5 and 8 are all patterns in which the "W phase lower arm" is selected.

First, in step S628, it is determined whether or not all of the test patterns 2, 3, 5, and 8 are failure determinations. That is, in step S628, it is determined whether or not "failure" is stored in all of the test patterns 2, 3, 5, and 8 in the TP determination result table.

Here, if "failure" is stored in all of the test patterns 2, 3, 5 and 8, the result is "YES" in step S628, and the process proceeds to step S629. In step S629, "failure" is stored in the W phase lower arm in the failure information table. After the execution of step S629, the process proceeds to step S630, and the test patterns 2, 3, 5 and 8 are set to prohibit evaluation.

On the other hand, when a value other than "failure" is stored in at least one of the test patterns 2, 3, 5 and 8, the result is "NO" in step S628, and the process proceeds to step S631. In step S631, it is determined whether or not all of the test patterns 2, 3, 5 and 8 are normal determinations. That is, in step S631, it is determined whether or not "normal" is stored in all of the test patterns 2, 3, 5 and 8 in the TP determination result table.

Here, when "normal" is stored in all of the test patterns 2, 3, 5 and 8, the result is "YES" in step S631 and the process proceeds to step S632. In step S632, "normal" is stored in the W phase lower arm in the failure information table. On the other hand, when a value other than "normal" is stored in at least one of the test patterns 2, 3, 5 and 8, the result is "NO" in step S631 and the process ends. The process ends even after the execution of step S630 or S632.

In this embodiment, the combination of test patterns 1, 2, 7 and 8 corresponds to the combination of test patterns for identifying the failure or normality of the current detection unit corresponding to the U-phase upper arm. Further, the combination of the test patterns 3, 4, 5 and 6 corresponds to the combination of the test patterns for identifying the failure or normality of the current detection unit corresponding to the U-phase lower arm. Further, the combination of the test patterns 1, 3, 6 and 8 corresponds to the combination of the test patterns for identifying the failure or normality of the current detection unit corresponding to the V-phase upper arm. Further, the combination of the test patterns 2, 4, 5 and 7 corresponds to the combination of the test patterns for identifying the failure or normality of the current detection unit corresponding to the V-phase lower arm.

Further, the combination of the test patterns 1, 4, 6 and 7 corresponds to the combination of the test patterns for identifying the failure or normality of the current detection unit corresponding to the W phase upper arm. Further, the combination of the test patterns 2, 3, 5 and 8 corresponds to the combination of the test patterns for identifying the failure or normality of the current detection unit corresponding to the W phase lower arm.

According to the present embodiment described above, the following effects can be obtained.
The failure detection processing unit 29 represents eight test patterns 1 to 8 in which one of the upper and lower arms is selected for each phase of the three-phase half-bridge circuits 4u, 4v, and 4w, and the detection values of the current detection unit. A failure detection process for detecting a failure of the current detection unit based on the current detection signal Si is executed. The failure detection process includes a test pattern determination process and a final failure determination process. In the test pattern judgment process, a predetermined judgment operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm is subjected to the judgment calculation result. It is a process of determining whether or not a failure has occurred in the corresponding current detection unit. The final failure determination process is a process of detecting a failure of the current detection unit based on the result when the failure determination is established for at least one test pattern as a result of executing the test pattern determination process.

According to the above configuration, if any of the plurality of current detection units provided corresponding to each of the six arms constituting the half-bridge circuits 4u, 4v, and 4w fails, the drive control unit 28 will be used. The failure can be detected without being affected by the drive control of the motor 2. In the above configuration, when a failure determination is established for one test pattern, it can be specified that any of the current detection units provided corresponding to the arm selected in the test pattern has failed. Further, in the above configuration, when a failure determination is established for two or more test patterns, it is specified that one of the current detection units provided corresponding to the arms selected in all of the test patterns has failed. Can be done.

As described above, according to the above configuration, when a failure of the current detection unit is detected, the failed current detection unit can be identified, so that the drive control unit 28 has failed even after the failure detection. The drive control of the motor 2 can be continued by using the detection value of the current detection unit other than the specified current detection unit. Further, according to the above configuration, even after the failure is detected, the test pattern determination process is executed by using the test pattern excluding the test pattern in which the arm corresponding to the current detection unit identified as the failure is selected. Further failures of the current detection unit can be detected. Therefore, according to the above configuration, after detecting the failure of a predetermined current detection unit among the plurality of current detection units, it is possible to detect the failure of another current detection unit while continuing the control of the motor 2. The excellent effect is obtained.

In the final failure determination process of the present embodiment, when a failure determination is established for all the test patterns in which a predetermined arm is selected, it is specified that the current detection unit corresponding to the arm has failed. .. For example, when the failure determination is established for all the test patterns 1, 2, 7 and 8 in which the U-phase upper arm is selected, it is specified that the current detection unit corresponding to the U-phase upper arm has failed. Is. By doing so, it is possible to reliably identify the failed current detection unit.

In the final failure determination process, when the failure determination is established for two or more test patterns as a result of executing the test pattern determination process, the process of identifying the failed current detection unit is performed based on the results. It may be included. For example, when the failure determination is established for the two test patterns 1 and 2 in which the U-phase upper arm is selected, it may be specified that the current detection unit corresponding to the U-phase upper arm has failed. The reasons for this change are as follows.

That is, when the failure determination is established for the test patterns 1 and 2, not only the case where the current detection unit corresponding to the U-phase upper arm is failed, but also the case corresponding to each of the V-phase upper arm and the W-phase upper arm, respectively. It is also possible that at least one of the current detection units and at least one of the current detection units corresponding to the V-phase lower arm and the W-phase lower arm are out of order. However, since the current detection unit of the present embodiment adopting the current detection method using the sense cell 26 has a relatively low probability of failure, that is, a failure rate, a plurality of currents are detected at the same time in the configuration of the present embodiment. It is extremely unlikely that a part failure will occur. Therefore, even if the latter case is excluded from the above two cases, no major problem will occur. Therefore, when the failure determination is established for two or more test patterns in which a predetermined arm is selected, it is possible to identify the failed current detection unit based on the results.

In the final failure determination process of the present embodiment, when the failure determination is unsuccessful for all the test patterns in which a predetermined arm is selected, it is specified that the current detection unit corresponding to the arm is normal. It has become. For example, if the failure determination is unsuccessful for all the test patterns 1, 2, 7 and 8 for which the U-phase upper arm is selected, it is specified that the current detection unit corresponding to the U-phase upper arm is normal. , And so on. By doing so, it is possible to reliably identify the normal current detection unit.

The final failure determination process is a process for identifying a normal current detection unit based on the results when the failure determination is unsuccessful for two or more test patterns as a result of executing the test pattern determination process. May be included. For example, if the failure determination is unsuccessful for the two test patterns 1 and 2 in which the U-phase upper arm is selected, even if it is specified that the current detection unit corresponding to the U-phase upper arm is normal. good.

In the present embodiment, the combination of test patterns for identifying the failure or normality of a predetermined current detection unit is different from the combination of test patterns for identifying the failure or normality of other current detection units, and the combination thereof. Not included in. Then, when a failure of a predetermined current detection unit is detected as a result of executing the final failure determination process, in the test pattern determination process executed thereafter, the arm corresponding to the current detection unit in which the failure is detected is detected. The test pattern for which is selected is excluded from the judgment target. By doing so, even after the failure of one current detection unit is detected, the same failure detection process as before is continuously executed, so that further failure of the current detection unit can be detected and at the same time. The failed current detector can be identified. According to the present embodiment, it is possible to detect up to two failures of the current detection unit at the maximum.

For example, if the current detection unit corresponding to the W phase lower arm fails and the failure is detected, the test patterns 2, 3, 5 and 8 are set to "evaluation prohibited", and the test patterns executed thereafter are set to "evaluation prohibited". Excluded from the judgment target in the judgment process. Therefore, in the failure determination process executed thereafter, only four test patterns 1, 4, 6 and 7 are used, but in the test patterns 1, 4, 6 and 7, the W phase lower arm is excluded. All five arms are selected. Therefore, by performing the failure determination process using these four test patterns 1, 4, 6 and 7, the failure of the current detection unit corresponding to each of the remaining five arms is detected, and the failed current is detected. The detection unit can be specified.

The eight test patterns 1 to 8 used in the failure detection process of the present embodiment are set so as to include a selectable combination of arms in just proportion. By doing so, it is possible to detect the failure of the current detection unit without being affected by the drive state of the six arms, that is, the drive control of the motor 2 by the drive control unit 28.

In the failure detection process of the present embodiment, the final failure determination process is executed after the test pattern determination process is executed for all of the eight test patterns 1 to 8. By doing so, the final failure determination process is executed in a state where the evaluation results of all the test patterns 1 to 8 are available, so that the frequency of erroneous determination of the failure determination of the current detection unit can be suppressed to a low level. As a result, the accuracy of failure detection can be improved.

In the failure detection process of the present embodiment, when the failure determination is unsuccessful for all the test patterns 1 to 8 as a result of executing the test pattern determination process, it is detected that all the current detection units are normal. A process (hereinafter referred to as a normality determination process) is included, and the normality determination process is executed at the beginning of the final failure determination process. As described above, the failure rate of the current detection unit of the present embodiment is relatively low. Therefore, if the normality determination process is executed at the beginning of the final failure determination process, the processes after the normality determination process will not be executed as long as all the current detection units are normal. Therefore, according to such a configuration, the effect that the processing load of the control circuit 17 during normal operation can be reduced can be obtained.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIG.
In the second embodiment, the content of the failure detection process is different from that in the first embodiment. The configuration of the motor control system 1 is the same as that of the first embodiment.

The failure detection process includes a process of storing a determination history indicating whether or not the test pattern determination process has been executed for each of the test patterns. In this case, the content recorded in the TP determination result table represents the determination history. That is, when "normal" or "failure" is stored in the TP determination result table, it corresponds to a state in which the determination history indicating that the test pattern determination process has been executed is stored.

Further, when "unevaluated" is stored in the TP determination result table, it corresponds to a state in which the determination history indicating that the test pattern determination process is not executed is stored. Therefore, steps S402 and S403 shown in FIG. 7 correspond to the process of storing the determination history. Further, in this case, step S700 in the failure determination process corresponds to the process of initializing all the above-mentioned determination histories after the execution of the final failure determination process.

In the failure detection process of the present embodiment, the test pattern determination process is not executed again for the test pattern in which the determination history indicating that the test pattern determination process has been executed is stored. Hereinafter, such a failure determination process of the present embodiment will be described with reference to FIG.

As shown in FIG. 10, the failure detection process of the present embodiment differs from the failure detection process of the first embodiment in that step S250 is added. Step S250 is executed when the determined test pattern is available, that is, when "YES" is obtained in step S200. In step S250, it is determined whether or not the determined test pattern has already executed the test pattern determination process, that is, whether or not the determination has been completed.

As described above, such a determination is made based on the contents recorded in the TP determination result table. Here, if the determined test pattern is one in which "normal" or "failure" is stored in the TP determination result table, "YES" is set in step S250, and the process ends as it is. On the other hand, if the determined test pattern has "unevaluated" stored in the TP determination result table, the result is "NO" in step S250, and the process proceeds to step S300. Since the processing after step S300 is the same as that of the first embodiment, the description thereof will be omitted.

As described above, in the failure detection process of the present embodiment, when the test pattern determination process using a predetermined test pattern is executed, the same test pattern is used until the final failure determination process is executed thereafter. The test pattern judgment process used is not executed. Therefore, according to the present embodiment, the test pattern determination processing using the same test pattern is not executed in duplicate, and the effect that the processing load of the control circuit 17 is reduced by that amount can be obtained. ..

(Third Embodiment)
Hereinafter, the third embodiment will be described with reference to FIGS. 11 and 12.
In the third embodiment, the content of the failure detection process is different from that in the first embodiment. The configuration of the motor control system 1 is the same as that of the first embodiment.

In the failure detection process of each of the above embodiments, the final failure determination process is executed after the test pattern determination process is executed for all of the test patterns 1 to 8. Here, the test patterns 1 to 8 are set so as to include a selectable combination of arms in just proportion. Therefore, in the failure determination process of each of the above embodiments, the test pattern determination process for all the test patterns 1 to 8 is executed, and a period corresponding to at least one cycle of motor control is required until the evaluation results are obtained. It will be necessary.

For this reason, in the failure detection process of each of the above embodiments, it takes a relatively long time until the final failure detection process is executed and it is finally determined whether or not the current detection unit has failed. As a result, there was room for improvement in terms of the responsiveness of failure detection. Therefore, in the present embodiment, the following measures have been added in order to further improve the responsiveness of failure detection.

That is, as shown in FIG. 11, one cycle of the voltage command value (hereinafter, also referred to as the AC voltage command value) that commands the AC voltage of the U phase, the V phase, and the W phase is 6 based on the magnitude relationship of each phase. It can be divided into two areas 1 to 6. The voltage command value is generated by the drive control unit 28 based on the current detection signal Si, the position detection signal Sp, the torque command signal St, and the like, and one cycle thereof is the three-phase AC voltage command value. It corresponds to one cycle.

The triangular wave in FIG. 11 is used to turn on / off the power elements 19 to 24 by the triangular wave comparison PWM method, which is a well-known PWM modulation technique. Then, ON / OFF of the power elements 19 to 24 is determined by the magnitude relationship between the voltage command value and the triangular wave. Specifically, during the period when the voltage command value exceeds the triangular wave, the power element (19, 21, 23) of the upper arm is turned on and the power element (20, 22, 24) of the lower arm is turned off. Further, during the period when the voltage command value is lower than the triangular wave, the power element (20, 22, 24) of the lower arm is turned on and the power element (19, 21, 23) of the upper arm is turned off.

The test pattern that can be taken in each region, that is, determined from the combination of arms that are on, is as shown in FIG. That is, test patterns 1, 8, 3 and 5 in region 1, test patterns 1, 6, 3 and 5 in region 2, test patterns 1, 6, 4 and 5 in region 3, and test patterns 1, 7, 7 in region 4. Test patterns 1, 7, 2 and 5 in regions 4 and 5, and test patterns 1, 8, 2 and 5 in region 6 are possible test patterns.

Here, there is the following characteristic relationship between the regions 1 to 6 and the possible test patterns. First, the first characteristic relationship is that "all test patterns appear in one cycle of the voltage command value". The second characteristic relationship is that "when the area is switched, only one test pattern is switched from the set of test patterns that can be taken in the immediately preceding area". In the failure detection process of the present embodiment, it is possible to make good use of such a characteristic relationship and further improve the responsiveness of failure detection. Hereinafter, the failure detection process of the present embodiment will be described with reference to FIG.

As shown in FIG. 12, the failure detection process of the present embodiment differs from the failure detection process of the first embodiment in that steps S10 and S20 are added, steps S700 are omitted, and the like. In this case, when the failure detection process is started, step S10 is executed first.

In step S10, it is determined whether or not the region has changed, that is, whether or not the region has changed, based on the change in the magnitude relation of the voltage command values of the three phases. Here, when the region changes, "YES" is set in step S10, and step S20 is executed before proceeding to step S100. On the other hand, if the region has not changed, the result is "NO" in step S10, and the process proceeds to step S100 without executing step S20.

In step S20, the failure determination of the test pattern that is a test pattern that can be taken in the region after the transition, that is, the current region, and that can be evaluated is initialized. Specifically, in step S20, the test patterns that can be taken in the region after the transition are initialized so that each value in the TP determination result table becomes “unevaluated”. However, the value of the test pattern set to "evaluation prohibited" is not initialized, and the value as it is, that is, "failure" is maintained.

Such step S20 corresponds to the process of initializing the determination history for the test pattern in which the combination of arms that can be driven on in the region after the transition is selected when the region transitions. In the present embodiment, by adding steps S10 and S20, the determination history of the test pattern that can be taken in the region after the transition is initialized every time the region transitions, that is, every 1/6 cycle of the motor control. It has become like. Therefore, in the present embodiment, it is not necessary to initialize the determination history after the execution of the final failure determination process, and step S700 is omitted. Therefore, in the present embodiment, the process ends after the execution of step S600.

As described above, in the failure detection process of the present embodiment, the addition of steps S10 and S20 causes the determination history of the test pattern that can be taken in the region after the transition to be initialized every time the region transitions. ing. As a result, for example, when transitioning from the area 6 to the area 1, only the judgment histories of the test patterns 1, 8, 3 and 5 that can be taken in the area 1 are initialized, and the other test patterns 2, 4, 6 and 7 are judged. The history is maintained without being initialized.

After that, by executing the processes of steps S100 to S500, new determination results (evaluation results) for the test patterns 1, 8, 3 and 5 that can be taken in the region 1 are acquired. Then, in the final failure determination process of step S600, the new determination results of the test patterns 1, 8, 3 and 5 that can be taken in the region 1 and the other test patterns 2, 4, 6 and 7 are acquired one cycle before. The final failure determination for each current detection unit is executed using the old determination result.

According to the failure detection process of the present embodiment as described above, the final failure determination for each current detection unit is executed every 1/6 cycle of the three-phase AC voltage command value. Therefore, according to the present embodiment, as compared with each of the above-described embodiments, the time required for finally determining whether or not the current detection unit has failed is shortened, so that the responsiveness of failure detection is improved. The effect of being able to do is obtained.

(Fourth Embodiment)
Hereinafter, the fourth embodiment will be described with reference to FIGS. 13 to 16.
In the fourth embodiment, the content of the failure detection process is different from that in the first embodiment. The configuration of the motor control system 1 is the same as that of the first embodiment.

In the test pattern of the present embodiment, one of the upper and lower arms is selected for each phase of the two phases of the three-phase half-bridge circuit 4u, 4v, and 4w, and the test pattern is as shown in FIG. 13, for example. There is. In this case, the test pattern No. Reference numeral 1 is a pattern in which the U-phase upper arm and the V-phase lower arm are selected. Test pattern No. Reference numeral 2 is a pattern in which the U-phase upper arm and the W-phase lower arm are selected. Test pattern No. Reference numeral 3 is a pattern in which the V-phase upper arm and the W-phase lower arm are selected. Test pattern No. Reference numeral 4 is a pattern in which the U-phase lower arm and the V-phase upper arm are selected.

Test pattern No. Reference numeral 5 is a pattern in which the U-phase lower arm and the W-phase upper arm are selected. Test pattern No. Reference numeral 6 is a pattern in which the V-phase lower arm and the W-phase upper arm are selected. Test pattern No. Reference numeral 7 is a pattern in which the U-phase upper arm and the V-phase upper arm are selected. Test pattern No. Reference numeral 8 is a pattern in which the U-phase upper arm and the W-phase upper arm are selected.

Test pattern No. Reference numeral 9 is a pattern in which the V-phase upper arm and the W-phase upper arm are selected. Test pattern No. Reference numeral 10 is a pattern in which the U-phase lower arm and the V-phase lower arm are selected. Test pattern No. Reference numeral 11 is a pattern in which the U-phase lower arm and the W-phase lower arm are selected. Test pattern No. Reference numeral 12 is a pattern in which the V-phase lower arm and the W-phase lower arm are selected.

As described above, the 12 test pattern Nos. 1-No. Reference numeral 12 is set so that the combination of selectable arms is included in just proportion. In the following description, the test pattern No. 1-No. Twelve are also referred to as test patterns 1 to 12, respectively.

In FIG. 13, each test pattern 1 to 12 is associated with a determination target in the test pattern determination process. That is, in the test pattern determination process using the test pattern 1, the failure determination (evaluation) of the current detection unit corresponding to the U-phase upper arm and the V-phase lower arm is performed. In the test pattern determination process using the test pattern 2, the failure determination of the current detection unit corresponding to the U-phase upper arm and the W-phase lower arm is performed. In the test pattern determination process using the test pattern 3, the failure determination of the current detection unit corresponding to the V-phase upper arm and the W-phase lower arm is performed. In the test pattern determination process using the test pattern 4, the failure determination of the current detection unit corresponding to the U-phase lower arm and the V-phase upper arm is performed.

In the test pattern determination process using the test pattern 5, the failure determination of the current detection unit corresponding to the U-phase lower arm and the W-phase upper arm is performed. In the test pattern determination process using the test pattern 6, the failure determination of the current detection unit corresponding to the V-phase lower arm and the W-phase upper arm is performed. In the test pattern determination process using the test pattern 7, the failure determination of the current detection unit corresponding to the U-phase upper arm and the V-phase upper arm is performed. In the test pattern determination process using the test pattern 8, the failure determination of the current detection unit corresponding to the U-phase upper arm and the W-phase upper arm is performed.

In the test pattern determination process using the test pattern 9, the failure determination of the current detection unit corresponding to the V phase upper arm and the W phase upper arm is performed. In the test pattern determination process using the test pattern 10, failure determination of the current detection unit corresponding to the U-phase lower arm and the V-phase lower arm is performed. In the test pattern determination process using the test pattern 11, the failure determination of the current detection unit corresponding to the U-phase lower arm and the W-phase lower arm is performed. In the test pattern determination process using the test pattern 12, the failure determination of the current detection unit corresponding to the V-phase lower arm and the W-phase lower arm is performed.

The determination result by the test pattern determination process as described above is stored as, for example, a table as shown in FIG. 14 (hereinafter, also referred to as a TP determination result table). The table shown in FIG. 14 is stored in, for example, a storage area secured on a memory included in the control circuit 17. In the table shown in FIG. 14, "normal", "failure", or "unevaluated" is stored as a determination result corresponding to each of the test patterns 1 to 12. In addition, each of these values represents the same content as each value of the TP determination result table of the first embodiment.

In the example shown in FIG. 14, the failure determination is unsuccessful in the test pattern determination process performed using the test patterns 1 and 2, and the failure determination is performed in the test pattern determination process performed using the test patterns 3 to 6. The contents indicate that the above is satisfied and that the test pattern determination process using the test patterns 7 to 12 has not been performed.

As shown in FIG. 15, there are eight combinations of on-drive of each arm of the half-bridge circuits 4u, 4v, and 4w. In this embodiment, there are three test patterns that can be implemented for each of these combinations. For example, when the U-phase upper arm, the V-phase lower arm, and the W-phase lower arm are driven on, the test patterns that can be implemented (possible) are test patterns 1, 2, and 12.

In the test pattern determination process of the present embodiment, as a determination operation, the other one is based on the detection value of the current detection unit corresponding to the two arms during the period when the two arms selected in the test patterns 1 to 12 are turned on. The d-axis current value and the q-axis current value are calculated by estimating the current flowing through the arms and performing dq conversion using the detected value of the current flowing through the two arms and the estimated value of the current flowing through one arm. Then, in the test pattern determination process of the present embodiment, each change amount of the d-axis current value and the q-axis current value is compared with a predetermined determination threshold value, and two arms are supported based on the comparison result. It is designed to determine whether or not a failure has occurred in the current detection unit.

The specific contents of the test pattern determination process of the present embodiment will be described with reference to FIG. As shown in FIG. 16, in step S441, the detection value of the current detection unit corresponding to the two arms selected in the current test pattern, that is, the two current detection values read in step S300 are used for another. The current flowing through one arm is estimated.

As described above, in the configuration of the present embodiment, the total sum of the three-phase currents is zero unless a failure has occurred in each current detection unit or the like. Therefore, the current flowing through the other one arm is a value obtained by inverting the signs of the two detected current detection values and adding them together. For example, when the W phase current is estimated from the detected value iU of the U phase current and the detected value iV of the V phase current, the estimated value iW of the W phase current is expressed by the following equation (1).
iW = -iU-iV ... (1)

In the present embodiment, since the current flowing through the other one arm is estimated as described above, the absolute value of the total sum of the acquired three-phase currents is always zero. Therefore, in the present embodiment, the same method as that of the first embodiment or the like, that is, a method of comparing the absolute value of the total sum of the three-phase currents with the determination threshold value cannot be adopted. Therefore, in the present embodiment, the following failure determination method is used.

That is, in step S442, the d-axis current value id and the q-axis current value iq are obtained by performing dq conversion using the three-phase current values iu, iv, iwa and the electric angle θ. The electric angle θ can be obtained by multiplying the position detection signal Sp by the number of pole pairs of the motor 2. The d-axis current value id and the q-axis current value iq are expressed by the following equation (2).

The d-axis current value id and the q-axis current value iq are particularly large when the torque command signal St representing the torque command value (d-axis current command value, q-axis current command value) continues to be unchanged. It doesn't change. This is because the drive control unit 28 feedback-controls (vector control) the drive of the motor 2 so that the d-axis current value id and the q-axis current value iq match the d-axis current command value and the q-axis current command value, respectively. Because it is doing.

Focusing on such a point, in step S443, it is determined whether or not the torque command signal St has changed for a predetermined time or more. The predetermined time can be set to, for example, the step response time. Whether or not the torque command signal St has changed is determined by the torque command value (previous value) represented by the previously acquired torque command signal St and the torque command value (current value) represented by the torque command signal St acquired this time. It can be judged from the difference with.

Here, if the torque command signal St has not changed for a predetermined time or longer, "YES" is set in step S443, and the processes of steps S444 to S446 are performed. On the other hand, if the torque command signal St has not changed for a predetermined time or longer, the process proceeds to step S447 without processing of steps S444 to S446.

In step S444, it is determined whether or not the amount of change in the d-axis current value id is less than the predetermined determination threshold value Td, and whether or not the amount of change in the q-axis current value iq is less than the predetermined determination threshold value Tq. Is judged. The amount of change in the d-axis current value id and the q-axis current value iq can be obtained as the absolute value of the difference between the previous value and the current value.

Due to the influence of various errors in the configuration related to current detection, it is conceivable that the amount of change may not be completely zero even when the current detection unit is normal. Therefore, in the present embodiment, the determination threshold values Td and Tq are set to values that do not cause erroneous determination due to the influence of such an error, for example, values that are larger than zero by a predetermined margin.

Here, if the amount of change in the d-axis current value id is less than the determination threshold value Td and the amount of change in the q-axis current value iq is less than the determination threshold value Tq, the result is “YES” in step S444, and the process proceeds to step S445. Step S445 is the same process as step S402 shown in FIG. 7, and "normal" is stored as the determination result of the current test pattern in the TP determination result table.

On the other hand, if at least one of the amount of change in the d-axis current value id and the amount of change in the q-axis current value iq is equal to or higher than the determination threshold values Td and Tq, the result is “NO” in step S444, and the process proceeds to step S446. Step S446 is the same process as step S403 shown in FIG. 7, and "failure" is stored as the determination result of the current test pattern in the TP determination result table.

After executing step S445 or S446, the process proceeds to step S447. In step S447, the torque command value represented by the torque command signal St acquired in the test pattern determination process this time, and the d-axis current value id and the q-axis current value iq obtained in the test pattern determination process this time are obtained. It is stored as the previous value. Each previous value stored here will be used in the test pattern determination process to be executed next time.

Although not shown, the final failure determination process of the present embodiment is modified in consideration of the fact that the test pattern is changed with respect to the final failure determination process of the first embodiment shown in FIGS. 8 and 9. It is an added content.

The same effect as that of the first embodiment can be obtained by the present embodiment described above. Further, in the failure detection process of the present embodiment, the failure determination of the current detection unit is performed using the detection values of the two-phase currents, so that when the two current detection units corresponding to the upper and lower arms of one phase fail. However, the control of the system is continued by using the current detection unit corresponding to the remaining two phases, and further failure can be detected, so that the effect of further improving the reliability of the system can be obtained.

Note that step S443 shown in FIG. 16 may be omitted depending on the settings of the determination threshold values Td and Tq. This is because the amount of change in the d-axis current value id and the q-axis current value iq does not become an extremely large value in the normal control state, but in an abnormal state in which an abnormality such as a failure occurs in the current detection unit occurs. Is likely to be an extremely large value. Therefore, if the determination threshold values Td and Tq are set to the upper limit of the amount of change in the normal control state plus a predetermined margin and step S443 is omitted, the torque command value (torque command signal St) changes. It is possible to always determine the failure regardless of the period when there is no such thing.

In the test pattern determination process of the present embodiment, at least one of the change amount of the d-axis current value id and the change amount of the q-axis current value iq is compared with the predetermined determination threshold value, and 2 is based on the comparison result. It suffices to determine whether or not the current detection unit corresponding to one arm has a failure. Specifically, in step S444 shown in FIG. 16, the determination may be changed to use only one of the d-axis current value id and the q-axis current value iq. By doing so, the calculation load (processing load) in the control circuit 17 is reduced, although the accuracy of the determination is slightly lower than the determination using both the d-axis current value id and the q-axis current value iq. The effect is obtained.

(Fifth Embodiment)
Hereinafter, the fifth embodiment will be described with reference to FIGS. 17 and 18.
In the fifth embodiment, the content of the test pattern determination process is different from that in the first embodiment. The configuration of the motor control system 1 is the same as that of the first embodiment.

In the test pattern determination process of the present embodiment, the determination operation is executed a plurality of times for the same test pattern, and the determination is performed based on the average value of the results of the plurality of determination operations, more specifically, the moving average. It has come to be. The test pattern determination process of the present embodiment as described above is specifically a process as shown in FIG.

First, in step S451, the sum of the detection values of the current detection units corresponding to the three arms selected in the test pattern (hereinafter referred to as the current test pattern) to be determined in the test pattern determination process, that is, 3 The absolute value of the sum of the phase currents is calculated. In step S452, the value calculated in step S451 is stored in the queue assigned to the current test pattern.

The operation of the queue will be described with reference to FIG. In the present embodiment, eight shift registers are facilitated for each of the test patterns 1 to 8, and eight values are stored. For example, when the current test pattern is test pattern 1, the shift register assigned to test pattern 1 is shifted to the right by one, the oldest value is deleted, and a free register (the leftmost queue in FIG. 18) is created. ) Will store the latest value calculated in step S451.

In step S453, it is determined whether or not the values are stored in all the registers of the queue. Such a determination can be made, for example, by counting the number of times the process of step S452 is executed and whether or not the count value becomes the number of shift registers (= 8) or more. Here, if the values are stored in all the registers of the queue, the result is "YES" in step S435, and the process proceeds to step S454. On the other hand, if the value is not stored in at least one register among all the registers in the queue, the result is "NO" in step S453, and the process ends as it is.

In step S454, the average value of the data (values) in the queue allocated to the current test pattern is calculated. After the execution of step S454, the process proceeds to step S455, and it is determined whether or not the average value calculated in step S454 is equal to or less than a predetermined determination threshold value. In this case, the determination threshold value can be set in the same manner as the determination threshold value in the first embodiment.

If the average value is equal to or less than the determination threshold value, the result is “YES” in step S455, and the process proceeds to step S456. Step S456 is the same process as step S402 shown in FIG. 7, and "normal" is stored as the determination result of the current test pattern in the TP determination result table.

On the other hand, if the average value is larger than the determination threshold value, the result becomes "NO" in step S455, and the process proceeds to step S457. Step S457 is the same process as step S403 shown in FIG. 7, and "failure" is stored as the determination result of the current test pattern in the TP determination result table. After the execution of step S456 or S457, the test pattern determination process ends.

The same effect as that of the first embodiment can be obtained by the present embodiment described above. Further, in the test pattern determination process of the present embodiment, after calculating the absolute value of the total sum of the three-phase currents, a moving average (simple moving average) is taken and the value is not immediately compared with the determination threshold value. By comparing with the determination threshold value, the failure determination is performed. In this way, if the absolute value of the total sum of the three-phase currents suddenly (temporarily) becomes an abnormal value due to the influence of noise or the like, it is erroneously determined that the current detection unit has failed. It will never happen. That is, according to the present embodiment, there is an effect that the occurrence of erroneous determination can be suppressed low in the failure determination of the current detection unit.

(Sixth Embodiment)
Hereinafter, the sixth embodiment will be described with reference to FIGS. 19 to 21.
In the sixth embodiment, the content of the test pattern determination process is different from that in the first embodiment. The configuration of the motor control system 1 is the same as that of the first embodiment.

As shown in FIG. 19, the test patterns 1 to 8 used in the first embodiment and the like include a specific combination including all of the six arms constituting the three-phase half-bridge circuits 4u, 4v, and 4w. (Pair) exists. Specifically, test patterns 1 and 5, test patterns 2 and 6, test patterns 3 and 7, and test patterns 4 and 8 correspond to a combination in which all six arms are included. Hereinafter, the combination (pair) of these test patterns is also referred to as a specific test pattern pair.

When both evaluation results (judgment results) are "normal" for such a specific test pattern pair, it can be said that all of the current detection units corresponding to the six arms are normal. Focusing on such a point, in the failure detection process of the present embodiment, a device for reducing the processing load in the control circuit 17 or the like in the normal state is added.

That is, in the failure detection process of the present embodiment, when the failure determination is not established for a specific test pattern pair as a result of executing the test pattern determination process, it is detected that all the current detection units are normal. Processing is included. Hereinafter, the specific contents of the failure processing of the present embodiment will be described with reference to FIG. 20.

As shown in FIG. 20, in the failure detection process of the present embodiment, steps S460, S470 and S480 are added to the failure detection process of the first embodiment. Step S460 is to be executed after the execution of step S400. In step S460, it is determined whether or not the evaluation is completed for at least one of the four specific test pattern pairs.

Here, if the evaluation is not completed for any of the specific test pattern pairs, the result is "NO" in step S460, and the process ends as it is. On the other hand, if the evaluation is completed for at least one of the specific test pattern pairs, the result is "YES" in step S460, and the process proceeds to step S470. In step S470, it is determined whether or not all of the test pattern pairs for which evaluation has been completed are normal determination. It should be noted that such a determination can be made using the TP determination result table.

Here, if a value other than "normal" is stored in at least one of the test pattern pairs for which evaluation has been completed, the result is "NO" in step S470, and the process proceeds to step S500. On the other hand, when "normal" is stored in all the test pattern pairs for which the evaluation is completed, "YES" is set in step S470, and the process proceeds to step S480. Step S480 is the same process as step S602 shown in FIG. 8, and "normal" is stored for all the arms that are not stored as "failure" in the failure information table. After the execution of step S480, the process proceeds to step S700.

In the present embodiment, the final failure determination process is also changed due to the above-mentioned change in the failure detection process. That is, as shown in FIG. 21, in the final failure determination process of the present embodiment, steps S601 and S602 are omitted with respect to the final failure determination process of the first embodiment. In this case, when the final failure determination process is started, step S603 is executed first.

The same effect as that of the first embodiment can be obtained by the present embodiment described above. Further, in the failure detection process of the present embodiment, when the evaluation results of both of the specific test pattern pairs including all of the six arms are "normal", it is detected that all the current detection units are normal. It has become like. According to such a configuration, it is possible to reduce the number of test patterns to be used (execute the test pattern determination process) to a minimum of two under normal conditions where no failure has occurred in the current detection unit, which is normal. The effect that the processing load of the control circuit 17 and the like at the time can be further reduced can be obtained.

(Other embodiments)
It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, and can be arbitrarily modified, combined, or extended without departing from the gist thereof.
The numerical values and the like shown in each of the above embodiments are examples and are not limited thereto.

The present invention is not limited to the power converter 3 used in the motor drive system 1 described in each of the above embodiments, and can be applied to all power converters that drive a three-phase AC motor.
The detection circuits 5 to 10 may be configured to detect currents flowing through the upper arm and the lower arm of the half-bridge circuits 4u, 4v, and 4w, and the specific configuration thereof can be appropriately changed.
The switching elements constituting the half-bridge circuits 4u, 4v, and 4w are not limited to the power elements 19 to 24 which are power MOSFETs, and various power elements such as IGBTs, that is, power devices can be used.

The present disclosure has been described in accordance with the examples, but it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various variations and variations within a uniform range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are within the scope and scope of the present disclosure.

2 ... Motor, 3 ... Power converter, 4u, 4v, 4w ... Half-bridge circuit, 5-10 ... Detection circuit, 26 ... Sense cell, 28 ... Drive control unit, 29 ... Failure detection processing unit.

Claims (17)

A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
In the final failure determination process, when failure determination is established for two or more test patterns as a result of executing the test pattern determination process, the current detection unit that has failed is specified based on the results. A power converter that contains processing. The combination of two or more test patterns for identifying the failure of the predetermined current detector is different from the combination of the two or more test patterns for identifying the failure of the other current detector. The power converter according to claim 1 , which is not included in the combination. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
In the final failure determination process, when the failure determination is unsuccessful for two or more test patterns as a result of executing the test pattern determination process, the normal current detection unit is specified based on the results. A power converter that contains processing. The combination of two or more test patterns for identifying the normality of the predetermined current detection unit is different from the combination of the two or more test patterns for identifying the normality of the other current detection unit. The power converter according to claim 3 , which is not included in the combination. The power converter according to any one of claims 1 to 4 , wherein the plurality of test patterns are set so as to include a selectable combination of arms in just proportion. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
When a failure of the predetermined current detection unit is detected as a result of executing the final failure determination process, the test pattern determination process executed thereafter corresponds to the current detection unit in which the failure is detected. A power converter whose arm is excluded from the judgment target for the selected test pattern. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
The final failure determination process is a power converter executed after the test pattern determination process is executed for all of the plurality of test patterns. The failure detection process includes a process of detecting that all the current detection units are normal when the failure determination is unsuccessful for all the test patterns as a result of executing the test pattern determination process. The power converter according to any one of claims 1 to 7. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
In the failure detection process, when a failure determination is not established for a specific combination of the test patterns as a result of executing the test pattern determination process, a process for detecting that all the current detection units are normal. Is included,
A power converter in which the arms selected in the test pattern of the particular combination include all the arms that make up the three-phase half-bridge circuit. The failure detection process includes a process of storing a determination history indicating whether or not the test pattern determination process has been executed for each of the test patterns.
According to any one of claims 1 to 9 , the test pattern determination process for which the determination history is stored, which indicates that the test pattern determination process has been executed, is not executed again. The power converter described. The power converter according to claim 10 , wherein the failure detection process includes a process of initializing all the determination histories after the execution of the final failure determination process. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
The failure detection process includes a process of storing a determination history indicating whether or not the test pattern determination process has been executed for each of the test patterns.
The test pattern determination process is not executed again for the test pattern in which the determination history indicating that the test pattern determination process has been executed is stored.
When one cycle of the voltage command value that commands the three-phase AC voltage output from the three-phase half-bridge circuit is divided into six regions based on the magnitude relationship of each phase,
The failure detection process includes a process of initializing the determination history of the test pattern for which a combination of the arms that can be driven on in the region after the transition when the region transitions is selected. vessel. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
In the test pattern, one of the upper and lower arms is selected for each phase of the three phases of the half-bridge circuit.
In the test pattern determination process,
As the determination calculation, the absolute value of the sum of the detection values of the current detectors corresponding to the three arms during the period when the three arms selected in the test pattern are turned on is calculated.
A power converter that compares the absolute value with a predetermined determination threshold value and determines whether or not a failure has occurred in the current detection unit corresponding to the three arms based on the comparison result. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
In the test pattern, one of the upper and lower arms is selected for each phase of the two phases of the three-phase half-bridge circuit.
In the test pattern determination process,
As the determination calculation, the current flowing through the other arm is estimated based on the detection value of the current detection unit corresponding to the two arms during the period when the two arms selected in the test pattern are turned on. The d-axis current value and the q-axis current value are calculated by dq conversion using the detected value of the current flowing through the two arms and the estimated value of the current flowing through the one arm.
At least one of the change amount of the d-axis current value and the change amount of the q-axis current value is compared with a predetermined determination threshold value, and based on the comparison result, the current detection unit corresponding to the two arms fails. A power converter that determines whether or not is occurring. The drive control unit has a configuration that controls the drive of the three-phase AC motor based on a torque command value that commands the torque of the three-phase AC motor.
The power converter according to claim 14 , wherein in the test pattern determination process, the determination is performed when the torque command value does not change for a predetermined period or longer. A power converter (3) that drives a three-phase AC motor (2).
A three-phase half-bridge circuit (4u, 4v, 4w) that generates a three-phase current to be supplied to the three-phase AC motor, and
A current detector (5-10, 26) for detecting the current flowing through the upper arm and the lower arm of the half-bridge circuit, and
A drive control unit (28) that controls the drive of the three-phase AC motor by controlling the operation of the half-bridge circuit based on the detection value of the current detection unit.
A failure detection process for detecting a failure of the current detection unit is executed based on a plurality of test patterns in which one of the upper and lower arms is selected for each phase of at least two phases of the half-bridge circuit and the detection value of the current detection unit. Failure detection processing unit (29)
Equipped with
For the failure detection process,
A predetermined determination operation is executed using the detection value of the current detection unit corresponding to the arm during the period when the arm selected in the predetermined test pattern is turned on, and the arm corresponds to the arm based on the result of the determination operation. A test pattern determination process for determining whether or not a failure has occurred in the current detection unit.
When a failure determination is established for at least one test pattern as a result of executing the test pattern determination process, a final failure determination process for detecting a failure of the current detection unit based on the result is included .
In the test pattern determination process,
The determination operation is executed a plurality of times for the same test pattern, and the determination operation is executed a plurality of times.
A power converter in which the determination is made based on the average value of the results of the determination operations a plurality of times. The power converter according to claim 16 , wherein the average value is a moving average.

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