JP6131940B2 - Inverter failure detection method and inverter inspection device - Google Patents

Description

  The present invention relates to an inverter failure detection method, and more particularly to a technique for detecting a failure based on a current flowing through an inverter.

  Patent Document 1 describes a failure detection method for detecting an inverter failure. Patent Document 1 exemplifies a three-phase inverter. In this three-phase inverter, a pair of a high arm side switching element and a low arm side switching element connected in series with each other has three phases (U phase, V phase and W phase).

  In Patent Document 1, a control signal is output to an inverter so that a predetermined switching pattern is sequentially adopted by the inverter. And in each switching pattern, the location where the open failure has occurred is detected by detecting the current flowing through the inverter.

JP 2002-136147 A

  There is a demand for an inspection apparatus that can detect not only open faults but also short-circuit faults with a small switching pattern.

  In view of the above, an object of the present invention is to provide an inverter inspection device that can detect not only an open fault but also a short-circuit fault with a small switching pattern.

The first aspect of the inverter fault detection method according to the present invention includes a first DC line (LH) and a second DC line (LL), and an output terminal (Pu, Pv) of N (N is a natural number of 3 or more) phase. , Pw), a first switching element (Sup, Svp, Swp) connected between the first DC line and each of the output ends, and between the second DC line and each of the output ends. A device for inspecting an inverter (20) comprising a second switching element (Sun, Svn, Swn) connected to a kth (1 ≦ k ≦ N) phase with a load connected to the inverter The k-phase first switching element (Sup) connected to the output terminal and the m-th phase second switching element connected to the m-th (1 ≦ m ≦ N, m ≠ k) phase output terminal. a switching element (Svn) first switching pattern for conducting only (S1), is employed in the inverter, the current flowing through the second current line (Idc) is first A first range smaller than a quasi-value (Iref1), a second range between a second reference value (Iref2) greater than the first reference value and the first reference value, and a value greater than the second reference value It is determined which one of the large third ranges belongs, and when the current is determined to belong to the first range, the output terminal (Pu) of the k-th phase and the first DC line (LH) and at least one of the output terminal (Pv) of the m-th phase and the second DC line (LL) are detected, and the current is Because it is determined that the output belongs to three ranges, the output between the output terminals (Pv, Pw) other than the k-th phase and the first DC line (LH), and the output other than the m-th phase. end (Pu, Pw) and at least detects a short-circuit failure in any one, k, the in-sequentially changing the value of m between the second DC line (LL) A plurality of switching patterns are employed in the data (20), and based on a result of the determination with respect to the current (Idc) for each switching pattern, a position of an open fault and a position of a short-circuit fault are detected, and the first Connected to the first switching element (Sup) of the kth phase and the output terminal (Pw) of the nth (1 ≦ n ≦ N, n ≠ m, n ≠ k) phase. The current (Idc) belongs to the second range and the other switching pattern (S3) in both of the second switching pattern (S2) for conducting only the second switching element (Swn). To S6), it is determined that the current belongs to the third range, and therefore a short-circuit fault between the output terminal (Pu) of the k-phase and the first DC line (LH) is caused. Detect .

A second aspect of the inverter of the fault detection method according to the present invention, an inverter failure detecting method according to the first aspect, the first of said switching pattern (S1), before Symbol second switching element ( In both of the second switching pattern (S2) that conducts only Swn), the current (Idc) belongs to the first range, and in all the other switching patterns (S3 to S6), When it is determined that the current belongs to the second range, an open fault between the output terminal (Pu) of the k-th phase and the first DC line (LH) is detected.

The first aspect of the inverter inspection apparatus according to the present invention includes a first DC line (LH) and a second DC line (LL) and an output terminal (Pu, Pv, Pw) of N (N is a natural number of 3 or more) phase. ), A first switching element (Sup, Svp, Swp) connected between the first DC line and each of the output terminals, and between the second DC line and each of the output terminals An inverter (20) having a second switching element (Sun, Svn, Swn) connected, and the k-phase first switching element connected to the output terminal of the k-th (1 ≦ k ≦ N) phase (Sup) and a first switching pattern (S1) for conducting only the m-th phase second switching element (Svn) connected to the output terminal of the m-th (1 ≦ m ≦ N, m ≠ k) phase The inverter control unit (21) that employs the inverter, the current detection unit (50) that detects the current (Idc) flowing through the second DC line, and the current A first range smaller than the value (Iref1), a second range between the second reference value (Iref2) larger than the first reference value and the first reference value, and larger than the second reference value A current determination unit (22) for determining which of the third range belongs, and when the current belongs to the first range, the output terminal (Pu) of the k-th phase and the first DC It is determined that an open circuit fault has occurred between at least one of the line (LH) and between the output terminal (Pv) of the m-th phase and the second DC line (LL); When the current belongs to the third range, between the output terminals (Pv, Pw) other than the k-th phase and the first DC line (LH), and the outputs other than the m-th phase A fault detection unit (23) for determining that a short circuit fault has occurred in at least one of the ends (Pu, Pw) and the second DC line (LL), The unit sequentially changes the values of k and m to cause the inverter (20) to adopt a plurality of the switching patterns, and the failure detection unit determines the result of the determination on the current (Idc) for each switching pattern. And detecting a position of an open fault and a position of a short-circuit fault, and the fault detection unit detects the first switching pattern (S1), the first switching element (Sup) of the k-th phase, and the first a second switching pattern (S2) for conducting only the second switching element (Swn) connected to the output terminal (Pw) of the n (1 ≦ n ≦ N, n ≠ m, n ≠ k) phase; In both cases, it is determined that the current (Idc) belongs to the second range and that the current belongs to the third range in all the other switching patterns (S3 to S6). K-phase output terminal (Pu) and Detecting a short circuit fault between the serial first DC line (LH).

  A second aspect of the inverter inspection apparatus according to the present invention is the inverter inspection apparatus according to the first aspect, wherein the current determination unit (42) compares the current with the first reference value. A comparison unit (422); and a second comparison unit (421) for comparing the current and the second reference value, wherein the inverter control unit (41) is configured by the first comparison unit or the second comparison unit. Based on the comparison result, the inverter is stopped.

According to the first aspect of the inverter failure detection method of the present invention, the open failure range and the short-circuit failure can be detected with one switching pattern. In addition, the position of the open fault and the position of the short-circuit fault can be detected. Furthermore, the position of the short-circuit fault can be detected.

According to the second aspect of the inverter failure detection method of the present invention, the position of the open failure can be detected.

According to the first aspect of the inverter inspection apparatus of the present invention, the open fault range and the short-circuit fault range can be detected with one switching pattern. In addition, the position of the open fault and the position of the short-circuit fault can be detected. Furthermore, the position of the short-circuit fault can be detected.

  According to the 2nd aspect of the inverter test | inspection apparatus concerning this invention, the comparison result of a 1st comparison part or a 2nd comparison part is used for the condition determination for stopping an inverter. Therefore, the cost can be reduced as compared with the case where the comparator for determining the condition and the comparator for determining the open fault and the short-circuit fault are provided separately.

It is a figure which shows schematically an example of a structure of the inspection apparatus of an inverter. It is a figure which shows an example of an equivalent circuit schematically. It is a figure which shows an example of an equivalent circuit schematically. It is a figure which shows an example of an equivalent circuit schematically. It is a figure which shows an example of an equivalent circuit schematically. It is a figure which shows schematically an example of a structure of the inspection apparatus of an inverter.

  FIG. 1 is a diagram schematically showing an example of an inverter inspection device. In the illustration of FIG. 1, the inverter 20 includes three-phase legs 21 to 23 connected in parallel between the DC lines LH and LL. A DC voltage Vdc is applied between the DC lines LH and LL. Here, the potential applied to the DC line LH is higher than the potential applied to the DC line LL.

  In the illustration of FIG. 1, this DC voltage Vdc is generated by the rectifier 10 and the smoothing capacitor C1. The rectifier 10 rectifies the AC voltage input from the AC power supply E1, and the rectified DC voltage is smoothed by the smoothing capacitor C1. Smoothing capacitor C1 supports DC voltage Vdc. Since both ends of the smoothing capacitor C1 are connected to the DC lines LH and LL, respectively, the DC voltage Vdc is applied between the DC lines LH and LL as described above. The rectifier 10 is, for example, a diode full wave rectifier.

  The U-phase leg 21 has switching elements Sup and Sun. The switching element Sup is connected between the output terminal Pu and the DC line LH, and the switching element Sun is connected between the output terminal Pu and the DC line LL. The V-phase leg 22 has switching elements Svp and Svn. The switching element Svp is connected between the output terminal Pv and the DC line LH, and the switching element Svn is connected between the output terminal Pv and the DC line LL. The W-phase leg 23 includes switching elements Swp and Swn. The switching element Swp is connected between the output terminal Pw and the DC line LH, and the switching element Swn is connected between the output terminal Pw and the DC line LL.

  In such an inverter 20, the switching elements Sup, Sun, Svp, Svn, Swp, and Swn are appropriately controlled, so that the inverter 20 converts the DC voltage Vdc into a three-phase AC voltage and outputs them to the output terminal. It is possible to output from Pu, Pv, Pw.

  Although the three-phase inverter 20 is illustrated here, an N (natural number) phase inverter 20 having three or more phases may be employed.

  Hereinafter, the switching elements Sup, Svp, and Swp are also referred to as upper switching elements, and the switching elements Sun, Svn, and Swn are also referred to as lower switching elements.

  In the illustration of FIG. 1, a load 30 is connected to the inverter 20 on the output side. The load 30 has resistors R31 to R33, for example. In the example of FIG. 1, one ends of the resistors R31 to R33 are connected to each other, and the other ends are connected to the output ends Pu, Pv, and Pw of the inverter 20, respectively. That is, the resistors R31 to R33 are connected by so-called star connection. As the load 30, for example, a balanced load having the same impedance for each phase can be adopted. In this case, the resistance values of the resistors R31 to R33 are substantially equal to each other, for example.

  In the example of FIG. 1, an inspection control device 40 for inspecting the inverter 20 is provided. The inspection control device 40 may be provided in, for example, a facility that performs inspection, or may be mounted on a product in which the inverter 20 is accommodated.

  The inspection control device 40 includes an inverter control unit 41, a current determination unit 42, and a failure detection unit 43.

  Here, the inspection control device 40 is configured to include a microcomputer and a storage device. The microcomputer executes each processing step (in other words, a procedure) described in the program. The storage device is composed of one or more of various storage devices such as a ROM (Read Only Memory), a RAM (Random Access Memory), a rewritable nonvolatile memory (EPROM (Erasable Programmable ROM), etc.), and a hard disk device, for example. Is possible. The storage device stores various information, data, and the like, stores a program executed by the microcomputer, and provides a work area for executing the program. It can be understood that the microcomputer functions as various means corresponding to each processing step described in the program, or can realize that various functions corresponding to each processing step are realized. The inspection control device 40 is not limited to this, and various procedures executed by the inspection control device 40 or various means or various functions implemented may be realized by hardware.

  The inverter control unit 41 outputs a control signal to the switching elements Sup, Sun, Svp, Svn, Swp, Swn so that the inverter 20 adopts a switching pattern for inspection described later.

  In the switching pattern for inspection, a control signal for conducting only one of the upper switching element and the lower switching element belonging to different legs is output. As a more general explanation, an N-phase inverter 20 will be used to describe the k-th (1 ≦ k ≦ N) phase upper switching element and the m-th (1 ≦ m ≦ N, m ≠) in the inspection switching pattern. k) A control signal for conducting only one set of the lower switching elements of the phase is output.

  For example, a control signal for outputting the U-phase upper switching element Sup and the V-phase lower switching element Svn and making the other switching elements Sun, Svp, Swp, Swn non-conductive is output.

  If no failure has occurred in the inverter 20, the switching elements Sup, Sun, Svp, Svn, Swp, Swn are controlled according to the control signal. FIG. 2 schematically shows an example of an equivalent circuit of the inverter 20 at this time. Since the switching elements Sun, Svp, Swp, and Swn are non-conductive, they are not shown. At this time, the direct current Idc flowing through the direct current lines LH and LL is expressed by the following equation using the resistance value R of the resistors R31 to R33.

  Idc = Vdc / (2.R) (1)

  On the other hand, for example, if an open failure has occurred in the switching element Sup, the switching element Sup is not conducted even if a conduction control signal is output to the switching element Sup. FIG. 3 schematically shows an example of an equivalent circuit when an open circuit failure occurs in the switching element Sup. In the example of FIG. 3, since the open failure has occurred in the switching element Sup, the DC line LH is not connected to the output terminal Pu.

  At this time, since no current flows through the inverter 20, the direct current Idc is substantially zero. Similarly, when an open circuit failure occurs in the switching element Svn, the DC current Idc is substantially zero.

  In other words, if it is detected that the DC current Idc in the state where the control signal for conducting only the switching elements Sup and Svn is output is almost zero, at least one of the switching elements Sup and Svn has an open failure. You can detect what is happening.

  In the above description, as an example, a case where an open failure occurs in a switching element (for example, the switching element Sup) is considered. However, for example, even if an open failure (for example, disconnection of the wiring) occurs in the wiring between the DC line LH and the output terminal Pu, the same action is brought about. That is, the open failure of the switching element Sup here means a failure in which the switch cannot be turned on. For example, not only the occurrence of an open failure inside the switching element Sup but also the connection between the DC line LH and the output terminal Pu. Including an open circuit failure between. Alternatively, for example, an open failure caused by a failure of a control signal circuit (for example, the inverter control unit 41) or a failure of a switching element drive circuit (not shown) is also included. Hereinafter, an open failure between the DC line LH and the output terminal Pu may be referred to as an open failure on the switching element Sup side. Similar names are used for open failures occurring in other locations.

  FIG. 4 schematically shows an example of an equivalent circuit in the case where a short circuit fault has occurred in the switching element Swn. Also in the example of FIG. 4, a control signal for conducting only the switching elements Sup and Svn is output, the switching elements Sup and Svn are conducted, and the switching elements Sun, Svp, and Swp are non-conducting. Since a short circuit failure has occurred in the switching element Swn, the DC line LL is connected to the output terminal Pw regardless of the control signal to the switching element Swn.

  At this time, the direct current Idc is expressed by the following equation.

  Idc = Vdc / (3 · R / 2) (2)

  As can be understood from the comparison between Expression (1) and Expression (2), when a short circuit failure occurs in the switching element Swn, the direct current Idc is higher than the normal value (the value of Expression (1)).

  Further, when a short circuit failure occurs in the switching element Swp instead of the switching element Swn, the DC line LL is disconnected from the output terminal Pw, and the DC line LH is connected to the output terminal Pw. The direct current Idc in this case also takes the same value as that in the expression (2).

  When a short circuit failure occurs in the switching element Sun, the DC lines LH and LL are short-circuited via the switching elements Sup and Sun. Since the resistance value in this path is very small, the direct current Idc is still higher than the value of equation (1). Similarly, when a short circuit failure occurs in the switching element Svp, the direct current Idc is higher than the value of the expression (1).

  In other words, if it is detected that the DC current Idc in the state where the control signal for conducting only the switching elements Sup and Svn is output is larger than the value of the expression (1), switching other than the switching elements Sup and Svn is performed. It is possible to detect that a short circuit fault has occurred in at least one of the elements. In other words, it is possible to detect that a short circuit fault has occurred in at least one of the upper switching elements Svp and Swp and the lower switching elements Sun and Swn to which the non-conductive control signal is given.

  In the above example, the case where a short circuit failure occurs in the switching element (for example, the switching element Swn) is considered. However, for example, even if the DC line LL and the output end Pw are connected to each other by a conductor (for example, a metal piece or the like), the same action is brought about. That is, the short-circuit failure of the switching element Swn here means a failure in which the switch is turned on. For example, not only the short-circuit failure has occurred inside the switching element Swn, but also the DC line LL and the output through the conductor. This includes a short-circuit fault in which the end Pw is electrically connected to each other. Alternatively, for example, a failure of a control signal circuit (for example, the inverter control unit 41) or a short circuit failure due to a failure of a drive circuit (not shown) of a switching element is included. Hereinafter, a short circuit failure between the DC line LL and the output terminal Pw is also referred to as a short circuit failure on the switching element Swn side. Similar names are used for short-circuit faults occurring at other locations.

  In the present embodiment, as shown in FIG. 1, a current detection unit 50 that detects a direct current Idc is provided. In the illustration of FIG. 1, although the current detection unit 50 detects the current flowing through the DC line LL as the DC current Idc, the current flowing through the DC line LH may be detected. This is because the DC current Idc flows with the same magnitude in both the DC lines LH and LL.

  The detected direct current Idc is output to the current determination unit 42. The current determination unit 42 includes a first range in which the direct current Idc is smaller than the reference value Iref1, a second range between the reference value Iref1 and the reference value Iref2 (> Iref1), and a third range larger than the reference value Iref2. It is determined which one belongs (hereinafter sometimes referred to as “current determination”). FIG. 5 is a diagram schematically showing an example of the direct current Idc and the reference values Iref1 and Iref2 in the expressions (1) and (2). The reference value Iref1 is a positive value that is smaller than the direct current Idc in equation (1), and the reference value Iref2 is a value between the direct current Idc in equation (1) and the direct current Idc in equation (2). .

  The reference value Iref1 is set to a positive value smaller than the direct current Idc in the equation (1), and the reference value Iref2 is set to the value of the direct current Idc in the equation (1) and the direct current Idc in the equation (2). This is because the variation of the direct current Idc is taken into consideration. Such variations are caused by variations in the resistance value R.

  The determination result of the current determination unit 42 is output to the failure detection unit 43. The failure detection unit 43 also receives a control signal output from the inverter control unit 41, for example. The failure detection unit 43 recognizes the switching pattern based on this control signal, and detects the failure as follows according to the switching pattern and the determination result.

  That is, when the direct current Idc belongs to the first range smaller than the reference value Iref1, for example, referring to FIG. 3, the upper switching element (for example, the switching element Sup) side and the lower switching element to which the conduction control signal is given. It detects that an open circuit failure has occurred in at least one of the (for example, switching element Svn) side.

  When the direct current Idc belongs to the third range larger than the reference value Iref2, for example, referring to FIG. 4, for example, an upper switching element (for example, switching element Sup) and a lower switching element (for example, switching element Sup) to which a conduction control signal is given. For example, it is determined that a short-circuit failure has occurred on at least one switching element side other than the pair of switching elements Svn). In other words, a short circuit fault occurs on at least one switching element side of the upper switching element (for example, switching element Svp, Swp) and the lower switching element (for example, switching element Sun, Swn) to which the non-conductive control signal is given. Detect that.

  In the following, as a more general description, a case where an N-phase inverter is used will be described. First, in the switching pattern, the upper switching element (for example, the switching element Sup) connected to the k-phase output terminal (for example, the output terminal Pu) and the lower switching element connected to the m-th phase output terminal (for example, the output terminal Pv). Only one set of side switching elements (for example, the switching element Svn) is conducted.

  When the DC current Idc in the state where this switching pattern is adopted is smaller than the reference value Iref1, the failure detection unit 43 is connected between the k-phase output terminal (for example, the output terminal Pu) and the DC line LH. In addition, it detects that an open circuit failure has occurred in at least one of the m-phase output terminal (for example, the output terminal Pv) and the DC line LL.

  On the other hand, when the DC current Idc in the state where this switching pattern is adopted is larger than the reference value Iref2, the failure detection unit 43 connects the DC terminals to the output terminals other than the k-th phase (for example, the output terminals Pv and Pw). It is detected that a short circuit fault has occurred between the line LH and at least one of the output terminals other than the m-th phase (for example, the output terminals Pu and Pw) and the DC line LL.

  As described above, the short-circuit fault range and the open fault range can be detected by the inspection in one switching pattern.

  Next, a case where a plurality of switching patterns are used to specify the positions of the open fault and the short fault will be described. There are six types of switching patterns as shown in Table 1. The switching patterns S1 to S6 are shown in Table 1 when the conduction / non-conduction of the switching element is indicated by “◯” and “x”, respectively.

  Table 2 shows the position where the open failure has occurred and the determination results in each of the switching patterns S1 to S6.

  In Table 2, a portion between the DC line LH and the U-phase output end Pu is expressed as “upper side of the U phase”, and a portion between the DC line LL and the U-phase output end Pu is expressed as “U-phase”. "Underside". The same applies to the V phase and the W phase. Further, “X” indicates that an open failure has occurred, and “◯” indicates that no open failure has occurred.

  In Table 2, it is indicated as “normal” that the direct current Idc belongs to the second range between the reference values Iref1 and Iref2, and the direct current Idc belongs to the first range smaller than the reference value Iref1. This is indicated by “Z”.

  For example, when no failure occurs anywhere, the determination result is “normal” in all of the switching patterns S1 to S6.

  On the other hand, for example, when an open failure occurs only in “upper U phase”, the determination result is “Z” in both of the switching patterns S1 and S2 for conducting the switching element Sup located in “upper U phase”. It becomes. Because, if an open failure occurs on the upper switching element Sup side, even if a control signal for conduction is output to the upper switching element Sup, the DC line LH does not conduct to the output terminal Pu (for example, see FIG. 3). This is because the direct current Idc becomes substantially zero.

  In the other switching patterns S3 to S6, since the switching element to which the conduction control signal is given conducts appropriately, the direct current Idc takes a value according to the equation (1). That is, the direct current Idc belongs to the second range that is larger than the reference value Iref1 and smaller than the reference value Iref2.

  Accordingly, the determination results corresponding to the switching patterns S1 to S6 when the open failure occurs in “upper U phase” are “Z”, “Z”, “normal”, “normal”, and “normal”, respectively, as shown in Table 2. “Normal”.

  The same applies to the case where an open failure occurs in other parts. In short, the determination result is “Z” in both of the two switching patterns that conduct the switching element located in the part where the open failure occurs, and the determination result is “normal” in all the other switching patterns. .

  As can be understood from the above description, since the pattern of the determination result changes depending on the position where the open failure occurs, the position where the open failure occurs can be detected according to the pattern of the determination result.

  Table 3 shows the position where the short-circuit failure has occurred and the determination results in the switching patterns S1 to S6.

  In Table 3, “X” indicates that a short-circuit failure has occurred, and “◯” indicates that no short-circuit failure has occurred. Further, “0” indicates that the direct current Idc is larger than the reference value Iref2.

  For example, when no failure occurs anywhere, the determination result is “normal” in all of the switching patterns S1 to S6.

  On the other hand, for example, when a short-circuit failure occurs on the “lower side of the W phase”, the DC current Idc is the reference in both of the switching patterns S2 and S4 for conducting the switching element Swn positioned on the “lower side of the W phase”. It belongs to the second range between the values Iref1, Iref2. That is, the determination result is “normal”. This is because the DC line LL and the w-phase output terminal Pw are electrically connected to each other due to a short-circuit failure, so that the DC line LL and the output terminal Pw are also output even when a control signal for connecting the lower switching element Swn is output. This is because they are electrically connected to each other.

  In the other switching patterns S1, S3, S5, and S6, the direct current Idc belongs to the third range larger than the reference value Iref2, and the determination result is “0”. This is because in the switching patterns S1, S3, S5, and S6, even when a non-conduction control signal is given to the lower switching element Swn, the DC line LL and the output terminal Pw are electrically connected to each other due to a short circuit failure (for example, FIG. 4). The determination results corresponding to the switching patterns S1 to S6 at this time are “0”, “normal”, “0”, “normal”, “0”, and “0”, as shown in Table 3.

  The same applies to the case where a short-circuit failure occurs in another part. In short, the determination result is “normal” in both of the two switching patterns in which the switching element located in the portion where the short-circuit failure occurs is conducted, and the determination result is “0” in all the other switching patterns.

  As can be understood from the above description, since the pattern of the determination result changes depending on the position where the short-circuit fault occurs, the position where the short-circuit fault occurs can be detected according to the pattern of the determination result.

  Therefore, the inverter control unit 41 sequentially outputs control signals corresponding to these switching patterns in order to cause the inverter 20 to sequentially adopt the switching patterns S1 to S6. The current detection unit 50 detects a direct current Idc for each of the switching patterns S1 to S6. The current determination unit 42 performs the current determination based on the direct current Idc for each of the switching patterns S1 to S6, and outputs the determination result. The failure detection unit 43 detects the position of the open failure and the position of the short-circuit failure based on the determination result patterns of the switching patterns S1 to S6.

  Referring to Table 2, for example, if the pattern of the determination result is “Z”, “Z”, “normal”, “normal”, “normal”, “normal”, the failure detection unit 43 has an open failure on the upper switching element Sup side. Determine that it has occurred.

  The open fault detection method described above will be described using the N-phase inverter 20 as a more general description.

  A switching pattern (for example, switching pattern S1) for conducting only one set of the k-phase upper switching element (for example, switching element Sup) and the m-th phase lower switching element (for example, switching element Svn), and the k-phase upper side switching element A switching pattern (for example, switching pattern S2) for conducting a switching element (for example, switching element Sup) and a lower switching element (for example, switching element Swn) of the nth (1 ≦ n ≦ 1, n ≠ m, n ≠ k) phase; In both cases, when the determination result is “Z” and the determination result is “normal” in all the other switching patterns, the k-phase output terminal (for example, output terminal Pu) and the DC line LH It is detected that an open failure has occurred between

  In addition, a switching pattern (for example, switching pattern S3) for conducting only one set of the k-phase lower switching element (for example, switching element Sun) and the m-th phase upper switching element (for example, switching element Svp), and the k-th phase The determination result is “Z” in both the lower switching element (for example, switching element Sun) and the switching pattern (for example, switching pattern S5) that conducts the n-th phase upper switching element (for example, switching element Swp). In all other switching patterns, when the determination result is “normal”, it is detected that an open circuit failure has occurred between the k-phase output terminal (for example, output terminal Pu) and the DC line LL. .

  Referring to Table 3, for example, if the determination result is “normal”, “normal”, “0”, “0”, “0”, “0”, the failure detection unit 43 has a short circuit failure on the upper switching element Sup side. It is determined that

  This short-circuit fault detection method will also be described using the N-phase inverter 20 as a more general description.

  A switching pattern (for example, switching pattern S1) for conducting only one set of the k-phase upper switching element (for example, switching element Sup) and the m-th phase lower switching element (for example, switching element Svn), and the k-phase upper side switching element The determination result is “normal” in both the switching element (for example, the switching element Sup) and the switching pattern (for example, the switching pattern S2) that conducts the lower switching element (for example, the switching element Swn) of the nth phase, and In all other switching patterns, when the determination result is “0”, it is detected that a short circuit failure has occurred between the k-phase output terminal (for example, output terminal Pu) and the DC line LH.

  In addition, a switching pattern (for example, switching pattern S3) for conducting only one set of the k-phase lower switching element (for example, switching element Sun) and the m-th phase upper switching element (for example, switching element Svp), and the k-th phase The determination result is “normal” in both the lower switching element (for example, the switching element Sun) and the switching pattern (for example, the switching pattern S5) for conducting the n-phase upper switching element (for example, the switching element Swp). In all the other switching patterns, when the determination result is “0”, it is detected that a short-circuit failure has occurred between the k-phase output terminal (for example, output terminal Pu) and the DC line LL. .

  The relationship between the determination result patterns in Tables 2 and 3 (hereinafter also referred to as a registered pattern), the type of failure (open failure / short-circuit failure), and position is stored in advance in a storage unit (not shown). Just do it. Then, it is only necessary to determine which of the registered patterns matches the pattern of the determination result and detect a failure based on the relationship.

  As described above, according to this failure detection method, it is possible to detect the position of the short-circuit failure and the position of the open failure.

  In the above example, the resistors R31 to R33 are connected to each other by star connection. However, the resistors R31 to R33 may be connected by a delta connection. In this case, the reference values Iref1 and Iref2 need to be changed appropriately. Hereinafter, the setting of the current flowing through the inverter 20 and the reference values Iref1 and Iref2 when the resistors R31 to R33 are connected by delta connection will be described.

  If no fault has occurred in the inverter 20, when the inspection switching pattern is adopted, the DC current Idc is parallel to any one of the resistors R31 to R33 and the series circuit of the other two resistors. Flow through the circuit. This is because in the switching pattern for inspection, one of the upper switching element and the lower switching element of different phases are conducted. Therefore, the normal DC current Idc is expressed by the following formula.

  Idc = Vdc / (2 · R / 3) (3)

  Further, when an open circuit failure has occurred in the switching element to which the conduction control signal is given in the switching pattern, the direct current Idc is almost zero. Therefore, a positive value smaller than the direct current Idc expressed by the equation (3) may be adopted as the reference value Iref1 for detecting the open failure.

  For example, when a short circuit fault has occurred on the switching element Swn side in the switching pattern in which the switching elements Sup and Svn are conducted, one resistor corresponds to being short-circuited by the switching element on the side where the short circuit fault has occurred. The direct current Idc flows through the remaining two resistors connected in parallel to each other. Therefore, the direct current Idc is expressed by the following equation.

  Idc = 2 · Vdc / R (4)

  Therefore, as the reference value Iref2 for detecting the short-circuit failure, a value between the direct current Idc in Expression (3) and the direct current Idc in Expression (4) may be adopted.

  In the above example, the load 30 is the resistors R31 to R33, but the load 30 may be a motor. In this case, the resistance component of the armature winding can be considered as the resistors R31 to R33. However, the DC current Idc changes with time and reaches a steady value due to the inductance component of the armature winding. Therefore, for example, this steady value may be considered as the direct current Idc. Alternatively, a direct current Idc at a time point when a predetermined time has elapsed after outputting the control signal may be used.

  Further, the inverter 20 may be provided with an overcurrent protection function, for example. The overcurrent protection function is a function for stopping the inverter 20 when the DC current Idc flowing through the inverter 20 exceeds a reference value. Thereby, it is suppressed that an overcurrent flows into the inverter 20.

  This overcurrent protection function is realized by, for example, the current detection unit 50, the comparison unit 421, and the inverter control unit 41 shown in FIG. One of the reference values Iref1 and Iref2 and the direct current Idc detected by the current detection unit 50 are input to the comparison unit 421. Here, as an example, the reference value Iref2 is input to the comparison unit 421. The reference value Iref2 is expressed by, for example, a DC voltage, and in the example of FIG. 6, this DC voltage is input to the comparison unit 421. The comparison unit 421 is, for example, a comparator, compares the direct current Idc with the reference value Iref2, and outputs the comparison result.

  The inverter control unit 41 can output not only the switching pattern for inspection described above but also a control signal for causing the inverter 20 to output an AC voltage. The generation of such a control signal is known. For example, the control signal can be generated based on a comparison between a command value for the AC voltage output from the inverter 20 and a triangular wave. By supplying this control signal to the switching element of the inverter 20, the inverter 20 can convert the DC voltage Vdc into an AC voltage and output it.

  The comparison result of the comparison unit 421 is input to the inverter control unit 41. The inverter control unit 41 protects the inverter 20 based on the comparison result. For example, when the direct current Idc is larger than the reference value Iref2, the inverter 20 is stopped. More specifically, for example, the switching elements Sup, Sun, Svp, Svn, Swp, and Swn are made non-conductive. Thereby, it is possible to suppress the direct current Idc exceeding the reference value Iref2 from flowing through the inverter 20.

  In the example of FIG. 6, the comparison result of the comparison unit 421 is also input to the failure detection unit 43. In FIG. 6, a comparison unit 422 is also provided. The comparison unit 422 receives the direct current Idc detected by the current detection unit 50 and the reference value Iref1. The reference value Iref1 is also expressed by, for example, a DC voltage, and this DC voltage is input to the comparison unit 422 in the example of FIG. The comparison unit 422 is, for example, a comparator, compares the direct current Idc and the reference value Iref1, and outputs the comparison result to the failure detection unit 43.

  The failure detection unit 43 can determine to which of the first range to the third range the direct current Idc belongs based on the comparison results of the comparison units 421 and 422.

  The failure detection unit 43 outputs an instruction to start inspection to the inverter control unit 41, for example. In response to this, the inverter control unit 41 outputs a control signal so as to cause the inverter 20 to adopt the switching pattern for inspection. The current detection unit 50 detects the direct current Idc in a state where the switching pattern is adopted. Each of comparison units 421 and 422 compares DC current Idc with each of reference values Iref 2 and Iref 1, and outputs the comparison result to failure detection unit 43. The failure detection unit 43 detects an open failure and a short-circuit failure based on the direct current Idc as described above.

  From the viewpoint of fault inspection, the comparison units 421 and 422 can be considered to belong to the current determination unit 42.

  As described above, in the example of FIG. 6, the comparison unit 421 is used for both overcurrent protection and failure inspection. Therefore, the manufacturing cost can be reduced as compared with the case where both the comparison part for overcurrent protection and the comparison part for failure detection are provided.

  In the above example, the inverter 20 is stopped for overcurrent protection. However, the inverter 20 may be stopped based on the magnitude relationship between the DC current Idc and the reference value from a viewpoint different from the overcurrent protection. For example, when it is detected that the direct current Idc is small, it may be determined that a failure has occurred and the inverter 20 may be stopped. In such a case, the comparison result of the comparison unit 421 or the comparison unit 422 can be used for condition determination for stopping the inverter 20. According to this, compared with the case where both the comparison part for the condition determination of the stop of the inverter 20 and the comparison part for failure detection are provided, manufacturing cost can be reduced.

  In FIG. 6, for example, the inverter 20, the current detection unit 50, the comparison unit 421, and the inverter control unit 41 are mounted on the product side. That is, when the inverter 20 drives a motor, these are mounted on a product as a motor drive device. Therefore, as the inspection apparatus, a connection unit with the comparison unit 421, the comparison unit 422, and the failure detection unit 43 may be provided.

  In addition, at least one of the comparison unit 422 and the failure detection unit 43 may be mounted on the product. Or the control signal output part which outputs the control signal corresponding to the switching pattern for a test | inspection may be provided separately from the inverter control part 41, and this control signal output part may be provided in the test | inspection apparatus side.

  In the present invention, the above-described various embodiments can be appropriately modified and omitted within the scope of the present invention as long as they do not contradict each other.

20 Inverter 41 Inverter control unit 42 Current determination unit 43 Failure detection unit LH, LL DC line Pu, Pv, Pw Output terminal Sup, Sun, Svp, Svn, Swp, Swn Switching element

Claims (4)

A first DC line (LH) and a second DC line (LL);
N (N is a natural number of 3 or more) phase output terminals (Pu, Pv, Pw),
A first switching element (Sup, Svp, Swp) connected between the first DC line and each of the output ends;
A method for inspecting an inverter (20) comprising a second switching element (Sun, Svn, Swn) connected between the second DC line and each of the output ends,
In a state where a load is connected to the inverter, the k-th phase first switching element (Sup) and the m-th (1 ≦ m ≦ N) connected to the k-th (1 ≦ k ≦ N) -phase output terminal. a first switching pattern (S1) for conducting only the second switching element ( Svn ) of the m-th phase connected to the output terminal of the m ≠ k) phase is adopted in the inverter;
A first range in which a current (Idc) flowing through the second DC line is smaller than a first reference value (Iref1), a second reference value (Iref2) larger than the first reference value, and the first reference value. Determining whether it belongs to the second range between and the third range larger than the second reference value,
Since it is determined that the current belongs to the first range, between the output end (Pu) of the k-phase and the first DC line (LH), and the m-phase By detecting an open fault in at least one of the output terminal (Pv) and the second DC line (LL), and determining that the current belongs to the third range, Between the output terminals (Pv, Pw) other than the k-phase and the first DC line (LH), and between the output terminals (Pu, Pw) other than the m-th phase and the second DC line (LL) Detecting a short-circuit fault in at least one of
The inverter (20) adopts a plurality of the switching patterns by sequentially changing the values of k and m.
Based on the result of the determination with respect to the current (Idc) for each switching pattern, detects the position of an open fault and the position of a short-circuit fault,
The first switching pattern (S1), the first switching element (Sup) of the k-th phase, and the output end (Pw) of the n-th (1 ≦ n ≦ N, n ≠ m, n ≠ k) phase. The current (Idc) belongs to the second range in both the second switching pattern (S2) for conducting only the second switching element (Swn) connected to the second switching element (Swn), and the other switching is performed. In all of the patterns (S3 to S6), when the current is determined to belong to the third range, between the output terminal (Pu) of the k-phase and the first DC line (LH). Inverter failure detection method that detects short-circuit failures . The first of said switching pattern (S1), in both the pre-Symbol second of said switching pattern (S2), the current (Idc) belongs to the first range and the other of said switching pattern (S3 To S6), an open fault between the output terminal (Pu) of the k-th phase and the first DC line (LH) is determined by determining that the current belongs to the second range. The inverter failure detection method according to claim 1, wherein the inverter failure detection method is detected. A first DC line (LH) and a second DC line (LL);
N (N is a natural number of 3 or more) phase output terminals (Pu, Pv, Pw),
A first switching element (Sup, Svp, Swp) connected between the first DC line and each of the output terminals, and a connection between the second DC line and each of the output terminals. An inverter (20) having a second switching element (Sun, Svn, Swn);
The k-phase first switching element (Sup) connected to the k-th (1 ≦ k ≦ N) phase output terminal and the m-th (1 ≦ m ≦ N, m ≠ k) phase output terminal An inverter control section (21) for causing the inverter to adopt a first switching pattern (S1) for conducting only the second switching element (Svn) of the connected m-th phase;
A current detector (50) for detecting a current (Idc) flowing through the second DC line;
A first range in which the current is smaller than a first reference value (Iref1); a second range between a second reference value (Iref2) greater than the first reference value and the first reference value; A current determination unit (22) for determining which of the third range is larger than the second reference value;
When the current belongs to the first range, between the output end (Pu) of the k-th phase and the first DC line (LH), and the output end (Pv) of the m-th phase And when the current belongs to the third range, the output other than the k-th phase is determined. Between at least one end (Pv, Pw) and the first DC line (LH) and between the output terminal (Pu, Pw) other than the m-th phase and the second DC line (LL) A fault detection unit (23) that determines that a short circuit fault has occurred,
The inverter control unit sequentially changes the values of k and m to cause the inverter (20) to adopt a plurality of the switching patterns,
The failure detection unit detects a position of an open fault and a position of a short-circuit fault based on the result of the determination for the current (Idc) for each switching pattern,
The failure detection unit includes the first switching pattern (S1), the first switching element (Sup) in the k-th phase, and the n-th (1 ≦ n ≦ N, n ≠ m, n ≠ k) phase. The current (Idc) belongs to the second range both in the second switching pattern (S2) for conducting only the second switching element (Swn) connected to the output terminal (Pw) of In addition, in all the other switching patterns (S3 to S6), when the current is determined to belong to the third range, the k-phase output terminal (Pu) and the first DC line ( Inverter inspection device that detects short-circuit faults with LH). The current determination unit (42)
A first comparison unit (422) for comparing the current and the first reference value;
A second comparison unit (421) for comparing the current and the second reference value;
The inverter inspection device according to claim 3, wherein the inverter control unit (41) stops the inverter based on a comparison result of the first comparison unit or the second comparison unit.

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