JP6963951B2 - Gate driver drive circuit and liquid crystal display - Google Patents

Description

The present invention relates to a gate driver drive circuit and a liquid crystal display device.

In recent years, as the size of the liquid crystal panel has increased, the parasitic impedance of the scanning line has increased. As a result, the difference in amplitude of the scanning signal at both ends of the liquid crystal panel becomes large, and the liquid crystal panel flickers (flicker), which is a problem. A liquid crystal display device having a gate shading function is known for such a problem.

For example, in the liquid crystal display device described in Patent Document 1, by inclining the waveform of the gate voltage supplied to the gate driver, the roundness of the scanning signal due to the distance from the gate driver is made uniform, and the TFT is turned on. Off timing deviation is reduced.

Japanese Unexamined Patent Publication No. 2015-166870

However, when the waveform of the gate voltage is inclined as described in Patent Document 1, it is difficult to incline the gate voltage immediately after the input voltage or the control signal changes, and there is a delay in inclining the gate voltage. As a result, the timing at which the TFT is turned on is delayed, so that the display of the liquid crystal display is delayed.

Therefore, an object of the present invention is a gate driver drive circuit capable of supplying a voltage to the gate driver so that the liquid crystal panel does not flicker and the display of the liquid crystal panel is not delayed, and such a gate. It is to provide a liquid crystal display device provided with a driver drive circuit.

The gate driver drive circuit of the present invention has a predriver that outputs a drive voltage to a first node in response to a control signal having a steep rising or falling edge, a power supply terminal, and an output to which a gate driver is connected. A first transistor having a control electrode arranged between the terminals and connected to the first node, a capacitor arranged between the control electrode and the output terminal of the first transistor, and a first transistor. A second transistor arranged between the node and the ground and a control circuit for controlling the control electrode of the second transistor are provided. The control circuit turns on the second transistor when the voltage of the first node is higher than the voltage that turns on the first transistor.

Preferably, the control circuit turns off the second transistor when the voltage at the first node drops to the voltage that turns on the first transistor.

Preferably, the control circuit is located between the output terminal and the second node and between a third transistor having a control electrode connected to the first node and between the second node and ground. Includes placed resistors. The voltage of the control electrode of the second transistor changes according to the voltage of the second node.

Preferably, the control circuit has a logic having a first input terminal that receives a control signal, a second input terminal that receives the voltage of the second node, and an output terminal connected to the control electrode of the second transistor. It has a circuit.

Preferably, the first transistor is a NMOS transistor, the second transistor is an NMOS transistor, and the third transistor is a NMOS transistor.

Preferably, the logic circuit is a NOR circuit.
Preferably, a Schmitt trigger circuit is provided between the second node and the second input terminal of the logic circuit.

The liquid crystal display device of the present invention includes a liquid crystal panel, a source driver for driving the corresponding data lines of the liquid crystal panel, a gate driver for driving the corresponding scanning lines of the liquid crystal panel, and a gate driver drive circuit. The voltage output from the output terminal of the gate driver drive circuit is supplied to a plurality of gate drivers.

According to the present invention, it is possible to prevent the liquid crystal panel from flickering and the display on the liquid crystal panel from being delayed.

It is a figure which shows the structure of the liquid crystal display device. It is a figure which shows the structure of the 1st voltage generation part (voltage regulator) 300. It is a figure which shows the detailed structure of an error amplifier 12. It is a figure which shows the structure of the current limiting circuit 13a of a reference example. It is a figure which shows the structure of the current limiting circuit 13a of 2nd Embodiment. It is a figure which shows the structure of the gate driver drive circuit 400 of a reference example. It is a figure which shows the transition of the control signal FLK, the voltage VX of the node NX, and the output voltage VGG in the gate driver drive circuit 400 of the reference example. It is a figure which shows the structure of the gate driver drive circuit 400 of 3rd Embodiment. It is a figure which shows the transition of the control signal FLK of the gate driver drive circuit 400 of 3rd Embodiment, the voltage VX of a node NX, and the output voltage VGG. It is a figure which shows the characteristic of the Schmitt trigger circuit 29. It is a figure which shows the structure of the switching power supply circuit 500 of a reference example. It is a figure which shows the structure of the driver control unit 31. It is a figure which shows the structure of the switching power supply circuit 500 of 4th Embodiment. It is a figure which shows the timing of the switching signal SW and the ON signal ON within one cycle in a normal time. It is a figure which shows the timing of the switching signal SW and the ON signal ON in a normal state. It is a figure which shows the timing of switching signal SW and ON signal ON at the time of light load. It is a figure which shows the timing of switching signal SW and ON signal ON when there is no load. It is a figure which shows the timing of switching signal SW and ON signal ON at the time of shutdown. It is a figure which shows the structure of the 3rd voltage generation part 500 of the modification of 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram showing a configuration of a liquid crystal display device.

The liquid crystal display device includes a liquid crystal module 140 and a drive circuit 120 mounted on the drive board 100. The liquid crystal module 140 includes a liquid crystal panel 700, a source circuit 900, and a gate circuit 800. The drive circuit 120 includes a timing controller 600 and a power management IC 200.

The liquid crystal panel 700 is, for example, an active matrix drive type panel. The liquid crystal panel 700 includes a panel composed of a plurality of pixels filled with a liquid crystal substance, and a glass substrate arranged on the back surface of the panel. On this glass substrate, a plurality of scanning lines arranged in the vertical direction and extending in the horizontal direction (for example, G1 to G4) and a plurality of data lines arranged in the horizontal direction and extending in the vertical direction (for example, S1) are provided. ~ S4) and are arranged. Pixels (for example, 2-a to 2-d) are provided in a matrix via a TFT (Thin Film Transistor) (for example, 1-a to 1-d) corresponding to an intersection of a scanning line and a data line. Has been done.

The gate circuit 800 includes a plurality of gate drivers (for example, 0-1 to 90-4). The gate driver 90-i is connected to the scanning line G-i.

The source circuit 900 includes a plurality of source drivers (for example, 91 to 91-4) and a control circuit 92. The source driver 91-i is connected to the data line Si.

The power management IC 200 operates by receiving the supply of the input voltage VIN and generates various voltages. The power management IC 200 includes a first voltage generation unit (voltage regulator circuit) 300, a second voltage generation unit (gate driver drive circuit) 400, and a third voltage generation unit (switching power supply circuit) 500.

The first voltage generation unit 300 generates a voltage VGG for driving the gate driver and supplies it to the gate drivers 90-1 to 90-4.

The second voltage generation unit 400 generates an analog power supply voltage A VDD and supplies it to the source drivers 91-1 to 91-4.

The third voltage generation unit 500 generates the logic system power supply voltage VDD and supplies it to the timing controller 600 and the control circuit 92.

The timing controller 600 operates by receiving the supply of the logic system power supply voltage VDD. The timing controller 600 controls the vertical synchronization of the gate driver (for example, 90-1 to 90-4) and the source driver (for example, 91-1 to 91-4) based on commands and data input from a host device (not shown). Horizontal synchronization control of.

The gate driver 90-i (eg, i = 1-4) receives a voltage VGG and operates based on a vertical sync signal. For example, the gate driver 90-i receives a voltage VGG. The gate driver 90-i uses the voltage VGG as a power supply voltage to generate a gate voltage GX and supplies it to the scanning line G-i.

The source driver 91-i (for example, i = 1 to 4) is supplied with the analog power supply voltage A VDD and operates based on the horizontal synchronization signal. For example, the source driver 91-i responds to the gradation value (for example, 0 to 255 gradations) of the digital video signal input from the host device by driving the source amplifier using the analog power supply voltage A VDD. The source voltage SSi is generated and supplied to the pixels of the liquid crystal panel 700 through the data line Si.

The control circuit 92 operates by receiving the supply of the logic system power supply voltage VDD. The control circuit 92 controls the source driver 91-i (for example, i = 1 to 4).

[Second Embodiment]
The second embodiment relates to the detailed configuration and operation of the first voltage generator (voltage regulator circuit) 300. Specifically, a voltage regulator having a current limiting function will be described.

FIG. 2 is a diagram showing the configuration of the first voltage generating unit (voltage regulator) 300.
The first voltage generation unit 300 includes a reference voltage generation unit 11, an error amplifier 12, current limiting circuits 13a and 13b, a MOSFET transistor M1, an NMOS transistor M2, and a feedback unit 68.

The reference voltage generation unit 11 generates a reference voltage VREF from the input voltage VIN input to the input terminal A1 and outputs the reference voltage VREF to the error amplifier 12.

The epitaxial transistor M1 is arranged between the input terminal A1 and the node ND1 connected to the output terminal P1.

The return unit 68 includes a resistor R1 and a resistor R2. The voltage of the node ND2 between the resistors R1 and R2 is supplied to the error amplifier 12 as a feedback voltage VF. The feedback voltage VF is R1 / (R1 + R2) of the output voltage A VDD output from the output terminal P1. As a result, the magnitude of the output voltage A VDD and the magnitude of the feedback voltage VF are adjusted to the magnitude of the reference voltage VREF.

The NMOS transistor M2 is arranged between the node ND1 and the ground GND. When the NMOS transistor M2 is turned on, the current input from the terminal P1 flows to the ground.

The error amplifier 12 controls on and off of the NMOS transistor M1 and the NMOS transistor M2.

The current limiting circuit 13a suppresses an increase in the current flowing through the epitaxial transistor M1. The current limiting circuit 13b suppresses an increase in the current flowing through the NMOS transistor M2.

FIG. 3 is a diagram showing a detailed configuration of the error amplifier 12.
The error amplifier 12 includes an input differential amplifier circuit 14 and an output differential amplifier circuit 15.

The input differential amplifier circuit 14 includes resistors R61 and R62, NMOS transistors N61 and N62, and a constant current source IS1.

The resistor R61 is arranged between the terminal A1 that receives the input voltage VIN and the node ND2. The resistor R62 is arranged between the terminal A1 that receives the input voltage VIN and the node ND3.

The NMOS transistor N61 is arranged between the node ND2 and the node ND61. The gate of the NMOS transistor N61 receives the feedback voltage FB. The NMOS transistor N62 is arranged between the node ND3 and the node ND61. The gate of the NMOS transistor N62 receives a reference voltage VREF. The constant current source IS1 is arranged between the node ND61 and the ground GND.

The output differential amplifier circuit 15 includes MOSFET transistors P61, P62, P63 and NMOS transistors N63, N65, N66.

The epitaxial transistor P61 is arranged between the node ND2 and the node ND9. The gate of the epitaxial transistor P61 receives a voltage BIAS.

The epitaxial transistor P62 is arranged between the node ND3 and the node ND4. The gate of the epitaxial transistor P62 receives a voltage BIAS.

The epitaxial transistor P63 is arranged between the node ND4 and the node ND565. The gate of the epitaxial transistor P63 receives the voltage BIAS2.

The epitaxial transistor P64 is arranged between the node ND4 and the node ND565. The gate of the epitaxial transistor P64 receives the voltage BIAS3.

The NMOS transistor N65 is arranged between the node ND9 and the ground GND. The NMOS transistor N66 is arranged between the node ND65 and the ground GND. The gate and drain of the NMOS transistor N65 are connected to the gate of the NMOS transistor N66.

The node ND4 is connected to the gate of the epitaxial transistor M1, and the node ND65 is connected to the gate of the epitaxial transistor M2.

(Current limiting circuit in reference example)
FIG. 4 is a diagram showing the configuration of the current limiting circuit 13a of the reference example.

The current limiting circuit 13a of the reference example includes a MIMO transistor M3, a resistor RA, and a PNP transistor Q.

The resistor RA is arranged between the input terminal A1 that receives the input voltage VIN and the node ND10. The epitaxial transistor M3 is arranged between the node ND10 and the node ND1. The gate of the epitaxial transistor M1 and the gate of the epitaxial transistor M3 are connected to the node ND4. The PNP transistor Q1 is arranged between the input terminal A1 that receives the input voltage VIN and the node ND4. The base of the PNP transistor Q1 is connected to the node ND10.

(Operation of current limiting circuit in reference example)
Since the gate of the polyclonal transistor M1 and the gate of the epitaxial transistor M3 are connected, and the drain of the epitaxial transistor M1 and the drain of the epitaxial transistor M3 are connected, when the current flowing through the epitaxial transistor M1 increases, it flows through the epitaxial transistor M3. The current also increases. Assuming that the size of the epitaxial transistor M3 is K times the size of the epitaxial transistor M1, the current I2 flowing through the epitaxial transistor M3 is expected to be K × I1 when the current flowing through the epitaxial transistor M1 is I1.

Therefore, as I1 increases, the potential of node ND10 decreases. The base-emitter voltage of the PNP transistor Q1 increases, and the on-resistance of the PNP transistor Q1 decreases. As a result, the decrease in the voltage of the node ND4, which is the gate voltage of the epitaxial transistor M1, is suppressed, so that the increase in the current of the epitaxial transistor M1 is suppressed.

(Problems with the current limiting circuit in the reference example)
When the current I2 flows through the resistor RA, the source potential of the epitaxial transistor M3 (the potential of the node ND10) becomes lower than the potential of the source of the epitaxial transistor M1. As a result, the current I2 may deviate from K × I1, and the epitaxial transistor M3 cannot correctly monitor the current I1 flowing through the epitaxial transistor M1. This is a problem especially when the resistance RA is large.

(Current limiting circuit of the second embodiment)
FIG. 5 is a diagram showing the configuration of the current limiting circuit 13a of the second embodiment.

The current limiting circuit 13a of the second embodiment includes a NMOS transistor M30, a PNP transistor Q2, a variable resistor RB, a MOSFET transistors M4 and M5, an NMOS transistors M6 and M7, and a constant current source IS2.

The size of the epitaxial transistor M30 is K1 times the size of the epitaxial transistor M1. The size of the epitaxial transistor M5 is K1 times the size of the epitaxial transistor M5. The size of the NMOS transistor M7 is K2 times the size of the NMOS transistor M6.

The epitaxial transistor M30 is arranged between the input terminal A1 that receives the input voltage VIN and the node ND11.

The resistor RB is arranged between the input terminal A1 that receives the input voltage VIN and the node ND12.

The PNP transistor Q2 is arranged between the input terminal A1 that receives the input voltage VIN and the node ND4. The base of the PNP transistor Q2 is connected to the node ND12.

The NMOS transistor M7 is arranged between the node ND12 and the ground GND.
A MOSFET transistor M5 and an NMOS transistor M6 are connected in series between the node ND 11 and the ground GND.

A epitaxial transistor M4 and a constant current source IS2 are connected in series between the node ND1 and the ground GND.

The gate of the epitaxial transistor M4 and the gate of the epitaxial transistor M5 are connected, and the gate of the epitaxial transistor M4 and the drain are connected. The epitaxial transistor M4 and the epitaxial transistor M5 constitute the current mirror circuit CM1.

The current mirror circuit CM1 replicates the current I1 flowing through the epitaxial transistor M4, so that the replicated current I2 flows through the epitaxial transistor M5. The current I2 is K1 × I1.

The gate of the NMOS transistor M6 and the gate of the NMOS transistor M7 are connected, and the gate and drain of the NMOS transistor M6 are connected. The NMOS transistor M6 and the NMOS transistor M7 form the current mirror circuit CM2.

The current mirror circuit CM2 replicates the current I2 flowing through the epitaxial transistor M30, the epitaxial transistor M4, and the NMOS transistor M6, so that the replicated current I3 flows through the epitaxial transistor M7. The current I3 is K2 × I2.

(Operation of the current limiting circuit of the second embodiment)
Since the gate of the epitaxial transistor M1 and the gate of the epitaxial transistor M3 are connected, and the source of the epitaxial transistor M1 and the source of the epitaxial transistor M3 are connected, when the current flowing through the epitaxial transistor M1 increases, the current flows through the epitaxial transistor M30. The current also increases. Since the size of the polyclonal transistor M3 is K1 times the size of the epitaxial transistor M1, it is expected that the current I2 flowing through the epitaxial transistor M30 is K1 × I1 when the current flowing through the epitaxial transistor M1 is I1.

Since the size of the epitaxial transistor M7 is K2 times that of the epitaxial transistor M6, the current I3 flowing through the epitaxial transistor M7 is K2 × I2 (= K2 × K1 × I1) due to the current mirror circuit CM2.

When the current I1 increases, the current I2 increases, and when the current I2 increases, the current I3 increases. As the current I3 increases, the potential of node ND12 decreases. The base-emitter voltage of the PNP transistor Q2 increases, and the on-resistance of the PNP transistor Q2 decreases. As a result, the decrease in the voltage of the node ND4, which is the gate voltage of the epitaxial transistor M1, is suppressed, so that the increase in the current of the epitaxial transistor M1 is suppressed.

In the present embodiment, since the drain of the epitaxial transistor M1 and the drain of the epitaxial transistor M3 are not connected, the potential of the drain of the epitaxial transistor M1 and the potential of the drain of the epitaxial transistor M3 are not equal, and the current I2 is generated. It may not be K × I1. By the current mirror circuit CM1, the potential of the drain of the epitaxial transistor M1 and the potential of the drain of the epitaxial transistor M30 become the same, and the current I2 = K1 × I1 can be confirmed.

Further, by adjusting the resistance value of the variable resistor RB, the upper limit value of the current I1 flowing through the epitaxial transistor M1 can be adjusted. The magnitude of the resistors R1 and R2 can be adjusted by a signal from the timing controller 600.

Instead of the variable resistor RB, a resistor having a fixed resistance value may be used.
Even if the current mirror circuit CM1 is not provided, the current mirror circuit CM1 can be omitted if the difference between the potential of the drain of the epitaxial transistor M1 and the potential of the drain of the epitaxial transistor M3 is small and does not cause a problem.

As described above, according to the present embodiment, it is possible to correctly monitor the current flowing through the epitaxial transistor M1 and limit the inrush current flowing through the load.

[Third Embodiment]
The present embodiment relates to the detailed configuration and operation of the second voltage generation unit 400 (gate driver drive circuit). Specifically, a gate driver control circuit having a gate shading function will be described.

(Gate driver drive circuit in reference example)
FIG. 6 is a diagram showing the configuration of the gate driver drive circuit 400 of the reference example.

The gate driver drive circuit 400 of the reference example includes a pre-driver PD, a epitaxial transistor M11, and a capacitor CA.

The input terminal A2 has a steep rising portion and a steep falling portion, and receives a control signal FLK that changes periodically. This control signal FLK is, for example, a signal generated by the timing controller 600 and synchronized with the vertical synchronization signal.

The pre-driver PD responds to the control signal FLK and outputs a voltage VX to the node NDX in order to drive the epitaxial transistor M11.

The epitaxial transistor M11 is a node NDW connected to the power supply terminal A3 that receives the power supply voltage VCS generated by the power management IC 200, and a node NDZ connected to the output terminal P2 connected to the gate drivers 90-1 to 90-4. It is placed between and.

The gate of the epitaxial transistor M11 is connected to the node NDX and receives the voltage VX. When the magnitude of the voltage VX becomes smaller, the epitaxial transistor M11 is turned on, and the magnitude of the output voltage VGG of the node NDZ becomes smaller.

The capacitor CA is arranged between the node NDX and the node NDW.
FIG. 7 is a diagram showing transitions of the control signal FLK, the voltage VX of the node NX, and the output voltage VGG in the gate driver drive circuit 400 of the reference example.

In FIG. 7, the voltages VX and VGG when the drive capacity of the pre-driver PD is high are shown by solid lines, and the voltages VX and VGG when the drive capacity of the pre-driver PD is low are shown by broken lines.

First, the operation when the drive capacity of the pre-driver PD is high will be described.
When the control signal FLK drops to a low level at time t0, the voltage VX of the node NDX is lowered by the pre-driver PD. Since the pre-driver PD cannot suddenly lower the voltage VX, the voltage VX drops to the threshold voltage Vth of the epitaxial transistor M11 at the slope K1X.

At time t1, the voltage VX drops to the threshold voltage Vth of the epitaxial transistor M11. At this timing, the epitaxial transistor M11 is turned on and the output voltage VGG starts to decrease.

After that, the voltage VX maintains the threshold voltage Vth for a certain period of time by the action of the capacitor CA. During this time, the output voltage VGG decreases with the slope K1O.

At the timing of time t3, the pre-driver PD causes the voltage VX to tilt again and begin to drop at K1X. At this timing, the output voltage VGG reaches the minimum value.

At time t4, the voltage VX reaches the minimum value.
As described above, the output voltage VGG decreases with a constant slope K1O after ΔT1 (= t1-t0) time elapses from the timing of the fall of the control signal FLK.

The voltage VGG is supplied to the gate drivers 90-1 to 90-4.
For example, the gate driver 90-1 receives a voltage VGG. The gate driver 90-i uses the voltage VGG as a power supply voltage to generate a gate voltage GX and supplies it to the scanning line G-1. The outer shape of the gate voltage GX is the same as the outer shape of the voltage VGG.

It is assumed that the voltage supplied to the gate of TFT1-a at a certain time is Va. It is assumed that voltages of Vb, Vc, and Vd are applied to the gates of TFT1-b, 1-c, and 1-d in an ideal state where there is no parasitic capacitance on the scanning line G-1. Here, it is assumed that Vb = 2 × Va, Vc = 3 × Va, and Vd = 4 × Va. The distances between the gate driver 90-1 and TFT1-a, 1-b, 1-c, 1-d are D1, D2 (= 2 × D1), D3 (= 3 × D1), D4 (= 4 ×). Let it be D1).

It is assumed that the voltages applied to TFT1-b, TFT1-c, and TFT1-d become 1/2, 1/3, and 1/4 of the ideal state due to the parasitic capacitance of the scanning line G-1. As a result, the gates of TFTs 1-a to 1-d can all be turned on by receiving a voltage of the same magnitude at a certain time. As a result, the timing at which the TFT is turned on does not shift in the scanning line direction of the liquid crystal panel 700, so that it is possible to prevent the liquid crystal panel 700 from causing uneven brightness.

As described above, the luminance unevenness can be prevented by generating the voltage VGG that decreases with a constant inclination by using the falling edge of the control signal FLK as a trigger. Therefore, the gate driver drive circuit 400 of the reference example also has a gate shading function.

However, since the output voltage VGG starts to decrease after the timing of the falling edge of the control signal FLK, the TFT of the liquid crystal panel 700 does not turn on immediately from the falling edge of the control signal FLK, and the display of the liquid crystal panel 700 is displayed. You will be late.

Next, the operation when the drive capacity of the pre-driver PD is low will be described.
When the control signal FLK drops to a low level at time t0, the voltage VX of the node NDX is lowered by the pre-driver PD. Due to the pre-driver PD, the voltage VX drops to the threshold voltage Vth of the epitaxial transistor M11 at the slope K2X.

At time t2, the voltage VX drops to the threshold voltage Vth of the epitaxial transistor M11. At this timing, the epitaxial transistor M11 is turned on and the output voltage VGG starts to decrease.

After that, the voltage VX maintains the threshold voltage Vth for a certain period of time by the action of the capacitor CA. During this time, the output voltage VGG is tilted and decreases with K2O.

At the timing of time t4, the voltage VX tilts again due to the pre-driver PD and begins to decrease at K2X. At this timing, the output voltage VGG reaches the minimum value.

At time t5, the voltage VX reaches the minimum value.
As described above, the output voltage VGG decreases with a constant slope K2O after ΔT2 (= t2-t0) time elapses from the timing of the fall of the control signal FLK.

By lowering the drive capability of the pre-driver PD, it is possible to generate a voltage VGG that decreases with a smaller slope by using the falling edge of the control signal FLK as a trigger. However, the delay in the time when the output voltage VGG starts to decrease also increases. Therefore, if the drive capability of the pre-driver PD is reduced, the delay in the display of the liquid crystal panel 700 will increase.

(Gate driver drive circuit of the third embodiment)
FIG. 8 is a diagram showing the configuration of the gate driver drive circuit 400 of the third embodiment.

The gate driver drive circuit 400 includes a pre-driver PD, a MPa transistor M11, a capacitor CA, an NMOS transistor M13, and a control circuit 78.

Similar to the reference example, the input terminal A2 has a steep rising portion and a steep falling portion, and receives a control signal FLK that changes periodically.

Similar to the reference example, the pre-driver PD responds to the control signal FLK and outputs a voltage VX to the node NDX in order to drive the epitaxial transistor M11.

Similar to the reference example, the epitaxial transistor M11 includes a node NDW connected to the power supply terminal A3 that receives the power supply voltage VCS, and a node NDZ connected to the output terminal P2 connected to the gate drivers 90-1 to 90-4. Placed between.

The gate of the epitaxial transistor M11 is connected to the node NDX and receives the voltage VX. When the magnitude of the voltage VX becomes small, the epitaxial transistor M11 is turned on, and the magnitude of the output voltage VGG of the node NDZ becomes large.

The capacitor CA is arranged between the node NDX and the node NDW.
The NMOS transistor M13 is arranged between the node NDX and the ground GND. The gate of the NMOS transistor M13 is controlled by the control circuit 78.

The control circuit 78 turns on the NMOS transistor M13 by applying a high level voltage to the gate of the NMOS transistor M13 when the voltage of the node NDX is greater than the threshold voltage Vth that turns on the NMOS transistor M11. As a result, the voltage of the node NDX can be drastically reduced. The control circuit 78 turns off the NMOS transistor M13 by applying a low level voltage to the gate of the NMOS transistor M13 when the voltage of the node NDX drops to the threshold voltage Vrh that turns on the NMOS transistor M11. As a result, the control of the voltage of the node NDX via the NMOS transistor M13 is completed, and the voltage of the node NDX is controlled by the pre-driver PD.

The control circuit 78 includes a NOR, a epitaxial transistor M12, a resistor Rd, and a Schmitt trigger circuit 29.

The NOR circuit NOR has an input terminal IN1 that receives the control signal FLK, an input terminal IN2 that receives the output of the Schmitt trigger circuit 29, and an output terminal OUT that is connected to the NMOS transistor M13.

The epitaxial transistor M12 is arranged between the node NDZ and the node NDY. The gate of the epitaxial transistor M12 is connected to the node NDX.

The resistor Rd is arranged between the node NDY and the ground GND.
It is assumed that the threshold voltage of the epitaxial transistor M11 and the threshold voltage of the epitaxial transistor M12 are both Vth.

The Schmitt trigger circuit 29 receives the voltage VA of the node NDY and outputs the voltage VB to the input terminal IN2 of the NOR circuit NOR.

FIG. 9 is a diagram showing transitions of the control signal FLK of the gate driver drive circuit 400 of the third embodiment, the voltage VX of the node NX, and the output voltage VGG.

At time t0, the control signal FLK drops to a low level. At this timing, the control signal FLK input to the NOR circuit NOR is at a low level, and the output of the Schmitt trigger circuit 29 is at a low level, so that the output of the NOR is at a high level. Therefore, the NMOS transistor M13 is turned on, and the voltage VX of the node NDX suddenly drops to the threshold voltage Vth of the NMOS transistor M11. In this state, as in the reference example, the pre-driver PD also tries to gradually reduce the voltage VX of the node NDX, but the contribution of the NMOS transistor M13 is dominant. Further, at this timing, the epitaxial transistor M11 is turned on, and the output voltage VGG starts to decrease.

When the voltage of the node NDX drops to the threshold voltage Vth, the epitaxial transistor M12 is also turned on, and the voltage of the node NDY changes to the voltage of the output voltage VGG. As a result, the output of the Schmitt trigger circuit 29 changes to a high level, the output of the NOR circuit NOR becomes a low level, and the NMOS transistor M13 is turned off.

After that, the voltage VX maintains the threshold voltage Vth for a certain period of time by the action of the pre-driver PD and the capacitor CA. During this time, the output voltage VGG is tilted and decreases at K3O.

At the timing of time t6, the voltage VX tilts again due to the pre-driver PD and begins to decrease at K3X. At this timing, the output voltage VGG reaches the minimum value.

In the present embodiment, the output voltage VGG decreases with a constant slope K3O without delay from the timing of the falling edge of the control signal FLK.

Similar to the reference example, the voltage VGG is supplied to the gate drivers 90-1 to 90-4.
It is assumed that the voltages applied to TFT1-b, TFT1-c, and TFT1-d become 1/2, 1/3, and 1/4 of the ideal state due to the parasitic capacitance of the scanning line G-1. As a result, the gates of TFTs 1-a to 1-d are all turned on at a certain time by receiving a voltage of the same magnitude. As a result, the timing at which the TFT is turned on does not shift in the scanning line direction of the liquid crystal panel 700.

Further, in the present embodiment, the output voltage VGG starts to decrease without delaying from the fall timing of the control signal FLK, so that the TFT of the liquid crystal panel 700 is immediately turned on from the fall of the control signal FLK. It is possible to prevent the display of the liquid crystal panel 700 from being delayed.

FIG. 10 is a diagram showing the characteristics of the Schmitt trigger circuit 29.
When the voltage VA of the node NDY rises, the output voltage VB becomes a high level when the threshold value VH is exceeded. When the voltage VA of the node NDY decreases, the output voltage VB becomes a low level when it becomes smaller than the threshold value VL. As a result, fluctuations due to noise of the voltage VA of the node NDY can be removed, so that malfunction can be prevented.

As described above, according to the present embodiment, by providing the NMOS transistor M13 and the control circuit 78, the gate driver provides a voltage that does not cause flicker in the liquid crystal panel and does not delay the display of the liquid crystal panel. It can be supplied to the drive circuit.

[Fourth Embodiment]
The present embodiment relates to the detailed configuration and operation of the third voltage generation unit (switching power supply circuit) 500. Specifically, a switching power supply circuit having a function of preventing noise of parts will be described.

(Switching power supply circuit of reference example)
FIG. 11 is a diagram showing a configuration of a switching power supply circuit 500 of a reference example.

The switching power supply circuit 500 of the reference example includes an asynchronous rectifying DC-DC circuit 35, a driver control unit 31, and a discharge control unit 32.

The asynchronous rectifying DC-DC circuit 35 includes a first switching element, a MOSFET transistor M21, a resistor RC, an NMOS transistor M22, a choke coil LA, a diode DA, and a smoothing capacitor CB.

The epitaxial transistor M21 is arranged between the input terminal A4 that receives the input voltage VIN and the node NX. The gate of the epitaxial transistor 21 is connected to the driver control unit 31. The gate of the epitaxial transistor M21 receives a switching signal SW from the driver control unit 31.

The choke coil LA is arranged between the node NX and the node NY connected to the output terminal P3. The output terminal P3 is connected to the load LD. Specifically, the load LD is a timing controller 600 and a control circuit 92.

The capacitor CB is arranged between the node NY and the ground GND.
The diode DA is arranged between the node NX and the ground GND. The anode of the diode DA is connected to the ground GND and the cathode of the diode DA is connected to the node NX.

The resistor RC is placed between the node NX and the node NZ.
The NMOS transistor M22 is arranged between the node NZ and the ground GND. The gate of the NMOS transistor M22 is connected to the discharge control unit 32. The gate of the NMOS transistor M22 receives the discharge signal DSC from the discharge control unit 32.

When the epitaxial transistor M21, which is a switching element, is in the ON state, energy is stored in the choke coil LA by the current flowing from the input terminal A4 to the output terminal P3. When the epitaxial transistor M21 is turned from the on state to the off state, the choke coil LA releases the stored energy, an electromotive force is generated in a direction that hinders the current change, and an induced current is passed to obtain a direct current. .. This direct current is smoothed by the capacitor CB and output to the output terminal P3.

When the power is turned off, the discharge control unit 32 receives the shutdown signal SDW and turns on the NMOS transistor M22 by raising the discharge signal DSC to a high level. As a result, the electric charge stored in the capacitor CB is discharged. Since the NMOS transistor M22 operates to draw out a current, a large size MOSFET is used.

FIG. 12 is a diagram showing the configuration of the driver control unit 31.
The driver control unit 31 includes voltage dividing resistors R11 and R12, a reference voltage generation unit 34, an overvoltage threshold control unit 38, an error amplifier 36, an overvoltage detector 37, and a PWM (Pulse Width Modulation) signal generation circuit 39. To be equipped.

The voltage dividing resistor R11 and the voltage dividing resistor R10 divide the voltage VDD of the node NY to generate a feedback voltage VB.

The reference voltage generation unit 34 generates a reference voltage VREF from the input voltage VIN and outputs it to the error amplifier 36 and the overvoltage detector 37.

The error amplifier 36 outputs an error voltage VEA that amplifies the difference between the feedback voltage VB and the reference voltage VREF.

The overvoltage threshold control unit 38 receives the reference voltage VREF and outputs the threshold voltage VREF2 which is ΔV larger than the reference voltage VREF.

The overvoltage detector 37 outputs a low-level skip signal SK when the feedback voltage VB is equal to or less than the threshold voltage VREF2, and outputs a high-level skip signal SK when the feedback voltage VB exceeds the threshold voltage VREF2.

Normally, the feedback voltage VB does not exceed the threshold voltage VREF2, so that the skip signal SK output from the overvoltage detector 37 becomes a low level.

When the skip signal SK is at a low level, the PWM signal generation circuit 39 drives the MPa transistor M21, which is a switching element, at regular intervals. That is, the PWM signal generation circuit 39 maintains the on-time at the minimum on-time until the error voltage VEA reaches the set voltage TH from 0. When the error voltage VEA exceeds the set voltage TH, the PWM signal generation circuit 39 increases the on-time in direct proportion to the increase in the error voltage VEA. The PWM signal generation circuit 39 generates a switching signal SW based on the on-time. The PWM signal generation circuit 39 generates a switching signal SW having the minimum pulse width when the on time is set to the minimum on time. When the on-time exceeds the minimum on-time, the PWM signal generation circuit 39 increases the pulse width of the switching signal SW as the on-time increases.

The output voltage VDD increases at light load and no load. When the output voltage VDD rises, the feedback voltage VB also rises and exceeds the threshold voltage VREF2. As a result, the skip signal SK output from the overvoltage detector 37 becomes a high level. The PWM signal generation circuit 39 skips the switching operation while the skip signal SK is at a high level. That is, the pulse of the switching signal SW is skipped. As a result, the switching loss can be reduced and the output voltage VDD can be prevented from rising.

When the switching frequency of the epitaxial transistor M21, which is the frequency of the switching signal SW, drops to the audible range (20Hz to 20KHz) as a result of pulse skipping under light load and no load, the components constituting the switching power supply circuit 500 make a sound. A ringing phenomenon occurs. The switching power supply circuit 500 of the reference example has such a problem of sounding.

(Switching power supply circuit of the fourth embodiment)
FIG. 13 is a diagram showing the configuration of the switching power supply circuit 500 of the fourth embodiment.

The switching power supply circuit 500 of the fourth embodiment includes an NMOS transistor M23, which is a second switching element, and a discharge control unit 33, in addition to the components of the reference example.

The NNOS transistor M23 is arranged in parallel with the NMOS transistor M22 between the node NZ and the ground GND.

The discharge control unit 33 outputs an ON signal ON for turning on the NMOS transistor M23 while the NMOS transistor M21 is off. When the ON signal is turned ON and the NMOS transistor M23 is turned ON, the electric charge stored in the capacitor CB is discharged. As a result, an increase in the output voltage VDD can be suppressed so that pulse skipping does not occur.

However, the size of the NMOS transistor M23 shall be smaller than the size of the NMOS transistor M22 so that only a small amount of current flows through the NMOS transistor M23.

FIG. 14 is a diagram showing the timing of switching signal SW and ON signal ON within one cycle in a normal time.

As shown in FIG. 14, the driver control unit 31 lowers the switching signal SW in order to turn on the first switching element, the MPa transistor M21, during any period during which the internal clock CLK of the period T is off. Activated to.

The discharge control unit 33 activates the ON signal ON to a high level in order to turn on the NMOS transistor M23, which is the second switching element, during the period when the internal clock CLK of the period T is ON.

FIG. 15 is a diagram showing the timing of switching signal SW and ON signal ON in a normal state.

Normally, since the feedback voltage VB does not exceed the threshold voltage VREF2, pulse skipping does not occur. The driver control unit 31 changes the switching signal SW so that the first switching element, the MIMO transistor M21, is turned on and off for each cycle of the internal clock CLK.

The discharge control unit 33 changes the ON signal ON so that the NMOS transistor M23, which is the second switching element, is turned ON and OFF for each cycle of the internal clock CLK.

FIG. 16 is a diagram showing the timing of switching signal SW and ON signal ON at the time of light load.

When the load is light, the error voltage VEA becomes small, so that the pulse width of the switching signal SW becomes small. Further, when the load is light, the feedback voltage VB exceeds the threshold voltage VREF2, so that pulse skipping occurs. As a result, the switching cycle becomes large.

However, the NMOS transistor M23 discharges the charge stored in the capacitor CB. As a result, it is possible to prevent the switching frequency of the epitaxial transistor M21, which is the frequency of the switching signal SW, from dropping to the audible range (20 Hz to 20 KHz), so that the components constituting the switching power supply circuit 500 do not generate sound. can do.

FIG. 17 is a diagram showing the timing of switching signal SW and ON signal ON when no load is applied.

Even when there is no load, the feedback voltage VB exceeds the threshold voltage VREF2 as in the case of light load, so pulse skipping occurs. However, even when there is no load, the pulse may not disappear completely due to the influence of the current leakage component. In such a case, the switching cycle becomes large as in the case of a light load. However, even in such a case, since the charge stored in the capacitor CB is discharged by the NMOS transistor M23, it is possible to prevent noise from being generated from the components constituting the switching power supply circuit 500.

FIG. 18 is a diagram showing the timing of switching signal SW and ON signal ON at shutdown.

The driver control unit 31, the discharge control unit 32, and the discharge control unit 22 receive the shutdown signal SDW from the timing controller 600 when the power is turned off.

When the shutdown signal SDW is activated to a high level, the driver control unit 31 ends the switching of the epitaxial transistor M21.

The discharge control unit 33 terminates the switching of the NMOS transistor M23 when the shutdown signal SDW is activated to a high level.

When the shutdown signal SDW is activated to a high level, the discharge control unit 32 activates the discharge signal DSC to the gate of the NMOS transistor M22 to a high level. When the discharge signal DSC is activated to a high level, the NMOS transistor M22 is turned on, and the charge accumulated in the capacitor CB is discharged through the NMOS transistor M22.

As described above, according to the present embodiment, the pulse skip function can reduce the switching loss and prevent the switching frequency from being reduced to the audible frequency band, so that the components constituting the switching power supply circuit make noise. It can be prevented from occurring.

[Modification 1 of the fourth embodiment]
In the fourth embodiment, the on-signal is activated and the charge of the capacitor CB is discharged through the NMOS transistor M23 regardless of the switching frequency of the MOSFET transistor M21, but the present invention is not limited to this. No.

For example, the charge of the capacitor CB may be discharged through the NMOS transistor M23 only when the switching frequency of the MOSFET transistor M21 drops to the audible frequency band.

The discharge control unit 33 detects the switching frequency of the epitaxial transistor M21. For example, the discharge control unit 33 detects the switching frequency of the epitaxial transistor M21 by monitoring the pulse skip by the driver control unit 31. When the detected switching frequency of the epitaxial transistor M21 is within a predetermined range, the discharge control unit 33 is a second switching element, an NMOS transistor, while the first switching element, the NMOS transistor M21, is off. Turn on M23 to discharge the charge of the transistor CB.

[Modification 2 of the fourth embodiment]
FIG. 19 is a diagram showing the configuration of the third voltage generation unit 500 of the modified example of the fourth embodiment.

In the fourth embodiment, the switching power supply circuit includes, but is limited to, an NMOS transistor M22 for discharging the charge of the capacitor CB at shutdown and a discharge control unit 32 for controlling the NMOS transistor M22. It's not a thing.

As shown in FIG. 19, the switching power supply circuit 500 may not include the NMOS transistor M22 and the discharge control unit 32.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1-a to 1-d TFT, 2-a to 2-d pixels, 11,34 reference voltage generator, 12 differential amplifier, 13a, 13b current limiting circuit, 14 input differential amplifier circuit, 15 output difference Dynamic amplifier circuit, 29 Schmidt trigger circuit, 31 driver control unit, 32, 33 discharge control unit, 35, 45, 55 asynchronous rectifier circuit, 36 error amplifier, 37 overvoltage detector, 38 voltage threshold control unit, 39 PWM signal generation circuit , 68 feedback unit, 90-1 to 90-4 gate driver, 91-1 to 91-4 source driver, 78,92 control circuit, 100 drive board, 120 drive circuit, 140 liquid crystal module, 200 power circuit IC, 300th 1 voltage generator (voltage regulator circuit), 400 second voltage generator (gate driver drive circuit), 500 third voltage generator (switching power supply circuit), 600 timing controller, 700 liquid crystal panel, 800 gate circuit, 900 Source circuit, DA diode, CM1, CM2 Current mirror circuit, R1, R2, R10, R11, R61, R62, RA, RB, RC, Rd resistor, CA, CB capacitor, LD load, A1, A2, A3, A4 , P1, P2, P3 terminals, M1, M4, M5, M11, M12, M21, M3, P61, P62, P63 ProLiant transistors, M2, M6, M7, M13, M22, M23, N61, N62, N63, N65, N66 NMOS transistor, IS1, IS2 constant current source, Q1, Q2 PNP transistor, PD predriver, NOR negative logic sum circuit.

Claims (8)

In response to a control signal having a steep falling edge, a pre-driver that outputs a driving voltage to the first node,
A first transistor having a control electrode arranged between a power supply terminal and an output terminal to which a gate driver is connected and connected to the first node, and a first transistor.
A capacitor arranged between the control electrode of the first transistor and the power supply terminal,
A second transistor arranged between the first node and ground,
A control circuit for controlling the control electrode of the second transistor is provided.
When the voltage of the first node is higher than the threshold voltage for turning on the first transistor, the first transistor is turned off, and when the voltage of the first node is equal to or less than the threshold voltage, the first transistor is turned off. The first transistor is turned on and
The control circuit is a gate driver drive circuit that turns on the second transistor when the voltage of the first node is higher than the threshold voltage. The gate driver drive circuit according to claim 1, wherein the control circuit turns off the second transistor when the voltage of the first node drops to the threshold voltage. The control circuit
A third transistor arranged between the output terminal and the second node and having a control electrode connected to the first node, and a third transistor.
Includes a resistor located between the second node and ground
The gate driver drive circuit according to claim 2, wherein the voltage of the control electrode of the second transistor changes according to the voltage of the second node. The control circuit
A logic circuit including a first input terminal that receives the control signal, a second input terminal that receives the voltage of the second node, and an output terminal connected to a control electrode of the second transistor. The gate driver drive circuit according to claim 3. The first transistor is a epitaxial transistor and
The second transistor is an NMOS transistor.
The gate driver drive circuit according to claim 4, wherein the third transistor is a epitaxial transistor. The gate driver drive circuit according to claim 5, wherein the logic circuit is a NOR OR circuit. The gate driver drive circuit according to claim 4, further comprising a Schmitt trigger circuit arranged between the second node and the second input terminal of the logic circuit. LCD panel and
The source driver that drives the data line of the liquid crystal panel and
A gate driver that drives the scanning lines of the liquid crystal panel and
The gate driver drive circuit according to claim 1 is provided.
A liquid crystal display device in which a voltage output from the output terminal of the gate driver drive circuit is supplied to the plurality of gate drivers.

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