WO2012157257A1

WO2012157257A1 - Driver system

Info

Publication number: WO2012157257A1
Application number: PCT/JP2012/003163
Authority: WO
Inventors: 直人濱口
Original assignee: シャープ株式会社
Priority date: 2011-05-19
Filing date: 2012-05-15
Publication date: 2012-11-22

Abstract

Provided is a driver system that is capable of reducing a current flowing through a load in the event of the restitution of a power supply voltage after a momentary drop in the power supply voltage. The driver system is equipped with: a switching circuit that, upon receiving a power supply voltage, switches the current which flows through a display panel; a driver that generates a control voltage which has been pulse-modulated on the basis of an output voltage from the switching circuit and supplies the control voltage to the switching circuit in order to drive the switching circuit; and a controller that reduces the duty ratio of the control voltage in response to a falling edge of the power supply voltage.

Description

Driver system

This disclosure relates to a driver used with a display panel.

The driver system is a system that supplies a voltage for driving the display panel. In order to drive the display panel, a switching regulator is used as a driver. The driver system receives a voltage for driving the display panel from a power source. A driver according to the prior art is described in Patent Document 1, for example.

JP 2009-33090 A

The inventors of the present invention have recognized that, in the conventional system, when the power supply voltage drops momentarily, an overcurrent flows through the load (for example, a display panel) when the power supply voltage is restored. In the system according to the prior art, it has not been possible to prevent an overcurrent from flowing through the load in the above-described state. SUMMARY OF THE INVENTION An object of the present invention is to provide a driver system that can reduce the current flowing through a load when the power supply voltage is restored after the power supply voltage has dropped instantaneously.

According to an embodiment, the driver system receives a power supply voltage, and generates a control circuit that switches a current that flows through a display panel, and a control voltage that is pulse-width modulated based on an output voltage of the switching circuit. A driver for driving the switching circuit by applying a voltage to the switching circuit; and a controller for reducing a duty ratio of the control voltage in response to a fall of the power supply voltage.

With the above configuration, when the power supply voltage recovers after the power supply voltage drops instantaneously, the current flowing through the load can be reduced.

According to an embodiment, the controller includes a detector that detects a falling edge of the power supply voltage and a comparator that compares the power supply voltage with a predetermined threshold.

With the above configuration, the period for reducing the duty ratio can be determined appropriately.

According to an embodiment, the switching circuit is a boost converter, and the boost converter includes a field effect transistor.

With the above configuration, a desired output voltage can be generated with higher efficiency.

According to an embodiment, the controller and the driver are provided on one semiconductor chip.

With the above configuration, more stable circuit operation, lower manufacturing cost, and / or smaller size can be achieved compared to realizing these circuits with individual elements mounted on a printed circuit board.

According to the present invention, it is possible to provide a driver system that can reduce the current flowing through the load when the power supply voltage recovers after the power supply voltage has dropped instantaneously.

FIG. 1 is a diagram illustrating a driver system according to an exemplary embodiment of the present invention. FIG. 2 is a waveform diagram showing the operation of the driver system. FIG. 3 is a waveform diagram showing the operation of the conventional system. FIG. 4 is a waveform diagram showing the operation of the driver system in more detail. FIG. 5 is a block diagram showing the configuration of the driver. FIG. 6 is a block diagram showing the configuration of the controller. FIG. 7 is a waveform diagram illustrating the operation of a driver according to an embodiment. FIG. 8 is a waveform diagram showing the operation of the driver according to another embodiment.

Hereinafter, exemplary embodiments of a driver system according to the present invention will be described in detail with reference to the drawings. In the drawings, the same or similar components are represented by the same reference numerals.

(Constitution)
FIG. 1 is a diagram illustrating a driver system 100 according to an exemplary embodiment of the present invention. The driver system 100 is used for a television having a liquid crystal display (LCD) panel 110, a display monitor for a personal computer, and the like. The driver system 100 supplies a voltage to the LCD panel 110. A backlight 120 may be provided on the back surface of the LCD panel 110. The driver system 100 includes a switching circuit 130, a driver 140, and a controller 150.

In the driver system 100, the driver 140 and the controller 150 are preferably provided on one semiconductor chip 160. However, the method of putting the functional blocks of the driver system 100 in a package is not limited to this. For example, the driver 140 may be provided on one semiconductor chip, and the controller 150 may be separately provided outside the driver chip. Alternatively, the driver 140 and the controller 150 may be provided on the LCD panel 110. In addition, the switching circuit 130 may be provided on the LCD panel 110.

The backlight 120 irradiates the back surface of the LCD panel 110 with light. The light from the backlight 120 passes through the LCD panel 110 and reaches the user. With such a configuration, the user can view an image on the LCD panel 110. The backlight 120 is typically driven by a dedicated power source that is different from the driver system 100.

The switching circuit 130 receives the power supply voltage Vcc and controls the voltage Vout supplied to the LCD panel 110 based on the control voltage Vg. By this operation, the driver system 100 generates a reference voltage for the LCD panel 110. Examples of the reference voltage of the LCD panel 110 include a high-side gate voltage (Vgh), a low-side gate voltage (Vgl), and a source voltage (Vs). Switching circuit 130 is typically a boost converter.

The switching circuit 130 includes a switching element 132, an inductor 134, a diode 136, and a capacitor 138. The switching element 132 is preferably a field effect transistor (FET). The specific configuration of the switching circuit 130 is not limited to the circuit shown in FIG. 1 and may be any appropriate switching regulator. In order to realize a high-efficiency step-up converter, a switching element 132 that can be turned off at high speed and a diode 136 with a short reverse recovery time are preferably used.

The driver 140 drives the switching circuit 130 by applying a pulse width modulated control voltage Vg to the control terminal of the switching element 132 (here, the gate of the FET). The switching circuit 130 feeds back the output voltage Vout at the output node OUT to the driver 140. With this feedback loop, the driver 140 can control the operation of the switching circuit 130 so that the output voltage Vout becomes a desired value. For example, when the output voltage Vout is larger than a desired value, the driver 140 decreases the duty ratio of the control voltage Vg. Conversely, when the output voltage Vout is smaller than a desired value, the driver 140 increases the duty ratio of the control voltage Vg. Here, the desired value of the output voltage Vout may be a constant value or a value that varies depending on the brightness of the image.

Controller 150 reduces the duty ratio of control voltage Vg in response to the fall of power supply voltage Vcc. That is, the controller 150 outputs the reset signal Vreset to the driver 140 when the power supply voltage Vcc falls to the threshold value Vth at the falling edge of the power supply voltage Vcc. The driver 140 sets the duty ratio of the control voltage Vg to be small while the reset signal Vreset is asserted. The reduction of the duty ratio of the control voltage Vg will be described in detail later with reference to FIGS.

In this specification, the term “assert” refers to activating (or validating) a signal (or logical value) in a digital circuit. For example, when a positive logic signal is asserted, it becomes H level. Conversely, when a negative logic signal is asserted, it goes to the L level. Various circuits described in this disclosure may be implemented in either positive logic or negative logic.

(Operation)
FIG. 2 is a waveform diagram showing the operation of the driver system 100. The horizontal axis represents time, and the vertical axis represents the power supply voltage Vcc, the reset signal Vreset, the control voltage Vg, the output voltage Vout, and the current Icc from the top. The power supply voltage Vcc is a rated value (also referred to as a normal value) before time t0. An instantaneous voltage drop occurs at time t0. In this specification, the term “instantaneous voltage drop” means that the power supply voltage Vcc drops instantaneously.

At time t1, the power supply voltage Vcc drops to the threshold value Vth. At time t1, the controller 150 detects the falling edge of the power supply voltage Vcc and detects that the power supply voltage Vcc has dropped to the threshold value Vth. The controller 150 asserts the reset signal Vreset and outputs it to the driver 140 during a predetermined period Reset from time t1 to time t3. In the example of FIG. 2, the power supply voltage Vcc returns to the rated value at time t2, but the controller 150 keeps the reset signal Vreset asserted until time t3.

The driver 140 sets the duty ratio of the control voltage Vg to be small during the period Reset (time t1 to time t3) during which the reset signal Vreset is asserted. Specifically, a waveform indicated by a dotted line in the control voltage Vg in FIG. 2 is a control voltage output by a conventional system that does not have the controller 150. In contrast, the driver system 100 having the controller 150 outputs a control voltage Vg having a waveform indicated by a solid line to the switching circuit 130. That is, the driver system 100 sets the duty ratio of the control voltage Vg to be smaller than that of the conventional system during the period Reset when the power supply voltage is momentarily reduced. The period Treset need only be long enough to cover the transient state of the power supply voltage, and is preferably on the order of several tens of microseconds.

The output voltage Vout rises again after the instantaneous voltage drop. However, a surge voltage is not generated at the output node OUT due to the duty ratio reduction. Therefore, the surge of the current Icc has only a peak value that can be tolerated.

(effect)
FIG. 3 is a waveform diagram showing the operation of the conventional system. The horizontal axis represents time, and the vertical axis represents the power supply voltage Vcc, the output voltage Vout, and the current Icc from the top. In the conventional system, the duty ratio of the control voltage is not reduced in response to the instantaneous voltage drop (time t0). Therefore, the rising edge of the output voltage Vout at time t1 becomes very steep. As a result, a surge current also appears in the current Icc (time t1). This surge current causes an undesirable overcurrent to flow through the load.

FIG. 4 is a waveform diagram showing the operation of the driver system 100 in more detail. The horizontal axis represents time, and the vertical axis represents the power supply voltage Vcc, the output voltage Vout, and the current Icc from the top. The broken line in FIG. 4 represents a waveform indicating the operation of the conventional system.

In the driver system 100, the controller 150 reduces the duty ratio of the control voltage Vg in response to the instantaneous voltage drop (time t0). Therefore, the rising edge of the output voltage Vout at time t1 is not as steep as the edge in the conventional system. As a result, no high surge current appears in the current Icc. Unlike the surge current of FIG. 3, the surge current at current Icc of FIG. 4 is usually acceptable.

The liquid crystal panel needs to be driven with a constant voltage. Therefore, the above operation is advantageous when an irregular power supply voltage Vcc is input.

(Driver details)
FIG. 5 is a block diagram showing the configuration of the driver 140. The driver 140 includes a comparator 510 and a pulse width modulation (PWM) circuit 520. Comparator 510 receives output voltage Vout at non-inverting input node 512 and receives reference voltage Vref at inverting input node 514. Comparator 510 asserts output 516 when output voltage Vout is greater than a predetermined reference voltage Vref. The comparator 510 is generally realized by an operational amplifier (OP amplifier) having a high amplification factor. The specific amplification factor depends on how much the change in the output voltage Vout is fed back as the change in the pulse width of the control voltage Vg.

The PWM circuit 520 makes the output voltage Vout constant by performing pulse width modulation on the control voltage Vg based on the output 516. Specifically, when the output voltage Vout is larger than the reference voltage Vref, the output voltage Vout is lowered by narrowing the pulse width of the control voltage Vg. Conversely, when the output voltage Vout is smaller than the reference voltage Vref, the output voltage Vout is increased by increasing the pulse width of the control voltage Vg. In addition to this control, the PWM circuit 520 reduces the duty ratio of the control voltage Vg when the reset signal Vreset is asserted compared to when the reset signal Vreset is not. In this specification, the term “duty ratio reduction” means that the duty ratio is reduced more than when the reset signal Vreset is not asserted (or a conventional example).

(Details of controller)
FIG. 6 is a block diagram showing the configuration of the controller 150. The controller 150 has an input node 602, a comparator 610, a falling edge detector 650, an AND gate 690, and an output node 698. Controller 150 receives power supply voltage Vcc at input node 602 and outputs reset signal Vreset at output node 698.

The comparator 610 compares the power supply voltage Vcc with a predetermined threshold voltage Vth. For example, when the power supply voltage Vcc falls below the threshold voltage Vth, the comparator 610 asserts its output node. The falling edge detector 650 includes

inverters

652 and 654, a resistor 656, a capacitor 658, and a NOR gate 662. The falling edge detector 650 detects the falling edge of the power supply voltage Vcc, and asserts the output node 664 for a predetermined period from the detected time. AND gate 690 generates a logical product of the comparison between power supply voltage Vcc and threshold voltage Vth and the detection of the falling edge of power supply voltage Vcc, and outputs the logical product to output node 698.

(Duty ratio limit)
FIG. 7 is a waveform diagram illustrating the operation of the driver 140 according to an embodiment. The horizontal axis represents time, and the vertical axis represents the reset signal Vreset and the duty ratio D of the control voltage Vg from the top. The driver 140 according to an embodiment generates the control voltage Vg so that the duty ratio D of the control voltage Vg is limited by the duty ratio limit Dlimit during the period Reset when the reset signal Vreset is asserted, and outputs the control voltage Vg to the switching circuit 130. To do. With this operation, even if an instantaneous voltage drop occurs, the duty ratio D of the control voltage Vg does not reach the maximum value Dfull, but is limited by the duty ratio limit Dlimit. In general, such voltage limitation is also called clipping. As a specific example, preferably the driver 140 limits the duty ratio D of the control voltage Vg to a duty ratio limit Dlimit equal to the maximum value Dfull / 2. The value with which the driver 140 limits the duty ratio D is not limited to Dlimit used in the present embodiment, and may be any appropriate value.

FIG. 8 is a waveform diagram showing the operation of the driver 140 according to another embodiment. The horizontal axis represents time, and the vertical axis represents the reset signal Vreset and the duty ratio D of the control voltage Vg from the top. The driver 140 according to an embodiment sets the control voltage Vg such that the duty ratio D of the control voltage Vg is limited in stages by the plurality of duty ratios D1, D2, and D3 during the period Reset during which the reset signal Vreset is asserted. And output to the switching circuit 130. By this operation, even if an instantaneous voltage drop occurs, the duty ratio D of the control voltage Vg does not reach the maximum value Dfull, but is limited step by step with the duty ratios D1, D2, and D3. As a specific example, the driver 140 preferably limits the duty ratio D of the control voltage Vg step by step to duty ratios D1, D2, and D3 equal to 0.25Dfull, 0.50Dfull, and 0.75Dfull, respectively. The value that the driver 140 limits the duty ratio D is not limited to D1, D2, and D3 used in the present embodiment, and may be any appropriate value.

In this specification, the term “duty ratio reduction” may be a constant frequency of the control voltage Vg or may be changed. That is, the driver 140 may maintain the frequency of the control voltage Vg constant, reduce the ratio of the on period, or reduce the absolute length of the on period. In either case, as a result, the driver 140 reduces the duty ratio of the control voltage Vg.

In the above description, various functions can be realized as individual elements. Conversely, a plurality of functions may be realized as a single element. For example, a plurality of functions may be realized as a single circuit element such as a single semiconductor chip or a single hybrid integrated circuit. It may be realized above.

As will be understood by those skilled in the art, some of the various elements described above (hardware elements, software steps, etc.) may be omitted. Conversely, additional elements may be used.

What has been described above includes various examples of the present invention. For the purposes of describing the present invention, it is of course impossible to describe every possible combination of elements and procedures, but those skilled in the art will recognize that many further combinations and permutations of the present invention are possible. right. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.

The present invention is useful in that it can provide a driver system that can reduce the current flowing through the load when the power supply voltage recovers after the power supply voltage drops momentarily.

100 Driver System 110 LCD Panel 120 Backlight 130 Switching Circuit 132 Switching Element 134 Inductor 136 Diode 138 Capacitor 140 Driver 150 Controller 160 Semiconductor Chip

Claims

A switching circuit that receives a power supply voltage and switches a current flowing through the display panel;
A driver for driving the switching circuit by generating a pulse width modulated control voltage based on the output voltage of the switching circuit and providing the control voltage to the switching circuit;
And a controller that reduces a duty ratio of the control voltage in response to a fall of the power supply voltage.
The controller is
A detector for detecting a falling edge of the power supply voltage;
The driver system according to claim 1, further comprising a comparator that compares the power supply voltage with a predetermined threshold value.
3. The driver system according to claim 2, wherein the switching circuit is a boost converter, and the boost converter includes a field effect transistor.
4. The driver system according to claim 3, wherein the controller and the driver are provided on one semiconductor chip.