JP6961686B2 - トリガ動作を用いたｇｐｕリモート通信 - Google Patents

トリガ動作を用いたｇｐｕリモート通信 Download PDF

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Publication number
JP6961686B2
JP6961686B2 JP2019517022A JP2019517022A JP6961686B2 JP 6961686 B2 JP6961686 B2 JP 6961686B2 JP 2019517022 A JP2019517022 A JP 2019517022A JP 2019517022 A JP2019517022 A JP 2019517022A JP 6961686 B2 JP6961686 B2 JP 6961686B2
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remote communication
network remote
generated network
communication command
gpu
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Japanese (ja)
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JP2019532427A5 (enExample
JP2019532427A (ja
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ダブリュー． ルビーン マイケル
ケイ． ラインハルト スティーブン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17331—Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computer And Data Communications (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP2019517022A 2016-10-18 2017-09-19 トリガ動作を用いたｇｐｕリモート通信 Active JP6961686B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/297,079 US10936533B2 (en) 2016-10-18 2016-10-18 GPU remote communication with triggered operations
US15/297,079 2016-10-18
PCT/US2017/052250 WO2018075182A1 (en) 2016-10-18 2017-09-19 Gpu remote communication with triggered operations

Publications (3)

Publication Number Publication Date
JP2019532427A JP2019532427A (ja) 2019-11-07
JP2019532427A5 JP2019532427A5 (enExample) 2020-11-12
JP6961686B2 true JP6961686B2 (ja) 2021-11-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019517022A Active JP6961686B2 (ja) 2016-10-18 2017-09-19 トリガ動作を用いたｇｐｕリモート通信

Country Status (6)

Country Link
US (1) US10936533B2 (enExample)
EP (1) EP3529706B1 (enExample)
JP (1) JP6961686B2 (enExample)
KR (1) KR102245247B1 (enExample)
CN (1) CN109690512B (enExample)
WO (1) WO2018075182A1 (enExample)

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US10783102B2 (en) 2016-10-11 2020-09-22 Oracle International Corporation Dynamically configurable high performance database-aware hash engine
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US10725947B2 (en) 2016-11-29 2020-07-28 Oracle International Corporation Bit vector gather row count calculation and handling in direct memory access engine
US20190044809A1 (en) * 2017-08-30 2019-02-07 Intel Corporation Technologies for managing a flexible host interface of a network interface controller
US11429413B2 (en) * 2018-03-30 2022-08-30 Intel Corporation Method and apparatus to manage counter sets in a network interface controller
US10740163B2 (en) * 2018-06-28 2020-08-11 Advanced Micro Devices, Inc. Network packet templating for GPU-initiated communication
US10795840B2 (en) 2018-11-12 2020-10-06 At&T Intellectual Property I, L.P. Persistent kernel for graphics processing unit direct memory access network packet processing
US12267229B2 (en) * 2019-05-23 2025-04-01 Hewlett Packard Enterprise Development Lp System and method for facilitating data-driven intelligent network with endpoint congestion detection and control
US11182221B1 (en) * 2020-12-18 2021-11-23 SambaNova Systems, Inc. Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
US11665113B2 (en) * 2021-07-28 2023-05-30 Hewlett Packard Enterprise Development Lp System and method for facilitating dynamic triggered operation management in a network interface controller (NIC)
US11960813B2 (en) 2021-08-02 2024-04-16 Advanced Micro Devices, Inc. Automatic redistribution layer via generation
US12418906B2 (en) 2022-02-27 2025-09-16 Nvidia Corporation System and method for GPU-initiated communication
US20230276301A1 (en) * 2022-02-27 2023-08-31 Nvidia Corporation System and method for gpu-initiated communication
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US12210468B2 (en) 2023-01-19 2025-01-28 SambaNova Systems, Inc. Data transfer between accessible memories of multiple processors incorporated in coarse-grained reconfigurable (CGR) architecture within heterogeneous processing system using one memory to memory transfer operation
US12380041B2 (en) 2023-01-19 2025-08-05 SambaNova Systems, Inc. Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using two memory to memory transfer operations
US20250254137A1 (en) * 2024-02-05 2025-08-07 Mellanox Technologies, Ltd. Low latency communication channel over a communications bus using a host channel adapter

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Also Published As

Publication number Publication date
EP3529706A1 (en) 2019-08-28
US10936533B2 (en) 2021-03-02
WO2018075182A1 (en) 2018-04-26
KR20190058483A (ko) 2019-05-29
KR102245247B1 (ko) 2021-04-27
CN109690512A (zh) 2019-04-26
EP3529706B1 (en) 2023-03-22
EP3529706A4 (en) 2020-03-25
CN109690512B (zh) 2023-07-18
US20180107627A1 (en) 2018-04-19
JP2019532427A (ja) 2019-11-07

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