JP6954816B2 - Interface unit and semiconductor device - Google Patents

Description

The present invention relates to a technique for connecting a semiconductor device in which a plurality of semiconductor modules are connected in parallel to an external device via an interface unit.

Semiconductor devices, especially power semiconductor devices (power semiconductor devices), are soldered or screwed to an external device such as a general-purpose inverter via a printed plate or a bus bar provided on the external device side. Connected by. Patent Document 1 discloses an interface unit as a technique for connecting a semiconductor device and an external device.

Further, in a power conversion device (semiconductor device) such as an inverter, the current flowing in the main circuit portion is detected by a current sensor. For example, Patent Document 2 includes a switching power module, a current sensor that detects an output signal proportional to the current flowing through the main circuit wiring, and a resin case in which the switching power module and the current sensor are integrally molded. The power converter is disclosed.

Further, Patent Document 3 includes a plurality of current paths installed in parallel and a magnetic detection element provided corresponding to each current path and detecting the strength of a magnetic field generated by a current flowing through each current path. A current detection device in which a magnetic detection unit and a part of a plurality of current paths are housed in a mold package is disclosed.

Japanese Patent Application No. 2017-075243 Japanese Unexamined Patent Publication No. 2004-343820 Japanese Unexamined Patent Publication No. 2016-99292

However, in the technique disclosed in Patent Document 1, mounting of a current sensor is not considered. On the other hand, although Patent Document 2 discloses a current sensor, it is not possible to select whether or not to mount the current sensor because the current sensor is integrated in the resin case of the semiconductor module. Therefore, the only way to make it possible to select whether or not to install a current sensor was to realize it with another module. Further, in the technique disclosed in Patent Document 3, it is necessary to connect a current detection device between a semiconductor module and a connecting device such as a motor, but in addition to the main current wiring, wiring such as sensor wiring is laid out. It is difficult and requires space for the current detector. As a result, there is a problem that the installation man-hours increase.

The present invention has been made by paying attention to the above problems, and an object of the present invention is to provide an interface unit in which the presence or absence of a sensor can be selected in a space-saving manner and a semiconductor device using the interface unit.

In order to solve the above problems, the first aspect of the interface unit according to the present invention is the interface unit connected to the semiconductor unit, which is defined by (a) the opposing first and second rising portions. A U-shaped part is sandwiched in the center, and both ends connected to the U-shaped part have a cross-sectional shape extending in the opposite direction on the same plane, and each of the plane parts at both ends is connected to a bus bar connection to a semiconductor unit. A rectangular parallelepiped with a plate-shaped bus bar as a part and (b) the first and second rising parts sealed with resin inside, and two surfaces parallel to the first and second rising parts as side surfaces. It has a portion, a cavity for a sensor is provided in the resin along the first rising portion of the rectangular parallelepiped portion, and a groove-shaped sensor wiring storage portion is provided on one bottom surface side of the rectangular parallelepiped portion on the side close to the bus bar connection portion. The gist is to provide a support part provided with a.

A first aspect of the semiconductor device according to the present invention includes mounting a semiconductor chip, a plurality of parallel semiconductor units, and an interface unit according to the first aspect connected to the plurality of semiconductor units. It is a summary.

According to the interface unit according to the present invention and the semiconductor device using the interface unit, it is possible to select whether or not the sensor is mounted on the interface unit in a space-saving manner.

FIG. 1 is a perspective view (bird's-eye view) schematically showing an outline of a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an exploded perspective view schematically showing an outline of the configuration of the semiconductor device according to the embodiment of the present invention. FIG. 3 is a plan view schematically showing an outline of the configuration of the upper surface of the interface unit according to the embodiment of the present invention. FIG. 4 is a plan view schematically showing a configuration of the lower surface of the interface unit according to the embodiment of the present invention in a state where the bottom cover is removed. FIG. 5 is a cross-sectional view taken from the direction of the VV line of FIG. FIG. 6 is a plan view showing a state in which the current sensor is housed in the sensor cavity portion of the interface unit according to the embodiment of the present invention.

Embodiments of the present invention will be described below. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the directions of "left and right" and "up and down" in the following description are merely definitions for convenience of explanation, and do not limit the technical idea of the present invention. Therefore, for example, if the paper surface is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the paper surface is rotated 180 degrees, "left" becomes "right" and "right" becomes "left". Of course it will be.

As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention includes a pair of semiconductor units 10 and 20 arranged side by side on a metal base plate 100, and semiconductor units 10 and 20. The interface unit 30 is provided so as to straddle the upper side of the above.

As can be seen from the exploded perspective view of FIG. 2, the interface unit 30 located on the upper side of FIG. 2 connects the corresponding terminals of the semiconductor unit 10 and the semiconductor unit 20 located on the lower side of FIG. 2 in parallel. The semiconductor device shown in FIG. 1 can be screwed (bolt) connected to a bus bar on the device side provided on the external device side such as a general-purpose inverter via the interface unit 30.

Each of the pair of semiconductor units 10 and 20 has a rectangular parallelepiped shape, and a semiconductor module on which a power semiconductor chip is mounted is sealed inside by a sealing resin 10a. As shown in FIG. 2, the pair of semiconductor units 10 and 20 have the long sides of a rectangle adjacent to each other in parallel, and are arranged side by side along the short side directions of the rectangles. Since the members having the same name have the same structure and function between the pair of semiconductor units 10 and 20, the semiconductor unit 10 shown on the left side in FIG. 2 will be mainly described below as a representative example, and duplicate description will be omitted as appropriate.

Although not shown, a power semiconductor chip forming an upper arm on the positive pole side and a power semiconductor chip forming a lower arm on the negative pole side are provided inside the sealing resin 10a of the semiconductor unit 10. The semiconductor unit 10 is a so-called "2in1 type". However, the semiconductor unit of this embodiment is not limited to the 2in1 type semiconductor unit, and may be a 1in1 type, a 6in1 type, or the like.
As the power semiconductor chip, transistors such as field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs) are adopted. The transistor may have a vertical structure or a horizontal structure. Further, a diode such as a freewheel diode (FWD) may be provided.
Hereinafter, a case of a 2in1 type in which MOSFETs are adopted as the semiconductor unit 10 will be described.

As shown in FIG. 2, in the center of the upper surface of the sealing resin 10a of the semiconductor unit 10, rectangular and plate-shaped positive pole terminals 15c, negative pole terminals 17c, and output terminals 19c are equally spaced in a plane pattern. Each of the longitudinal directions is provided so as to extend along the short side direction of the semiconductor unit 10.

The positive pole terminal 15c, the negative pole terminal 17c, and the output terminal 19c are all made of copper (Cu), aluminum (Al), or the like and have conductivity. At the center of each of the positive pole terminal 15c, the negative pole terminal 17c, and the output terminal 19c, a through hole substantially concentric with the hole of the nut, which is arranged on the upper part of the lower sealing resin 10a, is provided. ..

Further, the positive pole terminal 15c, the negative pole terminal 17c, and the output terminal 19c are joined to the drain connection terminal 15a, the source connection terminal 17a, and the output side connection terminal 19a at both ends on the lower surface side of each. Each of the drain connection terminal 15a, the source connection terminal 17a, and the output side connection terminal 19a is a rod-shaped terminal extending from the semiconductor module sealed inside the sealing resin 10a of the semiconductor unit 10.

The drain connection terminal 15a is joined to the positive electrode terminal 15c on the sealing resin 10a by welding, soldering, or the like. Similarly, the source connection terminal 17a is joined to the negative pole terminal 17c on the sealing resin 10a, and the output side connection terminal 19a is joined to the output terminal 19c on the sealing resin 10a by welding, soldering, or the like. The drain connection terminal 15a supplies a current to the drain electrode of the power semiconductor chip of the upper arm mounted on the semiconductor module. The source connection terminal 17a allows a current to flow to the outside from the source electrode of the power semiconductor chip of the lower arm. The output side connection terminal 19a is electrically connected to the source electrode of the power semiconductor chip of the upper arm and the drain electrode of the power semiconductor chip of the lower arm, and causes an output current to flow.

On the upper surface of the sealing resin 10a of the semiconductor unit 10, mounting holes for inserting screws or the like for mounting the semiconductor unit 10 to other members, devices, or the like are provided at both ends in the longitudinal direction. Around the mounting hole, a side wall that rises upward from the upper surface of the sealing resin 10a is provided. The side walls form hakama portions 16 and 18 that form a U-shaped arc so that the wall surface surrounds the mounting holes in a flat pattern.

The upper ends of the source signal terminal 11 for the upper arm and the source signal terminal 13 for the lower arm extending linearly upward from the semiconductor module are shown at the positions closer to the center on both sides of the hakama portion 16. There is. The source signal terminal 11 for the upper arm and the source signal terminal 13 for the lower arm are symmetrically provided on the same straight line along the parallel direction of the pair of semiconductor units 10 and 20 centering on the hakama portion 16. ing. The source signal terminal 11 for the upper arm and the source signal terminal 13 for the lower arm detect their respective source voltages.

Further, at positions near the ends on both sides of the hakama portion 16, the upper ends of the left gate signal terminal 12 and the right gate signal terminal 14 extending linearly upward from the semiconductor module are shown. The gate signal terminal 12 on the left side and the gate signal terminal 14 on the right side are symmetrically provided on the same straight line along the parallel direction of the pair of semiconductor units 10 and 20 centering on the hakama portion 16. The gate signal terminal 12 on the left side and the gate signal terminal 14 on the right side control ON / OFF of the power semiconductor chip.

<Interface unit>
As shown in FIGS. 1 to 3, the interface unit 30 has a flat pattern similar to an inverted T shape due to the storage portion 30a and the support portion 30b having a rectangular parallelepiped portion. The "inverted T-shape" is configured by attaching the lower end of the support portion 30b in the longitudinal direction in the direction orthogonal to the center of the storage portion 30a in the longitudinal direction (horizontal direction) in FIG. In the top view of FIG. 3, the storage portion 30a has a shape like a double bridge in which two semicircular arch-shaped notches 30a1 and 30a2 are connected under the rectangular parallelepiped portion. As can be seen from the perspective view, it has a box shape as a whole.

-Storage-
The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are densely packed in the center on the flat upper surface of the storage portion 30a at equal intervals. It is arranged close to each other. The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are arranged so as to be located at four corners of a square in a plane pattern. As shown in FIG. 2, the first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are rod-shaped, respectively, and are upper surfaces of the accommodating portion 30a. It extends vertically upward with respect to.

The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are each inserted into the housing portion 30a. The lower ends of the first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are provided inside the storage portion 30a. It is connected to each internal wiring. The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 constitute an external connection control terminal.

The first source signal terminal 31 is simultaneously connected to the source signal terminal 11 for the upper arm of each of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the housing portion 30a. The first gate signal terminal 32 is simultaneously connected to the gate signal terminal 12 on the left side of each of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the housing portion 30a. The second source signal terminal 33 is simultaneously connected to the source signal terminal 13 for each lower arm of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the housing portion 30a. The second gate signal terminal 34 is simultaneously connected to the gate signal terminal 14 on the right side of each of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the housing portion 30a.

As shown in FIG. 3, a central region that can be regarded as a substantially rectangular shape is provided between the two semicircular arch-shaped notches 30a1 and 30a2 of the storage portion 30a. A first source signal terminal 31, a first gate signal terminal 32, a second source signal terminal 33, and a second gate signal terminal 34 are provided on the upper surface of this central region. The semicircular arch-shaped shape of the notches 30a1 and 30a2 of the storage portion 30a follows the arc of the hakama portion 16 of the sealing resin 10a of the semiconductor unit 10. As shown in FIG. 3, the width measured in the vertical direction is the narrowest just above the semicircular arch. That is, when looking at the space between the ends along the horizontal direction of FIG. 3, the region where the width of the storage portion 30a is narrowest along the short side direction sandwiches the central region due to the provision of the notches 30a1 and 30a2. Is formed of.

As shown in FIG. 2, recesses are provided symmetrically on both sides of each notch 30a1 of the storage portion 30a. Similarly, recesses are provided symmetrically on both sides of the notch 30a2. The ends of the first source signal internal wiring 91 and the first gate signal internal wiring 92 are exposed inside the left recess of the left notch 30a1.

As can be seen from FIG. 3, even inside the recess on the right side of the notch 30a1 on the left side, another end of the internal wiring 91 for the first source signal and another internal wiring 92 for another first gate signal The edges are similarly exposed. Similarly, the ends of the second source signal internal wiring 93 and the second gate signal internal wiring 94 are exposed inside the left recess of the right notch 30a2. Further, inside the recess on the right side of the notch 30a2 on the right side, another end of the internal wiring 93 for the second source signal and another end of the internal wiring 94 for the second gate signal are exposed. It is provided.

As can be seen from FIG. 2, a step having a height difference is provided in the lower portion of the recess in which the first source signal internal wiring 91 and the first gate signal internal wiring 92 are provided. The end of the first source signal internal wiring 91 is arranged at the lower stage of the step provided in the recess on the left side of the notch 30a1, and the end of the first gate signal internal wiring 92 is located at the upper stage of the step. Have been placed. Through holes are provided at each end on the step. The source signal terminal 11 for the upper arm extending from the semiconductor unit 10 on the lower side of FIG. 2 is inserted into the through hole of the first source signal internal wiring 91. Further, the upper end of the left gate signal terminal 12 is inserted into the through hole of the first gate signal internal wiring 92.

Although not shown, inside the storage portion 30a, there is an internal wiring 91 for a first source signal, an internal wiring 92 for a first gate signal, and a second source signal connected to each end. The internal wiring 93 and the internal wiring 94 for the second gate signal are arranged.

Inside the storage portion 30a, the first source signal internal wiring 91, the first gate signal internal wiring 92, the second source signal internal wiring 93, and the second gate signal internal wiring 94 are connected to each other. It is stacked vertically apart. The source signal terminal 11 for the upper arm, the gate signal terminal 12 on the left side, the source signal terminal 13 for the lower arm, and the gate signal terminal 14 on the right side of the semiconductor unit 10 are all made of metal such as Cu. It can be made of a conductive material.

The first source signal internal wiring 91, the first gate signal internal wiring 92, the second gate signal internal wiring 94, and the second source signal internal wiring 93 are, in this order, inside the accommodating portion 30a. It is arranged from the bottom to the top. An insulating resin or the like is provided between the internal wiring 91 for the first source signal, the internal wiring 92 for the first gate signal, the internal wiring 93 for the second source signal, and the internal wiring 94 for the second gate signal. Is filled.

At the bottom of the storage portion 30a, there are a source signal terminal 11 for the upper arm extending from the lower side, a gate signal terminal 12 on the left side, a source signal terminal 13 for the lower arm, and a gate signal terminal 14 on the right side. Through holes are provided corresponding to the positions. The through holes 91h and 92h shown in FIG. 4 are provided at positions concentric with the through holes provided at the ends of the first source signal internal wiring 91 and the first gate signal internal wiring 92, respectively. Has been done. The through holes 93h and 94h shown in FIG. 4 are provided at positions concentric with the through holes provided at the ends of the second source signal internal wiring 93 and the second gate signal internal wiring 94, respectively. Has been done.

The source signal terminals 11 and 21 for the upper arms of the pair of left and right semiconductor units 10 and 20, respectively, are collectively connected by the left and right branch portions of the first source signal internal wiring 91 of the storage portion 30a. NS. Further, the source signal terminals 11 and 21 for the upper arm are electrically connected to the first source signal terminal 31 extending upward outside the storage portion 30a via the central branch portion of the first source signal internal wiring 91. Connected to.

Further, the gate signal terminals 12 and 22 on the left side of the pair of left and right semiconductor units 10 and 20, respectively, are collectively connected by the left side branch portion and the right side branch portion of the first gate signal internal wiring 92 of the storage portion 30a. NS. Further, the left gate signal terminals 12 and 22 are electrically connected to the first gate signal terminal 32 extending upward outside the storage portion 30a via the central branch portion of the first gate signal internal wiring 92. Will be done.

Further, the source signal terminals 13 and 23 for the lower arms of the pair of left and right semiconductor units 10 and 20, respectively, are grouped by the left side branch and the right side branch of the second source signal internal wiring 93 of the storage portion 30a. Be connected. Further, the source signal terminals 13 and 23 for the lower arm are electrically connected to the second source signal terminal 33 extending upward outside the storage portion 30a via the central branch portion of the second source signal internal wiring 93. Connected to.

Further, the gate signal terminals 14 and 24 on the right side of the pair of left and right semiconductor units 10 and 20, respectively, are collectively connected by the left side branch portion and the right side branch portion of the second gate signal internal wiring 94 of the storage portion 30a. NS. Further, the gate signal terminals 14 and 24 on the right side are electrically connected to the second gate signal terminal 34 extending upward on the outside of the storage portion 30a via the central branch portion of the second gate signal internal wiring 94. Will be done.

-Support part-
As shown in FIGS. 1 to 4, the support portion 30b of the interface unit 30 has a positive pole bus bar 35, a negative pole bus bar 37, and an output bus bar 39, all of which are made of a conductive plate-shaped member such as Cu. Is provided. As shown in the cross-sectional view of FIG. 5, the positive pole bus bar 35, the negative pole bus bar 37, and the output bus bar 39 are bilaterally symmetrical bent through each of the four right-angled bent portions 4a, 4b, 4c, and 4d. Right angle ohm (Ω) type. The Ω type has a bent portion 4a between the horizontal first region and the vertical second region, a bent portion 4b between the second region and the horizontal third region, and a bent portion between the third region and the vertical fourth region. The portion 4c is configured via a bent portion 4d between the fourth region and the horizontal fifth region. The first region and the fifth region located at both ends of the Ω type formed at right angles extend in the same plane in opposite directions. As shown in FIG. 5, the second region, which is the first rising portion, and the fourth region, which is the second rising portion facing the first rising portion, are inverted U-shaped with the third region in between. (U-shaped part) is composed. A U-shaped portion composed of the second to fourth regions is sandwiched in the center, and the first region and the fifth region located at both ends extend in the same plane in opposite directions, and Ω defined by four right-angled portions. It has a cross-sectional shape of the mold. Although FIG. 5 shows a cross-sectional view of the negative pole bus bar 37 as an example, the positive pole bus bar 35 and the output bus bar 39 also have the same cross-sectional shape as the negative pole bus bar 37. Although it is described as a symmetrical right-angled Ω type in which the bent portions 4a, 4b, 4c, and 4d are bent at four right angles, the cross-sectional shape is not limited. For example, the second region and the fourth region may rise at an acute angle or an obtuse angle with respect to the horizontal first region and the fifth region, and may not be symmetrical. Further, a part or all of the second region and the fourth region may be formed of a curved surface. That is, it suffices that the first region and the fifth region are substantially on the same plane, the third region is substantially horizontal to the first region and the fifth region, and the third region is located on a different surface above.

At the left end of the Ω type, the first region whose main surface extends horizontally from the support portion 30b is a negative pole bus bar connecting portion 37a fixed and electrically joined to the negative pole terminal 17c provided on the semiconductor module 10. At the right end of the Ω type, the fifth region whose main surface extends horizontally from the support portion 30b is a negative pole bus bar connecting portion 37b fixed and electrically joined to the negative pole terminal 17c provided on the semiconductor module 20. Further, the third region of the negative pole bus bar 37, which is the Ω-shaped ceiling portion, is the negative pole external connection portion 37c which is electrically connected to the device side bus bar of the external device by being fixed by a screw or the like.

The negative pole external connection portion 37c is exposed on the upper surface of the support portion 30b, and has a through hole for connecting to an external device in the center of the main surface. Further, the left and right negative pole bus bar connecting portions 37a and 37b extend horizontally from the outer surface of the supporting portion 30b to the outside, and a through hole for connecting to the semiconductor unit 10 is provided in the center of the main surface.

As shown in FIG. 5, between the negative pole bus bar connecting portion 37a (first region) and the negative pole external connecting portion 37c, there is a first rising portion parallel to the side surface of the rectangular parallelepiped portion of the supporting portion 30b. A side wall region 37d1 (second region) is provided. The side wall region 37d1 is integrally fixed by being resin-sealed in the resin 30d of the main body of the support portion 30b. The boundary between the negative pole bus bar connecting portion 37a and the side wall region 37d1 is bent about 90 degrees with respect to the main surface of the negative pole bus bar connecting portion 37a at the bent portion 4a. The boundary between the negative pole external connection portion 37c (third region) and the side wall region 37d1 is bent at the bent portion 4b at about 90 degrees with respect to the main surface of the side wall region 37d1 and on the side opposite to the bent portion 4a. The side wall region 37d1 is integrally fixed by being resin-sealed in the resin 30d of the main body of the support portion 30b.

A side wall region 37d2 (fourth region), which is a second rising portion, is provided between the negative pole bus bar connecting portion 37b and the negative pole external connecting portion 37c in parallel with the side surface of the rectangular parallelepiped portion of the supporting portion 30b. ing. The side wall region 37d2 is also integrally fixed by being resin-sealed in the resin 30d of the main body of the support portion 30b. The boundary between the negative pole bus bar connecting portion 37b (fifth region) and the side wall region 37d2 is bent about 90 degrees with respect to the main surface of the negative pole bus bar connecting portion 37b at the bent portion 4d. The boundary between the negative pole external connection portion 37c and the side wall region 37d2 is bent at about 90 degrees with respect to the main surface of the side wall region 37d2 at the bent portion 4c, on the side opposite to the bent portion 4d.

Similarly, positive pole bus bar connection portions 35a and 35b are provided at both ends of the positive pole bus bar 35, and a positive pole external connection portion 35c is provided in the center of the positive pole bus bar connection portion 35a and the positive pole external connection portion 35c. A side wall region is provided between the space and between the positive pole bus bar connection portion 35b and the positive pole external connection portion 35c, respectively, in parallel with the side surface of the rectangular parallelepiped portion of the support portion 30b. Further, output bus bar connection portions 39a and 39b are provided at both ends of the output bus bar 39, and an output external connection portion 39c is provided at the center of the output bus bar 39. A side wall region is provided between the space and between the output bus bar connection portion 39b and the output external connection portion 39c, respectively, in parallel with the side surface of the rectangular parallelepiped portion of the support portion 30b. Since the structures of the positive pole bus bar 35 and the output bus bar 39 are equivalent to the negative pole bus bar 37, duplicate description will be omitted.

As shown in FIG. 5, in the vicinity of the bent portion 4a of the negative pole bus bar 37, the resin 30d on the lower surface side of the support portion 30b along at least a part of the side wall region 37d1 (second region) which is the first rising portion. It has a sensor cavity 40b that exposes the open end. Similarly, as shown in FIG. 6, when viewed from the lower surface side of the support portion 30b, the sensor cavity portion is located in the vicinity of the bent portion 4a of the output bus bar 39 along at least a part of the side wall region which is the rising portion. It has an open end of 40a. Further, when viewed from the lower surface side of the support portion 30b, the sensor cavity portion 40c has an open end in the vicinity of the bent portion 4a of the positive pole bus bar 35 along at least a part of the side wall region. Although not shown, the main body of the support portion 30b between the left and right side wall regions of each bus bar is provided with a space for nut gloves for accommodating nuts.

Further, as shown in FIG. 4, the support portion 30b is connected to the sensor cavities 40a, 40b and 40c provided on the lower surface thereof, and is connected to the bus bar connection portion 35a, the negative pole bus bar connection portion 37a and the output bus bar connection. On the lower surface (bottom surface) side of the rectangular parallelepiped portion on the side closer to the portion 39a, a groove portion 50 (sensor wiring storage portion) extending from the output bus bar 39 side to the end portion of the storage portion 30a along the longitudinal direction of the support portion 30b is provided. Have.

A current sensor can be accommodated in each of the sensor cavities 40a, 40b, and 40c, and wiring for the current sensor is arranged in the groove 50. For example, as shown in FIGS. 5 and 6, the current sensor 60 is inserted into the sensor cavity 40b and sealed with resin or the like. The current sensor 60 may be inserted so as to come into contact with the side wall region 37d1, or may be inserted between the current sensor 60 and the side wall region 37d1 via a resin or the like. The wiring 60a of the current sensor 60 is arranged along the groove 50. The current sensor 60 measures the current flowing through the negative pole bus bar 37. As shown in FIG. 5, the groove 50 may be located between the side wall region 37d1 of the bus bar and the side wall region 37d2 facing the bus bar. The depth of the groove 50 may be greater than or equal to the depth at which the wiring 60a of the current sensor 60 is accommodated, and may be shallower than the sensor cavity 40b. The width of the groove 50 may be equal to or larger than the width in which the wiring 60a of the current sensor 60 is accommodated, and may be the same as or narrower than the width between the side wall region 37d1 of the bus bar and the side wall region 37d2 facing the bus bar.

Although FIG. 6 shows an example in which the current sensor 60 is arranged only in the sensor cavity 40b corresponding to the negative pole bus bar 37, the current is applied to two or more of the sensor cavities 40a, 40b, and 40c. Sensors may be placed. For example, current sensors are arranged in all the sensor cavities 40a, 40b, and 40c, and the wiring of each current sensor is arranged together in the groove 50, so that the output bus bar 39, the negative pole bus bar 37, and the positive pole bus bar are arranged together. The current flowing through 35 may be measured.

As the current sensor, a magnetoresistive sensor using a highly sensitive magnetoresistive element such as an anisotropic magnetoresistive (AMR) element, a giant magnetoresistive (GMR) element, or a tunnel magnetoresistive (TMR) element is adopted.

As shown in FIG. 5, the bottom cover 30c is fitted to the lower surface side of the support portion 30b to cover the sensor cavities 40a, 40b and 40c, and the groove portion 50. As the coating means, a noise removing film may be used, or a resin sealing means may be adopted.

According to the interface unit 30 of the present embodiment, the sensor cavities 40a, 40b and 40c for arranging the current sensor 60 and the groove portion 50 for arranging the wiring 60a of the current sensor 60 are arranged on the lower surface of the support portion 30b. By providing the above, it is possible to select whether or not the current sensor 60 is mounted according to the purpose of use. When the current sensor 60 is not required, the lower surface of the support portion 30b may be covered with the bottom cover 30c without mounting the current sensor 60 on the interface unit 30.

Further, by mounting the current sensor 60, a semiconductor device having a short circuit protection function and an overcurrent protection function can be realized. For example, it is possible to stably detect an abnormal current of a semiconductor device, and to instantly soft-shut down the semiconductor device in the event of a malfunction such as an overcurrent.

Further, since the current sensor 60 and its wiring 60a can be housed in the interface unit 30, it is not necessary to increase the size of the interface unit 30, and a miniaturized semiconductor device can be realized.

Further, the sensor cavities 40a, 40b and 40c are provided in the vicinity of the bent portions 4a of the output bus bar 39, the negative pole bus bar 37, and the positive pole bus bar 35, so that the current flowing through each bus bar can be current with high sensitivity. It can be detected by the sensor 60.

Further, since the wiring 60a of the current sensor 60 is arranged in the groove portion 50 formed on the lower surface of the support portion 30b, it is possible to secure a space for arranging the wiring 60a without increasing the interface unit 30. Further, since a certain distance can be secured between the main current wiring on the upper surface of the support portion 30b and the wiring 60a formed on the lower surface, the output bus bar 39, the negative pole bus bar 37, and the positive pole bus bar 35 It is less likely to receive electromagnetic noise from. Furthermore, since it can be kept away from the main current wiring of the external device, the possibility of receiving electromagnetic noise from the external device is reduced. Further, since the current sensor 60 and the wiring 60a are covered with a covering means such as a bottom cover 30c or a noise removing film, malfunctions are prevented even in an environment where electromagnetic noise is relatively large.

Further, the groove portion 50 extends from the output bus bar 39 to the end portion of the storage portion 30a along the longitudinal direction of the lower surface of the support portion 30b, that is, the external connection control terminal (first source signal terminal 31, first gate signal). Since the area where the terminal 32, the terminal for the second source signal 33, and the terminal for the second gate signal 34) are provided is formed, the main current wiring of the output bus bar 39 is not unnecessarily crossed. With such a configuration, noise due to the switching current flowing through the output bus bar 39 is not received, so that the possibility of causing a malfunction of the current sensor is reduced. Since a direct current flows through the negative pole bus bar 37 and the positive pole bus bar 35, there is no problem even if the wiring 60a crosses.

Further, by adopting a magnetoresistive sensor using a high-sensitivity magnetoresistive element such as an AMR element, a GMR element, or a TMR element as the current sensor, a large magnetic core for focusing magnetic flux and increasing the sensitivity is provided. It can be stored in the interface unit 30 without any problem.

As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description. It is a thing.

4a, 4b, 4c, 4d Bending part 10 Semiconductor unit 10a Encapsulating resin 11 Source signal terminal for upper arm 12 Gate signal terminal on the left side 13 Source signal terminal for lower arm 14 Gate signal terminal on the right side 15a Drain Connection terminal 15c Positive pole terminal 16 Hakama part 18 Hakama part 17a Source connection terminal 17c Negative pole terminal 19a Output side connection terminal 19c Output terminal 20 Semiconductor unit 21 Upper arm source signal terminal 22 Left gate signal terminal 23 Lower Source signal terminal for arm 24 Right gate signal terminal 30 Interface unit 30a Storage section 30b Support section 30c Bottom cover 31 First source signal terminal 32 First gate signal terminal 33 Second source signal terminal 34 Second Gate signal terminal 35 Positive pole bus bar 35a, 35b Positive pole bus bar connection 35c Positive pole external connection 37 Negative pole bus bar 37a, 37b Negative pole bus bar connection 37c Negative pole external connection 37d1, 37d2 Side wall area 39 Output bus bar 39a , 39b Output bus bar connection 39c Output external connection 40a, 40b, 40c Sensor cavity 50 Groove 60 Current sensor 60a Wiring 91 Internal wiring for first source signal 92 Internal wiring for first gate signal 93 Second Internal wiring for source signal 94 Internal wiring for second gate signal 91h, 92h, 93h, 94h Through hole 100 Base plate

Claims (6)

An interface unit connected to a semiconductor unit
A U-shaped portion defined by the first and second rising portions facing each other is sandwiched in the center, and both ends connected to the U-shaped portion have a cross-sectional shape extending in the opposite direction on the same plane. A plate-shaped bus bar having each of the flat portions of the above as a bus bar connecting portion connected to the semiconductor unit, and
The first and second rising portions are internally sealed with a resin, and the rectangular parallelepiped portion having two surfaces parallel to the first and second rising portions as side surfaces is provided. A support portion in which a sensor cavity portion is provided in the resin along the first rising portion, and a groove-shaped sensor wiring storage portion is provided on the bottom surface side of one of the rectangular parallelepiped portions on the side close to the bus bar connection portion. ,
An interface unit characterized by being equipped with. The interface unit according to claim 1, wherein the sensor wiring accommodating portion is provided along the longitudinal direction of the bottom surface of the support portion. Each has a plurality of busbars having the same configuration as the busbar.
The plurality of bus bars are arranged side by side in the longitudinal direction of the rectangular parallelepiped portion.
The interface unit according to claim 1 or 2, wherein each of the plurality of bus bars is arranged in the longitudinal direction along the lateral direction of the rectangular parallelepiped portion. The interface unit according to claim 3, wherein the sensor cavity is provided for each of the plurality of bus bars. The interface unit according to any one of claims 1 to 4, further comprising a covering portion for covering the sensor cavity portion and the sensor wiring accommodating portion. With multiple semiconductor units mounted in parallel on a semiconductor chip,
An interface unit connected to the plurality of semiconductor units and
With
The interface unit is
It has an ohm-shaped cross-sectional shape in which a U-shaped portion defined by the first and second rising portions facing each other is sandwiched in the center, and both ends connected to the U-shaped portion extend in opposite directions on the same plane. , A plate-shaped bus bar having each of the flat portions at both ends as a bus bar connecting portion connected to the semiconductor unit.
The first and second rising portions are internally sealed with a resin, and the rectangular parallelepiped portion having two surfaces parallel to the first and second rising portions as side surfaces is provided. A support portion in which a sensor cavity portion is provided in the resin along the first rising portion, and a groove-shaped sensor wiring storage portion is provided on one bottom surface side of the rectangular parallelepiped portion on the side close to the bus bar connection portion. When,
A semiconductor device characterized by having.

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