JP6136657B2 - Semiconductor module - Google Patents

Description

  The present invention relates to a semiconductor module. In particular, the present invention relates to a structure of a terminal of a semiconductor module.

  A semiconductor module generally includes at least one semiconductor chip, a plurality of terminals, and a case. For example, in the case of a power semiconductor module, the plurality of terminals are arranged one-dimensionally or two-dimensionally on one surface of the housing. A semiconductor module having such a configuration is disclosed in, for example, Non-Patent Document 1 (supervised by Koji Imai, “Power Electronics Handbook”, R & D Planning, Inc., February 20, 2002, p142, p150).

Supervised by Koji Imai, “Power Electronics Handbook”, R & D Planning, Inc., February 20, 2002, p142, p150

  According to the configuration disclosed in the above document, it is necessary to reduce the interval between the plurality of terminals in order to reduce the size of the semiconductor module. On the other hand, when the interval between the plurality of terminals is reduced, it is difficult to secure a space for connecting each terminal to an electrode such as a bus bar or wiring. For this reason, according to the conventional configuration, it is not easy to reduce the size of the semiconductor package.

  An object of the present invention is to provide a semiconductor module having a configuration suitable for miniaturization.

  A semiconductor module according to one aspect of the present invention includes at least one semiconductor chip, a substrate on which at least one semiconductor chip is mounted, a housing that houses the substrate, and each of which is electrically connected to at least one semiconductor chip. And a first terminal and a second terminal that are connected and project from the first surface of the housing. At least a part of the main surface of the first terminal faces the main surface of the second terminal outside the housing.

  According to the present invention, a miniaturized semiconductor module can be provided.

1 is a plan view schematically showing a semiconductor module 101 according to a first embodiment of the present invention. 1 is a side view of a semiconductor module 101 according to a first embodiment of the present invention. It is sectional drawing of the semiconductor module 101 which concerns on the 1st Embodiment of this invention along the III-III line of FIG. 1 is a plan view schematically showing the inside of a semiconductor module 101 according to a first embodiment of the present invention. 1 is an exploded perspective view of a semiconductor module 101 according to a first embodiment of the present invention. 1 is an equivalent circuit diagram of a semiconductor module 101 according to a first embodiment of the present invention. It is a figure for demonstrating the effect by the 1st Embodiment of this invention. It is a top view which shows roughly the semiconductor module 102 which concerns on the 2nd Embodiment of this invention. It is a side view of the semiconductor module 102 which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor module 102 which concerns on the 2nd Embodiment of this invention along the XX line of FIG. It is a disassembled perspective view of the semiconductor module 102 which concerns on the 2nd Embodiment of this invention. It is a top view of the semiconductor module 103 which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the semiconductor module 103 along the XIII-XIII line | wire shown in FIG. It is a top view of the semiconductor module 104 concerning the 4th Embodiment of this invention. It is sectional drawing of the semiconductor module 104 along the XV-XV line | wire shown in FIG. It is a top view of the semiconductor module 105 which concerns on the 5th Embodiment of this invention. It is sectional drawing of the semiconductor module 105 along the XVII-XVII line shown in FIG. It is a figure explaining another example of arrangement of external derivation terminal 21 and external derivation terminal 22.

[Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described.

  (1) A semiconductor module according to an embodiment of the present invention includes at least one semiconductor chip, a substrate on which the at least one semiconductor chip is mounted, a housing that houses the substrate, and each of the at least one semiconductor. And first and second terminals that are electrically connected to the chip and project from the first surface of the housing. At least a part of the main surface of the first terminal faces the main surface of the second terminal outside the housing.

  According to this configuration, a miniaturized semiconductor module can be provided. At least a part of the main surface of the first terminal faces the main surface of the second terminal outside the housing. As a result, the area of the surface (first surface) of the housing from which the first and second terminals are drawn can be reduced. Therefore, a miniaturized semiconductor module can be realized. “At least a part of the main surface of the first terminal faces the main surface of the second terminal” means “at least a part of the main surface of the second terminal is the main surface of the first terminal. It is equivalent to "facing".

  The size of the overlapping portion between the first terminal and the second terminal is not particularly limited. Only one part or the whole of one of the first terminal and the second terminal may overlap the other of the first terminal and the second terminal.

  The first surface of the housing is not particularly limited. The first surface of the housing may be a surface from which both the first terminal and the second terminal protrude. “Projecting” means extending from the first surface of the housing. The length of the portion protruding from the first surface of the housing is not particularly limited.

  (2) Preferably, on the outside of the housing, the entire main surface of one of the first terminal and the second terminal is out of the first terminal and the second terminal. Opposite the other main surface.

According to this configuration, a more miniaturized semiconductor module can be realized.
(3) Preferably, the said housing | casing has a 2nd surface which forms a level | step difference between the said 1st surface of the said housing | casing. The at least one semiconductor chip includes a first semiconductor chip and a second semiconductor chip that are electrically connected in series. The semiconductor module further includes an output terminal disposed on the second surface and connected to a connection point between the first semiconductor chip and the second semiconductor chip inside the housing.

  According to this configuration, the spatial distance and creepage distance between the first and second terminals and the output terminal can be increased. Therefore, it becomes easy to ensure electrical insulation between the first and second terminals and the output terminal.

  (4) Preferably, the said housing | casing further has a 3rd surface which forms a level | step difference between the said 1st surface of the said housing | casing. The semiconductor module further includes an input terminal disposed on the third surface and electrically connected to an input electrode of the at least one semiconductor chip inside the housing.

  According to this configuration, the spatial distance and creepage distance between the first and second terminals and the input terminal can be increased. Therefore, it becomes easy to ensure electrical insulation between the first terminal and the output terminal and between the second terminal and the output terminal. The “input terminal” is, for example, a terminal for supplying a signal to the semiconductor chip.

  (5) Preferably, the said semiconductor module is formed with the insulating material, and is provided with the supporting member arrange | positioned between the said 1st and 2nd terminal, and a fixing member. The fixing member fixes the first external electrode and the first terminal overlaid on each other to the surface of the support member, and connects the second external electrode and the second terminal overlaid on each other. Fix to the surface of the support member.

  According to this configuration, the electrical connection between the first terminal and the first external electrode and the electrical connection between the second terminal and the second external electrode can be easily achieved. . The fixing member may be a screw fixed to the support member, for example. The fixing member may be a spring, for example. The spring is a force for fixing the first external electrode and the first terminal to the surface of the support member, and a force for fixing the second external electrode and the second terminal to the surface of the support member. Can be generated. The number of fixing members may be at least one.

  (6) Preferably, the semiconductor module further includes a cover member that is disposed on the first surface of the housing and covers the first and second terminals. The first external electrode is a first conductive plate, and the second external electrode is a second conductive plate. The cover member includes a first side having a first slit for passing the first conductive plate, a second slit for passing the second conductive plate, and a first side. A second side surface having a third slit formed at a position facing the first slit and a fourth slit formed at a position opposed to the second slit. The first to fourth slits have a short axis along the first surface of the housing and a long axis intersecting the short axis.

  According to this configuration, since the area of the first surface of the housing can be reduced, the semiconductor module can be reduced in size. When the first and second conductive plates are arranged so that the main surfaces (surfaces having a wide width) of the first conductive plate and the second conductive plate face the first surface of the housing, the housing The area of the first surface of the body must be increased. However, according to the above configuration, the first conductive plate and the second conductive plate are arranged such that the main surfaces (wide surfaces) of the first conductive plate and the second conductive plate intersect the first surface of the housing. Two conductive plates can be arranged. Thereby, the area of the 1st surface of a housing | casing can be reduced.

(7) Preferably, the semiconductor chip includes a wide band gap semiconductor.
According to this configuration, since the mounting area of the semiconductor chip can be reduced, the semiconductor module can be reduced in size. A semiconductor element including a wide band gap semiconductor can reduce the chip area as compared with a silicon semiconductor element having the same current driving capability, for example. Therefore, the mounting area of the semiconductor chip can be reduced.

  (8) Preferably, the at least one semiconductor chip is a power semiconductor chip.

According to this configuration, the power semiconductor module can be reduced in size.
[Details of the embodiment of the present invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference numerals, and detailed description thereof will not be repeated.

  The X axis, the Y axis, and the Z axis shown in the drawings are axes orthogonal to each other. A plane defined by the X axis and the Y axis is referred to as an XY plane. The XY plane is defined as a surface on which the semiconductor module according to the embodiment of the present invention is installed. In one example, the XY plane is a horizontal plane. However, the XY plane is not limited to a horizontal plane. For example, the XY plane may be a vertical plane.

<Embodiment 1>
FIG. 1 is a plan view schematically showing a semiconductor module 101 according to the first embodiment of the present invention. FIG. 2 is a side view of the semiconductor module 101 according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of the semiconductor module 101 according to the first embodiment of the present invention taken along line III-III in FIG. FIG. 4 is a plan view schematically showing the inside of the semiconductor module 101 according to the first embodiment of the present invention. FIG. 5 is an exploded perspective view of the semiconductor module 101 according to the first embodiment of the present invention. FIG. 4 shows a state where the lid and cover member of the semiconductor module are removed.

  1 to 5, a semiconductor module 101 according to the first embodiment is a power semiconductor module applied to, for example, an inverter circuit. The semiconductor module 101 includes semiconductor chips 1, 2, 3, 4, an insulating substrate 6, source terminals 14 a and 15 a, gate terminals 14 b and 15 b, an output terminal 16, external lead-out terminals 21 and 22, a housing 10 and.

  In this embodiment, each of the semiconductor chips 1 to 4 includes a wide band gap semiconductor. The wide gap semiconductor can be SiC, GaN or diamond.

  Wide bandgap semiconductor devices are characterized by high breakdown voltage, low on-resistance, and stable operation in high temperature environments as compared to silicon semiconductor devices. By fabricating each of the semiconductor chips 1 to 4 using a wide band gap semiconductor, the chip area can be reduced as compared with, for example, a silicon semiconductor element having the same current driving capability. Therefore, according to this embodiment, the mounting area of the semiconductor chip (area of the insulating substrate 6) can be reduced. As a result, a miniaturized semiconductor package can be realized.

  In general, an inverter circuit includes a switching element such as an FET or an IGBT, and a diode that is antiparallel to the switching element. This diode is also called a “freewheel diode”. When an inverter circuit is configured by a silicon-based semiconductor element, generally, the switching element and the free wheel diode are manufactured on separate semiconductor chips.

  In this embodiment, each of semiconductor chips 1 to 4 is a power semiconductor chip made of, for example, SiC. In one embodiment, each of the semiconductor chips 1 to 4 is a power MOSFET. In the case of a MOSFET formed of SiC, a diode built in the MOSFET can be used as a free wheel diode. Therefore, according to this embodiment, the number of semiconductor chips accommodated in the housing 10 can be reduced.

  As shown in FIGS. 3 and 4, the insulating substrate 6 includes an insulating plate 7, electrode patterns 8 a, 8 b, 8 c, and an electrode pattern 9. The electrode patterns 8 a to 8 c are arranged on one main surface of the insulating plate 7. The electrode pattern 9 is disposed on the other main surface of the insulating plate 7.

  Each of the semiconductor chips 1 to 4 (MOSFET) has a drain electrode, a source electrode, and a gate electrode. In this embodiment, the drain electrode is formed on the back surface of the semiconductor chip. The source electrode and the gate electrode are formed on the front surface of the semiconductor chip. The gate electrode corresponds to an input electrode for receiving a signal.

  The drain electrodes (not shown) of the semiconductor chips 1 and 2 are electrically connected to the electrode pattern 8a via a conductive material (not shown) such as solder. The gate electrode 1b of the semiconductor chip 1 and the gate electrode 2b of the semiconductor chip 2 are connected to each other by a wire. Furthermore, the gate electrode 1b of the semiconductor chip 1 is connected to the gate terminal 14b by a wire.

  The source electrode 1a of the semiconductor chip 1 and the source electrode 2a of the semiconductor chip 2 are connected to the electrode pattern 8c by wires. The source electrode 1a of the semiconductor chip 1 and the source electrode 2a of the semiconductor chip 2 are connected to each other by a wire. Furthermore, the source electrode 1a of the semiconductor chip 1 is connected to the source terminal 14a by a wire.

  Similarly, each drain electrode (not shown) of the semiconductor chips 3 and 4 is electrically connected to the electrode pattern 8c through a conductive material (not shown) such as solder. The gate electrode 3b of the semiconductor chip 3 and the gate electrode 4b of the semiconductor chip 4 are connected to each other by a wire. The gate electrode 3b of the semiconductor chip 3 is connected to the gate electrode 15b by a wire.

  The source electrode 3a of the semiconductor chip 3 and the source electrode 4a of the semiconductor chip 4 are connected to the electrode pattern 8b by wires. The source electrode 3a of the semiconductor chip 3 and the source electrode 3a of the semiconductor chip 4 are connected to each other by a wire. Furthermore, the source electrode 3a of the semiconductor chip 3 is connected to the source terminal 15a by a wire.

  The electrode pattern shown in FIG. 4 is an example. Therefore, the shape of the electrode pattern and the arrangement of the semiconductor chips 1 to 4 are not limited as shown in FIG.

  The housing 10 accommodates the insulating substrate 6 on which the semiconductor chips 1 to 4 are mounted. As illustrated in FIG. 3, the housing 10 includes a base 11, a frame body 12, and a lid body 31.

  The base 11 may be a metal base including a metal such as copper (Cu) or aluminum (Al). The base 11 is electrically connected to the electrode pattern 9 of the insulating substrate 6. The base 11 can function as a heat radiating plate for releasing the heat generated by the semiconductor chips 1 to 4 to the outside of the housing 10. Furthermore, the base 11 can be used as a ground electrode.

  The frame body 12 is formed of an insulator (for example, resin). The frame body 12 is formed so as to surround the base 11 and constitutes a side wall of the housing 10. The frame body 12 and the base 11 accommodate the insulating substrate 6 on which the semiconductor chips 1 to 4 are mounted. The insulating substrate 6 is sealed with a sealing resin 28 inside the housing 10.

  The frame body 12 has support portions 18 a and 18 b for supporting the lid body 31. Screw holes 41a and 41b are formed in the support portion 18a, and screw holes 41c and 41d are formed in the support portion 18b. Screws 40a to 40d are passed through the lid 31 and fixed by screw holes 41a to 41d, respectively. Accordingly, the lid body 31 is attached to the frame body 12, and the lid body 31 closes the opening 20 of the housing 10. The upper surface 30 of the lid 31 forms at least a part of the main surface (first surface) of the housing 10.

  The external lead-out terminal 21 is connected to the electrode pattern 8 a and is drawn out from the inside of the housing 10 to the outside of the housing 10 through the upper surface 30 of the lid 31 (the first surface of the housing 10). Similarly, the external lead-out terminal 22 is electrically connected to the electrode pattern 8 b and is drawn from the inside of the housing 10 to the outside of the housing 10 through the upper surface 30 of the lid 31. That is, each of the external lead-out terminals 21 and 22 protrudes from the first surface of the housing 10.

  Further, at least a part of the main surface of the external lead-out terminal 21 faces the main surface of the external lead-out terminal 22 outside the housing 10. In this embodiment, when viewed along the X-axis direction, one whole of the main surface 21s of the external lead-out terminal 21 and the main surface 22s of the external lead-out terminal 22 is included in the other. More specifically, the main surface 21s of the external lead-out terminal 21 and the main surface 22s of the external lead-out terminal 22 overlap when viewed along the X-axis direction.

  The “main surface of the external lead-out terminal” means a surface having a large area among the surfaces of the external lead-out terminals. When the external lead-out terminal is plate-shaped, two surfaces having a relatively large area are arranged to face each other. Each of these two surfaces corresponds to a “main surface”. “At least a part of the main surface of the external lead-out terminal 21 faces the main surface of the external lead-out terminal 22” means “at least a part of the main surface of the external lead-out terminal 22 This is equivalent to “facing the main surface”.

  The housing 10 has a second surface 12a and a third surface 12b. Each of the second surface 12a and the third surface 12b forms a step with the main surface of the housing 10 (the upper surface 30 of the lid 31).

  The output terminal 16 is disposed on the second surface 12 a of the housing 10. The output terminal 16 is electrically connected to the electrode pattern 8d inside the housing 10. The electrode pattern 8d is connected to the electrode pattern 8c by a wire. On the other hand, source terminals 14 a and 15 a and gate terminals 14 b and 15 b are arranged on the third surface 12 b of the housing 10.

  The semiconductor module 101 further includes a support member 25, a screw 26, and a cover member 32.

  The cover member 32 covers the portions of the external lead-out terminals 21 and 22 exposed from the housing 10. The cover member 32 is inserted into openings 31 a, 31 b, 31 c, 31 d formed in the lid body 31 and fixed to the lid body 31. The cover member 32 preferably has a configuration for preventing the cover member 32 from coming off the lid 31.

  The support member 25 is formed of an insulating material (for example, resin). For example, the support member 25 is provided separately from the cover member 32. The support member 25 may be integrated with the cover member 32 inside the cover member 32.

  The support member 25 is disposed between the external lead-out terminal 21 and the external lead-out terminal 22. The screw 26 passes through the opening 35 of the cover member 32, the opening 51a (see FIG. 5) of the bus bar 51, and the opening 21a (see FIG. 5) of the external lead-out terminal 21, and is formed in the support member 25. Fixed by. By tightening the screw 26, the external lead-out terminal 21 and the bus bar 51 are both pressed against one surface of the support member 25. Therefore, the external lead-out terminal 21 and the bus bar 51 are fixed to one surface of the support member 25 in a state where they are overlapped with each other. Further, the other (opposite) surface of the support member 25 pushes the external lead-out terminal 22. Accordingly, the external lead-out terminal 22 is pressed against the bus bar 52. That is, the external lead-out terminal 22 and the bus bar 52 are fixed to the other (opposite side) surface of the support member 25 in a state where they overlap each other. Thereby, the electrical connection between the external lead-out terminal 21 and the bus bar 51 and the electrical connection between the external lead-out terminal 22 and the bus bar 52 can be easily and simultaneously achieved.

  In this embodiment, the external lead-out terminal 21 is disposed between the bus bar 51 and the support member 25. However, the bus bar 51 may be disposed between the external lead-out terminal 21 and the support member 25. Similarly, the bus bar 52 may be disposed between the external lead-out terminal 22 and the support member 25.

  As shown in FIGS. 2 and 5, the cover member 32 has a first side surface 33 and a second side surface 34. The first side surface 33 and the second side surface 34 face each other.

  The first side surface 33 includes a slit 33 a for passing the bus bar 51 and a slit 33 b for passing the bus bar 52. The second side surface 34 has a slit 34 a for passing the bus bar 51 and a slit 34 b for passing the bus bar 52. The slits 34a and 34b are formed on the second side surface 34 at positions facing the slits 33a and 33b, respectively.

  The slits 33a, 33b, 34a, 34b have a major axis and a minor axis. The short axis of each slit is along the first surface of the housing 10. On the other hand, the major axis of the slit intersects the minor axis of each slit. For example, the major axis of each slit is along the Z axis. On the other hand, the short axis of each slit is along the X axis. Therefore, the bus bars 51 and 52 are passed through the cover member 32 so that the main surfaces (surfaces having a large area) intersect the upper surface 30 of the lid 31.

  When the bus bars 51 and 52 are arranged along the upper surface 30 of the lid 31 (the main surface of the housing 10), the area of the main surface of the housing 10 must be increased. According to this embodiment, the main surfaces of the bus bars 51 and 52 are parallel to the direction intersecting the upper surface 30 of the lid 31. In other words, the thickness direction of the bus bars 51 and 52 is parallel to the first surface of the housing 10 (the upper surface 30 of the lid 31). Since each of the bus bars 51 and 52 is a conductive plate, its thickness direction is small. Thereby, the area of the main surface of the housing | casing 10 can be reduced. Therefore, a miniaturized semiconductor module can be realized.

  FIG. 6 is an equivalent circuit diagram of the semiconductor module 101 according to the first embodiment of the present invention. 6, semiconductor module 101 includes MOS transistors M1 and M2, diodes D1 and D2, source terminals 14a and 15a, gate terminals 14b and 15b, external lead terminals 21 and 22, and output terminal 16. And have.

  MOS transistor M1 and diode D1 are equivalent expressions of semiconductor chips 1 and 2 shown in FIG. Each of the semiconductor chips 1 and 2 has a MOS transistor and a diode built in the MOS transistor. As shown in FIG. 4, the semiconductor chips 1 and 2 are electrically connected in parallel. Therefore, the MOS transistor M1 represents two MOS transistors connected in parallel. The diode D1 represents a diode built in each of the two MOS transistors.

  MOS transistor M2 and diode D2 are equivalent expressions of semiconductor chips 3 and 4 shown in FIG. Since the configuration of semiconductor chips 3 and 4 is the same as that of semiconductor chips 1 and 2, the following description will not be repeated.

  The MOS transistors M1 and M2 are electrically connected in series between the external lead-out terminals 21 and 22. The external lead-out terminal 21 is electrically connected to the drain electrode of the MOS transistor M1. The external lead-out terminal 22 is electrically connected to the source electrode of the MOS transistor M2. External lead-out terminals 21 and 22 correspond to a positive electrode and a negative electrode, respectively.

  The output terminal 16 is connected to a connection point between the MOS transistors M1 and M2. The connection point of the MOS transistors M1 and M2 corresponds to the electrode pattern 8c shown in FIG.

  Further, the source terminals 14a and 15a are connected to the source electrode of the MOS transistor M1 and the source electrode of the MOS transistor M2, respectively. Gate terminals 14b and 15b are connected to the gate electrode of MOS transistor M1 and the gate electrode of MOS transistor M2, respectively.

  It is also possible to configure the circuit shown in FIG. 6 with only the semiconductor chips 1 and 3 (or the semiconductor chips 2 and 4). Further, the number of circuits (circuits shown in FIG. 6) included in the semiconductor module 101 may be plural. For example, if the number of circuits shown in FIG. 6 is two, the semiconductor module 101 can realize a single-phase inverter circuit. For example, if the number of circuits shown in FIG. 6 is three, the semiconductor module 101 can realize a three-phase inverter circuit.

  FIG. 7 is a diagram for explaining the effect of the first embodiment of the present invention. With reference to FIG. 7, the semiconductor module 201 has external lead-out terminals 221 and 222, an output terminal 216, and an input terminal 214. The external lead-out terminals 221, 222, the output terminal 216, and the input terminal 214 are the external lead-out terminals 21, 22, the output terminal 16, and the gate terminal of the semiconductor module according to the first embodiment of the present invention, respectively. 14b.

  In the semiconductor module 201, the external lead-out terminals 221 and 222 and the output terminal 216 are arranged in a plane. External lead-out terminals 221 and 222 and output terminal 216 are arranged on the main surface of casing 210 along the X axis. Alternatively, the external lead terminals 221 and 222 and the output terminal 216 are arranged on the main surface of the casing 210.

  The main surface of the casing 210 of the semiconductor module 201 needs to have an area that secures a space for connecting an external electrode (for example, a bus bar) to each of the external lead-out terminals 221 and 222. Accordingly, even if the semiconductor chip mounting area (the area of the insulating substrate 6) can be reduced by reducing the area of the semiconductor chip or the number of semiconductor chips, in the case of the semiconductor module 201, the housing 210 is not provided. It is difficult to reduce the size.

  On the other hand, according to the first embodiment of the present invention, the external lead-out terminals 21 and 22 protrude from the first surface of the housing (the upper surface 30 of the lid 31). Furthermore, at least a part of one main surface of the external lead-out terminal 21 and the external lead-out terminal 22 is opposed to the other main surface of the external lead-out terminal 21 and the external lead-out terminal 22 outside the housing 10. Thereby, the area of the surface of the housing | casing 10 required in order to arrange | position the external derivation | leading-out terminals 21 and 22 can be made small. Therefore, according to the first embodiment of the present invention, it is possible to reduce the size of the semiconductor module.

  Furthermore, according to the first embodiment of the present invention, a step is provided between the upper surface 30 of the lid 31 (not shown) and the second surface 12a of the housing 10. Thereby, a spatial distance and a creepage distance can be secured between the external lead-out terminals 21 and 22 and the output terminal 16. Therefore, the insulation performance between the external lead-out terminals 21 and 22 and the output terminal 16 can be ensured.

<Embodiment 2>
FIG. 8 is a plan view schematically showing a semiconductor module 102 according to the second embodiment of the present invention. FIG. 9 is a side view of the semiconductor module 102 according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view of the semiconductor module 102 according to the second embodiment of the present invention taken along line XX of FIG. FIG. 11 is an exploded perspective view of the semiconductor module 102 according to the second embodiment of the present invention.

  8 to 11, the semiconductor module 102 according to the second embodiment of the present invention is different from the semiconductor module 101 according to the first embodiment in that a screw 27 is added. The screw 27 passes through the opening 36 of the cover member 32, the opening 52a of the bus bar 52 (see FIG. 11), and the opening 22a of the external lead-out terminal 22 (see FIG. 11). Fixed by.

  By tightening the screw 27, both the external lead-out terminal 22 and the bus bar 52 are pressed against the surface of the support member 25. Therefore, as in the first embodiment, electrical connection between the external lead-out terminal 22 and the bus bar 52 can be easily achieved.

  Since the configuration of other parts of the semiconductor module 102 is the same as the configuration of the corresponding part of the semiconductor module 101, the following description will not be repeated. Therefore, according to the second embodiment of the present invention, a miniaturized semiconductor module can be realized as in the first embodiment of the present invention.

<Embodiment 3>
FIG. 12 is a top view of the semiconductor module 103 according to the third embodiment of the present invention. FIG. 13 is a cross-sectional view of the semiconductor module 103 taken along line XIII-XIII shown in FIG. With reference to FIGS. 12 and 13, the frame 12 is not formed with a step for arranging the output terminal 16. That is, the upper surface 30 of the lid 31, the second surface 12 a of the housing 10, and the third surface 12 b of the housing 10 are included in the same plane.

  The configuration of other parts of the semiconductor module 103 is the same as the configuration of the corresponding part of the semiconductor module 101 according to the first embodiment. Therefore, according to the third embodiment of the present invention, as in the first and second embodiments of the present invention, a miniaturized semiconductor module can be realized.

<Embodiment 4>
FIG. 14 is a top view of a semiconductor module 104 according to the fourth embodiment of the present invention. FIG. 15 is a cross-sectional view of the semiconductor module 104 taken along line XV-XV shown in FIG. Referring to FIGS. 14 and 15, the fourth embodiment differs from semiconductor module 101 according to the first embodiment in that the three sides of output terminal 16 face the surface of frame body 12.

  Since the configuration of other parts of the semiconductor module 104 is the same as the configuration of the corresponding part of the semiconductor module 101, the following description will not be repeated. According to the fourth embodiment of the present invention, as in the first to third embodiments of the present invention, a miniaturized semiconductor module can be realized.

<Embodiment 5>
FIG. 16 is a top view of a semiconductor module 105 according to the fifth embodiment of the present invention. FIG. 17 is a cross-sectional view of the semiconductor module 105 taken along the line XVII-XVII shown in FIG. With reference to FIGS. 16 and 17, the semiconductor module 105 is different from the semiconductor module 101 according to the first embodiment in that a plate spring 29 is provided instead of the screw 26.

  One side of the leaf spring 29 is fixed to the inner surface of the cover member 32. When the bus bar 51 is inserted into the cover member 32, the leaf spring 29 is pushed by the bus bar 51. The repulsive force of the leaf spring 29 generates a force that presses the bus bar 51 against the external lead-out terminal 21. As a result, the bus bar 51 and the external lead-out terminal 21 are fixed to one surface of the support member 25 while being overlapped with each other, so that the bus bar 51 can be brought into contact with the external lead-out terminal 21 with certainty.

  Further, due to the repulsive force of the leaf spring 29, the surface of the support member 25 presses the external lead-out terminal 22 against the bus bar 52. As a result, the bus bar 52 and the external lead-out terminal 22 are fixed to the other surface of the support member 25 in a state of being overlapped with each other, so that the bus bar 52 can be reliably brought into contact with the external lead-out terminal 22. Therefore, as in the first embodiment, electrical connection between the external lead-out terminal 21 and the bus bar 51 and electrical connection between the external lead-out terminal 22 and the bus bar 52 can be easily and simultaneously achieved. it can.

  Note that a force for fixing the bus bar 51 and the external lead-out terminal 21 to the surface of the support member 25 and a force for fixing the bus bar 52 and the external lead-out terminal 22 to the surface of the support member 25 are generated. Any member can be used without being limited to the leaf spring 29. For example, a coil spring may be used instead of the leaf spring 29.

  Since the configuration of the other part of semiconductor module 105 is the same as the configuration of the corresponding part of semiconductor module 101, the following description will not be repeated. According to the fifth embodiment of the present invention, as with the first to fourth embodiments of the present invention, a miniaturized semiconductor module can be realized.

  In each of the above embodiments, the external lead-out terminal 21 and the external lead-out terminal 22 overlap each other outside the housing 10. That is, outside the housing 10, the external lead-out terminal 21 and the external lead-out terminal 22 have different positions in the X-axis direction, while the positions in the Y-axis direction are the same. However, if the main surface of the external lead-out terminal 21 and the main surface of the external lead-out terminal 22 face each other, the arrangement relationship between the external lead-out terminal 21 and the external lead-out terminal 22 is limited in this way. is not.

  FIG. 18 is a diagram illustrating another example of the arrangement of the external lead-out terminals 21 and the external lead-out terminals 22. For example, as shown in FIG. 18A, the main surface of the external lead-out terminal 21 and the main surface of the external lead-out terminal 22 may have the same size but may be shifted from each other in the Y-axis direction. Alternatively, as shown in FIG. 18B, the main surface of the external lead-out terminal 22 may be larger than the main surface of the external lead-out terminal 21. In this case, the entire main surface of the external lead-out terminal 21 overlaps the main surface of the external lead-out terminal 22. Conversely, the main surface of the external lead-out terminal 21 may be larger than the main surface of the external lead-out terminal 22.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1-4 semiconductor chip, 1a, 2a, 3a, 4a source electrode, 1b, 2b, 3b, 4b gate electrode, 6 insulating substrate, 7 insulating plate, 8a-8d, 9 electrode pattern 10, 210 housing, 11 base , 12 Frame, 12a 2nd surface, 12b 3rd surface, 14a, 15a Source terminal, 14b, 15b Gate terminal, 16, 216 Output terminal, 18a, 18b Support part, 20, 21a, 22a, 31a-31d , 35, 36, 51a, 52a opening, 21, 22, 221, 222 external lead terminal, 21s, 22s main surface, 25 support member, 26, 27, 40a-40d screw, 28 sealing resin, 29 leaf spring, 30 upper surface, 31 lid, 32 cover member, 33 first side surface, 33a, 34a, 33b, 34b slit, 34 second side surface, 41a- 1d screw holes 51 and 52 busbar, 101～105,201 semiconductor module, 214 an input terminal, D1, D2 diode, M1, M2 MOS transistor.

Claims (6)

At least one semiconductor chip;
A substrate on which the at least one semiconductor chip is mounted;
A housing for housing the substrate;
Each including first and second terminals electrically connected to the at least one semiconductor chip and projecting from a first surface of the housing;
Outside the housing, at least a part of the main surface of the first terminal faces the main surface of the second terminal ;
A support member formed of an insulating material and disposed between the first and second terminals;
A fixing member,
The fixing member fixes the first external electrode and the first terminal overlaid on each other to the surface of the support member, and connects the second external electrode and the second terminal overlaid on each other. Fixed to the surface of the support member,
A cover member disposed on the first surface of the housing and covering the first and second terminals;
The first external electrode is a first conductive plate;
The second external electrode is a second conductive plate;
The cover member is
A first side surface having a first slit for passing the first conductive plate and a second slit for passing the second conductive plate;
A second slit having a third slit formed at a position facing the first side surface and facing the first slit, and a fourth slit formed at a position facing the second slit. And have side
The first to fourth slits have a short axis along the first surface of the housing and a long axis that intersects the short axis .   Outside the casing, the entire main surface of one of the first terminal and the second terminal is on the other main surface of the first terminal and the second terminal. The semiconductor module according to claim 1, which faces each other. The housing has a second surface that forms a step with the first surface of the housing;
The at least one semiconductor chip includes a first semiconductor chip and a second semiconductor chip electrically connected in series;
The semiconductor module is
While being disposed on the second surface, further comprising an output terminal which in the interior of the housing is connected to a connection point between the first semiconductor chip and the second semiconductor chip, according to claim 1 or claim 2. The semiconductor module according to 2. The housing is
A third surface that forms a step with the first surface of the housing;
The semiconductor module is
4. The semiconductor module according to claim 3, further comprising an input terminal disposed on the third surface and electrically connected to an input electrode of the at least one semiconductor chip inside the housing. 5. The semiconductor module according to claim 1, wherein the at least one semiconductor chip includes a wide band gap semiconductor. The semiconductor module according to claim 1, wherein the at least one semiconductor chip is a power semiconductor chip.

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