JP6949536B2 - Semiconductor device - Google Patents

Description

One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one aspect of the invention relates to semiconductor wafers, modules and electronic devices.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor device such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of the semiconductor device. Display devices (liquid crystal display devices, light emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, image pickup devices, electronic devices, and the like may be said to have semiconductor devices.

One aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter.

In recent years, the development of semiconductor devices has been promoted, and LSIs, CPUs, and memories are mainly used. A CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes as connection terminals formed therein.

Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.

Further, a technique of constructing a transistor by using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

Further, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, a low power consumption CPU that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is low is disclosed (see Patent Document 1).

Further, for the purpose of improving the carrier mobility of the transistor, a technique for laminating oxide semiconductor layers having different electron affinities (or lower end levels of the conduction band) is disclosed (see Patent Documents 2 and 3).

Further, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for integrated circuits in which transistors and the like are integrated at high density. Further, it is required to improve the productivity of semiconductor devices including integrated circuits.

Japanese Unexamined Patent Publication No. 2012-257187 Japanese Unexamined Patent Publication No. 2011-124360 Japanese Unexamined Patent Publication No. 2011-138934

One aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention is to provide a highly productive semiconductor device.

Alternatively, one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. Another object of one aspect of the present invention is to provide a semiconductor device having a high information writing speed. Alternatively, one aspect of the present invention is to provide a semiconductor device having a high degree of freedom in design. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. Alternatively, one aspect of the present invention is to provide a novel semiconductor device.

The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. It should be noted that the problems other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the problems other than these from the description of the description, drawings, claims, etc. Is.

One aspect of the present invention is a first insulator disposed on a substrate, an oxide on the first insulator, a second insulator on the oxide, and conductivity on the second insulator. Of the body, the third insulator on the conductor, the fourth insulator in contact with the side surfaces of the conductor, and the side surfaces of the fourth insulator and the third insulator in contact with at least the top surface of the oxide. It has a fifth insulator in contact with the upper surface, and the oxide is in contact with a first region overlapping the second insulator, a second region overlapping the fourth insulator, and a second region. A semiconductor device having a third region, in which at least a portion of the third region is in contact with the fifth insulator, and the conductor and the second insulator have regions that do not overlap. ..

Further, the oxide is a semiconductor device containing In, an element M (M is Al, Ga, Y, or Sn), and Zn.

Further, the third region is a semiconductor device having a higher carrier density than the second region, and the second region is a semiconductor device having a higher carrier density than the first region.

The fourth insulator is a semiconductor device containing a metal oxide.

Further, the oxide is a semiconductor device having a curved surface between the side surface and the upper surface, and the radius of curvature of the curved surface is 3 nm or more and 10 nm or less.

Further, the conductor is a semiconductor device having a conductive oxide.

The fifth insulator is a semiconductor device having either or both of hydrogen and nitrogen.

Further, one aspect of the present invention is a storage device in which the above-mentioned semiconductor device and a semiconductor device having silicon in a channel forming region are electrically connected.

Further, in one aspect of the present invention, a first insulator is formed on a substrate, an oxide layer is formed on the first insulator, and a first insulating film is formed on the oxide layer. The conductive film and the second insulating film are formed in order, and the conductive film and the second insulating film are etched to form the second insulator and the conductor, and the first insulator, the oxide layer, and the second insulating film are formed. A third insulating film is formed by covering the second insulator and the conductor, and the third insulating film is processed to contact the side surface of the second insulator and the side surface of the conductor. By forming an insulator and processing the first insulating film using the third insulator as an etching mask, a fourth insulator is formed, and the first insulator, the oxide layer, and the third insulator are formed. This is a method for manufacturing a semiconductor device, which covers a body, a fourth insulator, and a conductor to form a fourth insulating film.

Further, the processing of the third insulating film is a method for manufacturing a semiconductor device, which performs anisotropic etching using a dry etching method.

According to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

Alternatively, it is possible to provide a semiconductor device capable of retaining data for a long period of time. Alternatively, it is possible to provide a semiconductor device having a high data writing speed. Alternatively, it is possible to provide a semiconductor device having a high degree of freedom in design. Alternatively, it is possible to provide a semiconductor device capable of suppressing power consumption. Alternatively, a new semiconductor device can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are naturally clarified from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Top view and sectional view of the semiconductor device according to one aspect of the present invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Sectional drawing of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure explaining the energy band structure of an oxide. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. A circuit diagram and a cross-sectional view of a storage device according to one aspect of the present invention. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. The cross-sectional view which shows the structure of the storage device which concerns on one aspect of this invention. The block diagram which shows the structural example of the storage device which concerns on one aspect of this invention. The circuit diagram which shows the structural example of the storage device which concerns on one aspect of this invention. The block diagram which shows the structural example of the storage device which concerns on one aspect of this invention. A block diagram and a circuit diagram showing a configuration example of a storage device according to one aspect of the present invention. The block diagram which shows the structural example of the semiconductor device which concerns on one aspect of this invention. A block diagram showing a configuration example of the semiconductor device according to one aspect of the present invention, a circuit diagram, and a timing chart showing an operation example of the semiconductor device. The block diagram which shows the structural example of the semiconductor device which concerns on one aspect of this invention. A circuit diagram showing a configuration example of the semiconductor device according to one aspect of the present invention, and a timing chart showing an operation example of the semiconductor device. The block diagram which shows the structural example of the AI system which concerns on one aspect of this invention. The block diagram explaining the application example of the AI system which concerns on one aspect of this invention. The perspective schematic diagram which shows the structural example of the IC which incorporated the AI system which concerns on one aspect of this invention. Top view of the display device. Sectional view of the display device. Sectional view of the display device. Block diagram and circuit diagram of the display device. Display module configuration example. Top view of the semiconductor wafer according to one aspect of the present invention. A flowchart and a schematic perspective view illustrating an example of a manufacturing process of electronic components. The figure which shows the electronic device which concerns on one aspect of this invention.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments and that the embodiments and details can be variously modified without departing from the spirit and scope thereof. .. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may be omitted for ease of understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular reference numeral may be added.

Further, in order to facilitate understanding of the invention, in particular, in a top view (also referred to as a “plan view”) or a perspective view, the description of some components may be omitted. In addition, some hidden lines may be omitted.

Further, in the present specification and the like, the ordinal numbers attached as the first, second and the like are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, the "first" can be appropriately replaced with the "second" or "third" for explanation. In addition, the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Further, in the present specification, terms indicating the arrangement such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes as appropriate according to the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

For example, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, the connection relationship is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or sentence, it is assumed that the connection relationship is also described in the figure or sentence.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. Elements (eg, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y when the element, light emitting element, load, etc. are not connected between X and Y. , A resistance element, a diode, a display element, a light emitting element, a load, etc.), and X and Y are connected to each other.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows. Alternatively, the switch has a function of selecting and switching the path through which the current flows. The case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion, etc.) Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, storage circuits, control circuits, etc. One or more can be connected between them. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. do. When X and Y are functionally connected, it includes a case where X and Y are directly connected and a case where X and Y are electrically connected.

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. Then, a channel forming region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel forming region. It is possible to pass an electric current through. In the present specification and the like, the channel region refers to a region in which a current mainly flows.

Further, the functions of the source and the drain may be interchanged when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.

The channel length is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other in a top view of a transistor, or a region in which a channel is formed. Refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, in the top view of a transistor, in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a region where a channel is formed. The length of the channel region in the vertical direction with respect to the channel length direction. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor (hereinafter, “apparently”). (Also called the channel width of)) and may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a transistor that is fine and has a gate electrode covering the side surface of the semiconductor, the proportion of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, the apparent channel width may be referred to as "surrounded channel width (SCW)". Further, in the present specification, when simply referred to as a channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

The semiconductor impurities are, for example, other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example, the DOS (Density of States) of the semiconductor may increase, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and an oxide semiconductor. There are transition metals other than the main components of the above, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, water may also function as an impurity. Further, in the case of an oxide semiconductor, oxygen deficiency may be formed due to, for example, mixing of impurities. When the semiconductor is silicon, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements other than oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

In the present specification and the like, the silicon oxynitride film has a higher oxygen content than nitrogen as its composition. For example, preferably, oxygen is 55 atomic% or more and 65 atomic% or less, nitrogen is 1 atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less. Those included in the concentration range. The silicon nitride film has a higher nitrogen content than oxygen in its composition. For example, preferably, nitrogen is 55 atomic% or more and 65 atomic% or less, oxygen is 1 atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0.1 atomic% or more and 10 atomic% or less. Those included in the concentration range.

Further, in the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

Further, in the present specification and the like, the term "insulator" can be paraphrased as an insulating film or an insulating layer. Further, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be paraphrased as a semiconductor film or a semiconductor layer.

Further, the transistors shown in the present specification and the like are field effect transistors unless otherwise specified. Further, the transistor shown in the present specification and the like shall be an n-channel type transistor unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be larger than 0V unless otherwise specified.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

In the present specification, the barrier membrane is a membrane having a function of suppressing the permeation of impurities such as hydrogen and oxygen, and when the barrier membrane has conductivity, it is referred to as a conductive barrier membrane. There is.

In the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS FET, it can be rephrased as a transistor having an oxide or an oxide semiconductor.

(Embodiment 1)
Hereinafter, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described.

<Semiconductor device configuration example 1>
1 (A), 1 (B), and 1 (C) are a top view and a cross-sectional view of the transistor 200 according to one aspect of the present invention and the periphery of the transistor 200.

FIG. 1A is a top view of a semiconductor device having a transistor 200. Further, FIGS. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 1C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 1A, some elements are omitted for the sake of clarity.

The semiconductor device of one aspect of the present invention includes a transistor 200, an insulator 210 that functions as an interlayer film, an insulator 212, and an insulator 280. Further, it has a conductor 203 (conductor 203a and conductor 203b) that is electrically connected to the transistor 200 and functions as wiring.

In the conductor 203, the conductor 203a is formed in contact with the inner wall of the opening of the insulator 212, and the conductor 203b is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be made about the same. Although the transistor 200 shows a configuration in which the conductor 203a and the conductor 203b are laminated, the present invention is not limited to this. For example, only the conductor 203b may be provided.

[Transistor 200]
As shown in FIG. 1, the transistor 200 is an insulator 214 and an insulator 216 arranged on a substrate (not shown) and a conductor 205 arranged so as to be embedded in the insulator 214 and the insulator 216. And an insulator 220 arranged on the insulator 216 and the insulator 205, an insulator 222 arranged on the insulator 220, an insulator 224 arranged on the insulator 222, and an insulator. Oxide 230 (Oxide 230a, Oxide 230b, and Oxide 230c) placed on 224, Insulator 250 placed on Oxide 230, and Conductivity placed on Insulator 250. Body 260 (conductor 260a and insulator 260b), insulator 270 arranged on the conductor 260, and insulator 271, and insulator 272 arranged in contact with the side surface of the conductor 260, at least oxidation. It has an insulator 274 arranged in contact with the upper surface of the object 230, the side surface of the insulator 272, and the upper surface of the insulator 271.

Although the transistor 200 shows a configuration in which the oxide 230a, the oxide 230b, and the oxide 230c are laminated, the present invention is not limited to this. For example, as shown in FIG. 1, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c, or a laminated structure of four or more layers may be used. Further, a single layer of the oxide 230b or a configuration in which the oxide 230b and the oxide 230c are provided may be provided. For example, it may be a single layer or a laminated structure of four or more layers.

Here, an enlarged view of the region 239 in the vicinity of the channel surrounded by the broken line in FIG. 1 (B) is shown in FIG. 10 (A).

As shown in FIG. 10, the oxide 230 has a region 234 that functions as a channel forming region of the transistor 200, a region 231 that functions as a source region or a drain region (regions 231a and 231b), and regions 234 and 231. It has a joining region 232 (joining region 232a and joining region 232b) between the two. The region 231 that functions as a source region or a drain region is a region having a high carrier density and a low resistance. Further, the region 234 that functions as a channel forming region is a region having a lower carrier density than the region 231 that functions as a source region or a drain region. Further, the junction region 232 is a region having a lower carrier density than the region 231 functioning as a source region or a drain region and a region having a higher carrier density than the region 234 functioning as a channel formation region. That is, the junction region 232 has a function as a junction region between the channel formation region and the source region or the drain region.

By providing the junction region, a high resistance region is not formed between the region 231 that functions as the source region or the drain region and the region 234 that functions as the channel formation region, and the on-current of the transistor can be increased.

Further, the bonding region 232 may function as a so-called overlapping region (also referred to as a Lov region) that overlaps with the conductor 260 that functions as a gate electrode.

The region 231 is preferably in contact with the insulator 274. Further, it is preferable that the concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen is larger in the region 231 than in the bonding region 232 and the region 234.

The joint region 232 has a region that overlaps with the insulator 272. The bonding region 232 preferably has a higher concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen than the region 234. On the other hand, it is preferable that the concentration of at least one of the metal element such as indium and the impurity element such as hydrogen and nitrogen is smaller than that of the region 231.

Region 234 overlaps with conductor 260. The region 234 is arranged between the bonding region 232a and the bonding region 232b, and the concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen is the region 231 and the bonding region 232. Smaller is preferable.

Further, in the oxide 230, the boundary between the region 231 and the bonding region 232 and the region 234 may not be clearly detected. The concentrations of metal elements such as indium and impurity elements such as hydrogen and nitrogen detected in each region are not limited to gradual changes in each region, but continuously change in each region (also called gradation). You may be doing it. That is, it is sufficient that the concentration of the metal element such as indium and the impurity element such as hydrogen and nitrogen decreases as the region is closer to the region 234 from the region 231 to the junction region 232.

Further, in FIG. 10, the region 234, the region 231 and the bonding region 232 are formed on the oxide 230b, but the region is not limited to this, and for example, these regions are also formed on the oxide 230a or the oxide 230c. It may be formed. Further, in the figure, the boundary of each region is displayed substantially perpendicular to the upper surface of the oxide 230, but the present embodiment is not limited to this. For example, the bonding region 232 may project toward the conductor 260 near the surface of the oxide 230b, and may recede toward the conductor 252a or the conductor 252b near the lower surface of the oxide 230b.

In the transistor 200, it is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor as the oxide 230. A transistor using an oxide semiconductor has an extremely small leakage current (off current) in a non-conducting state, so that a semiconductor device having low power consumption can be provided. Further, since the oxide semiconductor can be formed into a film by using a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device.

On the other hand, a transistor using an oxide semiconductor may have poor reliability because its electrical characteristics are liable to fluctuate due to impurities and oxygen deficiency in the oxide semiconductor. Further, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. Transistors using oxide semiconductors containing oxygen deficiency in the channel formation region tend to have normally-on characteristics. Therefore, it is preferable that oxygen deficiency in the channel formation region is reduced as much as possible.

In particular, if oxygen deficiency exists at the interface between the region 234 where the channel is formed in the oxide 230 and the insulator 250 that functions as a gate insulating film, the electrical characteristics are likely to fluctuate and the reliability is deteriorated. There is.

Therefore, it is preferable that the insulator 250 in contact with the region 234 of the oxide 230 contains more oxygen than oxygen (also referred to as excess oxygen) satisfying the stoichiometric composition. That is, the excess oxygen contained in the insulator 250 diffuses into the region 234, so that the oxygen deficiency in the region 234 can be reduced.

Further, it is preferable to provide the insulator 272 in contact with the insulator 250. For example, the insulator 272 preferably has a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate). Since the insulator 272 has a function of suppressing the diffusion of oxygen, it is efficiently supplied to the region 234. Therefore, the formation of oxygen deficiency at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.

Further, it is preferable that the transistor 200 is covered with an insulator having a barrier property to prevent impurities such as water and hydrogen from being mixed. The insulator having a barrier property, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 _O, NO, etc. NO _2), function of suppressing the diffusion of impurities such as copper atoms It is an insulator using an insulating material having (the above impurities are difficult to permeate). Further, it is preferable to use an insulating material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).

Hereinafter, a detailed configuration of the semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

The conductor 205 that functions as the second gate electrode is arranged so as to overlap the oxide 230 and the conductor 260.

Here, the conductor 205 may be provided larger than the region 234 in the oxide 230 so that the length in the channel width direction is larger. In particular, the conductor 205 is preferably stretched even in a region outside the end where the region 234 of the oxide 230 intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superposed on each other via the insulator on the side surface of the oxide 230 in the channel width direction.

Here, the conductor 260 may function as a first gate electrode. Further, the conductor 205 may function as a second gate electrode. In that case, the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with it. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be made larger than 0 V, and the off-current can be reduced. Therefore, the drain current when the voltage applied to the conductor 260 is 0 V can be reduced.

Further, as shown in FIG. 1A, the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is arranged so as to overlap with the conductor 260 even in a region outside the end portion intersecting the channel width direction (W length direction) of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on each other via an insulator on the outside of the side surface of the oxide 230.

With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a closed circuit and oxidize. The channel forming region formed on the object 230 can be covered.

That is, the channel forming region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having the function of the first gate electrode and the electric field of the conductor 205 having the function of the second gate electrode. .. In the present specification, the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate electrode and the second gate electrode is referred to as a surroundd channel (S-channel) structure.

In the conductor 205, the conductor 205a is formed in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and the conductor 205b is further formed inside. Here, the height of the upper surfaces of the conductor 205a and the conductor 205b can be made the same as the height of the upper surface of the insulator 216. Although the transistor 200 shows a configuration in which the conductor 205a and the conductor 205b are laminated, the present invention is not limited to this. For example, only the conductor 205b may be provided.

Here, the conductor 205a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule _(N 2 O, NO, etc. NO _2), the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a conductive material having (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate). In the present specification, the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

Since the conductor 205a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 205b from being oxidized and the conductivity from being lowered. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the conductor 205a, the conductive material may be a single layer or a laminated material. As a result, it is possible to prevent impurities such as hydrogen and water from diffusing from the substrate side of the insulator 214 to the transistor 200 side through the conductor 205.

Further, as the conductor 205b, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Although the conductor 205b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.

The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from being mixed into the transistor from the substrate side. Thus, the insulator 214 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule _(N 2 O, NO, etc. NO _2), has a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use an insulating material (which is difficult for the above impurities to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).

For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. As a result, it is possible to prevent impurities such as hydrogen and water from diffusing from the insulator 214 to the transistor side. Alternatively, it is possible to prevent oxygen contained in the insulator 224 or the like from diffusing from the insulator 214 toward the substrate side.

Further, the insulator 216 and the insulator 280 that function as an interlayer film preferably have a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

For example, the insulator 216 that functions as an interlayer film and the insulator 280 include silicon oxide, silicon nitride nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), and titanium. Insulators such as strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used in single layers or in layers. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated on the above insulator.

The insulator 220, the insulator 222, and the insulator 224 have a function as a gate insulator.

Here, as the insulator 224 in contact with the oxide 230, it is preferable to use an oxide insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 224 is formed with an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced and reliability can be improved.

Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. Oxides that desorb oxygen by heating are those in which the amount of oxygen desorbed in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3 in TDS (Thermal Desorption Spectroscopy) analysis. It is an oxide film having a ratio of 0.0 × 10 ²⁰ atoms / cm ^{3 or more.} The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.

Further, when the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate). Is preferable.

Since the insulator 222 has a function of suppressing the diffusion of oxygen, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. Further, it is possible to prevent the conductor 205 from reacting with oxygen in the excess oxygen region of the insulator 224.

The insulator 222 is a so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO _{3 (BST).} It is preferable to use an insulator containing a −k material in a single layer or in a laminated state. By using a high-k material for the insulator that functions as a gate insulator, the transistor can be miniaturized and highly integrated. In particular, it is preferable to use an insulating material having a function of suppressing diffusion of impurities and oxygen such as aluminum oxide and hafnium oxide (the above oxygen is difficult to permeate). When formed using such a material, it functions as a layer for preventing the release of oxygen from the oxide 230 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 200.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated on the above insulator.

Further, the insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with an insulator made of a high-k material to form a laminated structure that is thermally stable and has a high relative permittivity.

The insulator 220, the insulator 222, and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to the same material, and may be a laminated structure made of different materials. Further, the transistor 200 shows a configuration in which the insulator 220, the insulator 222, and the insulator 224 function as gate insulators, but the present embodiment is not limited to this. For example, as the gate insulator, any two layers or one layer of the insulator 220, the insulator 222, and the insulator 224 may be provided.

The oxide 230 has an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. The oxide 230 also has a region 231, a junction region 232, and a region 234. It is preferable that at least a part of the region 231 is in contact with the insulator 274. Further, it is preferable that at least a part of the region 231 has a concentration of at least one of a metal element such as indium, hydrogen, and nitrogen higher than that of the region 234.

When the transistor 200 is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least a part of the region 234 functions as a region where a channel is formed.

Here, as shown in FIG. 10, the oxide 230 preferably has a bonding region 232. With this configuration, in the transistor 200, the on-current can be increased and the leakage current (off-current) at the time of non-conduction can be reduced.

Further, by having the oxide 230b on the oxide 230a, it is possible to suppress the diffusion of impurities with respect to the oxide 230b from the structure formed below the oxide 230a. Further, by having the oxide 230b under the oxide 230c, it is possible to suppress the diffusion of impurities with respect to the oxide 230b from the structure formed above the oxide 230c.

As shown in FIG. 1, when the oxide 230c is contained, the oxide 230c can be a metal oxide that can be used for the oxide 230a or the oxide 230b.

The oxide film to be the oxide 230c may be formed under the same conditions as the film forming condition of the oxide film to be the oxide 230a, or may be formed under the same conditions as the film forming condition of the oxide film to be the oxide 230b. The film may be formed using the conditions of. Further, a film may be formed by combining these conditions.

In the present embodiment, as the oxide film to be the oxide 230c, a film is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic number ratio]. At this time, the film may be formed with the ratio of oxygen set to 70% or more, preferably 80% or more, and more preferably 100%.

The oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film forming conditions and the atomic number ratio.

Here, as shown in FIG. 1C, it is preferable that the oxide 230c is provided so as to cover the oxide 230a and the oxide 230b in the channel width direction. That is, the oxide 230b is surrounded by the oxide 230a and the oxide 230c. With this structure, it is possible to prevent impurities from being mixed into the oxide 230b on which the channel is formed in the region 234.

Further, when the oxide 230a and the oxide 230c are provided, the energy at the lower end of the conduction band of the oxide 230a and 230c is higher than the energy at the lower end of the conduction band in the region where the energy at the lower end of the conduction band of the oxide 230b is low. Is preferable. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity in the region where the energy at the lower end of the conduction band of the oxide 230b is low.

Here, in the oxide 230a, the oxide 230b, and the oxide 230c, the energy level at the lower end of the conduction band changes gently. In other words, it can also be said to be continuously changing or continuously joining. In order to do so, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c.

Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) other than oxygen, so that a mixed layer having a low defect level density is formed. be able to. For example, when the oxide 230b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 230a and 230c.

At this time, the main path of the carrier is the narrow gap portion formed in the oxide 230b. Since the defect level density at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be lowered, the influence of interfacial scattering on carrier conduction is small, and a high on-current is generated. can get.

Further, a curved surface is provided between the side surface of the oxide 230 and the upper surface of the oxide 230. That is, it is preferable that the end portion of the side surface and the end portion of the upper surface are curved (hereinafter, also referred to as a round shape). The curved surface preferably has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the oxide 230b, for example.

As the oxide 230, it is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor. For example, as the metal oxide in the region 234, it is preferable to use an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using the metal oxide having a wide energy gap, the off-current of the transistor can be reduced.

As shown in FIG. 20, the electron affinity or the energy level Ec at the lower end of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the upper end of the valence band, and the bandgap Eg. The ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) apparatus. The energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.

In addition, in this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

A transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state, so that a semiconductor device having low power consumption can be provided. Further, since the oxide semiconductor can be formed into a film by using a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device.

For example, as oxide 230, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium). , Neodymium, hafnium, tantalum, tungsten, gallium, etc. (one or more) and the like may be used. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

Here, the region 234 of the oxide 230 will be described.

Region 234 preferably has a laminated structure due to oxides having different atomic number ratios of each metal atom. Specifically, when the oxide 230a and the oxide 230b have a laminated structure, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 230a is the metal oxide used for the oxide 230b. It is preferable that it is larger than the atomic number ratio of the element M in the constituent elements. Further, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a. Further, as the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

Subsequently, the region 231 of the oxide 230 and the bonding region 232 will be described.

The region 231 and the bonding region 232 are regions in which a metal atom such as indium or an impurity is added to the metal oxide provided as the oxide 230 to reduce resistance. It should be noted that each region has at least higher conductivity than the oxide 230b in the region 234. In order to add impurities to the region 231 and the junction region 232, for example, plasma treatment, an ion implantation method in which ionized raw material gas is added by mass separation, and ionized raw material gas without mass separation. A metal element such as indium and a dopant which is at least one of impurities may be added by using an ion implantation method, a plasma implantation ion implantation method, or the like to be added.

That is, by increasing the content of metal atoms such as indium in the oxide 230 in the region 231 and the bonding region 232, the electron mobility can be increased and the resistance can be reduced.

Alternatively, impurities can be added to the region 231 and the bonding region 232 by forming an insulator 274 containing an element that becomes an impurity in contact with the oxide 230.

That is, the region 231 and the junction region 232 are reduced in resistance by adding an element that forms an oxygen deficiency or an element that is captured by the oxygen deficiency. Typical examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of noble gas elements include helium, neon, argon, krypton, xenon and the like. Therefore, the region 231 and the bonding region 232 may be configured to contain one or more of the above elements.

For example, as the insulator 274, a film that extracts and absorbs oxygen contained in the region 231 and the bonding region 232 may be used. When oxygen is withdrawn, oxygen deficiency occurs in the region 231 and the junction region 232. The regions 231 and the junction region 232 have low resistance due to the capture of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, rare gas, etc. in the oxygen deficiency.

Further, in the transistor 200, by providing the junction region 232, a high resistance region is not formed between the region 231 that functions as the source region and the drain region and the region 234 in which the channel is formed. And the mobility can be increased. Further, by having the junction region 232, since the source region and the drain region and the gate do not overlap in the channel length direction, it is possible to suppress the formation of unnecessary capacitance. Further, by having the junction region 232, the leakage current at the time of non-conduction can be reduced.

Therefore, by appropriately selecting the range of the junction region 232, it is possible to easily provide a transistor having electrical characteristics that meets the requirements according to the circuit design.

The insulator 250 functions as a gate insulating film. The insulator 250 is preferably arranged in contact with the upper surface of the oxide 230c. The insulator 250 is preferably formed by using an insulator in which oxygen is released by heating. For example, in a heated desorption gas spectroscopy analysis (TDS analysis), the amount of oxygen desorbed in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ^20. It is an oxide film having atoms / cm ^{3 or more.} The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower.

By providing an insulator that releases oxygen by heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b. Further, similarly to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

The conductor 260 that functions as the first gate electrode has a conductor 260a and a conductor 260b on the conductor 260a. It is preferable to use a conductive oxide for the conductor 260a. For example, a metal oxide that can be used as the oxide 230a or the oxide 230b can be used. In particular, among In-Ga-Zn-based oxides, the atomic number ratio of the metal having high conductivity is [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, or a value close thereto. It is preferable to use one. By providing such a conductor 260a, it is possible to suppress the permeation of oxygen into the conductor 260b and prevent the electric resistance value of the conductor 260b from increasing due to oxidation.

Further, by forming the conductive oxide into a film by using a sputtering method, oxygen can be added to the insulator 250 and oxygen can be supplied to the oxide 230b. Thereby, the oxygen deficiency in the region 234 of the oxide 230 can be reduced.

As the conductor 260b, a conductor capable of improving the conductivity of the conductor 260a by adding an impurity such as nitrogen to the conductor 260a may be used. For example, it is preferable to use titanium nitride or the like for the conductor 260b. Further, as the conductor 260b, for example, a laminated structure of the above-mentioned titanium nitride or the like and tungsten having high conductivity or the like can be used.

Further, as shown in FIG. 1C, when the conductor 205 is stretched in a region outside the end portion intersecting the channel width direction of the oxide 230, the conductor 260 is in the region. It is preferable that they are superimposed via the insulator 250. That is, it is preferable that the conductor 205, the insulator 250, and the conductor 260 form a laminated structure on the outside of the side surface of the oxide 230.

With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to form a closed circuit and oxidize. The channel forming region formed on the object 230 can be covered.

That is, the channel forming region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having the function of the first gate electrode and the electric field of the conductor 205 having the function of the second gate electrode. ..

Further, an insulator 270 that functions as a barrier membrane may be arranged on the conductor 260b. As the insulator 270, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. For example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as an insulator containing one or both oxides of aluminum and hafnium, thereby preventing oxidation of the conductor 260. be able to. Further, it is possible to prevent impurities such as water and hydrogen from being mixed into the oxide 230 through the conductor 260 and the insulator 250.

Further, it is preferable to arrange the insulator 271 that functions as a hard mask on the insulator 270. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle formed by the side surface of the conductor 260 and the surface of the substrate is 75 degrees or more and 100 degrees or less. It can be preferably 80 degrees or more and 95 degrees or less. By processing the conductor into such a shape, the insulator 272 to be formed next can be formed into a desired shape.

Further, an insulator 272 that functions as a barrier film is provided in contact with the side surfaces of the conductor 260 and the insulator 270.

Here, as the insulator 272, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. For example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like, whereby oxygen in the insulator 250 is removed. It can be prevented from spreading to the outside. Further, it is possible to prevent impurities such as hydrogen and water from being mixed into the oxide 230 from the end portion of the insulator 250.

By providing the insulator 272, the upper surface and the side surface of the conductor 260 can be covered with an insulator having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. This makes it possible to prevent impurities such as water and hydrogen from being mixed into the oxide 230 via the conductor 260. Therefore, the insulator 272 functions as a side barrier that protects the gate electrode and the side surface of the gate insulating film.

Further, when the transistor is miniaturized and the channel length is formed to be about 10 nm or more and 30 nm or less, the impurity elements contained in the structure provided around the transistor 200 are diffused, and the region 231a, the region 231b, or the region 231b or The joining region 232a and the joining region 232b may be electrically conductive.

Therefore, as shown in the present embodiment, by forming the insulator 272, it is possible to prevent impurities such as hydrogen and water from being mixed into the conductor 260. Therefore, when the first gate voltage is 0 V, it is possible to prevent the source region and the drain region from being electrically conducted directly or through the junction region 232 and the like.

The insulator 274 has at least a region in contact with the oxide 230 and the insulator 272. In particular, the insulator 274 preferably has a region in contact with the region 231 of the oxide 230.

Further, it is preferable to use an insulating material having a function of suppressing the permeation of oxygen for the insulator 274. For example, as the insulator 274, it is preferable to use silicon nitride, silicon nitride oxide, silicon nitride nitride, aluminum nitride, aluminum nitride or the like. By forming such an insulator 274, it is possible to prevent oxygen from being mixed through the insulator 274 and supplying oxygen to the oxygen deficiency in the regions 231a and 231b to reduce the carrier density. ..

When the region 231 and the bonding region 232 are provided by forming the insulator 274, the insulator 274 preferably has at least one of hydrogen and nitrogen. By using an insulator having impurities such as hydrogen or nitrogen in the insulator 274, impurities such as hydrogen or nitrogen are added to the oxide 230 to form a region 231 and a bonding region 232 in the oxide 230. be able to.

It is preferable to provide an insulator 280 that functions as an interlayer film on the insulator 274. Like the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

The configuration of the transistor 200, which is one aspect of the present invention, is such that the leakage current between the conductor 260, which is the first gate electrode, and the oxide 230, which has a source region or a drain region, is reduced. ..

FIG. 11 shows an enlarged view of the side surface of the conductor 260 and the region 238 near the side surface of the insulator 250 surrounded by the broken line in FIG. 1 (B). FIG. 11A shows the configuration of the transistor 200, which is one aspect of the present invention. Further, FIG. 11B shows an example of a transistor having a configuration different from that of the transistor 200.

As shown in FIG. 11A, the transistor 200 has a region 250W in which the conductor 260 and the insulator 250 do not overlap. On the other hand, the transistor having a configuration different from that of the transistor 200 shown in FIG. 11B does not have a region 250W, and the side surface of the conductor 260 and the side surface of the insulator 250 substantially coincide with each other. In other words, the side surface of the conductor 260 and the side surface of the insulator 250 are substantially flush with each other.

This may be such a configuration when the formation of the conductor 260 and the formation of the insulator 250 are collectively formed. With such a configuration, the side surface of the insulator 250 and the oxide 230c are located between the conductor 260 having a function as a gate electrode and the region 231 having a function as a source region or a drain region of the oxide 230. And current may flow through the junction region 232. (Called leak current.).

This is because when the conductor 260 and the insulator 250 are formed at the same time by the dry etching method, the etching product generated during the dry etching is the side surface of the conductor 260 and the insulator 250. May adhere to the sides. The etching product may adhere to the vicinity of the region indicated by the dotted frame in FIGS. 11 (A) and 11 (B).

For example, when etching a conductive film to be a conductor 260 using a gas containing fluorine or chlorine, etching containing fluorine or chlorine and carbon and a part of the conductive film which are a part of a photoresist component as an etching mask. Products may adhere. The etching product may be conductive because it contains carbon, which is part of the conductive film and part of the photoresist component, as described above.

The etching product adheres to the vicinity indicated by the dotted frame in FIGS. 11 (A) and 11 (B), but is unlikely to adhere to a surface parallel to the bottom surface of the substrate, for example, a surface of region 250 W. .. This is because the direction of the electric field during dry etching is perpendicular to the surface of the region 250W, and since the etching proceeds in the direction of this electric field, the surface parallel to the bottom surface of the substrate, for example, the surface of the region 250W Etching products are less likely to accumulate. On the other hand, since the neighborhoods shown by the dotted lines in FIGS. 11 (A) and 11 (B) are substantially parallel to the direction of the electric field during dry etching, there is almost no progress of etching, so FIG. 11 (A) ) And in the vicinity shown by the dotted frame in FIG. 11 (B), etching products are likely to be deposited.

The product can be removed by a cleaning process after the formation of the conductor 260 and the insulator 250, but it may not be completely removed, and even a small amount of the remaining product may cause leakage current. It may be a route. As described above, the etching product adhering to the side surface of the conductor 260 and the side surface of the insulator 250 serves as a path for the leak current. In FIGS. 11A and 11B, the leakage current path 260L is shown by a straight line with an arrow.

In a transistor having such a leak current path, for example, a leak current flows when a potential difference occurs between a conductor 260 having a function as a gate electrode and a source region or a drain region. Therefore, it may interfere with the normal operation of the semiconductor device having the transistor. For example, in a storage device, the leak current may make it impossible to retain the memory for a long period of time.

Therefore, the transistor 200 according to one aspect of the present invention shown in FIG. 11A has a region 250W in which the conductor 260 and the insulator 250 do not overlap, thereby blocking the leakage current path. can. As described above, the etching product is unlikely to be deposited in the region 250W. In order to make this configuration, it is not necessary to form the conductor 260 and the insulator 250 at once, and only the conductor 260 needs to be formed. The insulator 250 may be formed collectively at the time of forming the insulator 272, which is a later step. The number of steps and the number of masks used for processing are the same as in the case where the conductor 260 and the insulator 250 are formed at once. Further, by adopting such a forming method, the film thickness of the insulator 250 in the region 250W that is not in contact with the conductor 260 is thinner than the film thickness of the insulator 250 in the region that is in contact with the conductor 260. There is.

By configuring the semiconductor device having the transistor 200 as described above, the leakage current between the gate electrode of the transistor 200 and the source region and the drain region can be reduced, so that the semiconductor device has high performance and high reliability. It can be a semiconductor device having a transistor.

<Semiconductor device configuration example 2>
2 (A), 2 (B), and 2 (C) are a top view and a cross-sectional view of the transistor 200a and the periphery of the transistor 200a according to one aspect of the present invention.

FIG. 2A is a top view of the semiconductor device having the transistor 200a. 2 (B) and 2 (C) are cross-sectional views of the semiconductor device. Here, FIG. 2B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 2A, and is also a cross-sectional view of the transistor 200a in the channel length direction. Further, FIG. 2C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 2A, and is also a cross-sectional view of the transistor 200a in the channel width direction. In the top view of FIG. 2A, some elements are omitted for the sake of clarity.

[Transistor 200a]
As shown in FIG. 2, the transistor 200a includes an insulator 214 and an insulator 216 arranged on a substrate (not shown) and a conductor 205 arranged so as to be embedded in the insulator 214 and the insulator 216. And an insulator 220 arranged on the insulator 216 and the insulator 205, an insulator 222 arranged on the insulator 220, an insulator 224 arranged on the insulator 222, and an insulator. The oxide 230 placed on the 224, the insulator 250 placed on the oxide 230, the conductor 260 placed on the insulator 250, and the insulation placed on the conductor 260. The body 270, the insulator 271, the insulator 272 arranged in contact with the side surface of the conductor 260, and the insulator arranged in contact with the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the insulator 272. It has at least an insulator 274 arranged in contact with the upper surface of the oxide 230, the side surface of the insulator 273, and the upper surface of the insulator 271.

As described above, the transistor 200a has an insulator 273 arranged in contact with the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the insulator 272, but the configuration is different from that of the transistor 200 shown in FIG. ..

The transistor 200a is in contact with the side surface of the insulator 250, and the insulator 273 is provided. For example, it is preferable that the insulator 273 has a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate). Since the insulator 273 has a function of suppressing the diffusion of oxygen, oxygen in the excess oxygen region is efficiently supplied to the region 234 without diffusing to the insulator 274 side. Therefore, the formation of oxygen deficiency at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200a can be further improved. For other configurations and effects, the description of the configuration example 1 of the semiconductor device having the transistor 200 shown in FIG. 1 is taken into consideration.

<Semiconductor device configuration example 3>
3 (A), 3 (B), and 3 (C) are a top view and a cross-sectional view of the transistor 200b and the periphery of the transistor 200b according to one aspect of the present invention.

FIG. 3A is a top view of the semiconductor device having the transistor 200b. 3 (B) and 3 (C) are cross-sectional views of the semiconductor device. Here, FIG. 3B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 3A, and is also a cross-sectional view of the transistor 200b in the channel length direction. Further, FIG. 3C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 3A, and is also a cross-sectional view of the transistor 200b in the channel width direction. In the top view of FIG. 3A, some elements are omitted for the sake of clarity.

[Transistor 200b]
As shown in FIG. 3, the transistor 200b includes an insulator 214 and an insulator 216 arranged on a substrate (not shown) and a conductor 205 arranged so as to be embedded in the insulator 214 and the insulator 216. And an insulator 220 arranged on the insulator 216 and the insulator 205, an insulator 222 arranged on the insulator 220, an insulator 224 arranged on the insulator 222, and an insulator. The oxide 230 placed on the 224, the insulator 250 placed on the oxide 230, the conductor 260 placed on the insulator 250, and the insulation placed on the conductor 260. The body 270, the insulator 271, the insulator 272 arranged in contact with the side surface of the conductor 260, and at least the upper surface of the oxide 230, the side surface of the oxide 230c, the side surface of the insulator 250 and the side surface of the insulator 272 and It has an insulator 273A arranged in contact with the upper surface of the insulator 271 and an insulator 274 on the insulator 273.

As described above, the transistor 200b has an insulator 273A arranged in contact with the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the insulator 272, but the configuration is different from that of the transistor 200 shown in FIG. ..

Further, as shown in FIG. 3, the transistor 200b is a film that suppresses the diffusion of hydrogen or nitrogen as an insulator 273A between the oxide 230 and the insulator 274 that is a film containing hydrogen or nitrogen. It is configured to provide. By providing the insulator 274 on the region 231 of the oxide 230 via the insulator 273A, it is possible to prevent excess hydrogen or nitrogen from being added to the region 234 of the oxide 230. ..

Further, the insulator 273A can also function as a side barrier that protects the side surfaces of the conductor 260 having a function as a gate electrode and the insulator 250 having a function as a gate insulator. When it has a function as a side barrier, as shown in FIG. 3, the insulator 273A is provided so as to cover at least the side surface of the conductor 260 and the side surface of the insulator 250. It is preferable that the insulator 273A has a function of suppressing the diffusion of at least one oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate). Since the insulator 273A has a function of suppressing the diffusion of oxygen, oxygen in the excess oxygen region is efficiently supplied to the region 234 without diffusing to the insulator 274 side. Therefore, the formation of oxygen deficiency at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200a can be further improved. For other configurations and effects, the description of the configuration example 1 of the semiconductor device having the transistor 200 shown in FIG. 1 is taken into consideration.

<Semiconductor device configuration example 4>
4 (A), 4 (B), and 4 (C) are a top view and a cross-sectional view of the transistor 200c and the periphery of the transistor 200c according to one aspect of the present invention.

FIG. 4A is a top view of the semiconductor device having the transistor 200c. Further, FIG. 4B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 4A, and is also a cross-sectional view of the transistor 200c in the channel length direction. Further, FIG. 4C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 4A, and is also a cross-sectional view of the transistor 200c in the channel width direction. In the top view of FIG. 4A, some elements are omitted for the sake of clarity.

[Transistor 200c]
As shown in FIG. 4, the transistor 200c has a plurality of channel forming regions for one gate electrode, which is different from the configuration of the transistor 200 shown in FIGS. 1 (A), (B) and (C). The transistor 200c can obtain a large on-current by having a plurality of channel forming regions. Further, since each channel forming region has a structure covered with a gate electrode, that is, an s-channel structure, a large on-current can be obtained in each channel forming region. Note that FIG. 4 shows an example having three channel forming regions, but the number of channel forming regions is not limited to this. For other configurations and effects, the description of the configuration example 1 of the semiconductor device having the transistor 200 shown in FIG. 1 is taken into consideration.

<Semiconductor device configuration example 5>
5 (A), 5 (B), and 5 (C) are a top view and a cross-sectional view of the transistor 200d and the periphery of the transistor 200d according to one aspect of the present invention.

FIG. 5A is a top view of the semiconductor device having the transistor 200d. 5 (B) and 5 (C) are cross-sectional views of the semiconductor device. Here, FIG. 5 (B) is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 5 (A), and is also a cross-sectional view of the transistor 200d in the channel length direction. Further, FIG. 5C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 5A, and is also a cross-sectional view of the transistor 200d in the channel width direction. In the top view of FIG. 5A, some elements are omitted for the sake of clarity.

The semiconductor device of one aspect of the present invention includes a transistor 200d, and an insulator 210, an insulator 212, and an insulator 280 that function as interlayer films.

[Transistor 200d]
As shown in FIG. 5, the transistor 200d is arranged on an insulator 220 arranged on a substrate (not shown), an insulator 224 arranged on the insulator 220, and an insulator 224. The oxide 230, the insulator 250 placed on the oxide 230, the conductor 260 placed on the insulator 250, the insulator 270 placed on the conductor 260, and the insulator. It has 271, an insulator 272 arranged in contact with the side surface of the conductor 260, and at least an insulator 274 arranged in contact with the upper surface of the oxide 230, the side surface of the insulator 272, and the upper surface of the insulator 271. ..

The transistor 200d is different from the transistor 200 shown in FIGS. 1 (A), (B) and (C) in that it does not have the conductor 203 and the conductor 205. For other configurations and effects, the description of the configuration example 1 of the semiconductor device having the transistor 200 shown in FIG. 1 is taken into consideration.

<Semiconductor device configuration example 6>
6 (A), 6 (B), and 6 (C) are a top view and a cross-sectional view of the transistor 200e and the periphery of the transistor 200e according to one aspect of the present invention.

FIG. 6A is a top view of the semiconductor device having the transistor 200e. 6 (B) and 6 (C) are cross-sectional views of the semiconductor device. Here, FIG. 6B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 6A, and is also a cross-sectional view of the transistor 200e in the channel length direction. Further, FIG. 6C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG. 6A, and is also a cross-sectional view of the transistor 200e in the channel width direction. In the top view of FIG. 6A, some elements are omitted for the sake of clarity.

The semiconductor device of one aspect of the present invention includes a transistor 200e, and an insulator 210, an insulator 212, and an insulator 280 that function as interlayer films.

[Transistor 200e]
As shown in FIG. 6, the transistor 200e is arranged on an insulator 224 arranged on a substrate (not shown), an oxide 230 arranged on the insulator 224, and an oxide 230. Insulator 250, a conductor 260 arranged on the insulator 250, an insulator 271 arranged on the conductor 260, and an insulator 272 arranged in contact with the side surface of the insulator 260. It has at least the upper surface of the oxide 230, the side surface of the insulator 272, and the insulator 274 arranged in contact with the upper surface of the insulator 271.

The transistor 200e is different from the transistor 200 shown in FIGS. 1A, 1B, and 1C in that it does not have the conductor 203, the conductor 205, the insulator 220, the insulator 222, and the insulator 270. For other configurations and effects, the description of the configuration example 1 of the semiconductor device having the transistor 200 shown in FIG. 1 is taken into consideration.

<Semiconductor device configuration example 7>
7 (A), 7 (B), and 7 (C) are a top view and a cross-sectional view of the transistor 100A and the periphery of the transistor 100A according to one aspect of the present invention.

FIG. 7A is a top view of the semiconductor device having the transistor 100A. 7 (B) and 7 (C) are cross-sectional views of the semiconductor device. Here, FIG. 7B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 7A, and is also a cross-sectional view of the transistor 100A in the channel length direction. Further, FIG. 7C is a cross-sectional view of the portion shown by the alternate long and short dash line of B1-B2 in FIG. 7A, and is also a cross-sectional view of the transistor 100A in the channel width direction. In the top view of FIG. 7A, some elements are omitted for the sake of clarity.

[Transistor 100A]
The conductor 100A includes an insulating layer 104 on the substrate 102, a semiconductor layer 108 on the insulating layer 104, an insulating layer 140 on the semiconductor layer 108, a metal oxide layer 114 on the insulating layer 140, and a metal oxide layer 114. The upper conductive layer 142, the insulating layer 115 arranged in contact with the side surface of the metal oxide layer 114 and the side surface of the conductive layer 142, and at least the upper surface of the semiconductor layer 108, the side surface of the insulating layer 115, and the upper surface of the conductive layer 142. It has an insulating layer 116 arranged in contact with the insulation layer 116. The portion of the semiconductor layer 108 that overlaps with the conductive layer 142 functions as a channel forming region.

For the semiconductor layer 108, the same material as the above-mentioned oxide 230 can be used.

Further, as shown in FIGS. 7A, 7B, and 7C, the semiconductor device having the transistor 100A has an insulating layer 118 on the insulating layer 116. Further, the conductive layer 121a and the conductive layer 121b which are electrically connected to the region 108n may be provided via the opening 141a or the opening 141b provided in the insulating layer 116 and the insulating layer 118, respectively.

In the present specification and the like, the insulating layer 104 is the first insulating film, the insulating layer 140 is the second insulating film, the insulating layer 116 is the third insulating film, and the insulating layer 118 is the fourth insulating film. , Each may be called. Further, the conductive layer 142 has a function as a gate electrode, the conductive layer 121a has a function as a source electrode, and the conductive layer 121b has a function as a drain electrode.

Similar to the above-mentioned transistor 200, the transistor 100A has a region in which the conductive layer 142 and the insulating layer 140 do not overlap. By having the region, the leakage current path between the conductive layer 142 and the semiconductor layer 108 can be blocked.

Further, the region 108n is a region in which a metal atom such as indium or an impurity is added to the metal oxide provided as the semiconductor layer 108 to reduce the resistance. The region 108n has at least higher conductivity than the region where the insulating layer 140 of the semiconductor layer 108 and the semiconductor layer 108 are in contact with each other. In order to add impurities to the region 108n, for example, plasma treatment, an ion implantation method in which ionized raw material gas is added by mass separation, and an ion implantation method in which ionized raw material gas is added without mass separation. , A metal element such as indium and a dopant which is at least one of impurities may be added by using a plasma implantation ion implantation method or the like.

That is, by increasing the content of metal atoms such as indium in the semiconductor layer 108 in the region 108n, the electron mobility can be increased and the resistance can be reduced.

Alternatively, impurities can be added to the region 108n by forming an insulating layer 116 containing an element that becomes an impurity in contact with the semiconductor layer 108.

That is, the region 108n is reduced in resistance by adding an element that forms an oxygen deficiency or an element that is captured by the oxygen deficiency. Typical examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of noble gas elements include helium, neon, argon, krypton, xenon and the like. Therefore, the region 108n may be configured to contain one or more of the above elements.

For example, as the insulating layer 116, a film that extracts and absorbs oxygen contained in the region 108n may be used. When oxygen is withdrawn, oxygen deficiency occurs in the region 108n. The region 108n has a low resistance due to the capture of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, rare gas, etc. in the oxygen deficiency.

The insulating layer 140 that functions as a gate insulating layer has an excess oxygen region. Since the insulating layer 140 has an excess oxygen region, excess oxygen can be supplied into the semiconductor layer 108. Therefore, the oxygen deficiency that can be formed in the semiconductor layer 108 can be compensated by excess oxygen, so that a highly reliable semiconductor device can be provided.

The metal oxide layer 114 located between the insulating layer 140 and the conductive layer 142 functions as a barrier membrane that prevents oxygen released from the insulating layer 140 from diffusing toward the conductive layer 142. For the metal oxide layer 114, for example, a material that is less permeable to oxygen than the insulating layer 140 can be used.

As the metal oxide layer 114, an insulating material or a conductive material can be used. When the metal oxide layer 114 has an insulating property, it functions as a part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductivity, it functions as a part of the gate electrode.

In particular, it is preferable to use an insulating material having a dielectric constant higher than that of silicon oxide as the metal oxide layer 114. In particular, it is preferable to use an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like.

Further, a metal oxide film such as an aluminum oxide film or a hafnium oxide film that does not contain nitrogen as a main component can be used between the semiconductor layer 108 and the conductive layer 142 that functions as a gate electrode. Therefore, the metal oxide layer 114 is a nitrogen oxide that can form a level in the film (NO _x , x is greater than 0 and 2 or less, preferably 1 or more and 2 or less, typically NO ₂ or NO). The content of the above can be extremely small. As a result, a transistor having excellent electrical characteristics and reliability can be realized.

The aluminum oxide film, hafnium oxide film, hafnium aluminate film, etc. have sufficiently high barrier properties even when the film thickness is thin (for example, about 5 nm in thickness), so that they can be formed thin and improve productivity. Can be made to. For example, the thickness of the metal oxide layer 114 can be 1 nm or more and 50 nm or less, preferably 3 nm or more and 30 nm. Further, the aluminum oxide film, the hafnium oxide film and the hafnium aluminate film have a feature of having a higher dielectric constant than the silicon oxide film and the like. Since the insulating film having a high dielectric constant can be thinly formed as the metal oxide layer 114 in this way, the strength of the gate electric field applied to the semiconductor layer 108 can be increased as compared with the case where a silicon oxide film or the like is used. As a result, the drive voltage can be lowered and the power consumption can be reduced.

Further, the metal oxide layer 114 is preferably formed by using a sputtering apparatus. For example, when the aluminum oxide film is formed by using a sputtering apparatus, oxygen can be suitably added to the semiconductor layer 108 by forming the film in an atmosphere containing oxygen gas. Further, when an aluminum oxide film is formed by using a sputtering device, the film density can be increased, which is preferable.

When a conductive material is used as the metal oxide layer 114, an oxide conductive material such as indium oxide or indium tin oxide can be used.

Further, it is preferable that the metal oxide layer 114 does not easily diffuse water or hydrogen. As a result, even when the conductive layer 142 uses a material that easily diffuses water or hydrogen, it is possible to prevent water or hydrogen from diffusing into the insulating layer 140 or the semiconductor layer 108. In particular, an aluminum oxide film and a hafnium oxide film are preferable because they have a high barrier property against water and hydrogen.

In order to supply excess oxygen into the semiconductor layer 108, excess oxygen may be supplied to the insulating layer 104 formed below the semiconductor layer 108. In this case, the excess oxygen contained in the insulating layer 104 can also be supplied to the region 108n. If excess oxygen is supplied into the region 108n, the resistance in the region 108n becomes high, which is not preferable. On the other hand, by configuring the insulating layer 140 formed above the semiconductor layer 108 to have excess oxygen, it is possible to selectively supply excess oxygen only to the region superimposing on the conductive layer 142.

Here, the oxygen deficiency that can be formed in the semiconductor layer 108 will be described.

The oxygen deficiency formed in the semiconductor layer 108 affects the transistor characteristics, which is a problem. For example, when an oxygen deficiency is formed in the semiconductor layer 108, hydrogen is bonded to the oxygen deficiency and can serve as a carrier supply source. When a carrier supply source is generated in the semiconductor layer 108, fluctuations in the electrical characteristics of the transistor 100A, typically a shift in the threshold voltage, occur. Therefore, in the semiconductor layer 108, the smaller the oxygen deficiency, the more preferable.

Therefore, in one aspect of the present invention, the insulating film in the vicinity of the semiconductor layer 108, specifically, the insulating layer 140 formed above the semiconductor layer 108 is configured to contain excess oxygen. By moving oxygen or excess oxygen from the insulating layer 140 to the semiconductor layer 108, it is possible to reduce oxygen deficiency in the semiconductor layer 108.

The insulating layer 104 located below the semiconductor layer 108 may contain excess oxygen. At this time, by moving excess oxygen from the insulating layer 104 to the semiconductor layer 108, it is possible to further reduce the oxygen deficiency of the semiconductor layer 108.

Further, the insulating layer 118 located above the semiconductor layer 108 may contain excess oxygen. Since the insulating layer 118 and the insulating layer 104 have a contact area, excess oxygen can be transferred from the insulating layer 118 through the insulating layer 104 to the semiconductor layer 108, so that the oxygen deficiency of the semiconductor layer 108 is further reduced. It becomes possible.

Here, impurities such as hydrogen and water mixed in the semiconductor layer 108 affect the transistor characteristics, which causes a problem. Therefore, in the semiconductor layer 108, it is preferable that there are few impurities such as hydrogen and water.

As the semiconductor layer 108, it is preferable to use a metal oxide film having a low impurity concentration and a low defect level density, because a transistor having excellent electrical characteristics can be manufactured. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is referred to as high-purity intrinsic or substantially high-purity intrinsic. A metal oxide film having high-purity intrinsic or substantially high-purity intrinsic has a small number of carrier sources, so that the carrier density can be lowered. Therefore, the transistor in which the channel region is formed in the metal oxide film is unlikely to have an electrical characteristic (also referred to as normal on) in which the threshold voltage is negative. In addition, a metal oxide film having high-purity intrinsicity or substantially high-purity intrinsicity has a low defect level density, so that the trap level density may also be low. The metal oxide film is a highly purified intrinsic or substantially highly purified intrinsic, the off current is extremely small, even the channel length a channel width of 1 × 10 ⁶ μm is an element of 10 [mu] m, a source electrode and a drain When the voltage between the electrodes (drain voltage) is in the range of 1 V to 10 V, it is possible to obtain the characteristic that ^{the off-current is below the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 -13 A or less.}

The transistor 100A can be used as a display device. For example, it can be used for a pixel circuit, a gate driver circuit, and a source driver circuit of a display device.

<Semiconductor device configuration example 8>
8 (A), 8 (B), and 8 (C) are a top view and a cross-sectional view of the transistor 100B and the periphery of the transistor 100B according to one aspect of the present invention.

FIG. 8A is a top view of the semiconductor device having the transistor 100A. 8 (B) and 8 (C) are cross-sectional views of the semiconductor device. Here, FIG. 8B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 8A, and is also a cross-sectional view of the transistor 100B in the channel length direction. Further, FIG. 8C is a cross-sectional view of the portion shown by the alternate long and short dash line of B1-B2 in FIG. 8A, and is also a cross-sectional view of the transistor 100B in the channel width direction. In the top view of FIG. 8A, some elements are omitted for the sake of clarity.

[Transistor 100B]
The transistor 100B is in contact with the insulating layer 104 on the substrate 102, the semiconductor layer 108 on the insulating layer 104, the insulating layer 140 on the semiconductor layer 108, the conductive layer 142 on the insulating layer 140, and the side surface of the conductive layer 142. It has an insulating layer 115 arranged in a row. The portion of the semiconductor layer 108 that overlaps with the conductive layer 142 functions as a channel forming region.

For the semiconductor layer 108, the same material as the above-mentioned oxide 230 can be used.

Further, as shown in FIGS. 8A, 8B, and 8C, the semiconductor device having the transistor 100B has an insulating layer 118 on the transistor 100B. Further, it may have a conductive layer 121a and a conductive layer 121b that are electrically connected to the region 108n, respectively, via an opening 141a or an opening 141b provided in the insulating layer 118.

Similar to the above-mentioned transistor 100A, the transistor 100B has a region in which the conductive layer 142 and the insulating layer 140 do not overlap. By having the region, the leakage current path between the conductive layer 142 and the semiconductor layer 108 can be blocked.

Further, the region 108n is a region in which a metal atom such as indium or an impurity is added to the metal oxide provided as the semiconductor layer 108 to reduce the resistance. The region 108n has at least higher conductivity than the region where the insulating layer 140 of the semiconductor layer 108 and the semiconductor layer 108 are in contact with each other. In order to add impurities to the region 108n, for example, plasma treatment, an ion implantation method in which ionized raw material gas is added by mass separation, and an ion implantation method in which ionized raw material gas is added without mass separation. , A metal element such as indium and a dopant which is at least one of impurities may be added by using a plasma implantation ion implantation method or the like.

That is, by increasing the content of metal atoms such as indium in the semiconductor layer 108 in the region 108n, the electron mobility can be increased and the resistance can be reduced. For other configurations and effects, the description of the configuration example 7 of the semiconductor device having the transistor 100A shown in FIG. 7 is taken into consideration.

<Semiconductor device configuration example 9>
FIG. 9 shows an example of a semiconductor device having a capacitive element in addition to the transistor.

FIG. 9A is a cross-sectional view of a semiconductor device having the transistor 200 and the capacitive element 100, and is also a cross-sectional view of the transistor 200 in the channel length direction.

[Capacitive element 100]
For the configuration of the transistor 200, the description of the configuration example 1 of the semiconductor device shown in FIG. 1 is taken into consideration. The capacitive element 100 shown in FIG. 9 (A) has an oxide 230 (oxide 230a, oxide 230b, and oxide 230c1) arranged on the insulator 224 and an insulator arranged on the insulator 230. A body 250a, a conductor 260_1a (conductor 260_1a and a conductor 260_1b) arranged on the insulator 250a, an insulator 270a arranged on the insulator 260_1, an insulator 271a, and a conductor 260_1. It has an insulator 272a arranged in contact with the side surface, and at least an insulator 274 arranged in contact with the upper surface of the oxide 230, the side surface of the insulator 272a, and the upper surface of the insulator 271a.

The oxide 230 has a function as one electrode of the capacitive element 100, and the conductor 260_1 has a function as the other electrode of the capacitive element 100. Further, the insulator 250a has a function as a dielectric of the capacitance element 100.

The capacitive element 100 has a region in which the conductor 260_1 and the insulator 250a do not overlap. The region is formed in the same manner as the region 250W of the transistor 200 shown in FIG. 11 (A). Therefore, by having the region, it is possible to reduce the leakage current between the oxide 230 having a function as one electrode of the capacitive element 100 and the conductor 260_1 having a function as the other electrode. .. That is, the charge retention characteristic of the capacitive element 100 can be improved.

Further, since the capacitive element 100 is formed on the same layer as the transistor 200 at the same time, it can be manufactured without increasing the number of manufacturing steps of the semiconductor device.

FIG. 9B is a cross-sectional view of a semiconductor device having a transistor 100A and a capacitive element 200A, and is also a cross-sectional view of the transistor 100A in the channel length direction.

[Capacitive element 200A]
For the configuration of the transistor 100A, the description of the configuration example 7 of the semiconductor device shown in FIG. 7 is taken into consideration. The capacitive element 200A shown in FIG. 9B has an insulating layer 104 on the substrate 102, a semiconductor layer 108 on the insulating layer 104, an insulating layer 140a on the semiconductor layer 108, and a metal oxide layer on the insulating layer 140a. 114a, the conductive layer 142a on the metal oxide layer 114a, the insulating layer 115a arranged in contact with the side surface of the metal oxide layer 114a and the side surface of the conductive layer 142a, and at least the upper surface of the semiconductor layer 108 and the insulating layer 115a. It has an insulating layer 116 arranged in contact with the side surface and the upper surface of the conductive layer 142a.

The semiconductor layer 108 including the region 108n has a function as one electrode of the capacitive element 200A, and the metal oxide layer 114a and the conductive layer 142a have a function as the other electrode of the capacitive element 200A. Further, the insulating layer 140a has a function as a dielectric of the capacitance element 200A.

The capacitive element 200A has a region in which the conductive layer 142a and the insulating layer 140a do not overlap. The region has the same configuration as the region in which the conductive layer 142 of the transistor 100A and the insulating layer 140 shown in FIG. 7 do not overlap. Therefore, by having the region, the semiconductor layer 108 including the region 108n having the function as one electrode of the capacitance element 200A, and the metal oxide layer 114a and the conductive layer 142a having the function as the other electrode The leakage current between them can be reduced. That is, the charge retention characteristic of the capacitive element 200A can be improved.

Further, since the capacitive element 200A is formed on the same layer as the transistor 100A at the same time, it can be manufactured without increasing the number of manufacturing steps of the semiconductor device.

<Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used in semiconductor devices will be described.

<< Board >>
As the substrate on which the above-mentioned transistor is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like. Further, examples of the semiconductor substrate include a single semiconductor substrate such as silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided in an insulator substrate, a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like. Alternatively, those on which an element is provided may be used. Elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.

Further, a flexible substrate may be used as the substrate. As a method of providing the transistor on the flexible substrate, there is also a method of forming the transistor on the non-flexible substrate, peeling off the transistor, and transposing it to the substrate which is a flexible substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Alternatively, it may have a property of not returning to the original shape. The substrate has, for example, a region having a thickness of 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of the semiconductor device having a transistor can be reduced. Further, by making the substrate thinner, it may have elasticity even when glass or the like is used, or it may have a property of returning to the original shape when bending or pulling is stopped. Therefore, it is possible to alleviate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, it is possible to provide a durable semiconductor device.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. Further, as the substrate, a sheet, a film, a foil or the like in which fibers are woven may be used. As for the substrate which is a flexible substrate, the lower the coefficient of linear expansion, the more the deformation due to the environment is suppressed, which is preferable. As the substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less may be used. .. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic and the like. In particular, aramid has a low coefficient of linear expansion and is therefore suitable as a substrate that is a flexible substrate.

<< Insulator >>
Examples of the insulator include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, metal nitride oxides and the like having insulating properties.

Here, as the insulator that functions as a gate insulator, by using a high-k material having a high relative permittivity for the insulator that functions as a gate insulator, it is possible to miniaturize and highly integrate transistors. Become. On the other hand, for the insulator that functions as an interlayer film, a material having a low relative permittivity is used as the interlayer film, so that the parasitic capacitance generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides or nitrides having silicon and hafnium.

Examples of insulators having a low specific dielectric constant include silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and empty. There are silicon oxide or resin with pores.

In particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure that is thermally stable and has a low relative permittivity can be obtained. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like. Further, for example, silicon oxide and silicon oxide nitride can be combined with an insulator having a high relative permittivity to form a laminated structure that is thermally stable and has a high relative permittivity.

Further, the electric characteristics of the transistor can be stabilized by surrounding the transistor using the oxide semiconductor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.

Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, tantalum, and zirconium. Insulators containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.

For example, as the insulator 210, insulator 214, insulator 222, insulator layer 115, insulator layer 115a, insulator 270, insulator 270a, insulator 272, insulator 272a and insulator 273A, impurities such as hydrogen and oxygen are used. An insulator having a function of suppressing permeation may be used. The insulator 210, insulator 214, insulator 222, insulator layer 115, insulator layer 115a, insulator 270, insulator 270a, insulator 272, insulator 272a and insulator 273A are, for example, aluminum oxide and hafnium oxide. , Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, metal oxides such as neodymium oxide or tantalum oxide, silicon nitride or silicon nitride may be used.

Examples of the insulating layer 104, the insulating layer 140, the insulating layer 140a, the insulator 220, the insulator 224, the insulator 250, the insulator 250a, the insulating layer 116 and the insulator 274 include boron, carbon, nitrogen and oxygen. Insulators containing fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lantern, neodymium, hafnium or tantalum may be used in a single layer or in layers. Specifically, it is preferable to have silicon oxide, silicon oxide nitride, or silicon nitride.

For example, in an insulating layer 140, an insulating layer 140a, an insulator 220, an insulator 224, an insulator 250 and an insulator 250a that function as a gate insulator, aluminum oxide, gallium oxide or hafnium oxide is combined with oxide 230 or semiconductor layer 108. By adopting the structure in contact with each other, it is possible to prevent silicon contained in silicon oxide or silicon oxide nitride from being mixed into the oxide 230 or the semiconductor layer 108. On the other hand, in the insulating layer 140, the insulating layer 140a, the insulator 220, the insulator 224, the insulator 250 and the insulator 250a, the structure is such that silicon oxide or silicon oxide is in contact with the oxide 230 or the semiconductor layer 108 to oxidize. A trap center may be formed at the interface between aluminum, gallium oxide or hafnium oxide and silicon oxide or silicon nitride. The trap center may be able to fluctuate the threshold voltage of the transistor in the positive direction by capturing electrons.

The insulating layer 118, the insulator 212, the insulator 216, the insulator 271, the insulator 271a and the insulator 280 preferably have an insulator having a low relative permittivity. For example, the insulating layer 118, the insulator 212, the insulator 216, the insulator 271, the insulator 271a and the insulator 280 include silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, and carbon. It is preferable to have silicon oxide to which the above is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, or a resin. Alternatively, the insulating layer 118, the insulator 212, the insulator 216, the insulator 271, the insulator 271a and the insulator 280 are made of silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, and carbon. It is preferable to have a laminated structure of added silicon oxide, added silicon oxide or silicon oxide having pores, and a resin. Since silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

<< Conductor >>
Metals selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more elements can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and SiO such as nickel silicide may be used.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

When an oxide is used in the channel forming region of the transistor, the conductor functioning as the gate electrode shall have a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Is preferable. In this case, a conductive material containing oxygen may be provided on the channel forming region side. By providing the conductive material containing oxygen on the channel forming region side, oxygen separated from the conductive material can be easily supplied to the channel forming region.

In particular, as the conductor that functions as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Further, the above-mentioned conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

The conductive layer 121a, the conductive layer 121b, the conductor 260a, the conductor 260b, the conductor 260_1a, the conductor 260_1b, the conductor 203a, the conductor 203b, the conductor 205a, and the conductor 205b include aluminum, chromium, copper, and silver. , Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. .. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and SiO such as nickel silicide may be used.

<< Metal Oxide >>
As the semiconductor layer 108 and the oxide 230, it is preferable to use a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the semiconductor layer and the oxide 230 according to the present invention will be described.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.

Here, consider the case where the oxide semiconductor is an In-M-Zn oxide having indium, the element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or the like. Examples of elements applicable to the other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases.

[Composition of metal oxide]
Hereinafter, the configuration of the CAC (Cloud-Linked Composite) -OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

In addition, in this specification and the like, it may be described as CAAC (c-axis aligned composite) and CAC (Cloud-Aligned Composite). CAAC represents an example of a crystal structure, and CAC represents an example of a function or a composition of a material.

The CAC-OS or CAC-metal oxide has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. When CAC-OS or CAC-metal oxide is used for the active layer of the transistor, the conductive function is the function of flowing electrons (or holes) that serve as carriers, and the insulating function is the function of flowing electrons (or holes) that serve as carriers. It is a function that does not shed. By making the conductive function and the insulating function act in a complementary manner, a switching function (on / off function) can be imparted to the CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carriers flow, the carriers mainly flow in the components having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[Structure of metal oxide]
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (c-axis aligned semiconductor semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), and pseudo-amorphous oxide semiconductor (a-lique). OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a region where the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned in the region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, a clear grain boundary (also referred to as grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. It is thought that this is the reason.

Further, CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as the (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can be expressed as the (In, M) layer.

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since a clear crystal grain boundary cannot be confirmed, it can be said that a decrease in electron mobility due to the crystal grain boundary is unlikely to occur. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor of one aspect of the present invention may have two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[Transistor with oxide semiconductor]
Subsequently, a case where the oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor as a transistor, a transistor having high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.

Further, it is preferable to use an oxide semiconductor having a low carrier density for the transistor. When the carrier density of the oxide semiconductor film is lowered, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density. In the present specification and the like, a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, oxide semiconductors have a carrier density of ^{less than 8 × 10 11} / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ^-9 /. It ^{may be cm 3} or more.

Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.

In addition, the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

[impurities]
Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

Further, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Therefore, in the oxide semiconductor, nitrogen is preferably reduced as much as possible, for example, the nitrogen concentration in the oxide semiconductor is ^{less than 5 × 10 19} atoms / cm ^{3 in} SIMS, preferably 5 × 10 ¹⁸ Atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency. When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS ^{is less than 1 × 10 20} atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably 5 × 10 ¹⁸ atoms / cm. ^{Less than 3} , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced in the channel region of the transistor, stable electrical characteristics can be imparted.

<Method of manufacturing semiconductor devices>
Next, the manufacturing method of the semiconductor device having the transistor 200 according to the present invention will be described with reference to FIGS. 1 and 12 to 19. Further, in FIGS. 1 and 12 to 19, (A) in each figure shows a top view. Further, (B) in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in (A). Further, (C) of each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A3-A4 in (A).

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The film of the insulator 210 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or a pulsed laser deposition (PLD) method. It can be done by using.

The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (Metal CVD) method and an organometallic CVD (MOCVD: Metalorganic CVD) method depending on the raw material gas used.

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage during film formation does not occur, so that a film having few defects can be obtained.

The ALD method is also a film forming method capable of reducing plasma damage to the object to be processed. Further, the ALD method also does not cause plasma damage during film formation, so that a film having few defects can be obtained.

The CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage. In particular, the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas. Further, for example, in the CVD method and the ALD method, a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, it is possible to shorten the time required for film formation by the amount of time required for transportation and pressure adjustment as compared with the case of forming a film using a plurality of film forming chambers. can. Therefore, it may be possible to increase the productivity of the semiconductor device.

In the present embodiment, aluminum oxide is formed as the insulator 210 by a sputtering method. Further, the insulator 210 may have a multi-layer structure. For example, the structure may be such that aluminum oxide is formed by a sputtering method and aluminum oxide is formed on the aluminum oxide by an ALD method. Alternatively, the structure may be such that aluminum oxide is formed by the ALD method and aluminum oxide is formed on the aluminum oxide by the sputtering method.

Next, the insulator 212 is formed on the insulator 210. The film formation of the insulator 212 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed as the insulator 212 by the CVD method.

Next, an opening is formed in the insulator 212 to reach the insulator 210. The opening also includes, for example, a groove or a slit. Further, the region where the opening is formed may be referred to as an opening. Although wet etching may be used to form the openings, it is preferable to use dry etching for microfabrication. Further, as the insulator 210, it is preferable to select an insulator that functions as an etching stopper film when the insulator 212 is etched to form a groove. For example, when a silicon oxide film is used for the insulator 212 forming the groove, it is preferable to use a silicon nitride film, an aluminum oxide film, or a hafnium oxide film for the insulator 210.

After forming the opening, a conductive film to be the conductor 203a is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The film formation of the conductor to be the conductor 203a can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the present embodiment, tantalum nitride is formed as a conductive film to be the conductor 203a by a sputtering method. By using such a metal nitride as the conductor 203a, it is possible to prevent the metal from diffusing out from the conductor 203a even if a metal such as copper which is easily diffused is used in the conductor 203b described later.

Next, a conductive film to be the conductor 203b is formed on the conductive film to be the conductor 203a. The film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, a low resistance conductive material such as copper is formed as a conductive film to be the conductor 203b.

Next, by performing the CMP treatment, the conductive film to be the conductor 203a and a part of the conductive film to be the conductor 203b are removed, and the insulator 212 is exposed. As a result, the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening. As a result, the conductor 203 including the conductor 203a and the conductor 203b having a flat upper surface can be formed (see FIG. 12). In addition, a part of the insulator 212 may be removed by the CMP treatment.

Next, the insulator 214 is formed on the conductor 203. The film formation of the insulator 214 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon nitride is formed as the insulator 214 by the CVD method. In this way, by using an insulator such as silicon nitride that does not easily allow copper to permeate as the insulator 214, even if a metal that easily diffuses such as copper is used for the conductor 203b, the metal is a layer above the insulator 214. It can be prevented from spreading to.

Next, the insulator 216 is formed on the insulator 214. The film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed as the insulator 216 by the CVD method.

Next, an opening is formed in the insulator 214 and the insulator 216 to reach the conductor 203. Although wet etching may be used to form the openings, it is preferable to use dry etching for microfabrication.

After forming the opening, a conductive film to be a conductor 205a is formed. The conductive film to be the conductor 205a preferably contains a conductive material having a function of suppressing the permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film with tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum-tungsten alloy. The film formation of the conductive film to be the conductor 205a can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the present embodiment, tantalum nitride is formed as a conductive film to be the conductor 205a by a sputtering method.

Next, a conductive film to be the conductor 205b is formed on the conductive film to be the conductor 205a. The film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In the present embodiment, titanium nitride is formed by a CVD method as a conductive film to be a conductor 205b, and tungsten is formed on the titanium nitride by a CVD method.

Next, by performing the CMP treatment, the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b are removed, and the insulator 216 is exposed. As a result, the conductor 205a and the conductive film to be the conductor 205b remain only in the opening. As a result, the conductor 205 including the conductor 205a and the conductor 205b having a flat upper surface can be formed (see FIG. 12). In addition, a part of the insulator 216 may be removed by the CMP treatment.

Next, the insulator 220 is formed on the insulator 216 and the conductor 205. The film of the insulator 220 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the insulator 222 is formed on the insulator 220. The film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In particular, it is preferable to form hafnium oxide as the insulator 222 by the ALD method. Hafnium oxide formed by the ALD method has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 do not diffuse to the inside of the transistor 200 and are contained in the oxide 230. The formation of oxygen deficiency can be suppressed.

Next, an insulating film 224A is formed on the insulator 222. The insulating film 224A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 12).

Subsequently, it is preferable to perform heat treatment. The heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower. The first heat treatment is carried out in an atmosphere of nitrogen or an inert gas, or an atmosphere containing 10 ppm or more and 1% or more or 10% or more of an oxidizing gas. The first heat treatment may be performed in a reduced pressure state. Alternatively, in the first heat treatment, the heat treatment is performed in an atmosphere of nitrogen or an inert gas, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.

By the above heat treatment, impurities such as hydrogen and water contained in the insulating film 224A can be removed.

Alternatively, as the heat treatment, plasma treatment containing oxygen may be performed in a reduced pressure state. For plasma treatment containing oxygen, for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulating film 224A by applying RF to the substrate side. Alternatively, the plasma treatment containing an inert gas may be performed using this device, and then the plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. In some cases, the first heat treatment may not be performed.

Further, the heat treatment can be performed after the film formation of the insulator 220 and after the film formation of the insulator 222, respectively. Although the above-mentioned heat treatment conditions can be used for the heat treatment, it is preferable that the heat treatment after the film formation of the insulator 220 is performed in an atmosphere containing nitrogen.

In the present embodiment, as the heat treatment, the insulating film 224A is formed and then treated in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.

Next, an oxide film 230A to be an oxide 230a and an oxide film 230B to be an oxide 230b are formed on the insulating film 224A in this order (see FIG. 13). It is preferable that the oxide film is continuously formed without being exposed to the atmospheric environment. By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.

The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film formed can be increased. Further, when the above-mentioned oxide film is formed by a sputtering method, the above-mentioned In—M—Zn oxide target can be used.

In particular, when the oxide film 230A is formed, a part of oxygen contained in the sputtering gas may be supplied to the insulating film 224A. The proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

Further, when the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. It is formed. Transistors using oxygen-deficient oxide semiconductors can obtain relatively high field-effect mobility.

In the present embodiment, the oxide film 230A is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic number ratio]. Further, as the oxide film 230B, a film is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]. Each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film forming conditions and the atomic number ratio.

Next, heat treatment may be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. By heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, after the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, the treatment is continuously carried out in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.

Next, the insulating film 224A, the oxide film 230A, and the oxide film 230B are processed into an island shape to form the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 14). In this step, for example, the insulator 222 can be used as the etching stopper film.

In the above step, the insulating film 224A does not necessarily have to be processed into an island shape. Half etching may be performed on the insulating film 224A. By half-etching the insulating film 224A, the insulator 224 remains under the oxide 230c formed in a later step. The insulating film 224A can be processed into an island shape when the insulating film 272A, which is a later step, is processed.

Here, the oxide 230 is formed so that at least a part thereof overlaps with the conductor 205. Further, the side surface of the oxide 230 is preferably substantially perpendicular to the insulator 222. Since the side surface of the oxide 230 is substantially perpendicular to the insulator 222, it is possible to reduce the area and increase the density when a plurality of transistors 200 are provided. The angle formed by the side surface of the oxide 230 and the upper surface of the insulator 222 may be an acute angle. In that case, the larger the angle formed by the side surface of the oxide 230 and the upper surface of the insulator 222, the more preferable.

Further, a curved surface is provided between the side surface of the oxide 230 and the upper surface of the oxide 230. That is, it is preferable that the end portion of the side surface and the end portion of the upper surface are curved (hereinafter, also referred to as a round shape). The curved surface preferably has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the oxide 230b, for example.

By not having a corner at the end, the coating property of the film in the subsequent film forming step is improved.

The oxide film may be processed by using a lithography method. Further, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication.

In the lithography method, first, the resist is exposed through a mask. Next, the exposed region is removed or left with a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used. When using an electron beam or an ion beam, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.

Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film to be a hard mask material is formed on the oxide film 230B, a resist mask is formed on the insulating film or a conductive film, and the hard mask material is etched to form a hard mask having a desired shape. can do. The etching of the oxide film 230A and the oxide film 230B may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the oxide film. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.

As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate type electrodes can be used. The capacitive coupling type plasma etching apparatus having the parallel plate type electrode may be configured to apply a high frequency power source to one electrode of the parallel plate type electrode. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate type electrodes. Alternatively, a high frequency power supply having the same frequency may be applied to each of the parallel plate type electrodes. Alternatively, a high frequency power supply having a different frequency may be applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

Further, by performing the above-mentioned dry etching or the like, impurities caused by the etching gas or the like may adhere to or diffuse to the surface or the inside of the oxide 230a and the oxide 230b. Impurities include, for example, fluorine or chlorine.

Cleaning is performed to remove the above impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.

As the wet cleaning, the cleaning treatment may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning with pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning is performed using pure water or carbonated water.

Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-mentioned heat treatment conditions can be used. In the present embodiment, after the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, the treatment is continuously carried out in an oxygen atmosphere at a temperature of 400 ° C. for 1 hour.

Next, on the insulator 224 and the oxide 230b, an oxide film 230C, an insulating film 250A, a conductive film 260A, a conductive film 260B, an insulating film 270A, and an insulating film 271A to be the oxide 230c are formed in this order (FIG. See 15.).

The oxide film 230C can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230C is formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film formed can be increased. Further, when the above-mentioned oxide film is formed by a sputtering method, the above-mentioned In—M—Zn oxide target can be used.

In particular, when the oxide film 230C is formed, a part of oxygen contained in the sputtering gas may be supplied to the oxide 230b and the oxide 230a. The proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

In the present embodiment, the oxide film 230C is formed by a sputtering method using a target with In: Ga: Zn = 1: 3: 4 [atomic number ratio].

Here, the oxide film 230C may be processed by a lithography method to form an oxide 230c. Here, by forming the oxide 230c, the shape of the oxide 230c can be made arbitrary.

The insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film 250A can be a multilayer film. For example, silicon oxide may be formed by a CVD method, and then aluminum oxide may be formed by a sputtering method. Oxygen can be added to silicon oxide by forming a film using a sputtering method in an atmosphere containing oxygen.

Further, heat treatment may be performed here. For the heat treatment, the above-mentioned heat treatment conditions can be used. By the heat treatment, the water concentration and the hydrogen concentration of the insulating film 250A can be reduced. In the present embodiment, the heat treatment here is not performed.

The conductive film 260A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, for example, the oxide semiconductor that can be used as the oxide 230 becomes a conductive oxide by subjecting it to a resistance reduction treatment. Therefore, an oxide that can be used as the oxide 230 may be formed as the conductive film 260A, and the resistance of the oxide may be reduced in a later step. Oxygen can be added to the insulator 250 by forming an oxide that can be used as the oxide 230 on the conductive film 260A by a sputtering method in an atmosphere containing oxygen. By adding oxygen to the insulator 250, the added oxygen can supply oxygen to the oxide 230 via the insulator 250.

The conductive film 260B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, when an oxide semiconductor that can be used as the oxide 230 is used for the conductive film 260A, the electric resistance value of the conductive film 260A is lowered to form a conductor by forming a film of the conductive film 260B by a sputtering method. be able to. This can be called an OC (Oxide Conductor) electrode. A conductor may be further formed on the conductor on the OC electrode by a sputtering method or the like.

Subsequently, heat treatment can be performed. For the heat treatment, the above-mentioned heat treatment conditions can be used. In some cases, the heat treatment may not be performed. In the present embodiment, the heat treatment here is not performed.

The insulating film 270A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the film thickness of the insulating film 270A is preferably thicker than the film thickness of the insulating film 272A formed in a later step. As a result, when the insulator 272 is formed in a later step, the insulator 270 can be easily left on the conductor 260.

The insulating film 271A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the insulating film 271A is etched to form the insulator 271. Subsequently, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched using the insulator 271 as an etching mask to form the conductor 260 (conductor 260a and the conductor 260b) and the insulator 270. (See FIG. 16). The conductor 260a, the conductor 260b, the insulator 270, and the insulator 271 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.

Further, it is preferable that the side surface of the conductor 260a, the side surface of the conductor 260b, the side surface of the insulator 270 and the side surface of the insulator 271 are substantially in the same plane.

Further, it is preferable that the same surface shared by the side surface of the conductor 260a, the side surface of the conductor 260b, the side surface of the insulator 270 and the side surface of the insulator 271 is substantially perpendicular to the substrate. That is, in the cross-sectional shape, the conductor 260a, the conductor 260b, the insulator 270, and the insulator 271 are preferably such that the angle with respect to the upper surface of the oxide 230 is closer to 90 degrees. The cross-sectional shape may be such that the angle formed by the side surfaces of the conductor 260a, the conductor 260b, the insulator 270 and the insulator 270 and the upper surface of the oxide 230 is an acute angle. In that case, the angle formed by the side surfaces of the conductor 260a, the conductor 260b, the insulator 270 and the insulator 271 and the upper surface of the oxide 230 is preferably close to 90 degrees.

Further, the etching may etch the upper part of the region of the insulating film 250A that does not overlap with the conductor 260. In this case, the film thickness of the region of the insulating film 250A that overlaps with the conductor 260 may be thicker than the film thickness of the region that does not overlap with the conductor 260.

Next, the insulating film 272A is formed by covering the insulating film 250A, the conductor 260, the insulator 270, and the insulator 271. As the insulating film 272A, a film can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The ALD method may be used to form the insulating film 272A. By using the ALD method, an insulating film 272A having better coverage can be formed on the side surfaces of the insulating film 250A, the conductor 260, and the insulator 270 and the insulator 271 (see FIG. 17). ).

Here, a metal atom such as indium or an impurity may be added to the oxide 230 via the insulating film 272A to form a low resistance region. To add impurities, for example, plasma treatment, ion implantation method in which ionized raw material gas is added by mass separation, ion doping method in which ionized raw material gas is added without mass separation, plasma imaging ion implantation. A metal element such as indium and a dopant which is at least one of impurities may be added by a method or the like. Alternatively, a rare gas such as argon or helium may be added. Here, since the conductor 260, the insulator 271 and the insulator 270 are located in the region where the oxide 230 and the conductor 260 overlap, the dopant is not injected. On the other hand, the dopant is injected into a region where the oxide 230 and the conductor 260 do not overlap. That is, it is possible to form a region in which the oxide 230 has a low resistance in a self-aligned manner.

Next, the insulating film 272A is anisotropically etched to form the insulator 272 in contact with the side surfaces of the conductor 260, the insulator 270, and the insulator 271. Further, the insulating film 250A and the oxide film 230C are processed to form the insulator 250 and the oxide 230c. As the anisotropic etching treatment, it is preferable to perform a dry etching treatment. Further, as a result, the insulating film 272A formed on a surface substantially parallel to the substrate surface can be removed, and the insulator 272 can be formed in a self-aligned manner. Further, it is possible to form a region 250W in which the conductor 260 and the insulator 250 shown in FIG. 11A do not overlap (see FIG. 18).

Next, the insulator 224, the oxide 230, the insulator 271, and the insulator 272 are covered to form an insulating film to be the insulator 274 to form the insulator 274. The film formation of the insulating film to be the insulator 274 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 19).

The film formation of the insulating film to be the insulator 274 is preferably performed in an atmosphere containing at least one of nitrogen and hydrogen. By forming a film in such an atmosphere, an oxygen deficiency is formed mainly in a region that does not overlap with the insulator 250 of the oxide 230b, and the oxygen deficiency is combined with an impurity element such as nitrogen or hydrogen to form a carrier. The density can be increased. In this way, the regions 231a and 231b with reduced resistance can be formed. As the insulating film to be the insulator 274, for example, silicon oxide, silicon oxide nitride, silicon nitride or silicon nitride can be used by using the CVD method. In the present embodiment, silicon nitride is used as the insulating film to be the insulator 274.

As described above, in the method for manufacturing the semiconductor device shown in the present embodiment, even in a transistor whose channel length is miniaturized to about 10 nm to 30 nm, the source region and the drain region are formed by forming an insulating film to be an insulator 274. It can be formed in a self-consistent manner. Therefore, even a miniaturized or highly integrated semiconductor device can be manufactured with a high yield.

Here, by covering the upper surface and the side surface of the conductor 260 with the insulator 272 and the insulator 271, it is possible to prevent impurity elements such as nitrogen and hydrogen from being mixed into the conductor 260.

Further, plasma treatment may be performed before forming the insulating film to be the insulator 274. The plasma treatment may be performed in an atmosphere containing, for example, the above-mentioned element forming an oxygen deficiency or an element binding to the oxygen deficiency.

The region 231a and the region 231b may be formed on the oxide 230 only by plasma treatment.

Next, an insulating film to be the insulator 280 is formed on the insulator 274. The film formation of the insulating film to be the insulator 280 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, the spin coating method, dip method, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife method, roll coater method, curtain coater method, or the like can be used. In this embodiment, silicon oxide nitride is used as the insulating film.

Next, a part of the insulating film to be the insulator 280 is removed to form the insulator 280. The insulator 280 is preferably formed so that the upper surface has a flat surface. For example, the upper surface of the insulator 280 may have a flat surface immediately after being formed as an insulating film to be the insulator 280. Alternatively, for example, the insulator 280 may have flatness by removing the insulator or the like from the upper surface so as to be parallel to the reference surface such as the back surface of the substrate after the film formation. Such a process is called a flattening process. Examples of the flattening treatment include a CMP treatment and a dry etching treatment. In this embodiment, a CMP process is used as the flattening process. However, the upper surface of the insulator 280 does not necessarily have to be flat.

From the above, the semiconductor device having the transistor 200 can be manufactured (see FIG. 1).

According to one aspect of the present invention, it is possible to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention can provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention can provide a semiconductor device having a small off-current. Alternatively, one aspect of the present invention can provide a transistor having a large on-current. Alternatively, one aspect of the present invention can provide a highly reliable semiconductor device. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a highly productive semiconductor device.

As described above, the configurations and methods shown in the present embodiment can be used in appropriate combinations with the configurations and methods shown in other embodiments.

(Embodiment 2)
In this embodiment, one embodiment of the semiconductor device will be described with reference to FIGS. 21 to 25.

<Storage device 1>
The storage device shown in FIG. 21 includes a transistor 300, a transistor 200, and a capacitive element 100. FIG. 21 is a cross-sectional view of the transistor 200 and the transistor 300 in the channel length direction. FIG. 22 shows a cross-sectional view of the transistor 300 in the vicinity of the transistor 300 in the channel width direction.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

In the storage device shown in FIG. 21, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100. ..

The storage device shown in FIG. 21 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as shown below.

Writing and retaining information will be described. First, the potential of the wiring 1004 is set to the potential at which the transistor 200 is in the conductive state, and the transistor 200 is brought into the conductive state. As a result, the potential of the wiring 1003 is given to the gate of the transistor 300 and the node SN electrically connected to one of the electrodes of the capacitive element 100. That is, a predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that either of the charges giving two different potential levels (hereinafter referred to as Low level charge and High level charge) is given. After that, the electric charge is held (retained) in the node SN by setting the potential of the wiring 1004 to the potential at which the transistor 200 is in the non-conducting state and putting the transistor 200 in the non-conducting state.

When the off-current of the transistor 200 is small, the charge of the node SN is retained for a long period of time.

Next, reading information will be described. When a predetermined potential (constant potential) is applied to the wiring 1001 and an appropriate potential (reading potential) is applied to the wiring 1005, the wiring 1002 takes a potential corresponding to the amount of electric charge held in the node SN. This is because, assuming that the transistor 300 is an n-channel type, the apparent threshold voltage _{Vth_H} when a high level charge is given to the gate of the transistor 300 is a Low level charge given to the gate of the transistor 300. This is because it is lower than the apparent threshold voltage _{Vth_L when the voltage is present.} Here, the apparent threshold voltage means the potential of the wiring 1005 required to bring the transistor 300 into the "conducting state". _{Therefore, by setting} the potential of the wiring 1005 to the potential _{V 0} between V th_H and V _{th_L} , the electric charge given to the node SN can be discriminated. For example, in writing, when a high level charge is given to the node SN, if the potential of the wiring 1005 becomes V ₀ (> V _{th_H} ), the transistor 300 is in the “conducting state”. On the other hand, when the node FG is given a Low level charge, the transistor 300 remains in the “non-conducting state” even _{if the potential of the wiring 1005 becomes V 0} (<V _{th_L).} Therefore, by discriminating the potential of the wiring 1002, the information held in the node SN can be read out.

<Structure of storage device 1>
As shown in FIG. 21, the storage device of one aspect of the present invention includes a transistor 300, a transistor 200, and a capacitive element 100. The transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200.

The transistor 300 is provided on the substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 composed of a part of the substrate 311 and a low resistance region 314a and a low resistance region 314b that function as a source region or a drain region. Have.

Further, as shown in FIG. 22, in the transistor 300, the upper surface of the semiconductor region 313 and the side surface in the channel width direction are covered with the conductor 316 via the insulator 315. By making the transistor 300 a Fin type in this way, the on-characteristics of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.

The transistor 300 may be either a p-channel type or an n-channel type.

It is preferable to include a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like. It preferably contains crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

In the low resistance region 314a and the low resistance region 314b, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic and phosphorus, or a p-type conductivity such as boron is imparted. Contains elements that

The conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron. A material or a conductive material such as a metal oxide material can be used.

The threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

The transistor 300 shown in FIGS. 21 and 22 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 300.

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, aluminum nitride and the like can be used. Just do it.

The insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 300 or the like provided below the insulator 322. For example, the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.

Further, as the insulator 324, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse in the region where the transistor 200 is provided from the substrate 311 or the transistor 300.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 200, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

The amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 in the range of 50 ° C. to 500 ° C. in the TDS analysis, in which the amount desorbed in terms of hydrogen atoms is converted into the area of the insulator 324. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ^{2 or less.}

The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3. Further, for example, the relative permittivity of the insulator 324 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative permittivity of the insulator 326. By using a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.

Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitance element 100, a conductor 328 electrically connected to the transistor 200, a conductor 330, and the like. The conductor 328 and the conductor 330 have a function as a plug or a wiring. Further, a conductor having a function as a plug or a wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is single-layered or laminated. Can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.

A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 21, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug or a wiring. The conductor 356 can be provided by using the same materials as the conductor 328 and the conductor 330.

For example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

As the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided on the insulator 350 and the conductor 356. For example, in FIG. 21, the insulator 360, the insulator 362, and the insulator 364 are laminated in this order. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or a wiring. The conductor 366 can be provided by using the same materials as the conductor 328 and the conductor 330.

For example, as the insulator 360, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 366 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. 21, the insulator 370, the insulator 372, and the insulator 374 are laminated in this order. Further, a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or a wiring. The conductor 376 can be provided by using the same materials as the conductor 328 and the conductor 330.

For example, as the insulator 370, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 376 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. 21, the insulator 380, the insulator 382, and the insulator 384 are laminated in this order. Further, a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or wiring. The conductor 386 can be provided by using the same materials as the conductor 328 and the conductor 330.

For example, as the insulator 380, it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324. Further, the conductor 386 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 200 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described above, the storage device according to the present embodiment has been described. It is not limited to this. The number of wiring layers similar to the wiring layer containing the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer containing the conductor 356 may be five or more.

An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are laminated on the insulator 384 in this order. As any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216, it is preferable to use a substance having a barrier property against oxygen and hydrogen.

For example, for the insulator 210 and the insulator 214, for example, a film having a barrier property that prevents hydrogen and impurities from diffusing from the area where the substrate 311 or the transistor 300 is provided to the area where the transistor 200 is provided is used. Is preferable. Therefore, the same material as the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by the CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 200, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.

Further, as the film having a barrier property against hydrogen, for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 210 and the insulator 214.

In particular, aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and water that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 200 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 200. Therefore, it is suitable for use as a protective film for the transistor 200.

Further, for example, the same material as that of the insulator 320 can be used for the insulator 212 and the insulator 216. Further, by using a material having a relatively low dielectric constant as an interlayer film for the insulating film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. The conductor 218 has a function as a plug or wiring for electrically connecting to the capacitance element 100 or the transistor 300. The conductor 218 can be provided by using the same material as the conductor 328 and the conductor 330.

In particular, the conductor 210 and the conductor 218 in the region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 200 can be completely separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. ..

A transistor 200 is provided above the insulator 216. As the structure of the transistor 200, the transistor included in the semiconductor device described in the previous embodiment may be used. Further, the transistor 200 shown in FIG. 21 is an example, and the transistor 200 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

An insulator 280 is provided above the transistor 200.

An insulator 286 is provided on the insulator 280. As the insulator 286, the same material as the insulator 320 can be used. Further, by using a material having a relatively low dielectric constant as an interlayer film for the insulating film, it is possible to reduce the parasitic capacitance generated between the wirings. For example, as the insulator 286, a silicon oxide film, a silicon nitride film, or the like can be used.

Further, a conductor 246, a conductor 248 and the like are embedded in the insulator 220, the insulator 222, the insulator 224, the insulator 274 and the insulator 280.

The conductor 246 and the conductor 248 function as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided by using the same materials as the conductor 328 and the conductor 330.

Subsequently, a capacitance element 100 is provided above the transistor 200. The capacitive element 100 has a conductor 110, a conductor 120, and an insulator 130.

Further, the conductor 112 may be provided on the conductor 246 and the conductor 248. The conductor 112 functions as a plug or wiring that electrically connects to the capacitive element 100, the transistor 200, or the transistor 300. The conductor 110 has a function as an electrode of the capacitive element 100. The conductor 112 and the conductor 110 can be formed at the same time.

The conductor 112 and the conductor 110 are formed of a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components. (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) and the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.

In FIG. 21, the conductor 112 and the conductor 110 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.

Further, an insulator 130 is provided on the conductor 112 and the conductor 110 as a dielectric of the capacitance element 100. The insulator 130 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, hafnium nitride, and the like. It may be used and may be provided in a laminated or single layer.

For example, for the insulator 130, it is preferable to use a material having a large dielectric strength such as silicon oxide nitride. With this configuration, the capacitive element 100 has the insulator 130, so that the dielectric strength is improved and the electrostatic breakdown of the capacitive element 100 can be suppressed.

The conductor 120 is provided on the insulator 130 so as to overlap with the conductor 110. As the conductor 120, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When it is formed at the same time as another structure such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.

An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 150 can be provided by using the same material as the insulator 320. Further, the insulator 150 may function as a flattening film that covers the uneven shape below the insulator 150.

By using this structure, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a large on-current. Alternatively, it is possible to provide a transistor having an oxide semiconductor having a small off-current. Alternatively, it is possible to provide a semiconductor device with reduced power consumption.

<Storage device 2>
The semiconductor device shown in FIG. 23 is a storage device having a transistor 400, a transistor 200, and a capacitive element 100. Hereinafter, one form as a storage device will be described with reference to FIG. 23.

FIG. 23 (A) shows an example of the connection relationship between the transistor 200, the transistor 400, and the capacitive element 100 in the semiconductor device shown in the present embodiment. Further, FIG. 23 (B) shows a cross-sectional view of the semiconductor device corresponding to the wiring 1004 to the wiring 1010 shown in FIG. 23 (A).

As shown in FIG. 23, in the transistor 200, the gate is electrically connected to the wiring 1004, one of the source and the drain is electrically connected to the wiring 1002, and the other of the source and the drain is electrically connected to one of the electrodes of the capacitive element 100. Further, the other electrode of the capacitance element 100 is electrically connected to the wiring 1005. Further, the drain of the transistor 400 is electrically connected to the wiring 1010. Further, as shown in FIG. 23 (B), the second gate of the transistor 200, the source of the transistor 400, the first gate, and the second gate are the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009. It is electrically connected via.

Here, by applying a potential to the wiring 1004, it is possible to control the on state and the off state of the transistor 200. By turning on the transistor 200 and applying an electric potential to the wiring 1003, an electric charge can be supplied to the capacitive element 100 via the transistor 200. At this time, by turning off the transistor 200, the electric charge supplied to the capacitive element 100 can be retained. Further, the wiring 1005 can control the potential of the connecting portion between the transistor 200 and the capacitive element 100 by capacitive coupling by giving an arbitrary potential. For example, when a ground potential is applied to the wiring 1005, it becomes easy to retain the above electric charge. Further, by applying a negative potential to the wiring 1010, a negative potential is given to the second gate of the transistor 200 via the transistor 400, the threshold voltage of the transistor 200 is made larger than 0V, and the off-current is reduced. It can be reduced and the drain current when the first gate voltage is 0V can be made very small.

The first gate and the second gate of the transistor 400 are connected to the source by a diode, and the source of the transistor 400 and the second gate of the transistor 200 are connected to each other. The gate voltage can be controlled. When holding the negative potential of the second gate of the transistor 200, the voltage between the first gate source and the voltage between the second gate sources of the transistor 400 becomes 0V. When the first gate voltage of the transistor 400 is 0 V, the drain current is very small and the threshold voltage is larger than the transistor 200. Therefore, with this configuration, the transistor 200 does not need to supply power to the transistor 400. The negative potential of the second gate can be maintained for a long time.

Further, by holding the negative potential of the second gate of the transistor 200, the drain current when the first gate voltage of the transistor 200 is 0V can be made very small without supplying power to the transistor 200. can. That is, the electric charge can be held in the capacitive element 100 for a long time without supplying power to the transistor 200 and the transistor 400. For example, by using such a semiconductor device as a storage element, it is possible to perform storage retention for a long time without supplying power. Therefore, it is possible to provide a storage device that has a low frequency of refresh operations or does not require a refresh operation.

The connection relationship between the transistor 200, the transistor 400, and the capacitive element 100 is not limited to that shown in FIGS. 23 (A) and 23 (B). The connection relationship can be changed as appropriate according to the required circuit configuration.

<Structure of storage device 2>
FIG. 23B is a cross-sectional view of a storage device including the capacitive element 100, the transistor 200, and the transistor 400. In the storage device shown in FIG. 23, the same reference numerals are added to the above-described embodiment, the semiconductor device shown in <Structure of storage device 1>, and the structure having the same function as the structure constituting the storage device. do.

As shown in FIG. 23, the storage device of one aspect of the present invention includes a transistor 200, a transistor 400, and a capacitive element 100. The transistor 200 and the transistor 400 are provided on the same layer, and the capacitive element 100 is provided above the transistor 300 and the transistor 200.

As the transistor 200, the capacitance and the transistor of the semiconductor device and the storage device described in the previous embodiment and FIG. 21 may be used. The capacitive element 100, the transistor 300, the transistor 200, and the transistor 400 shown in FIG. 23 are examples, and the transistor is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

The transistor 400 is a transistor that is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (conductor 460a and a conductor 460b) that functions as a first gate electrode, a conductor 405 that functions as a second gate electrode (conductor 405a, and a conductor 405b), and a conductor 405b. An insulator 470 in contact with the conductor 460, an insulator 472, an insulator 220 functioning as a gate insulating layer, an insulator 222, an insulator 224, and an insulator 450, and an oxide 430c having a region where a channel is formed. And an oxide 431a and an oxide 431b that function as one of the source or drain, and an oxide 432a and an oxide 432b that function as the other of the source or drain. Further, the conductor 405 that functions as the second gate electrode is electrically connected to the conductor 403 (conductor 403a and conductor 403b) that functions as wiring.

In the transistor 400, the conductor 405 is the same layer as the conductor 205. Oxide 431a, oxide 432a, and oxide 230a are in the same layer, and oxide 431b, oxide 432b, and oxide 230b are in the same layer. Oxide 430c is the same layer as oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260. Further, the insulator 470 is the same layer as the insulator 270. Further, the insulator 471 is the same layer as the insulator 271. Further, the insulator 472 is the same layer as the insulator 272.

The oxide 430c that functions as the active layer of the transistor 400 has reduced oxygen deficiency and reduced impurities such as hydrogen and water, similarly to the oxide 230 and the like. As a result, the threshold voltage of the transistor 400 can be made larger than 0V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small.

By using this structure, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
The semiconductor device shown in FIG. 24 is a storage device having a transistor 300, a transistor 200, and a capacitive element 100. Hereinafter, one form as a storage device will be described with reference to FIG. 24.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor, and the transistor shown in the above embodiment can be used. Since the transistor shown in the above embodiment can be formed with a good yield even if it is miniaturized, the transistor 200 can be miniaturized. By using such a transistor in a storage device, the storage device can be miniaturized or highly integrated. Since the transistor shown in the above embodiment has a small off current, it is possible to retain the stored contents for a long period of time by using the transistor as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

In FIG. 24, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200. .. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100. .. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is the drain of the transistor 400. Is electrically connected to. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

The semiconductor device shown in FIG. 24 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as shown below.

Writing and retaining information will be described. First, the potential of the wiring 1004 is set to the potential at which the transistor 200 is in the conductive state, and the transistor 200 is brought into the conductive state. As a result, the potential of the wiring 1003 is given to the gate of the transistor 300 and the node FG that is electrically connected to one of the electrodes of the capacitive element 100. That is, a predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that either of the charges giving two different potential levels (hereinafter referred to as Low level charge and High level charge) is given. After that, the electric charge is held (retained) in the node SN by setting the potential of the wiring 1004 to the potential at which the transistor 200 is in the non-conducting state and putting the transistor 200 in the non-conducting state.

When the off-current of the transistor 200 is small, the charge of the node SN is retained for a long period of time.

Next, reading information will be described. When a predetermined potential (constant potential) is applied to the wiring 1001 and an appropriate potential (reading potential) is applied to the wiring 1005, the wiring 1002 takes a potential corresponding to the amount of electric charge held in the node SN. This is because, assuming that the transistor 300 is an n-channel type, the apparent threshold voltage _{Vth_H} when a high level charge is given to the gate of the transistor 300 is a Low level charge given to the gate of the transistor 300. This is because it is lower than the apparent threshold voltage _{Vth_L when the voltage is present.} Here, the apparent threshold voltage means the potential of the wiring 1005 required to bring the transistor 300 into the "conducting state". _{Therefore, by setting} the potential of the wiring 1005 to the potential _{V 0} between V th_H and V _{th_L} , the electric charge given to the node SN can be discriminated. For example, in writing, when a high level charge is given to the node SN, if the potential of the wiring 1005 becomes V ₀ (> V _{th_H} ), the transistor 300 is in the “conducting state”. On the other hand, when the node SN is given a Low level charge, the transistor 300 remains in the “non-conducting state” even _{if the potential of the wiring 1005 becomes V 0} (<V _{th_L).} Therefore, by discriminating the potential of the wiring 1002, the information held in the node SN can be read out.

<Structure of storage device 3>

FIG. 24 is a cross-sectional view of a storage device including the capacitive element 100, the transistor 200, the transistor 300, and the transistor 400. The storage device shown in FIG. 24 has the same functions as the semiconductor device shown in the previous embodiment, <Structure of storage device 1>, and <Structure of storage device 2>, and the structure constituting the storage device. The same reference numerals are added to the structures having the same.

As shown in FIG. 24, the storage device of one aspect of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitive element 100. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300, the transistor 200 and the transistor 400.

As the capacitance element 100, the transistor 200, the transistor 300, and the transistor 400, the capacitance and the transistor possessed by the semiconductor device and the storage device described in the previous embodiment and FIGS. 21 to 23 may be used. The capacitive element 100, the transistor 300, the transistor 200, and the transistor 400 shown in FIG. 24 are examples, and the transistor is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

By using this structure, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

An example of the memory cell array of this embodiment is shown in FIG. A memory cell array can be configured by arranging the transistors 200 as memory cells in a matrix.

The storage device shown in FIG. 25 is a semiconductor device that constitutes a memory cell array by arranging the storage devices shown in FIGS. 21 and 24 in a matrix. One transistor 400 can control the back gate voltage of the plurality of transistors 200. Therefore, the number of transistors 400 may be smaller than that of the transistors 200.

Therefore, in FIG. 25, the transistor 400 shown in FIG. 24 is omitted. FIG. 25 is a cross-sectional view in which a part of a row is extracted when the storage devices shown in FIGS. 21 and 24 are arranged in a matrix.

Further, the configuration of the transistor 300 is different from that of FIG. 24. In the transistor 300 shown in FIG. 25, the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. The conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

In the storage device shown in FIG. 25, the memory cells 650a and the memory cells 650b are arranged adjacent to each other. The memory cell 650a and the memory cell 650b have a transistor 300, a transistor 200, and a capacitance element 100, and are electrically connected to the wiring 1001, the wiring 1002, the wiring 1003, the wiring 1004, the wiring 1005, and the wiring 1006. Similarly, in the memory cell 650a and the memory cell 650b, the node in which the gate of the transistor 300 and one of the electrodes of the capacitance element 100 are electrically connected is referred to as a node SN. The wiring 1002 is common to the adjacent memory cells 650a and the memory cells 650b.

When the memory cells are arranged in an array, the information of the desired memory cells must be read at the time of reading. For example, when the memory cell array has a NOR type configuration, only the information of the desired memory cell can be read by setting the transistor 300 of the memory cell that does not read the information into a non-conducting state. _{In this case, a potential that causes the} transistor 300 to be in a "non-conducting state" regardless of the charge given to the node SN, that is, a potential lower than V th_H is given to the wiring 1005 connected to the memory cell that does not read information. Just do it. Alternatively, for example, when the memory cell array has a NAND type configuration, only the information of the desired memory cell can be read by making the transistor 300 of the memory cell that does not read the information conductive. In this case, if a potential that causes the transistor 300 to be in a "conducting state" regardless of the charge given to the node SN, that is, a potential _{higher than V th_L} is applied to the wiring 1005 connected to the memory cell that does not read information. good.

By using this structure, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device using a transistor having an oxide semiconductor. Alternatively, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

As described above, the configuration, structure, method and the like shown in the present embodiment can be used in appropriate combination with the configuration, structure, method and the like shown in other embodiments.

(Embodiment 3)
In the present embodiment, using FIGS. 26 and 27, a transistor (hereinafter, referred to as an OS transistor) using an oxide as a semiconductor and a memory to which a capacitive element according to one aspect of the present invention is applied. As an example of the device, NO SRAM will be described. NOSRAM (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM having a gain cell type (2T type, 3T type) memory cell. In the following, a memory device using an OS transistor such as NOSRAM may be referred to as an OS memory.

In NOSRAM, a memory device (hereinafter, referred to as “OS memory”) in which an OS transistor is used as a memory cell is applied. The OS memory is a memory having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the OS transistor is a transistor with a minimum off-current, the OS memory has excellent holding characteristics and can function as a non-volatile memory.

<< NO SRAM >>
FIG. 26 shows a configuration example of the NO SRAM. The NOSRAM 1600 shown in FIG. 26 has a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. The NO SRAM 1600 is a multi-value NO SRAM that stores multi-value data in one memory cell.

The memory cell array 1610 has a plurality of memory cells 1611, a plurality of word lines WWL, RWL, a bit line BL, and a source line SL. The word line WWL is a writing word line, and the word line RWL is a reading word line. In the NOSRAM 1600, 3 bits (8 values) of data are stored in 1 memory cell 1611.

The controller 1640 comprehensively controls the entire NO SRAM 1600, writes data WDA [31: 0], and reads data RDA [31: 0]. The controller 1640 processes an external command signal (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660, and the output driver 1670.

The row driver 1650 has a function of selecting a row to be accessed. The row driver 1650 has a row decoder 1651 and a wordline driver 1652.

The column driver 1660 drives the source line SL and the bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.

DAC1663 converts 3-bit digital data into analog voltage. The DAC1663 converts 32-bit data WDA [31: 0] into analog voltage every 3 bits.

The write driver 1662 has a function of precharging the source line SL, a function of electrically suspending the source line SL, a function of selecting the source line SL, and inputting the write voltage generated by the DAC 1663 to the selected source line SL. It has a function of precharging the bit wire BL, a function of electrically floating the bit wire BL, and the like.

The output driver 1670 has a selector 1671, an ADC (analog-to-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to access and transmits the voltage of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.

<Memory cell>
FIG. 27A is a circuit diagram showing a configuration example of the memory cell 1611. The memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word line WWL, RWL, bit line BL, source line SL, and wiring BGL. The memory cell 1611 has a node SN, an OS transistor MO61, a transistor MP61, and a capacitance element C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a readout transistor, and is composed of, for example, a p-channel Si transistor. The capacitance element C61 is a holding capacitance for holding the voltage of the node SN. The node SN is a data holding node, and here corresponds to the gate of the transistor MP61.

Since the write transistor of the memory cell 1611 is composed of the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

In the example of FIG. 27 (A), the bit line is a bit line common to writing and reading, but as shown in FIG. 27 (B), a writing bit line WBL and a reading bit line RBL may be provided. good.

27 (C) -FIG. 27 (E) shows another configuration example of the memory cell. 27 (C) -FIG. 27 (E) shows an example in which a write bit line and a read bit line are provided, but as shown in FIG. 27 (A), a bit line shared by write and read. May be provided.

The memory cell 1612 shown in FIG. 27 (C) is a modification of the memory cell 1611, in which the read transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.

In the memory cells 1611 and 1612, the OS transistor MO61 may be an OS transistor without a back gate.

The memory cell 1613 shown in FIG. 27 (D) is a 3T type gain cell, and is electrically connected to a word line WWL, RWL, a bit line WBL, RBL, a source line SL, a wiring BGL, and a PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitive element C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.

The memory cell 1614 shown in FIG. 27 (E) is a modification of the memory cell 1613, in which the read transistor and the selection transistor are changed to n-channel transistors (MN62, MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.

The OS transistor provided in the memory cells 1611-1614 may be a transistor without a back gate or a transistor having a back gate.

Since the data is rewritten by charging / discharging the capacitive element C61, the NO SRAM 1600 can write and read data with low energy without any limitation on the number of rewrites in principle. Moreover, since the data can be retained for a long time, the refresh frequency can be reduced.

When the semiconductor device shown in the above embodiment is used for the memory cells 1611, 1612, 1613, 1614, the transistor 200 is used as the OS transistors MO61 and MO62, the capacitance element 100 is used as the capacitance elements C61 and C62, and the transistors MP61 and MN62 are used. Transistor 300 can be used.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

(Embodiment 4)
In the present embodiment, the DOS RAM will be described with reference to FIGS. 28 and 29 as an example of a storage device to which the OS transistor and the capacitive element according to one aspect of the present invention are applied. DOSRAM (registered trademark) is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having a 1T (transistor) 1C (capacity) type memory cell. The OS memory is applied to the DOS RAM as well as the NO SRAM.

<< DOSRAM1400 >>
FIG. 28 shows a configuration example of the DOS RAM. As shown in FIG. 28, the DOSRAM 1400 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).

The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 has a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, a global bit line GBLL, and GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a laminated structure in which the memory cell array 1422 is laminated on the sense amplifier array 1423. The global bit lines GBLL and GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure in which local bit lines and global bit lines are layered is adopted as the bit line structure.

The memory cell array 1422 has N (N is an integer of 2 or more) local memory cell array 1425 <0> -1425 <N-1>. FIG. 29 (A) shows a configuration example of the local memory cell array 1425. The local memory cell array 1425 has a plurality of memory cells 1445, a plurality of word line WLs, a plurality of bit lines BLL, and a BLR. In the example of FIG. 29 (A), the structure of the local memory cell array 1425 is an open bit linear type, but it may be a folded bit linear type.

FIG. 29B shows an example of the circuit configuration of the memory cell 1445. The memory cell 1445 has a transistor MW1, a capacitance element CS1, and terminals B1 and B2. The transistor MW1 has a function of controlling charging / discharging of the capacitive element CS1. The gate of the transistor MW1 is electrically connected to the word wire, the first terminal is electrically connected to the bit wire, and the second terminal is electrically connected to the first terminal of the capacitive element. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant voltage (for example, a low power supply voltage) is input to the terminal B2.

When the semiconductor device shown in the above embodiment is used for the memory cell 1445, the transistor 200 can be used as the transistor MW1 and the capacitance element 100 can be used as the capacitance element CS1.

The transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1. For example, the voltage of the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage of the terminal B1 may be changed according to the operation of the DOSRAM 1400.

The back gate of transistor MW1 may be electrically connected to the gate, source, or drain of transistor MW1. Alternatively, the transistor MW1 does not have to be provided with a back gate.

The sense amplifier array 1423 has N local sense amplifier arrays 1426 <0> -1426 <N-1>. The local sense amplifier array 1426 has one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging a bit line pair, a function of amplifying a voltage difference between the bit line pairs, and a function of maintaining this voltage difference. The switch array 1444 has a function of selecting a bit line pair and making the selected bit line pair and the global bit line pair conductive.

Here, the bit line pair means two bit lines that are simultaneously compared by the sense amplifier. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form a pair of bit lines. The global bit line GBLL and the global bit line GBLR form a set of global bit line pairs. Hereinafter, it is also referred to as a bit line pair (BLL, BLR) and a global bit line pair (BLL, BLR).

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 has a function of logically calculating a command signal input from the outside to determine an operation mode, and a function of generating control signals of the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. It has a function of holding an address signal input from the outside and a function of generating an internal address signal.

(Line circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target line.

The column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by the selection signal of the column selector 1413. A plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.

(Column circuit 1415)
The column circuit 1415 has a function of controlling the input of the data signal WDA [31: 0] and a function of controlling the output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between global bit line pairs (GBLL, GBLR) and a function of maintaining this voltage difference. The writing and reading of data to the global bit line pair (GBLL, GBLR) is performed by the input / output circuit 1417.

The outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. The data of the global bit line pair is held by the global sense amplifier array 1416. The switch array 1444 of the local sense amplifier array 1426 specified by the address writes the data of the global bit line pair to the bit line pair of the target column. The local sense amplifier array 1426 amplifies and retains the written data. In the designated local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the holding data of the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.

The outline of the read operation of the DOSRAM 1400 will be described. The address signal specifies one row of the local memory cell array 1425. In the designated local memory cell array 1425, the word line WL of the target line is selected, and the data of the memory cell 1445 is written to the bit line. The voltage difference between the bit line pairs in each column is detected and held as data by the local sense amplifier array 1426. The switch array 1444 writes the data of the column specified by the address among the retained data of the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and retains the data of the global bit line pair. The holding data of the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.

Since the data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no limitation on the number of rewrites in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, it is easy to increase the capacity.

The transistor MW1 is an OS transistor. Since the off-current of the OS transistor is extremely small, it is possible to suppress the leakage of electric charge from the capacitive element CS1. Therefore, the holding time of the DOSRAM 1400 is much longer than that of the DRAM. Therefore, since the frequency of refreshing can be reduced, the power required for the refreshing operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that frequently rewrites a large amount of data, for example, a frame memory used for image processing.

Since the MC-SA array 1420 has a laminated structure, the bit wire can be shortened to a length as long as the length of the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced, and the holding capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when the DOSRAM 1400 is accessed can be reduced, and the power consumption can be reduced.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

(Embodiment 5)
In the present embodiment, using FIGS. 30 to 33, an FPGA (Field Programmable Gate Array) is used as an example of a semiconductor device to which an OS transistor and a capacitive element according to one aspect of the present invention are applied. explain. In the FPGA of the present embodiment, the OS memory is applied to the configuration memory and the register. Here, such an FPGA is referred to as "OS-FPGA".

<< OS-FPGA >>
FIG. 30A shows a configuration example of OS-FPGA. The OS-FPGA3110 shown in FIG. 30A is capable of context switching, fine-grained power gating, and NOFF (normally off) computing by a multi-context structure. The OS-FPGA3110 has a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

The programmable area 3115 has two input / output blocks (IOB) 3117 and a core 3119. The IOB3117 has a plurality of programmable input / output circuits. The core 3119 has a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. LAB3120 has a plurality of PLE3121. FIG. 30B shows an example in which the LAB 3120 is composed of five PLE 3121. As shown in FIG. 30C, the SAB 3130 has a plurality of switch blocks (SB) 3131 arranged in an array. The LAB3120 is connected to its own input terminal and the LAB3120 in the 4 (up / down / left / right) direction via the SAB3130.

SB3131 will be described with reference to FIGS. 31 (A) to 31 (C). Data, data, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG. 31 (A). Data and data are configuration data, and data and data have a complementary logic relationship. The number of contexts of OS-FPGA3110 is 2, and the signal context [1: 0] is a context selection signal. The signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.

SB3131 has PRS (programmable routing switch) 3133 [0] and 3133 [1]. The PRS3133 [0] and 3133 [1] have a configuration memory (CM) capable of storing complementary data. When PRS3133 [0] and PRS3133 [1] are not distinguished, they are called PRS3133. The same applies to other factors.

FIG. 31 (B) shows a circuit configuration example of PRS3133 [0]. PRS3133 [0] and PRS3133 [1] have the same circuit configuration. The input context selection signal and word line selection signal are different between PRS3133 [0] and PRS3133 [1]. The signals context [0] and word [0] are input to PRS3133 [0], and the signals context [1] and word [1] are input to PRS3133 [1]. For example, in SB3131, when the signal context [0] becomes “H”, PRS3133 [0] becomes active.

PRS3133 [0] has a CM3135 and a Si transistor M31. The Si transistor M31 is a pass transistor controlled by CM3135. The CM3135 has memory circuits 3137 and 3137B. The memory circuits 3137 and 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitance element C31, an OS transistor MO31, and an MO32. The memory circuit 3137B includes a capacitance element CB31, an OS transistor MOB31, and a MOB32.

When the semiconductor device shown in the above embodiment is used for the SAB3130, the transistor 200 can be used as the OS transistors MO31 and MOB31, and the capacitance element 100 can be used as the capacitance elements C31 and CB31.

The OS transistors MO31, MO32, MOB31, and MOB32 have back gates, and each of these back gates is electrically connected to a power supply line that supplies a fixed voltage.

The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. Nodes N32 and NB32 are charge holding nodes of CM3135. The OS transistor MO32 controls the conduction state between the node N31 and the signal line for the signal context [0]. The OS transistor MOB32 controls the conduction state between the node N31 and the low potential power supply line VSS.

The data held by the memory circuits 3137 and 3137B are in a complementary relationship. Therefore, either the OS transistor MO32 or the MOB32 is conductive.

An operation example of PRS3133 [0] will be described with reference to FIG. 31 (C). Configuration data has already been written to PRS3133 [0], node N32 of PRS3133 [0] is "H", and node NB32 is "L".

PRS3133 [0] is inactive while the signal contex [0] is “L”. During this period, even if the input terminal of the PRS3133 [0] transitions to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS3133 [0] is also maintained at “L”.

PRS3133 [0] is active while the signal contex [0] is “H”. When the signal control [0] transitions to “H”, the gate of the Si transistor M31 transitions to “H” according to the configuration data stored in the CM3135.

When the input terminal transitions to “H” while PRS3133 [0] is active, the gate voltage of the Si transistor M31 rises due to boosting because the OS transistor MO32 of the memory circuit 3137 is the source follower. As a result, the OS transistor MO32 of the memory circuit 3137 loses its driving ability, and the gate of the Si transistor M31 is in a floating state.

In PRS3133 having a multi-context function, CM3135 also has a multi-pressor function.

FIG. 32 shows a configuration example of PLE3121. The PLE3121 has a LUT (look-up table) block 3123, a register block 3124, a selector 3125, and a CM3126. The LUT block 3123 is configured to multiplex the output of the internal 16-bit CM pair according to the input inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration stored in the CM3126.

The PLE3121 is electrically connected to a power supply line for voltage VDD via a power switch 3127. The on / off of the power switch 3127 is set by the configuration data stored in the CM3128. By providing the power switch 3127 in each PLE3121, fine particle power gating is possible. The fine-grained power gating function allows power gating of PLE3121 that is not used after switching contexts, so that standby power can be effectively reduced.

In order to realize NOFF computing, the register block 3124 is composed of a non-volatile register. The non-volatile register in PLE3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.

The register block 3124 has an OS-FF3140 [1] 3140 [2]. The signals user_res, load, and store are input to OS-FF3140 [1] and 3140 [2]. The clock signal CLK1 is input to the OS-FF3140 [1], and the clock signal CLK2 is input to the OS-FF3140 [2]. FIG. 33 (A) shows a configuration example of OS-FF3140.

The OS-FF3140 has an FF3141 and a shadow register 3142. FF3141 has nodes CK, R, D, Q, QB. A clock signal is input to the node CK. The signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node and node Q is a data output node. The logic of node Q and node QB is complementary.

The shadow register 3142 functions as a backup circuit for the FF3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back the backed up data to the nodes Q and QB according to the signal load.

The shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B. The memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS3133. The memory circuit 3143 includes a capacitance element C36, an OS transistor MO35, and an MO36. The memory circuit 3143B includes a capacitance element CB36, an OS transistor MOB35, and an OS transistor MOB36. Nodes N36 and NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes, respectively. Nodes N37 and NB37 are gates of Si transistors M37 and MB37.

When the semiconductor device shown in the above embodiment is used for the LAB 3120, the transistor 200 can be used as the OS transistors MO35 and MOB35, and the capacitive element 100 can be used as the capacitive elements C36 and CB36.

The OS transistors MO35, MO36, MOB35, and MOB36 have back gates, and each of these back gates is electrically connected to a power supply line that supplies a fixed voltage.

An example of the operation method of the OS-FF3140 will be described with reference to FIG. 33 (B).

(backup)
When the "H" signal store is input to the OS-FF3140, the shadow register 3142 backs up the data of the FF3141. The node N36 becomes "L" when the data of the node Q is written, and the node NB 36 becomes "H" when the data of the node QB is written. After that, power gating is performed and the power switch 3127 is turned off. Although the data of the nodes Q and QB of FF3141 is lost, the shadow register 3142 retains the backed up data even when the power is turned off.

(recovery)
The power switch 3127 is turned on to supply power to the PLE3121. After that, when the "H" signal load is input to the OS-FF3140, the shadow register 3142 writes back the backed up data to the FF3141. Since the node N36 is "L", the node N37 is maintained at "L", and the node NB36 is "H", so that the node NB37 is "H". Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF3140 returns to the state at the time of backup operation.

By combining the fine particle power gating and the backup / recovery operation of the OS-FF3140, the power consumption of the OS-FPGA3110 can be effectively reduced.

An example of an error that can occur in a memory circuit is a soft error due to radiation incident. Soft errors are caused by α-rays emitted from materials that make up memories and packages, and primary cosmic rays that enter the atmosphere from space and cause nuclear reactions with the atomic nuclei of atoms that exist in the atmosphere. This is a phenomenon in which a transistor is irradiated with ray neutrons or the like to generate electron-hole pairs, which causes a malfunction such as inversion of data held in a memory. OS memory using OS transistors has high soft error immunity. Therefore, by installing an OS memory, it is possible to provide a highly reliable OS-FPGA3110.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

(Embodiment 6)
In the present embodiment, the AI system to which the semiconductor device shown in the above embodiment is applied will be described with reference to FIGS. 34 to 36.

FIG. 34 is a block diagram showing a configuration example of the AI system 4041. The AI system 4041 has a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, a NOSRAM 4013, and an FPGA 4014. As the DOSRAM 4012, NOSRAM 4013, and FPGA 4014, the DOSRAM 1400, NO SRAM 1600, and OS-FPGA 3110 shown in the above embodiment can be used.

The control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, and a SRAM (Static Random Access Memory 40 Memory) Memory 40 A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.

The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.

The arithmetic unit 4010 can execute learning or inference by a neural network.

The analog arithmetic circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum arithmetic circuit.

The analog arithmetic circuit 4011 is preferably formed by using an OS transistor. The analog arithmetic circuit 4011 using the OS transistor has an analog memory, and can execute the product-sum operation required for learning or inference with low power consumption.

The DOSRAM 4012 is a DRAM formed by using an OS transistor, and the DOSRAM 4012 is a memory for temporarily storing digital data sent from the CPU 4021. The DOSRAM 4012 has a memory cell including an OS transistor and a read circuit unit including a Si transistor. Since the memory cell and the read circuit unit can be provided in different stacked layers, the overall circuit area of the DOSRAM 4012 can be reduced.

In the calculation using the neural network, the input data may exceed 1000. When the input data is stored in the SRAM, the SRAM has a limited circuit area and a small storage capacity, so that the input data must be stored in small pieces. The DOSRAM 4012 can arrange memory cells in a highly integrated manner even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can efficiently store the input data.

NOSRAM 4013 is a non-volatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data than a flash memory and other non-volatile memories such as ReRAM (Resistive Random Access Memory) and MRAM (Magnetoresistive Random Access Memory). Further, unlike flash memory and ReRAM, the element does not deteriorate when writing data, and there is no limit to the number of times data can be written.

Further, the NOSRAM 4013 can store two or more bits of multi-valued data in addition to one-bit binary data. The NOSRAM 4013 can reduce the memory cell area per bit by storing multi-valued data.

Further, the NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit. In the present specification, analog data refers to data having a resolution of 3 bits (8 values) or more. The above-mentioned multi-valued data may be included in the analog data.

The data and parameters used in the calculation of the neural network can be temporarily stored in the NOSRAM 4013. The above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021, but the NO SRAM 4013 provided inside may have higher speed and lower power consumption than the above data and parameters. Can be stored. Further, since the NOSRAM 4013 can have a longer bit line than the DOSRAM 4012, the storage capacity can be increased.

FPGA4014 is an FPGA using an OS transistor. By using the FPGA 4014, the AI system 4041 uses a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, and a deep Boltzmann machine (DBM), which will be described later in hardware. , Deep Belief Network (DBN), and other neural network connections can be constructed. By configuring the above neural network connection with hardware, it can be executed at higher speed.

FPGA4014 is an FPGA having an OS transistor. The OS-FPGA can have a smaller memory area than the FPGA composed of SRAM. Therefore, even if the context switching function is added, the area increase is small. In addition, OS-FPGA can transmit data and parameters at high speed by boosting.

The AI system 4041 can provide analog arithmetic circuits 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014 on one die (chip). Therefore, the AI system 4041 can execute the calculation of the neural network at high speed and low power consumption. Further, the analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014 can be manufactured by the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

The calculation unit 4010 does not have to have the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 at all. One or more of DOSRAM 4012, NOSRAM 4013, and FPGA 4014 may be selected and provided according to the problem to be solved by AI system 4041.

The AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DBM), depending on the problem to be solved. It is possible to execute operations such as DBN). The PROM 4025 can store a program for performing these operations. Moreover, you may store a part or all of these programs in NOSRAM 4013.

Many of the existing programs that exist as libraries are premised on GPU processing. Therefore, the AI system 4041 preferably has a GPU 4022. The AI system 4041 can execute the rate-determining product-sum operation among the product-sum operations used in learning and inference in the calculation unit 4010, and execute the other product-sum operations in the GPU 4022. By doing so, learning and inference can be performed at high speed.

The power supply circuit 4027 not only generates a low voltage potential for a logic circuit, but also generates a potential for analog calculation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce the power consumption by storing the reference potential in the OS memory.

The PMU4028 has a function of temporarily turning off the power supply of the AI system 4041.

The CPU 4021 and GPU 4022 preferably have an OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, the data (logical value) can be continuously held in the OS memory even when the power supply is turned off. As a result, the AI system 4041 can save power.

The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. By having the OS memory, the PLL 4023 can hold an analog potential that controls the oscillation cycle of the clock.

The AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. Further, the memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.

Part or all of the circuit shown in the control unit 4020 can be formed on the same die as the calculation unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and low power consumption.

The data used for the calculation of the neural network is often stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably has an external storage control circuit 4031 that functions as an interface with the external storage device.

Since learning and inference using neural networks often deal with audio and video, the AI system 4041 has an audio codec 4032 and a video codec 4033. The audio codec 4032 encodes (encodes) and decodes (decodes) audio data, and the video codec 4033 encodes and decodes video data.

The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus), I2C (Inter-Integrated Circuit), and the like.

The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 4035.

The analog arithmetic circuit 4011 may use a multi-valued flash memory as an analog memory. However, the flash memory has a limited number of rewritable times. In addition, it is very difficult to form a multi-valued flash memory by embedding (a calculation circuit and a memory are formed on the same die).

Further, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times, and has a problem in terms of storage accuracy. Further, since the element has two terminals, the circuit design for separating data writing and reading becomes complicated.

Further, the analog arithmetic circuit 4011 may use the MRAM as an analog memory. However, MRAM has a low resistance change rate and has a problem in terms of storage accuracy.

In view of the above, it is preferable that the analog arithmetic circuit 4011 uses the OS memory as the analog memory.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

(Embodiment 7)

<Application example of AI system>
In this embodiment, an application example of the AI system shown in the above embodiment will be described with reference to FIG. 35.

FIG. 35A is an AI system 4041A in which the AI systems 4041 described with reference to FIG. 34 are arranged in parallel to enable transmission and reception of signals between the systems via a bus line.

The AI system 4041A illustrated in FIG. 35 (A) has a plurality of AI systems 4041_1 to AI system 4041_n (n is a natural number). The AI system 4041_1 to AI system 4041_n are connected to each other via the bus line 4098.

Further, FIG. 35 (B) shows the AI system 4041B in which the AI system 4041 described with reference to FIG. 34 is arranged in parallel in the same manner as in FIG. 35 (A) to enable transmission / reception of signals between the systems via a network. be.

The AI system 4041B illustrated in FIG. 35 (B) has a plurality of AI systems 4041_1 to AI system 4041_n. The AI system 4041_1 to AI system 4041_n are connected to each other via the network 4099.

The network 4099 may be configured to provide communication modules in each of the AI system 4041_1 to the AI system 4041_n to perform wireless or wired communication. The communication module can communicate via the antenna. For example, the Internet, Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Male) Network, which are the foundations of World Wide Web (WWW). Each electronic device can be connected to a computer network such as Network) or GAN (Global Area Network) to perform communication. In the case of wireless communication, LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000, as a communication protocol or communication technology, are used. , W-CDMA (registered trademark) and other communication standards, or Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) and other communication standardized specifications can be used.

With the configurations shown in FIGS. 35A and 35B, analog signals obtained by an external sensor or the like can be processed by separate AI systems. For example, it is possible to acquire information such as brain waves, pulse, blood pressure, and body temperature with various sensors such as brain wave sensors, pulse wave sensors, blood pressure sensors, and temperature sensors, and process analog signals with separate AI systems, such as biological information. can. The amount of information processing per AI system can be reduced by processing or learning signals in each of the separate AI systems. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, the recognition accuracy can be improved. From the information obtained by each AI system, it can be expected that changes in biometric information that change in a complicated manner can be grasped instantly and in an integrated manner.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

(Embodiment 8)
This embodiment shows an example of an IC incorporating the AI system shown in the above embodiment.

The AI system shown in the above embodiment integrates a digital processing circuit made of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA and DOSRAM and NOSRAM on one die. be able to.

FIG. 36 shows an example of an IC incorporating an AI system. The AI system IC 7000 shown in FIG. 36 has a lead 7001 and a circuit unit 7003. In the circuit unit 7003, various circuits shown in the above embodiment are provided on one die. The circuit unit 7003 has a laminated structure in the above embodiment, for example, as shown in FIG. 21, and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be laminated on the Si transistor layer 7031, the AI system IC 7000 can be easily miniaturized.

In FIG. 36, QFP (Quad Flat Package) is applied to the package of the AI system IC7000, but the package mode is not limited to this.

A digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, and an OS memory such as OS-FPGA and DOSRAM and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in the present embodiment does not need to increase the manufacturing process even if the number of constituent elements increases, and the AI system can be incorporated at low cost.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

(Embodiment 9)
In this embodiment, an example of a display device having a transistor illustrated in the previous embodiment will be described.

[Configuration example]
FIG. 37A is a top view showing an example of the display device. The display device 700 shown in FIG. 37A has a pixel unit 702 provided on the first substrate 701, a source driver circuit unit 704 and a gate driver circuit unit 706 provided on the first substrate 701, and pixels. It has a sealing material 712 arranged so as to surround the unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706, and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are bonded to each other by the sealing material 712. That is, the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 are sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in FIG. 37 (A), a display element is provided between the first substrate 701 and the second substrate 705.

Further, the display device 700 is provided with an FPC terminal portion 708 (FPC: Flexible printed circuit board) in a region different from the region surrounded by the sealing material 712 on the first substrate 701. The FPC terminal unit 708 is electrically connected to the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the gate driver circuit unit 706, respectively. Further, the FPC 716 is connected to the FPC terminal unit 708, and various signals and the like are supplied to the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 by the FPC 716. Further, a signal line 710 is connected to each of the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708. Various signals and the like supplied by the FPC 716 are given to the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708 via the signal line 710.

Further, the display device 700 may be provided with a plurality of gate driver circuit units 706. Further, the display device 700 shows an example in which the source driver circuit unit 704 and the gate driver circuit unit 706 are formed on the same first substrate 701 as the pixel unit 702, but the present invention is not limited to this configuration. For example, only the gate driver circuit unit 706 may be formed on the first substrate 701, or only the source driver circuit unit 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate 701. .. The method for connecting the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

Further, the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 of the display device 700 have a plurality of transistors, and the transistor which is the semiconductor device of one aspect of the present invention can be applied. ..

Further, the display device 700 can have various elements. Examples of the element include an electroluminescence (EL) element (EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element, an LED, etc.), a light emitting transistor element (a transistor that emits light according to a current), and an electron. Emission element, liquid crystal element, electronic ink element, electrophoresis element, electrowetting element, plasma display panel (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror Devices (DMDs), digital micro shutter (DMS) devices, interferometric modulation (IMOD) devices, etc.), piezoelectric ceramic displays, and the like.

Further, as an example of a display device using an EL element, there is an EL display or the like. As an example of a display device using an electron emitting element, there is a field emission display (FED) or a SED type planar display (SED: Surface-conduction Electron-emitter Display). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display). An example of a display device using an electronic ink element or an electrophoresis element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

As the display method in the display device 700, a progressive method, an interlaced method, or the like can be used. Further, the color elements controlled by the pixels at the time of color display are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels of R pixel, G pixel, B pixel, and W (white) pixel. Alternatively, as in the pentile array, one color element may be composed of two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display device for color display, and can be applied to the display device for monochrome display.

Further, in order to display the display device in color by using white light emission (W) for the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.), a colored layer (also referred to as a color filter) may be used. good. As the colored layer, for example, red (R), green (G), blue (B), yellow (Y) and the like can be appropriately combined and used. By using the colored layer, the color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, the white light in the region without the colored layer may be directly used for display by arranging the region having the colored layer and the region without the colored layer. By arranging a region that does not have a colored layer in a part thereof, it is possible to reduce the decrease in brightness due to the colored layer and reduce the power consumption by about 20% to 30% at the time of bright display. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from an element having each emission color. By using the self-luminous element, the power consumption may be further reduced as compared with the case where the colored layer is used.

In addition, as a colorization method, in addition to the method of converting a part of the light emission from the white light emission into red, green, and blue by passing through a color filter (color filter method), red, green, and blue light emission are performed. The method used for each (three-color method) or the method of converting a part of the light emitted from the blue light emission to red or green (color conversion method, quantum dot method) may be applied.

The display device 700A shown in FIG. 37 (B) is a display device that can be suitably used for an electronic device having a large screen. For example, it can be suitably used for a television device, a monitoring device, a digital signage, and the like.

The display device 700A has a plurality of source driver ICs 721 and a pair of gate driver circuits 722.

Each of the plurality of source drivers IC721 is attached to the FPC723. Further, in the plurality of FPC723s, one terminal is connected to the substrate 701 and the other terminal is connected to the printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be arranged on the back side of the pixel portion 702 and mounted on an electric device.

On the other hand, the gate driver circuit 722 is formed on the substrate 701. As a result, an electronic device having a narrow frame can be realized.

With such a configuration, a large-sized and high-resolution display device can be realized. For example, it can be applied to a display device having a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. Further, it is possible to realize an extremely high resolution display device having a resolution of full high definition, 4K2K, 8K4K, or the like.

[Cross-section configuration example]
Hereinafter, a configuration using a liquid crystal element and an EL element as display elements will be described with reference to FIGS. 38 and 39. Note that FIG. 38 is a cross-sectional view taken along the alternate long and short dash line QR shown in FIG. 37, and has a configuration in which a liquid crystal element is used as the display element. Further, FIG. 39 is a cross-sectional view of the alternate long and short dash line QR shown in FIG. 37, and has a configuration in which an EL element is used as a display element.

First, the common parts shown in FIGS. 38 and 39 will be described first, and then the different parts will be described below.

[Explanation of common parts of display devices]
The display device 700 shown in FIGS. 38 and 39 includes a routing wiring unit 711, a pixel unit 702, a source driver circuit unit 704, and an FPC terminal unit 708. Further, the routing wiring portion 711 has a signal line 710. Further, the pixel unit 702 has a transistor 750 and a capacitance element 790. Further, the source driver circuit unit 704 has a transistor 752.

As the transistor 750 and the transistor 752, the transistor 100A exemplified in the first embodiment can be applied.

The transistor used in this embodiment has an oxide semiconductor film that is highly purified and suppresses the formation of oxygen deficiency. The transistor can reduce the off-current. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, the transistor used in the present embodiment can be driven at high speed because a relatively high field effect mobility can be obtained. For example, by using a transistor capable of such high-speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion can be formed on the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, also in the pixel portion, by using a transistor capable of high-speed driving, it is possible to provide a high-quality image.

The capacitive element 790 has a lower electrode formed through a step of processing the same conductive film as the first gate electrode of the transistor 750 and a conductive electrode of the transistor 750 that functions as a source electrode or a drain electrode. It has an upper electrode formed through a step of processing the same conductive film as the film. Further, an insulating film formed between the lower electrode and the upper electrode through a step of forming the same insulating film as the insulating film functioning as the first gate insulating film of the transistor 750, and the transistor 750. An insulating film formed through a step of forming the same insulating film as the insulating film functioning as a protective insulating film is provided. That is, the capacitive element 790 has a laminated structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.

Further, in FIGS. 38 and 39, a flattening insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitive element 790.

Further, in FIGS. 38 and 39, the configuration in which the transistor 750 included in the pixel unit 702 and the transistor 752 included in the source driver circuit unit 704 is used as a transistor having the same structure is illustrated, but the present invention is not limited thereto. For example, the pixel unit 702 and the source driver circuit unit 704 may use different transistors. Specifically, a top gate type transistor is used for the pixel unit 702 and a bottom gate type transistor is used for the source driver circuit unit 704, or a bottom gate type transistor is used for the pixel unit 702 and the source driver circuit unit 704 is used. For example, a configuration using a top gate type transistor can be mentioned. The source driver circuit unit 704 may be read as a gate driver circuit unit.

Further, the signal line 710 is formed through the same steps as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. When, for example, a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small, and display on a large screen becomes possible.

Further, the FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed through the same steps as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Further, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

Further, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. A spherical spacer may be used as the structure 778.

Further, on the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 that is in contact with the light-shielding film 738 and the colored film 736 are provided.

[Configuration example of a display device using a liquid crystal element]
The display device 700 shown in FIG. 38 has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the side of the second substrate 705 and has a function as a counter electrode.

Further, the display device 700 shown in FIG. 38 is an example of a configuration in which a transverse electric field method (for example, FFS mode) is used as a drive method for the liquid crystal element. In the case of the configuration shown in FIG. 38, the insulating film 773 is provided on the conductive film 772, and the conductive film 774 is provided on the insulating film 773. In this case, the conductive film 774 has a function as a common electrode (also referred to as a common electrode), and the orientation of the liquid crystal layer 776 is caused by the electric field generated between the conductive film 772 and the conductive film 774 via the insulating film 773. The state can be controlled.

Further, although not shown in FIG. 38, an alignment film may be provided on either one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776. Further, although not shown in FIG. 38, optical members (optical substrates) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

Further, the conductive film 772 is electrically connected to a conductive film that functions as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed on the flattening insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element.

As the conductive film 772, a conductive film that is translucent in visible light or a conductive film that is reflective in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which is reflective in visible light, for example, a material containing aluminum or silver may be used.

When a conductive film having a reflective light in visible light is used for the conductive film 772, the display device 700 becomes a reflective liquid crystal display device. Further, when a conductive film having translucency in visible light is used for the conductive film 772, the display device 700 becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates sandwiching the liquid crystal element are provided.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a polymer network type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like.

Further, when the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require an orientation treatment because it has a short response rate and is optically isotropic. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. .. Further, the liquid crystal material showing the blue phase has a small viewing angle dependence.

When a liquid crystal element is used as the display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Birefringent Micro-Cell) mode, and an ASM (Axially Birefringent Micro-Cell) mode Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric Liquid Crystal) mode, ECB (Electricular Liquid Crystal) mode, ECB (Electricular Liquid Crystal) mode, ECB (Electricular Liquid Crystal) mode, etc.

Further, a normally black type liquid crystal display device, for example, a transmissive type liquid crystal display device adopting a vertical orientation (VA) mode may be used. As the vertical orientation mode, for example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV mode and the like can be used.

[Display device using light emitting element]
The display device 700 shown in FIG. 39 has a light emitting element 782. The light emitting element 782 has a conductive film 772, an EL layer 786, and a conductive film 788. The display device 700 shown in FIG. 39 can display an image by emitting light from the EL layer 786 of the light emitting element 782 provided for each pixel. The EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

Examples of the material that can be used for the organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, and core-type quantum dot materials. Further, a material containing an element group of groups 12 and 16, groups 13 and 15, or groups 14 and 16 may be used. Alternatively, cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As). ), Aluminum (Al), and other quantum dot materials may be used.

In the display device 700 shown in FIG. 39, an insulating film 730 is provided on the flattening insulating film 770 and the conductive film 772. The insulating film 730 covers a part of the conductive film 772. The light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has translucency and transmits the light emitted by the EL layer 786. In the present embodiment, the top emission structure will be illustrated, but the present invention is not limited to this. For example, it can be applied to a bottom emission structure that emits light to the conductive film 772 side and a dual emission structure that emits light to both the conductive film 772 and the conductive film 788.

Further, a colored film 736 is provided at a position overlapping the light emitting element 782, and a light shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Further, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 39, a configuration in which the colored film 736 is provided has been illustrated, but the present invention is not limited to this. For example, when the EL layer 786 is formed in an island shape for each pixel, that is, it is formed by painting separately, the colored film 736 may not be provided.

The configuration examples exemplified in the present embodiment and the drawings and the like corresponding thereto can be carried out by appropriately combining at least a part thereof with other configuration examples or drawings and the like.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 10)
In the present embodiment, a display device having the semiconductor device of one aspect of the present invention will be described with reference to FIG. 40.

The display device shown in FIG. 40 (A) has a region having pixels of the display element (hereinafter referred to as pixel unit 502) and a circuit unit (hereinafter referred to as pixel unit 502) arranged outside the pixel unit 502 and having a circuit for driving the pixels. , Drive circuit unit 504), a circuit having an element protection function (hereinafter referred to as protection circuit 506), and a terminal unit 507. The protection circuit 506 may not be provided.

It is desirable that a part or all of the drive circuit unit 504 is formed on the same substrate as the pixel unit 502. As a result, the number of parts and the number of terminals can be reduced. When a part or all of the drive circuit unit 504 is not formed on the same substrate as the pixel unit 502, a part or all of the drive circuit unit 504 is formed by COG or TAB (Tape Implemented Bonding). Can be implemented.

The pixel unit 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in the X row (X is a natural number of 2 or more) and the Y column (Y is a natural number of 2 or more). The drive circuit unit 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (hereinafter referred to as a gate driver 504a). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507 and outputs the signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which the scanning signal is given. A plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can also supply another signal.

The source driver 504b has a shift register and the like. In the source driver 504b, in addition to the signal for driving the shift register, a signal (image signal) that is the source of the data signal is input via the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. Further, the source driver 504b has a function of controlling the output of the data signal according to the pulse signal obtained by inputting the start pulse, the clock signal and the like. Further, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) to which the data signal is given. Alternatively, the source driver 504b has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured by using, for example, a plurality of analog switches. The source driver 504b can output a time-division signal of an image signal as a data signal by sequentially turning on a plurality of analog switches. Further, the source driver 504b may be configured by using a shift register or the like.

In each of the plurality of pixel circuits 501, a pulse signal is input via one of the plurality of scanning lines GL to which the scanning signal is given, and the data signal is transmitted through one of the plurality of data line DLs to which the data signal is given. Entered. Further, in each of the plurality of pixel circuits 501, the writing and holding of the data of the data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and n-th column, a pulse signal is input from the gate driver 504a via the scanning line GL_m (m is a natural number of X or less), and the data line DL_n (n) is input according to the potential of the scanning line GL_m. Is a natural number less than or equal to Y), and a data signal is input from the source driver 504b.

The protection circuit 506 shown in FIG. 40 (A) is connected to, for example, a scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to the wiring between the source driver 504b and the terminal portion 507. The terminal portion 507 refers to a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 506 is a circuit that makes the wiring and another wiring conductive when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

As shown in FIG. 40 (A), by providing protection circuits 506 in the pixel unit 502 and the drive circuit unit 504, respectively, the resistance of the display device to overcurrent generated by ESD (Electrostatic Discharge) or the like is enhanced. be able to. However, the configuration of the protection circuit 506 is not limited to this, and for example, the configuration may be such that the protection circuit 506 is connected to the gate driver 504a or the protection circuit 506 is connected to the source driver 504b. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

Further, FIG. 40A shows an example in which the drive circuit unit 504 is formed by the gate driver 504a and the source driver 504b, but the present invention is not limited to this configuration. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

The pixel circuit 501 shown in FIG. 40B includes a liquid crystal element 570, a transistor 550, and a capacitance element 560. The transistor shown in the previous embodiment can be applied to the transistor 550.

The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the written data. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 of each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 of each row.

For example, as a method of driving a display device including a liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (Axially Sysmeric Aligned Micro-cell) mode, an OCB (Opticalally Compensated Birefringence) mode, and a FLC (Ferroelectric) mode are used. , AFLC (Antiferroelectric Liquid Crystal) mode, MVA mode, PVA (Partnered Vertical Birefringence) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode and the like may be used. Further, as the driving method of the display device, in addition to the driving method described above, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and the like. However, the present invention is not limited to this, and various liquid crystal elements and various driving methods thereof can be used.

In the pixel circuit 501 of the m-th row and n-th column, one of the source electrode or the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. NS. Further, the gate electrode of the transistor 550 is electrically connected to the scanning line GL_m. The transistor 550 has a function of controlling data writing of a data signal.

One of the pair of electrodes of the capacitive element 560 is electrically connected to the wiring to which the potential is supplied (hereinafter, the potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. NS. The potential value of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitance element 560 has a function as a holding capacitance for holding the written data.

For example, in the display device having the pixel circuit 501 of FIG. 40 (B), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 40 (A), the transistor 550 is turned on, and the data signal is displayed. Write data.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 550 is turned off. By doing this sequentially line by line, the image can be displayed.

Further, the plurality of pixel circuits 501 shown in FIG. 40 (A) can have the configuration shown in FIG. 40 (C), for example.

Further, the pixel circuit 501 shown in FIG. 40 (C) includes transistors 552 and 554, a capacitance element 562, and a light emitting element 572. The transistor shown in the previous embodiment can be applied to either one or both of the transistor 552 and the transistor 554.

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n) to which a data signal is given. Further, the gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter, referred to as a scanning line GL_m) to which a gate signal is given.

The transistor 552 has a function of controlling data writing of a data signal.

One of the pair of electrodes of the capacitive element 562 is electrically connected to the wiring to which the potential is applied (hereinafter referred to as the potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Will be done.

The capacitance element 562 has a function as a holding capacitance for holding the written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element containing an inorganic material may be used.

One of the potential supply line VL_a and the potential supply line VL_b is given a high power supply potential VDD, and the other is given a low power supply potential VSS.

In the display device having the pixel circuit 501 of FIG. 40 (C), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 40 (A), the transistor 552 is turned on, and the data of the data signal is input. Write.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

The configuration examples exemplified in the present embodiment and the drawings and the like corresponding thereto can be carried out by appropriately combining at least a part thereof with other configuration examples or drawings and the like.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 11)
In the present embodiment, the display module having the semiconductor device of one aspect of the present invention will be described with reference to FIG. 41.

[1. Display module]
The display module 8000 shown in FIG. 41 has a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery between the upper cover 8001 and the lower cover 8002. It has 8011.

The semiconductor device of one aspect of the present invention can be used, for example, in the display panel 8006.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006.

The touch panel 8004 can be used by superimposing a resistive film type or capacitance type touch panel on the display panel 8006. It is also possible to provide the opposite substrate (sealing substrate) of the display panel 8006 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 8006 to form an optical touch panel.

The backlight 8007 has a light source 8008. In FIG. 41, a configuration in which the light source 8008 is arranged on the backlight 8007 has been illustrated, but the present invention is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusing plate may be used. When a self-luminous light emitting element such as an organic EL element is used, or when a reflective panel or the like is used, the backlight 8007 may not be provided.

The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010, in addition to the protective function of the display panel 8006. Further, the frame 8009 may have a function as a heat radiating plate.

The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying electric power to the power supply circuit may be an external commercial power source or a power source supplied by a separately provided battery 8011. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

The configuration examples exemplified in the present embodiment and the drawings and the like corresponding thereto can be carried out by appropriately combining at least a part thereof with other configuration examples or drawings and the like.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 12)
In this embodiment, one embodiment of the semiconductor device will be described with reference to FIGS. 42 and 43.

<Semiconductor wafers and chips>
FIG. 42 (A) shows a top view of the substrate 811 before the dicing process is performed. As the substrate 811, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 812 are provided on the substrate 811. A semiconductor device or the like according to one aspect of the present invention can be provided in the circuit area 812.

Each of the plurality of circuit areas 812 is surrounded by a separation area 813. A separation line (also referred to as a “dicing line”) 814 is set at a position overlapping the separation region 813. By cutting the substrate 811 along the separation line 814, the chip 815 including the circuit area 812 can be cut out from the substrate 811. FIG. 42 (B) shows an enlarged view of the chip 815.

Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 813. By providing a conductive layer, a semiconductor layer, or the like in the separation region 813, ESD that may occur during the dicing step can be alleviated, and a decrease in yield due to the dicing step can be prevented. Further, in general, the dicing step is performed while supplying pure water with reduced specific resistance by dissolving carbon dioxide gas or the like to the cutting portion for the purpose of cooling the substrate, removing shavings, preventing antistatic, and the like. By providing a conductive layer, a semiconductor layer, or the like in the separation region 813, the amount of pure water used can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Moreover, the productivity of the semiconductor device can be increased.

<Electronic components>
An example of an electronic component using the chip 815 will be described with reference to FIGS. 43 (A) and 43 (B). The electronic component is also referred to as a semiconductor package or an IC package. Electronic components have a plurality of standards, names, etc., depending on the terminal take-out direction, the shape of the terminal, and the like.

In the assembly process (post-process), the electronic component is completed by combining the semiconductor device shown in the above embodiment and a component other than the semiconductor device.

The post-process will be described with reference to the flowchart shown in FIG. 43 (A). After forming the semiconductor device or the like according to one aspect of the present invention on the substrate 811 in the previous step, a “back surface grinding step” is performed to grind the back surface of the substrate 811 (the surface on which the semiconductor device or the like is not formed) (step S821). .. By thinning the substrate 811 by grinding, it is possible to reduce the size of electronic components.

Next, a "dicing step" for separating the substrate 811 into a plurality of chips 815 is performed (step S822). Then, a "die bonding step" is performed in which the separated chips 815 are bonded onto the individual lead frames (step S823). For joining the chip 815 and the lead frame in the die bonding step, a method suitable for the product is appropriately selected, such as joining with a resin or joining with a tape. The chip 815 may be bonded on the interposer substrate instead of the lead frame.

Next, a "wire bonding step" is performed in which the leads of the lead frame and the electrodes on the chip 815 are electrically connected by a thin metal wire (wire) (step S824). A silver wire, a gold wire, or the like can be used as the thin metal wire. Further, as the wire bonding, for example, ball bonding or wedge bonding can be used.

The wire-bonded chip 815 is subjected to a "sealing step (molding step)" in which the chip 815 is sealed with an epoxy resin or the like (step S825). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 815 and the lead can be protected from mechanical external force, and the characteristics deteriorate (reliability) due to moisture, dust, etc. (Decrease) can be reduced.

Next, a "lead plating step" for plating the leads of the lead frame is performed (step S726). The plating process prevents rust on the leads, and soldering can be performed more reliably when mounting on a printed circuit board later. Next, a "molding step" of cutting and molding the lead is performed (step S827).

Next, a "marking step" is performed in which a printing process (marking) is performed on the surface of the package (step S828). Then, the electronic component is completed through an "inspection step" (step S829) for checking the quality of the appearance shape, the presence or absence of malfunction, and the like.

Further, a schematic perspective view of the completed electronic component is shown in FIG. 43 (B). FIG. 43B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. The electronic component 850 shown in FIG. 43B has a lead 855 and a chip 815. The electronic component 850 may have a plurality of chips 815.

The electronic component 850 shown in FIG. 43B is mounted on, for example, a printed circuit board 852. A plurality of such electronic components 850 are combined and electrically connected to each other on the printed circuit board 852 to complete a substrate (mounting substrate 854) on which the electronic components are mounted. The completed mounting board 854 is used for electronic devices and the like.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

(Embodiment 13)

<Electronic equipment>
The semiconductor device according to one aspect of the present invention can be used in various electronic devices. FIG. 44 shows a specific example of an electronic device using the semiconductor device according to one aspect of the present invention.

FIG. 44A is an external view showing an example of an automobile. The car 2980 has a body 2981, wheels 2982, dashboard 2983, lights 2984 and the like. Further, the automobile 2980 includes an antenna, a battery and the like.

The information terminal 2910 shown in FIG. 44B has a display unit 2912, a microphone 2917, a speaker unit 2914, a camera 2913, an external connection unit 2916, an operation switch 2915, and the like in the housing 2911. The display unit 2912 includes a display panel and a touch screen using a flexible substrate. Further, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet-type information terminal, a tablet-type personal computer, an electronic book terminal, or the like.

The notebook personal computer 2920 shown in FIG. 44 (C) has a housing 2921, a display unit 2922, a keyboard 2923, a pointing device 2924, and the like. Further, the notebook personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

The video camera 2940 shown in FIG. 44 (D) has a housing 2941, a housing 2942, a display unit 2943, an operation switch 2944, a lens 2945, a connection unit 2946, and the like. The operation switch 2944 and the lens 2945 are provided in the housing 2941, and the display unit 2943 is provided in the housing 2942. Further, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected by a connecting portion 2946, and the angle between the housing 2941 and the housing 2942 can be changed by the connecting portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display unit 2943 can be changed, and the display / non-display of the image can be switched.

FIG. 44 (E) shows an example of a bangle type information terminal. The information terminal 2950 has a housing 2951, a display unit 2952, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2950 and the housing 2951. The display unit 2952 is supported by a housing 2951 having a curved surface. Since the display unit 2952 includes a display panel using a flexible substrate, it is possible to provide an information terminal 2950 that is flexible, light, and easy to use.

FIG. 44F shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display unit 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games.

The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. Further, the display unit 2962 is provided with a touch sensor and can be operated by touching the screen with a finger or a stylus. For example, the application can be started by touching the icon 2967 displayed on the display unit 2962. In addition to setting the time, the operation switch 2965 can have various functions such as power on / off operation, wireless communication on / off operation, manner mode execution / cancellation, and power saving mode execution / cancellation. .. For example, the function of the operation switch 2965 can be set by the operating system incorporated in the information terminal 2960.

In addition, the information terminal 2960 can execute short-range wireless communication standardized for communication. For example, by communicating with a headset capable of wireless communication, it is possible to make a hands-free call. Further, the information terminal 2960 is provided with an input / output terminal 2966, and data can be directly exchanged with another information terminal via a connector. It is also possible to charge via the input / output terminal 2966. The charging operation may be performed by wireless power supply without going through the input / output terminal 2966.

For example, a storage device using the semiconductor device according to one aspect of the present invention can hold the above-mentioned control information of an electronic device, a control program, and the like for a long period of time. By using the semiconductor device according to one aspect of the present invention, a highly reliable electronic device can be realized.

This embodiment can be implemented in combination with the configurations described in other embodiments and the like as appropriate.

100 Capacitive element 100A Transistor 100B Transistor 102 Substrate 104 Insulation layer 108 Semiconductor layer 108n Region 110 Conductor 112 Conductor 114 Metal oxide layer 114a Metal oxide layer 115 Insulation layer 115a Insulation layer 116 Insulation layer 118 Insulation layer 120 Conductor 121a Conductive Layer 121b Conductive layer 130 Insulation 140 Insulation layer 140a Insulation layer 141a Opening 141b Opening 142 Conductive layer 142a Conductive layer 150 Insulator 200 Transistor 200a Transistor 200A Capacitive element 200b Transistor 200c Transistor 200d Transistor 200e Transistor 203 Conductor 203a Conductor 203b Conductor 205 Conductor 205a Conductor 205b Conductor 210 Insulator 212 Insulator 214 Insulator 216 Insulator 218 Insulator 220 Insulator 222 Insulator 224 Insulator 224A Insulation film 230 Oxide 230a Oxide 230A Oxide film 230b Oxide 230B Oxide 230c Oxide 230c1 Oxide 230C Oxide 231 Region 231a Region 231b Region 232 Junction region 232a Junction region 232b Junction region 234 Region 238 Region 239 Region 246 Conductor 248 Conductor 250 Insulator 250a Insulation 250A Insulation film 252a Body 252b Conductor 260 Conductor 260_1 Conductor 260_1a Conductor 260_1b Conductor 260a Conductor 260A Conductor 260b Conductor 260B Conductor 260L Path 270 Insulation 270a Insulation 270A Insulation film 271 Insulation 271a Insulation Body 272a Insulation 272A Insulation film 273 Insulation 273A Insulation 274 Insulation 280 Insulation 286 Insulation 300 Transistor 311 Substrate 313 Semiconductor area 314a Low resistance area 314b Low resistance area 315 Insulation 316 Conductor 320 Insulation 322 Insulation 324 Insulator 326 Insulator 328 Conductor 330 Conductor 350 Insulator 352 Insulator 354 Insulator 356 Insulator 360 Insulator 362 Insulator 364 Insulator 366 Conductor 370 Insulator 372 Insulator 374 Insulator 376 Conductor 380 Insulator 382 Insulator 384 Insulator 386 Conductor 400 Conductor 403 Conductor 403a Conductor 403b Conductor 405 Conductor 405a Conductor 405b Conductor 430c Oxide 431a Oxide 431b Oxide 432a Oxide 432b Oxide 450 Insulator 460 Conductor 460a Conductor 460b Conductor 470 Insulator 471 Insulator 472 Insulator 501 Pixel circuit 502 504 Drive circuit unit 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal unit 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 57 Light emitting element 650a Memory cell 650b Memory cell 700 Display device 700A Display device 701 Board 702 pixels Part 704 Source driver circuit part 705 Board 706 Gate driver circuit part 708 FPC terminal part 710 Signal line 711 Wiring part 712 Sealing material 716 FPC
721 Source driver IC
722 Gate driver circuit 723 FPC
724 Printed circuit board 730 Insulation film 732 Encapsulation film 734 Insulation film 736 Colored film 738 Light-shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulation film 772 Conductive film 773 Insulation film 774 Conductive film 775 Liquid crystal element 77 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 782 Light emitting element 786 EL layer 788 Conductive element 790 Capacitive element 81 Board 812 Circuit area 813 Separation area 814 Separation line 815 Chip 850 Electronic component 852 Printed circuit board 854 Mounting board 855 Lead 1001 Wiring 1002 Wiring 1003 Wiring 1004 Wiring 1005 Wiring 1006 Wiring 1007 Wiring 1008 Wiring 1009 Wiring 1010 Wiring 1400 DOSRAM
1405 Controller 1410 Row circuit 1411 Decoder 1412 Word line driver circuit 1413 Column selector 1414 Sense amplifier driver circuit 1415 Column circuit 1416 Global sense amplifier array 1417 Input / output circuit 1420 MC-SA array 1422 Memory cell array 1423 Sense amplifier array 1425 Local memory cell array 1426 Local Sense Amplifier Array 1444 Switch Array 1445 Memory Cell 1446 Sense Amplifier 1447 Global Sense Amplifier 1600 NOSRAM
1610 Memory cell array 1611 Memory cell 1612 Memory cell 1613 Memory cell 1614 Memory cell 1640 Controller 1650 Row driver 1651 Row decoder 1652 Wordline driver 1660 Column driver 1661 Column decoder 1662 Driver 1663 DAC
1670 Output Driver 1671 Selector 1672 ADC
1673 Output buffer 2000 CDMA
2910 Information terminal 2911 Housing 2912 Display 2913 Camera 2914 Speaker 2915 Operation switch 2916 External connection 2917 Microphone 2920 Notebook personal computer 2921 Housing 2922 Display 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Housing 2942 Housing 2943 Display Part 2944 Operation switch 2945 Lens 2946 Connection part 2950 Information terminal 2951 Housing 2952 Display part 2960 Information terminal 2961 Housing 2962 Display part 2963 Band 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 Icon 2980 Car 2988 Car body 2982 Wheels 2983 Dashboard 2984 Light 3110 OS-FPGA
3111 Controller 3112 Word Driver 3113 Data Driver 3115 Programmable Area 3117 IOB
3119 Core 3120 LAB
3121 PLE
3123 LUT block 3124 Register block 3125 Selector 3126 CM
3127 Power switch 3128 CM
3130 SAB
3131 SB
3133 PRS
3135 CM
3137 Memory circuit 3137B Memory circuit 3140 OS-FF
3141 FF
3142 Shadow register 3143 Memory circuit 3143B Memory circuit 3188 Inverter circuit 3189 Inverter circuit 4010 Calculation unit 4011 Analog calculation circuit 4012 DOSRAM
4013 NO SRAM
4014 FPGA
4020 Control unit 4021 CPU
4022 GPU
4023 PLL
4025 PROM
4026 Memory controller 4027 Power supply circuit 4028 PMU
4030 Input / output unit 4031 External storage control circuit 4032 Audio codec 4033 Video codec 4034 General-purpose input / output module 4035 Communication module 4041 AI system 4041_n AI system 4041_1 AI system 4041A AI system 4041B AI system 4098 Bus line 4099 Network 7000 AI system IC
7001 Lead 7003 Circuit part 7031 Si Transistor layer 7032 Wiring layer 7033 OS Transistor layer 8000 Display module 8001 Top cover 8002 Bottom cover 8003 FPC
8004 touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims (7)

With the first insulator placed on the substrate,
With the oxide on the first insulator,
With the second insulator on the oxide,
With the conductor on the second insulator,
With the third insulator on the conductor
A fourth insulator in contact with the side surface of the conductor and
A fifth insulator in contact with the side surface of the fourth insulator and the side surface of the second insulator,
It said contact with at least the top surface of the oxide, and the fifth insulator aspect, the fifth top surface of the insulator, said fourth insulator top surface and said third sixth in contact with the upper surface of the insulator With an insulator,
The oxide has a first region that overlaps with the second insulator, a second region that overlaps with the fourth insulator and the fifth insulator, and a third region that is in contact with the second region. Has an area and
At least a part of the second region is in contact with the fifth insulator.
At least a part of the third region is in contact with the sixth insulator.
The conductor and the second insulator have a non-overlapping region.
The third region has a higher concentration of hydrogen or nitrogen than the second region.
The second region is a semiconductor device having a higher concentration of hydrogen or nitrogen than the first region. With the first insulator placed on the substrate,
With the oxide on the first insulator,
With the second insulator on the oxide,
With the conductor on the second insulator,
With the third insulator on the conductor
A fourth insulator in contact with the side surface of the conductor and
A fifth insulator in contact with the side surface of the fourth insulator and the side surface of the second insulator,
It said contact with at least the top surface of the oxide, and the fifth insulator aspect, the fifth top surface of the insulator, said fourth insulator top surface and said third sixth in contact with the upper surface of the insulator With an insulator,
The oxide has a first region that overlaps with the second insulator, a second region that overlaps with the fourth insulator and the fifth insulator, and a third region that is in contact with the second region. Has an area and
At least a part of the second region is in contact with the fifth insulator.
At least a part of the third region is in contact with the sixth insulator.
The conductor and the second insulator have a non-overlapping region.
The third region has a higher carrier density than the second region.
The second region is a semiconductor device having a higher carrier density than the first region. In claim 1 or 2,
A semiconductor device in which the oxide contains In, an element M (M is Al, Ga, Y, or Sn), and Zn. In any one of claims 1 to 3,
The fourth insulator is a semiconductor device containing a metal oxide. In any one of claims 1 to 4,
A semiconductor device in which the oxide has a curved surface between a side surface and an upper surface, and the radius of curvature of the curved surface is 3 nm or more and 10 nm or less. In any one of claims 1 to 5,
The conductor is a semiconductor device having a conductive oxide. In any one of claims 1 to 6,
The sixth insulator is a semiconductor device having either or both of hydrogen and nitrogen.

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