JP6943640B2 - Semiconductor integrated circuits, cooling devices, electronic devices - Google Patents

Description

The present invention relates to semiconductor integrated circuits.

With the recent increase in computer speed, the operating speed of arithmetic processing units (Large Scale Integrated circuits) such as CPUs (Central Processing Units), DSPs (Digital Signal Processors), and GPUs (Graphics Processing Units) continues to increase. There is. In such an LSI, the amount of heat generated increases as the operating speed, that is, the clock frequency increases. The heat generated by an LSI has a problem that it leads the LSI itself to thermal runaway or affects surrounding circuits. Therefore, proper thermal cooling of the LSI is extremely important.

As an example of the technique for cooling the LSI, there is an air-cooled cooling method using a cooling fan. In this method, for example, a cooling fan is installed facing the surface of the LSI, and cold air is blown to the LSI or a heat sink attached to the LSI by the cooling fan.

The drive circuit of the fan motor controls the rotation speed of the fan motor in response to a control input indicating the rotation speed of the cooling fan. A pulse width modulation signal is often used as the control input. For example, a duty ratio of 0% is associated with the minimum rotation speed, and a duty ratio of 100% is associated with the maximum rotation speed. When driving a fan motor by digital control, it is necessary to convert the duty ratio of the control input into a digital value.

Japanese Unexamined Patent Publication No. 2011-130611

The present invention has been made in such a situation, and one of the exemplary objects of the embodiment is to provide a semiconductor integrated circuit capable of detecting the duty ratio of a control input of a wide range of frequencies with high accuracy.

One aspect of the present invention relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes a duty ratio detection circuit that detects the duty ratio of the pulse width modulated external command signal. The duty ratio detection circuit includes a pulse width counter that measures the period during which the external command signal takes a predetermined level using a counter clock, a cycle counter that measures the cycle of the external command signal using a counter clock, and a cycle counter. It includes a clock generator that generates a counter clock whose frequency is adjusted so that the periodic count value is included in a predetermined range.

According to this aspect, the duty ratio of the control input of a wide range of frequencies can be detected with high accuracy.

When the number of bits of the pulse width count value and the cycle count value of the pulse width counter is N (N ≧ 2), the predetermined range may be 2 ^(N-1) to 2 ^N -1. This makes it possible to control the frequency of the counter clock by monitoring the most significant bit and overflow of the periodic count value.

The clock generator may include a frequency divider that divides the system clock by a frequency division ratio of 1/2 ^K to generate a counter clock, and a frequency controller that controls the parameter K (K ≧ 0). The frequency controller may increment the parameter K when the periodic count value exceeds the upper limit of the predetermined range, and decrement the parameter K when the periodic count value does not reach the lower limit of the predetermined range.

The semiconductor integrated circuit may further include a selector that selects one of the external command signal and the inverted signal of the external command signal and outputs the signal to the pulse width counter and the period counter.

The duty ratio detection circuit may further include a division circuit that divides the pulse width count value by the periodic count value to generate the duty ratio detection value.

The duty ratio detection circuit may further include a memory for sorting and holding the duty ratio detection values over a plurality of cycles, and may output the duty ratio detection value located at the center as a result of the sorting. As a result, the influence of noise can be reduced.

Another aspect of the invention relates to a cooling device. The cooling device may include a fan motor and the above-mentioned semiconductor integrated circuit for driving the fan motor.

Another aspect of the invention relates to electronic devices. The electronic device may include a processor and the cooling device described above for cooling the processor.

It should be noted that any combination of the above components or components and expressions of the present invention that are mutually replaced between methods, devices, systems, and the like are also effective as aspects of the present invention.

According to an aspect of the present invention, the duty ratio of the control input of a wide range of frequencies can be detected with high accuracy.

It is a block diagram of the semiconductor integrated circuit which concerns on embodiment. _{It is a figure which shows the frequency f CK} of a parameter and a counter clock, and the frequency range of a measurable external command signal PWM IN. It is an operation waveform diagram of the semiconductor integrated circuit of FIG. It is another operation waveform figure of the semiconductor integrated circuit of FIG. It is a block diagram of a motor drive system using a semiconductor integrated circuit. It is a block diagram which shows the configuration example of a speed controller. It is a figure which shows the computer which is equipped with a cooling device.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention, but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and that the member A and the member B are electrically connected to each other. It also includes the case of being indirectly connected via other members, which does not substantially affect the connection state, or does not impair the functions and effects performed by the combination thereof.

Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and their electricity. It also includes the case of being indirectly connected via other members, which does not substantially affect the connection state, or does not impair the functions and effects produced by the combination thereof.

FIG. 1 is a block diagram of the semiconductor integrated circuit 100 according to the embodiment. An external command signal PWMIN whose pulse width is modulated is input to the semiconductor integrated circuit 100, and signal processing based on the duty ratio of the external command signal PWMIN is executed. The semiconductor integrated circuit 100 includes an input terminal IN, a duty ratio detection circuit 200, and a signal processing unit 102. The duty ratio detection circuit 200 detects the duty ratio of the external command signal PWM IN input to the input terminal IN. The signal processing unit 102 executes signal processing according to the detected duty ratio. The content and type of the signal processing unit 102 are not particularly limited.

The duty ratio detection circuit 200 includes a pulse width counter 210, a cycle counter 220, a division circuit 230, a clock generator 240, a polarity selector 250, and a sort memory 260.

The pulse width counter 210 measures the period during which the external command signal PWMIN takes a predetermined level (for example, a high level) by using the counter clock CK. The cycle counter 220 measures the cycle of the external command signal PWMIN using the counter clock CK. A polarity selector 250 is provided in front of the pulse width counter 210 and the cycle counter 220. The polarity selector 250 selects one of the external command signal PWMIN and its inversion signal #PWMIN, which is specified by the polarity parameter POL, and outputs it to the pulse width counter 210 and the cycle counter 220. The polarity selector 250, can be selectively detected and the duty ratio for the high period _{T H} of the external command signal PWMIN, and a duty ratio for the low period _{T L.}

The division circuit 230 divides the pulse width count value PW of the pulse width counter 210 by the cycle count value TP of the cycle counter 220 to generate a duty ratio detection value DUTY indicating the ratio PW / TP.

The clock generator 240 generates a counter clock CK whose frequency is adjusted so that the periodic count value TP is included in a predetermined range.

When the number of bits of the pulse width count value PW and the cycle count value TP is N (N ≧ 2), the predetermined range can be 2 ^(N-1) to 2 ^N -1. When N = 10, the frequency of the counter clock CK is adjusted so that the periodic count value TP is included in 512 to 1023.

For example, the clock generator 240 includes a frequency divider 242 and a frequency controller 244. The frequency divider 242 divides the system clock CK _SYS by a frequency division ratio of 1/2 ^K to generate a counter clock CK. The frequency controller 244 increments the parameter K when the cycle count value TP exceeds the upper limit (1023) of the predetermined range, that is, when the cycle counter 220 overflows. When the parameter K is incremented, the frequency f _CK of the counter clock CK is halved.

On the contrary, the frequency controller 244 decrements the parameter K when the cycle count value TP is less than the lower limit (512) of the predetermined range, that is, when the most significant bit (MSB) of the cycle counter 220 is 0. When the parameter K is decremented, the frequency f _CK of the counter clock CK is doubled.

For example, assume that the parameter K is a hexadecimal number 0 to F. When 25MHz frequency _{f SYS} of the system clock _{CK SYS,} the frequency _{f CK} of the counter clock CK is, 25MHz, 12MHz, 6.25MHz, 3.12MHz , ···· 3.13kHz, 1.56kHz, 16 value of 780Hz Can be selected from. _{FIG. 2 is a diagram showing a frequency f CK} of a parameter and a counter clock, and a frequency range of a measurable external command signal PWM IN.

The sort memory 260 sorts and holds the duty ratio detection value DUTY over a plurality of cycles, and outputs the duty ratio detection value DUTY located at the center as a result of sorting. By providing the sort memory 260, the influence of noise can be reduced.

The above is the configuration of the semiconductor integrated circuit 100. Next, the operation will be described. FIG. 3 is an operation waveform diagram of the semiconductor integrated circuit 100 of FIG. Here, for the sake of simplicity, it is assumed that the number of bits of the pulse width counter 210 and the cycle counter 220 is N = 4, and the frequency of the counter clock CK is adjusted so that the cycle count value TP is included in 8 to 15. Here, for ease of understanding, a state in which the duty ratio is constant and the frequency of the PWM IN signal fluctuates is shown.

In the first cycle, the counter clock CK has a first frequency, and the cycle count value TP is 1100 in binary (decimal number 12) and is included in a predetermined range. The pulse width count value PW of the first cycle is 0110 in binary (decimal number 6), and a duty ratio of 0.5 is obtained.

In the second cycle, the counter clock CK continues to have the first frequency, and the cycle count value TP is 1000 in binary (decimal 8) and is included in the predetermined range. The pulse width count value PW of the second cycle is 0100 (decimal number 4) in binary, and the duty ratio is 0.5.

In the third cycle, the counter clock CK continues to have the first frequency. The period count value TP is binary 0100 (decimal 4), the pulse width count value PW is binary 0010 (decimal 2), and the duty ratio is 0.5. Since the cycle count value TP falls below the predetermined range, the frequency of the counter clock CK is doubled in the next cycle.

In the fourth cycle, the counter clock CK has a second frequency that is twice the first frequency. The periodic count value TP is 1000 in binary (8 in decimal), the pulse width count value PW is 0100 in binary (4 in decimal), and the duty ratio is 0.5. The same applies to the subsequent fifth cycle.

As described above, according to the semiconductor integrated circuit 100, the period and the pulse width of the PWM IN signal can be measured while making full effective use of the number of bits of the counter. As a result, the duty ratio can be detected with high accuracy in a wide range of frequencies of a wide range of PWM IN signals.

That is, according to the semiconductor integrated circuit 100, the degree of freedom of dynamically changing the frequency of the PWM IN signal is provided. For example, in an external CPU or microcomputer that generates a PWM IN signal, the power consumption of the circuit can be reduced by lowering the frequency of the PWM IN signal to about several Hz.

In FIG. 3, the measurement of the pulse width and the period and the division operation of the measurement result were executed in parallel. When the frequency of the PWMIN signal changes in a wide range such as 10 Hz to 50 kHz, and when the frequency of the PWMIN signal is low, the duty ratio can be calculated within one cycle as shown in FIG. 3, but the PWM signal When the frequency of is high, a situation may occur in which the calculation time becomes longer than the period of the PWMIN signal. In such a case, it may be operated as shown in FIG. FIG. 4 is another operating waveform diagram of the semiconductor integrated circuit of FIG. In FIG. 4, the pulse width capture phase and the calculation phase occur alternately. Specifically, when the capture of the period and the pulse width is completed, the operation phase is started. Then, when the calculation is completed, the process returns to the capture phase. According to the control of FIG. 4, it is possible to correspond to a PWM IN signal having a wider frequency range.

The above is the configuration of the duty ratio detection circuit 200. Subsequently, the use of the semiconductor integrated circuit 100 will be described. The semiconductor integrated circuit 100 can be used in a motor drive system.

FIG. 5 is a block diagram of a motor drive system 300 using the semiconductor integrated circuit 100. The motor drive system 300 includes a motor 302, an inverter 304, a motor driver 306, and a speed controller 308.

In this example, the motor 302 is a three-phase brassless DC motor, and the inverter 304 is a three-phase inverter. The motor drive system 300 receives a PWM IN signal having a duty ratio corresponding to a target value of the rotation speed of the motor 302 from a CPU or a microcomputer (not shown) so that the rotation speed of the motor 302 approaches the target rotation speed corresponding to the PWM IN signal. In addition, the motor 302 is feedback-controlled.

The speed controller 308 receives the PWMIN signal and the rotation speed detection signal indicating the actual rotation speed of the motor 302, so that the target rotation speed indicated by the PWMIN signal and the detection value of the rotation speed indicated by the rotation speed detection signal are close to each other. , Generates a control signal CNT. For example, the rotation speed detection signal may be an FG (Frequency Generation) signal having a frequency corresponding to the rotation speed. The control signal CNT corresponds to a voltage command value indicating a drive voltage to be applied to the motor 302, and specifically corresponds to a command value of the switching duty ratio of the inverter 304.

The control signal CNT may be an analog voltage representing a duty ratio, a digital signal, or a PWM signal having the duty ratio.

The motor driver 306 generates a PWM signal having a duty ratio corresponding to the control signal CNT, and PWM-drives the inverter 304 in response to the PWM signal. In FIG. 5, the motor driver 306 and the speed controller 308 may be integrated and integrated into one functional IC.

The above is the configuration of the motor drive system 300. In the motor drive system 300, the speed controller 308 can be configured using the architecture of the semiconductor integrated circuit 100 of FIG.

FIG. 6 is a block diagram showing a configuration example of the speed controller 308. The speed controller 308 has a PWM IN pin, an FGIN pin, and a PAYOUT pin. A PWMIN signal indicating a command value of the rotation speed is input to the PWMIN pin, and an FG signal indicating a detected value of the rotation speed is input to the FGIN pin.

The duty ratio detection circuit 310 of the speed controller 308 corresponds to the duty ratio detection circuit 200 of FIG. 1 and generates a digital signal DUTY indicating the duty ratio of the PWM IN signal.

The FG counter 312 to the output stage 318 correspond to the signal processing unit 102 of FIG. The FG counter 312 measures the frequency (period) of the FG signal and generates a feedback (FB) signal corresponding to the detected value of the rotation speed of the motor 302.

In the RPM converter 314, the duty ratio DUTY detected by the duty ratio detection circuit 310 and the target rotation speed are associated with each other on a one-to-one basis, and a target (REF) signal indicating the target rotation speed is generated. The feedback controller 316 generates the voltage command value CNT so that the error between the REF signal and the FB signal approaches zero. The feedback controller 316 may include a PI (proportional / integral) controller or may have other configurations.

The output stage 318 converts the voltage command value CNT into a format suitable for the motor driver 306 of FIG. 5 and outputs it. For example, when the motor driver 306 in the subsequent stage has a PWM signal interface, the output stage 318 may be configured by a PWM signal generator that converts the voltage command value CNT into a PWM OUT signal having a duty ratio corresponding to the value. ..

If, subsequent motor driver 306 of the speed controller 308, when having an interface of the digital signal, the output stage 318 can be configured by the interface circuit such as I ^{2 C.} When the motor driver 306 in the subsequent stage has an interface for analog signals, the output stage 318 can be configured by a D / A converter.

The above is the configuration of the speed controller 308.

The motor drive system 300 of FIG. 5 can be applied to a cooling device including a fan motor. That is, the motor 302 is a fan motor, and the PWMIN signal may be used as a command value of the rotation speed of the fan motor. FIG. 7 is a diagram showing a computer provided with the cooling device 2. The computer 500 includes a housing 502, a CPU 504, a motherboard 506, a heat sink 508, and a plurality of cooling devices 2.

The CPU 504 is mounted on the motherboard 506. The heat sink 508 is in close contact with the upper surface of the CPU 504. The cooling device 2_1 is provided so as to face the heat sink 508, and blows air onto the heat sink 508. The cooling device 2_2 is installed on the back surface of the housing 502, and sends external air into the housing 502.

In addition to the computer 500 shown in FIG. 7, the cooling device 2 can be mounted on various electronic devices such as workstations, notebook computers, televisions, and refrigerators.

The present invention has been described above based on the embodiments. This embodiment is an example, and it is understood by those skilled in the art that various modifications are possible for each of these components and combinations of each processing process, and that such modifications are also within the scope of the present invention. be. Hereinafter, such a modification will be described.

(First modification)
In FIG. 5, a three-phase motor is taken as an example, but the present invention can also be applied to drive a single-phase motor. Further, as described in Japanese Patent Application Laid-Open No. 2016-0193888, the present invention is also applicable to a motor drive system for driving a motor in an open loop.

(Second modification)
Further, the motor drive system can be applied to a wide range of applications including a motor, such as an electric vehicle and a hybrid vehicle, and the application is not particularly limited. Since the load of the fan motor is substantially constant, the duty ratio of the external command signal is a rotation speed command, but this is not the case. In applications where the load of the motor is not constant, the duty ratio of the external command signal may be the target value of the torque of the motor or the position command value in the servo system.
(Third modification example)
Furthermore, the application of the semiconductor integrated circuit 100 is not limited to the motor drive system, and can be adopted in various systems that give commands by PWM signals.

100 ... semiconductor integrated circuit, 102 ... signal processing unit, 200 ... duty ratio detection circuit, 210 ... pulse width counter, 220 ... period counter, 230 ... division circuit, 240 ... clock generator, 242 ... frequency divider, 244 ... frequency Controller, 250 ... Polarity selector, 260 ... Sort memory, 270 ... Selector, 272 ... Subtractor, 274 ... Bit counter, 276 ... Adder, 278 ... Left bit shifter, 300 ... Motor drive system, 302 ... Motor, 304 ... Inverter , 306 ... motor driver, 308 ... speed controller, 310 ... duty ratio detection circuit, 312 ... FG counter, 314 ... RPM converter, 316 ... feedback controller, 318 ... output stage, PWMIN ... external command signal.

Claims (7)

Equipped with a duty ratio detection circuit that detects the duty ratio of the pulse width modulated external command signal.
The duty ratio detection circuit is
A selector that selects and outputs one of the external command signal and the inverted signal of the external command signal, and
A pulse width counter that receives the output signal of the selector and measures the period during which the output signal of the selector takes a predetermined level by using a counter clock.
A cycle counter that receives the output signal of the selector and measures the cycle of the output signal of the selector using the counter clock.
A frequency controller that receives the cycle count value of the cycle counter and controls the parameter K so that the cycle count value is included in a predetermined range is included, and the counter clock having a frequency corresponding to the parameter K can be generated. and a clock generator, which is,
A semiconductor integrated circuit characterized by comprising. When the number of bits of the pulse width count value and the cycle count value of the pulse width counter is N (N ≧ 2), the predetermined range is 2 ^(N-1) to 2 ^N-1. The semiconductor integrated circuit according to claim 1. Wherein the clock generator includes a frequency divider for generating the counter clock by dividing the system clock by the frequency division ratio 1/2 ^K,
The frequency controller increments the parameter K when the cycle count value exceeds the upper limit of the predetermined range, and decrements the parameter K when the cycle count value is less than the lower limit of the predetermined range. The semiconductor integrated circuit according to claim 1 or 2. Any of claims 1 to 3, wherein the duty ratio detection circuit further includes a division circuit that divides the pulse width count value of the pulse width counter by the cycle count value to generate a duty ratio detection value. The semiconductor integrated circuit described in 1. The duty ratio detecting circuit further includes a memory for holding sorted the duty ratio detection values over a plurality of cycles, a result of the sort, claims and outputs the duty ratio detection values located in the center 4 The semiconductor integrated circuit described in 1. With a fan motor
The semiconductor integrated circuit according to any one of claims 1 to 5 for driving the fan motor.
A cooling device characterized by being provided with. With the processor
The cooling device according to claim 6 , which cools the processor.
An electronic device characterized by being equipped with.

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