JP2013186105A - Signal detection system, resolver signal processing system, and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect not only an abnormality of the output of an operation circuit but also an abnormality at a preceding stage when the operation circuit is operated by an AC voltage signal that is generated on the basis of a voltage control signal.SOLUTION: A data processing circuit outputs a voltage control signal, which is generated on the basis of a control value, to cause a power supply circuit to generate an AC voltage signal, and an operation circuit receives the voltage signal to be operated. The data processing circuit receives the voltage signal that is supplied to the operation circuit, determines whether the received voltage signal is within an allowable error range with respect to its corresponding control value, and makes a central processing unit execute required processing if the result of determination indicates it is not within the allowable error range.

Description

  The present invention provides a signal detection system for determining an operation state of a circuit that operates with a voltage signal generated according to a control signal, and further a resolver signal processing system capable of monitoring a generation state of a reference voltage signal of a resolver, The present invention relates to a semiconductor integrated circuit such as a microcomputer suitable for the detection system and the resolver signal processing system, and relates to a technique effective when applied to, for example, an abnormality detection of a resolver that detects a rotation angle of a rotor.

  As a method for measuring the rotational displacement, there is a resolver that uses a change in electromagnetic induction, which is used for servo control of a motor by detecting the rotation angle of the rotor, for example. The resolver is based on the principle that when an AC voltage is applied to either the stator winding or the rotor winding of the rotor, an AC voltage having the same frequency is induced in the other winding by electromagnetic induction. For example, a sinusoidal voltage signal is input as a reference voltage signal to the primary winding of the rotor, and both ends of the secondary windings of the two stators arranged with a phase difference of 90 ° C. according to the rotation angle. A resolver signal (Vsin, Vcos) is obtained as a voltage signal having an amplitude-modulated 90 ° C. phase difference. The resolver signal is A / D converted, and the rotation angle of the rotor is calculated based on the conversion result.

  There exists patent document 1 as an example of the literature described about the apparatus which detects a rotation angle using a resolver. With respect to the detection of the abnormality of the resolver, in Patent Document 1, the square sum operation of the resolver signal is performed by software processing of the CPU.

JP 2003-031415 A

  When the inventor operates an operating circuit such as a resolver by an AC voltage signal generated by an inverter or the like based on a voltage control signal such as a PWM signal, not only the detection of an abnormality based on the output of the operating circuit, The possibility of detecting in advance the deterioration of the operation accuracy of the operating circuit due to the abnormality in the previous stage was studied.

  According to this, for example, in a resolver signal processing system, as in Japanese Patent Application Laid-Open No. H10-133707, if only an output abnormality of a terminal resolver is detected, an AC voltage signal is generated after receiving the output PWM signal, It is impossible to detect in advance a situation in which an abnormality on the route up to the supply affects the detection accuracy of the resolver. Moreover, when it relies heavily on the software processing by CPU like patent document 1, time will be required for a detection.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the data processing circuit outputs a voltage control signal generated based on the control value, causes the power supply circuit to generate an AC voltage signal, and the operating circuit receives the voltage signal and operates. The data processing circuit receives the voltage signal supplied to the operating circuit, determines whether or not the received voltage signal is within the allowable error range for the corresponding control value, and the determination result is the allowable value The central processing unit is made to execute the necessary processing when it is determined that it is not within the error range.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, when the operation circuit is operated by an AC voltage signal generated based on the voltage control signal, it is possible to detect not only an abnormality in the output of the operation circuit but also an abnormality in the preceding stage.

FIG. 1 is a block diagram illustrating a resolver signal processing system according to a representative embodiment. FIG. 2 is a waveform diagram showing an example of an analog voltage waveform generated by the PWM waveform. FIG. 3 is an explanatory diagram illustrating the significance of trigger delay setting.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Signal detection system>
As illustrated in FIG. 1, the signal detection system according to the representative embodiment includes a data processing circuit (1) and an AC voltage based on a voltage control signal (Spwm) generated by the data processing circuit. A power supply circuit (2) for generating a signal (Vext); and an operating circuit (3) operated by receiving the voltage signal. The data processing circuit includes a central processing unit (10) that executes a program, and a voltage control circuit (20) that generates the voltage control signal based on a control value (Ddty / Dcyc) instructed by the central processing unit. A determination circuit (40) for determining whether or not the voltage signal output from the power supply circuit is within an allowable error range with respect to a control value corresponding to the voltage signal; A detection control circuit (303) for causing the central processing unit to execute processing necessary when it is determined not to fall within the range.

  According to this, the voltage signal generated outside the data processing circuit is fed back to the data processing circuit, and the determination result of whether or not the fed back voltage signal is within the allowable error range with respect to the corresponding control value Based on the above, it is possible to detect an abnormality up to the previous stage of the operation circuit outside the data processing circuit. Since the central processing unit of the data processing circuit only needs to execute processing according to the determination result, the processing can be speeded up as compared with the case where the determination is also performed by software processing of the central processing unit.

[2] <Reproducing control data from voltage signal>
In the signal detection system according to item 1, the determination circuit receives the voltage signal and reproduces the control value, and reproduces the reproduction control value, and the corresponding reproduction control value indicated by the central processing unit. And a discriminator (402, 403, 404) for discriminating whether or not the difference from the control value is within the allowable error range.

  According to this, since the corresponding control value inside is reproduced from the voltage signal generated outside the data processing circuit and used for the determination process, the determination process becomes easy.

[3] <PWM circuit, inverter>
In the signal detection system according to Item 2, the voltage control circuit is a PWM circuit (20) that generates a voltage control signal having a PWM waveform based on control data (Ddty, Dcyc) for determining a duty as the control value. The power supply circuit is an inverter (2) that generates the AC voltage signal according to the PWM waveform.

  Thereby, a required alternating voltage signal can be easily obtained by the PWM waveform and the inverter.

[4] <AD conversion and duty calculation>
In the signal detection system according to Item 3, the reproduction unit converts an AD converter (408) that converts the voltage signal into a digital signal, and converts the AD conversion result by the AD converter into the maximum conversion of the voltage signal by the AD converter. And an arithmetic unit (401) that calculates the duty by dividing by the value.

  According to this, the information necessary for the regeneration of the control value in addition to the voltage signal is the maximum conversion value of the voltage signal by the AD converter, and it is not necessary to obtain external information such as the value of the maximum output voltage of the inverter. Therefore, it is possible to easily reproduce the duty for discrimination. If the control value instructed to the voltage control circuit is converted into a voltage signal to determine an error from the fed back voltage signal, the maximum output voltage of the inverter must be obtained individually.

[5] <A/D conversion sample hold timing setting>
In the signal detection system according to item 4, the AD converter waits for the delay time set in the delay setting register (300) to elapse with respect to the generation timing of the voltage control signal in units of cycles by the voltage control circuit. Sample and hold the voltage signal.

  According to this, it is possible to easily set the sample hold timing according to the input delay of the voltage signal generated and fed back by the power supply circuit outside the data processing circuit.

[6] <Setting tolerance>
In the signal detection system according to Item 5, the non-discrimination unit defines a range specified by a set value of the allowable error register (301) with respect to the duty indicated by the control data supplied to the voltage control circuit as an allowable error range. To do.

  According to this, the allowable error can be easily set according to the degree of the influence that the accuracy of the voltage signal has on the operation circuit.

[7] <Programmable register by CPU>
In the signal detection system according to item 6, the delay setting register and the allowable error register are rewritable registers by the central processing unit.

  According to this, the sample hold timing and the allowable error can be easily set or changed according to the program of the central processing unit.

[8] <Interrupt request>
In the signal detection system according to Item 1, the detection control circuit issues an interrupt request (IRQ) to the central processing unit when a determination result that is out of the allowable error range is acquired from the determination circuit a predetermined number of times.

  According to this, it is possible to cope with the processing for the abnormality of the voltage signal by the desired interrupt processing defined by the program. In addition, a state that is regarded as an abnormality requiring interrupt processing can be determined according to the number of times that a deviation of the allowable error is detected, and the flexibility in detecting an abnormality is high.

[9] <Flag operation that can be referred to by the CPU>
In the signal detection system according to item 1, the detection control circuit sets a flag that can be referred to by the central processing unit when a determination result that is out of the allowable error range is obtained from the determination circuit a predetermined number of times.

  According to this, the detected abnormality can be dealt with without interrupting the processing of the central processing unit due to the interruption. The set flag may be referred to by the central processing unit by polling or the like.

[10] <Resolver>
In the signal detection system of item 1, the operating circuit generates a resolver signal (Vsin, Vcos) obtained by amplitude-modulating the voltage signal in accordance with a rotation angle of a rotation detection shaft coupled to a rotor of a motor (4). (3). The central processing unit detects the rotation angle of the rotor based on the resolver signal and performs rotation drive control of the motor.

  According to this, in a system in which the rotation angle is detected by a resolver to control the drive of the motor, the abnormality of the system is discriminated according to the error of the voltage signal to which reference is made before the resolver signal becomes abnormal. Is possible.

[11] <Resolver signal processing device>
A resolver signal processing device according to another embodiment includes a microcomputer (1) and an inverter (2) that generates an AC voltage signal (Vext) according to a PWM waveform of a voltage control signal (Spwm) generated by the microcomputer. And a resolver (3) that generates a resolver signal (Vsin, Vcos) by amplitude-modulating the voltage signal in accordance with the rotation angle of the rotation detection shaft coupled to the rotor of the motor (4). The microcomputer has the following circuits. Central processing unit (10) for executing the program. A PWM circuit (20) for generating a voltage control signal (Spwm) having a PWM waveform based on control data (Ddty, Dcyc) for determining a duty given from the central processing unit. A first AD converter circuit (50) for inputting the resolver signal and converting it into a digital signal. A second AD converter circuit (408) for converting the voltage signal into a digital signal; An arithmetic circuit (401) that calculates a duty by dividing an AD conversion result (Dadc) by the second AD conversion circuit by a maximum conversion value (Dmax) of the voltage signal by the second AD conversion circuit. A discriminating circuit (402, 403, 404) for discriminating whether or not the difference between the duty calculated by the arithmetic circuit and the duty specified by the control data corresponding thereto is within an allowable error range. A detection control circuit (303) for causing the central processing unit to recognize a discrimination result by the discrimination circuit; The central processing unit performs processing for detecting the rotation angle of the rotor based on the resolver signal, processing for controlling the rotational drive of the motor, and processing according to the determination result recognized via the detection control circuit.

  According to this, there exists an effect similar to claim | item 1 thru | or claim | item 4, and claim | item 9.

[12] <Setting of AD hold sample hold timing and allowable error>
In the resolver signal processing system according to item 11, the second AD converter circuit determines the passage of the delay time set in the delay setting register (300) with respect to the generation timing of the voltage control signal in units of cycles by the voltage control circuit. Wait and sample and hold the reference voltage signal. The determination circuit sets a range specified by a set value of the allowable error register (301) for a duty indicated by control data supplied to the voltage control circuit as a range of allowable error.

  According to this, there exists an effect similar to item 5 and 6.

[13] <Programmable register by CPU>
In the resolver signal processing circuit according to item 12, the delay setting register and the allowable error register are rewritable registers by the central processing unit.

  According to this, there exists an effect similar to item 7.

[14] <Interrupt request>
In the resolver signal processing system according to item 11, the detection control circuit issues an interrupt request (IRQ) to the central processing unit when a determination result that is out of an allowable error range is acquired from the determination circuit a predetermined number of times.

  According to this, there exists an effect similar to item 8.

[15] <Flag operation that can be referred to by the CPU>
In the resolver signal processing system according to item 11, the detection control circuit sets a flag that can be referred to by the central processing unit when a determination result that is out of the allowable error range is acquired from the determination circuit a predetermined number of times.

  According to this, there exists an effect similar to item 9.

[16] <Semiconductor integrated circuit>
The semiconductor integrated circuit (1) according to another embodiment outputs the voltage control signal (Spwm), and indicates the generation state of the AC voltage signal (Vext) generated by the external circuit (2) by the voltage control signal. It can be detected. This semiconductor integrated circuit has the following circuits. Central processing unit (10) for executing the program. A voltage control circuit (20) for generating the voltage control signal according to a control value instructed by the central processing unit; A determination circuit (40) for determining whether or not the voltage signal generated by the external circuit is within an allowable error range with respect to a control value corresponding to the voltage signal. A detection control circuit (303) for causing the central processing unit to execute a necessary process when a determination result by the determination circuit is not within an allowable error range;

  According to this, it can contribute to easy realization of the data processing circuit of item 1. That is, a voltage signal generated outside the semiconductor integrated circuit is fed back to the semiconductor integrated circuit, and based on a determination result of whether or not the fed back voltage signal is within an allowable error range with respect to a corresponding control value. Thus, the abnormality of the voltage signal generated by the external circuit can be detected outside the semiconductor integrated circuit. Since the central processing unit of the semiconductor integrated circuit only needs to execute processing according to the determination result, the determination can also contribute to speeding up the processing compared to the case where the determination is performed by software processing of the central processing unit.

[17] <Reproducing control data from voltage signal>
Item 16. The semiconductor integrated circuit according to Item 16, wherein the discriminating circuit receives the voltage signal from the outside and reproduces the control value, and reproduces the reproduction control value and the central processing unit instructed by the reproduction unit (401, 408). A discriminator (402, 403, 408) for discriminating whether or not the difference from the corresponding control value is within an allowable error range.

  According to this, the discrimination process becomes easy as in the case of item 2.

[18] <PWM circuit, inverter>
In the semiconductor integrated circuit of Item 17, the voltage control circuit is a PWM circuit that generates a voltage control signal having a PWM waveform based on control data (Ddty, Dcyc) indicating a cycle and a duty.

  This is suitable for generating an AC voltage signal in an external circuit, as in item 3.

[19] <AD conversion and duty calculation>
Item 18. The semiconductor integrated circuit of Item 18, wherein the circuit to be reproduced includes an AD converter (408) that converts the voltage signal into a digital signal, and an AD conversion result obtained by the AD converter. And an arithmetic unit (401) that calculates the duty by dividing by the converted value.

  According to this, similarly to the item 4, it is possible to easily reproduce the duty for discrimination.

[20] <AD conversion sample hold timing setting>
In the semiconductor integrated circuit of Item 19, the AD converter waits for the elapse of the delay time set in the delay setting register (300) with respect to the generation timing of the voltage control signal in units of cycles by the voltage control circuit. Sample and hold the voltage signal.

  According to this, similarly to the item 5, it is possible to easily set the sample hold timing in accordance with the input delay of the voltage signal generated and fed back externally.

[21] <Setting tolerance>
In the semiconductor integrated circuit of item 20, the determination unit sets a range specified by a setting value of the allowable error register (301) with respect to the duty indicated by the control data supplied to the voltage control circuit as a range of allowable error. .

  According to this, like the item 6, the allowable error can be easily set according to the degree of the influence of the decrease in the accuracy of the voltage signal.

[22] <Programmable register by CPU>
In the semiconductor integrated circuit of item 21, the delay setting register and the allowable error register are registers rewritable by the central processing unit.

  According to this, the same effect as that of Item 7 is obtained.

[23] <Interrupt request>
In the semiconductor integrated circuit of item 16, the detection control circuit makes an interrupt request (IRQ) to the central processing unit when a determination result that is out of the allowable error range is acquired from the determination circuit a predetermined number of times.

  According to this, there exists an effect similar to item 8.

[24] <Flag operation that can be referred to by CPU>
In the semiconductor integrated circuit of item 16, the detection control circuit sets a flag that can be referred to by the central processing unit when a determination result outside the allowable error range is acquired from the determination circuit a predetermined number of times.

  According to this, there exists an effect similar to item 9.

[25] <Resolver>
In the semiconductor integrated circuit of Item 16, a resolver signal (Vsin, Vcos) in which an AC voltage signal generated by the external power supply circuit is amplitude-modulated according to the rotation angle of the motor shaft is input from the resolver (3). The central processing unit detects a rotation angle of the motor shaft on the basis of the resolver signal and performs rotation drive control of the motor.

  According to this, similarly to the item 10, when applied to a system that detects the rotation angle by the resolver and controls the drive of the motor, the semiconductor integrated circuit can detect the voltage that it refers to before the resolver signal becomes abnormal. The system abnormality can be determined according to the signal error.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 1 illustrates a resolver signal processing device according to an embodiment. The resolver signal processing device shown in the figure is a device that measures the rotational displacement using a change in electromagnetic induction, and is not particularly limited, but it generates a steering assist torque for electric power steering (EPS). A signal detection system that detects a rotation angle of a motor to be used by using a resolver is applied.

  The resolver signal processing device is a DC that is an example of a power supply circuit together with a microcomputer 1 that constitutes an ECU (electronic control unit) for EPS connected to an in-vehicle LAN (Local Area Network) such as a CAN (Controller Area Network). -It has AC type inverter 2 and resolver 3. The microcomputer 1 gives a PWM signal Spwm to the inverter 2 as a voltage control signal. The inverter 2 supplies the resolver 2 with, for example, a sine wave voltage signal (also referred to as a resolver excitation voltage signal) Vext as a resolver excitation signal. Since the configuration of the resolver 2 is well known, detailed description thereof will be omitted here. However, when the resolver excitation voltage signal Vext is applied to the rotor winding of the rotor coupled to the rotating shaft of the motor 4, a phase difference of 90 ° C. Resolver signals Vsin and Vcos having a phase difference of 90 ° C. that are amplitude-modulated in accordance with the rotation angle of the rotor are obtained for each of the two stator windings arranged in the above. The microcomputer 1 detects the rotation angle of the motor 4 based on the resolver signals Vsin and Vcos, and controls the driving of the motor 4. Further, the microcomputer 1 receives the resolver excitation voltage signal Vext and performs processing for detecting an abnormality in the resolver excitation voltage signal Vext itself. That is, in this detection process, the PWM signal Spwm output from the microcomputer 1 is input to the inverter 2, so that there is some abnormality or voltage on the path until the resolver excitation voltage signal Vext generated by the inverter 2 is transmitted to the resolver. It is detected whether any factor that reduces the generation operation accuracy occurs. The microcomputer 1 performs necessary processing according to the detection result.

  The detection process will be further described in detail.

  The microcomputer 1 is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique.

  The microcomputer 1 has a central processing unit 10 that executes a program. Here, the central processing unit 10 may be grasped as a processor core, and may further include an accelerator such as a floating point arithmetic unit, a cache memory, and an address conversion buffer in addition to a so-called CPU. A program memory for storing a program executed by the CPU 10 and a work RAM are not shown.

  Various peripheral circuits are connected to the CPU 10, and here, a circuit for controlling the resolver 3 and the motor 4 is typically shown. 20 is a PWM circuit, 30 is a control circuit, 40 is a discrimination circuit, 50 is an analog-digital conversion circuit (ADC), 60 is a motor drive control circuit, and 70 is a network interface connected to an in-vehicle network.

  The PWM circuit 20 has a duty count value register 200 in which the duty count value Ddty is sequentially set as control data for determining the duty from the central processing unit 10, and a cycle count value register 201 in which the cycle count value Dcyc is sequentially set. The cycle count value Dcyc defines the cycle of the PWM signal Spwm, and the duty count value Ddty defines the high level period of the PWM signal Spwm. The counter 203 has a sufficient number of count bits to count the cycle count value Dcyc corresponding to the maximum cycle of the PWM signal Spwm. The comparison circuit 202 compares the count value of the counter 203 with the set values of the respective registers 200 and 201, and controls the output operation of the output circuit 204 that outputs the PWM signal Spwm and the count operation of the counter according to the comparison result. That is, when the counter 203 is cleared to the initial value zero, the comparison circuit 202 causes the output circuit 204 to set the PWM signal Spwm to the high level. When the count value of the counter 203 matches the duty count value Ddty, the comparison circuit 202 causes the output circuit 204 to invert the PWM signal Spwm to a low level. When the count value of the counter 203 coincides with the cycle count value Dcyc, the comparison circuit 202 clears the count value of the counter 203 to the initial value zero, whereby the output circuit 204 inverts the PWM signal Spwm to the high level, and the PWM signal One cycle of the Spwm PWM waveform is completed. The CPU 10 sequentially changes the values of the registers 200 and 201 in units of the period of the PWM signal Spwm. When the period of the PWM signal Spwm is fixed, the period count value Dcyc need only be initialized. As a result, for example, as illustrated in FIG. 2, a sine wave resolver excitation voltage signal Vext is output from the inverter 2 in accordance with the duty of the PWM signal Spwm.

  The determination circuit 40 includes a duty calculation circuit 400 for calculating a duty as a control value indicated by control data (duty count value Ddty, cycle count value Dcyc) set in the PWM circuit 20, and a resolver excitation voltage signal Vext. An analog-digital conversion circuit (ADC) 408 and a duty calculation circuit 401 for reproducing the duty based on the above are included. An analog-digital conversion circuit (ADC) 408 converts the resolver excitation voltage signal Vext into digital voltage data Dadc. The duty calculation circuit 401 divides the digital voltage data Dadc by the maximum voltage data (digital voltage data Dadc corresponding to Vext when the duty is 100%) Dmax to reproduce the duty. The reproduced duty is also referred to as a reproduction duty DTY_R. The duty calculation circuit 400 obtains the duty DTY_I indicated by the control data by dividing the duty count value Ddty set in the register 200 by the cycle count value Dcyc set in the register 201.

  In order to make the reproduction duty DTY_R correspond to the duty DTY_I, a delay circuit 407 for delaying the sample hold timing of the resolver excitation voltage signal Vext by the ADC 408 and a trigger delay value register 300 for setting the delay time are provided. The delay circuit 407 is configured by, for example, a down counter in which a delay value set in the trigger delay value register 300 is preset. The down counter 407 starts down counting when the count trigger signal Strgc is activated. When the count value reaches zero, the down counter 407 activates the signal Strgs and causes the ADC 408 to sample and hold the resolver excitation voltage signal Vext. When the count value reaches zero, the count value of the down counter 407 is returned to the preset value to prepare for the next down count operation. The delay value set in the trigger delay value register 300 is count value data for securing the delay time illustrated in FIG. 3 by the down-counting operation of the down counter 407. This delay time is determined depending on the characteristics of the wiring board on which the apparatus of FIG. 1 is mounted, the wiring delay, and the operating characteristics of the inverter 2. Thereby, the sample hold timing of the ADC 408 can be easily set according to the input delay of the resolver excitation voltage signal Vext generated and fed back by the inverter 2 outside the microcomputer 1.

  The determination circuit 40 includes an upper limit duty register 402, a lower limit duty register 403, and a comparison circuit 404 to determine whether or not the difference between the reproduction duty DTY_R and the duty DTY_I corresponding to the reproduction duty DTY_R is within the allowable error range. . The allowable error is determined by the allowable error data set in the allowable error register 301. The allowable error data is data of the same dimension as the duty, and if the reproduction duty DTY_R and the duty DTY_I are in units of percent, they are the same. The adder 405 adds the error data to the duty DTY_I and sets it in the register 402, and the subtractor 406 subtracts the error data from the duty DTY_I and sets it in the register 403. The comparison circuit 404 sets the allowable error range when the reproduction duty DTY_R is larger than the set value of the register 403 and smaller than the set value of the register 402, and determines whether or not the reproduction duty DTY_R is within the allowable error range. The error signal ERR is activated every time when it is outside the allowable error range.

  The detection control circuit 303 causes the central processing unit 10 to recognize the determination result by the error signal ERR by the determination circuit 40. For example, the detection control circuit 303 requests an interrupt to the CPU 10 by the interrupt request signal IRQ when the determination result that is outside the allowable error range is obtained from the determination circuit 40 a predetermined number of times. Thereby, the processing for the abnormality of the resolver excitation voltage signal Vext can be dealt with by a desired interrupt processing defined by the program. In addition, a state that is regarded as an abnormality requiring interrupt processing can be determined according to the number of times that a deviation of the allowable error is detected, and the flexibility in detecting an abnormality is high. Such a detection count may be indicated by a set value of the detection count register 302. The detection number register 302 has a register mapping that can be rewritten by the CPU 10 together with the trigger delay value register 300 and the allowable error register 301. Accordingly, the sample hold timing and allowable error can be easily set or changed according to the program of the CPU 10.

  Although not specifically shown, the detection control circuit 303 sets a flag that can be referred to by the CPU 10 when a determination result that is outside the allowable error range is obtained from the determination circuit 40 a predetermined number of times, thereby determining the error signal ERR. The result may be recognized by the CPU 10. The detected abnormality can be dealt with without interrupting the processing of the CPU 10 by the interruption. The set flag may be referred to by the CPU 10 by polling or the like.

  The motor drive control circuit 60 includes a timer, a motor driver, and the like. For example, the motor drive control circuit 60 generates a three-phase motor drive signal using the timer and supplies it to the motor 4. The analog-digital conversion circuit 50 converts the resolver signals Vsin and Vcos output from the resolver 3 into digital signals and gives them to the CPU 10. The CPU 10 calculates the rotation angle of the motor 4 based on it, and controls the rotation speed and rotation position of the motor based on it. At this time, the abnormality of the resolver excitation voltage signal Vext can be transmitted to the CPU 10 via the determination circuit 40 and the detection control circuit 303, and a large burden is not imposed on the CPU 10. Naturally, it is possible to detect the abnormality of the resolver excitation voltage signal Vext based on the detected rotation angle of the motor, but this places a heavy burden on the software processing of the CPU 10, and in parallel with the rotation drive control of the motor. Due to the nature that must be present, it is assumed that it takes a lot of data processing time to detect an abnormality. Therefore, according to this embodiment, it is possible to quickly detect the occurrence of abnormality from the generation of the PWM signal Spwm to the propagation of the resolver excitation voltage signal Vext.

  In particular, when the abnormality of the resolver excitation voltage signal Vext is detected exclusively by software processing based on the resolver signals Vsin and Vcos, it is necessary to accumulate the information output from the resolver 3 and determine the abnormality. It was difficult to determine whether the abnormality was the inverter 2 or the resolver 3 or the motor 4. In this respect, software processing that isolates the abnormality of the resolver excitation voltage signal Vext in software processing is not required at all. Therefore, in the EPS system that needs to detect an abnormality in a short time and perform safety processing, A signal detection system according to form is preferred.

  In the above embodiment, since the duty used for the internal control of the microcomputer 1 is reproduced from the resolver excitation voltage signal Vext generated outside the microcomputer 1 and used for the abnormality determination process, the determination process becomes easy.

  In particular, in addition to the AD conversion result Dadc of the resolver excitation voltage signal Vext, information necessary for duty recovery is the maximum conversion value Dmax of the voltage signal by the ADC 408, and external information such as the maximum output voltage value of the inverter 2 is obtained. Therefore, it is possible to easily reproduce the duty for discrimination. If the control data Ddty and Dcyc given to the PWM circuit 20 are converted into voltage signals to determine an error from the fed back resolver excitation voltage signal Vext, the maximum output voltage of the inverter 2 is obtained individually. There must be.

  It goes without saying that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  For example, although not shown, the generation of the trigger signal in the comparison circuit 202 is not limited to each PWM cycle, and can be performed every predetermined number of times. For example, a counter that counts the trigger signal Strgc in FIG. 1 may be provided, and when the count value of the counter reaches a predetermined value, the start of the downcount operation for the downcounter 407 may be indicated. As a result, it can be used as a periodic health check mechanism for the resolver excitation voltage signal Vext. The abnormality detection of the resolver excitation voltage signal Vext is not limited to being performed at any time, and may be operable in conjunction with the test mode setting at the time of initial failure test, initial diagnosis, failure diagnosis, and the like.

  The delay circuit 407 is not limited to a down counter and can be changed as appropriate.

  Although the resolver excitation voltage signal Vext is easily acquired by the PWM waveform and the inverter, the generation of the AC voltage signal is not limited thereto, and a power supply circuit that generates the AC voltage signal by multiplying the stepped control voltage may be used. .

  The signal detection system and the microcomputer 1 are not limited to application to EPS. The present invention can be widely applied to other motor control systems and systems using AC voltage as a drive power source.

DESCRIPTION OF SYMBOLS 1 Microcomputer 2 Inverter 3 Resolver Spwm PWM signal Vext Resolver excitation voltage signal 4 Motor Vsin, Vcos Resolver signal 10 Central processing unit 20 PWM circuit 30 Control circuit 40 Discriminating circuit 50 Analog digital conversion circuit 60 Motor drive control circuit 70 Network interface Ddty Duty Count value 200 Duty count value register Dcyc Period count value 201 Period count value register 202 Comparison circuit 203 Counter 204 Output circuit 400, 401 Duty calculation circuit Dadc Digital voltage data Dmax Maximum voltage data 408 Analog-digital conversion circuit 700 Down counter DTY_R Reproduction duty DTY_I Duty corresponding to playback duty Duty register 403 lower duty register 404 comparator circuit 303 detects the control circuit 302 detects the number of registers

Claims (25)

A data processing circuit;
A power supply circuit that generates an alternating voltage signal based on the voltage control signal generated by the data processing circuit;
An actuating circuit actuated upon receiving the voltage signal,
The data processing circuit includes a central processing unit that executes a program;
A voltage control circuit that generates the voltage control signal based on a control value instructed from the central processing unit;
A determination circuit for determining whether or not a voltage signal output from the power supply circuit is within an allowable error range with respect to a corresponding control value;
A signal detection system comprising: a detection control circuit that causes the central processing unit to execute processing necessary when a determination result by the determination circuit is not within an allowable error range. The discrimination circuit receives the voltage signal and reproduces the control value;
The signal detection system according to claim 1, further comprising: a determination unit that determines whether or not a difference between the reproduced reproduction control value and a corresponding control value instructed by the central processing unit is within an allowable error range. The voltage control circuit is a PWM circuit that generates a voltage control signal having a PWM waveform based on control data for determining a duty as the control value,
The signal detection system according to claim 2, wherein the power supply circuit is an inverter that generates the AC voltage signal according to the PWM waveform.   The reproduction unit includes an AD converter that converts the voltage signal into a digital signal, and an arithmetic unit that calculates a duty by dividing an AD conversion result by the AD converter by a maximum conversion value of the voltage signal by the AD converter. The signal detection system according to claim 3.   5. The AD converter samples and holds a voltage signal after a delay time set in a delay setting register elapses with respect to a generation timing of the voltage control signal in a cycle unit by the voltage control circuit. The signal detection system described.   The signal detection system according to claim 5, wherein the determination unit sets a range specified by a set value of an allowable error register for a duty indicated by control data supplied to the voltage control circuit as a range of allowable error.   The signal detection system according to claim 6, wherein the delay setting register and the allowable error register are rewritable registers by the central processing unit.   The signal detection system according to claim 1, wherein the detection control circuit issues an interrupt request to the central processing unit when a determination result that is out of an allowable error range is acquired from the determination circuit a predetermined number of times.   The signal detection system according to claim 1, wherein the detection control circuit sets a flag that can be referred to by the central processing unit when a determination result that is out of the allowable error range is acquired a predetermined number of times from the determination circuit. The operating circuit is a resolver that generates a resolver signal obtained by amplitude-modulating the voltage signal in accordance with a rotation angle of a rotation detection shaft coupled to a rotor of a motor.
2. The signal detection system according to claim 1, wherein the central processing unit detects a rotation angle of the rotor based on the resolver signal and controls rotation drive of the motor. A microcomputer,
An inverter that generates an AC voltage signal according to a PWM waveform of the voltage control signal generated by the microcomputer;
A resolver that generates a resolver signal by amplitude-modulating the voltage signal according to a rotation angle of a rotation detection shaft coupled to a rotor of a motor;
The microcomputer includes a central processing unit that executes a program;
A PWM circuit that generates a voltage control signal of a PWM waveform according to control data for determining a duty given from the central processing unit;
A first AD converter circuit for inputting the resolver signal and converting it into a digital signal;
A second AD converter circuit for converting the voltage signal into a digital signal;
An arithmetic circuit that calculates a duty by dividing an AD conversion result by the second AD conversion circuit by a maximum conversion value of the voltage signal by the second AD conversion circuit;
A discriminating circuit for discriminating whether or not the difference between the duty calculated by the arithmetic circuit and the duty specified by the control data corresponding to the duty is within the allowable error range;
A detection control circuit that causes the central processing unit to recognize a determination result by the determination circuit;
The central processing unit performs processing for detecting the rotation angle of the rotor based on the resolver signal, processing for controlling the rotational drive of the motor, and processing according to the determination result recognized through the detection control circuit. Resolver signal processing system. The second AD converter circuit samples and holds the reference voltage signal after the delay time set in the delay setting register elapses with respect to the generation timing of the voltage control signal in the period by the voltage control circuit,
12. The resolver signal processing system according to claim 11, wherein the determination circuit sets a range specified by a set value of an allowable error register for a duty indicated by control data supplied to the voltage control circuit as a range of allowable error.   The resolver signal processing system according to claim 12, wherein the delay setting register and the allowable error register are registers rewritable by the central processing unit.   The resolver signal processing system according to claim 11, wherein the detection control circuit issues an interrupt request to the central processing unit when a determination result that is out of an allowable error range is acquired a predetermined number of times from the determination circuit.   12. The resolver signal processing system according to claim 11, wherein the detection control circuit sets a flag that can be referred to by the central processing unit when a determination result that is out of an allowable error range is acquired a predetermined number of times from the determination circuit. A semiconductor integrated circuit that outputs a voltage control signal and enables detection of a generation state of an AC voltage signal generated by an external circuit based on the voltage control signal,
A central processing unit for executing the program;
A voltage control circuit that generates the voltage control signal according to a control value instructed by the central processing unit;
A determination circuit for determining whether or not the voltage signal generated by the external circuit is within an allowable error range with respect to a control value corresponding thereto;
And a detection control circuit that causes the central processing unit to execute a necessary process when a determination result by the determination circuit is not within an allowable error range. The discrimination circuit receives the voltage signal from the outside and reproduces the control data;
17. The semiconductor integrated circuit according to claim 16, further comprising: a discriminator that discriminates whether or not a difference between the reproduced reproduction control value and a corresponding control value instructed by the central processing unit is within an allowable error range.   18. The semiconductor integrated circuit according to claim 17, wherein the voltage control circuit is a PWM circuit that generates a voltage control signal having a PWM waveform based on control data for determining a duty as the control value.   The reproducing circuit includes an AD converter that converts the voltage signal into a digital signal, and an operation for calculating a duty by dividing an AD conversion result by the AD converter by a maximum conversion value of the voltage signal by the AD converter. The semiconductor integrated circuit according to claim 18, further comprising:   The AD converter samples and holds the voltage signal after the delay time set in the delay setting register elapses with respect to the generation timing of the voltage control signal in units of cycles by the voltage control circuit. The semiconductor integrated circuit as described.   21. The semiconductor integrated circuit according to claim 20, wherein the determination unit sets a range specified by a set value of an allowable error register for a duty indicated by control data supplied to the voltage control circuit as a range of allowable error.   23. The semiconductor integrated circuit according to claim 21, wherein the delay setting register and the allowable error register are rewritable registers by the central processing unit.   17. The semiconductor integrated circuit according to claim 16, wherein the detection control circuit issues an interrupt request to the central processing unit when a determination result that is out of an allowable error range is obtained a predetermined number of times from the determination circuit.   The semiconductor integrated circuit according to claim 16, wherein the detection control circuit sets a flag that can be referred to by the central processing unit when a determination result that is out of an allowable error range is obtained a predetermined number of times from the determination circuit. The resolver signal in which the AC voltage signal generated by the external power supply circuit is amplitude-modulated according to the rotation angle of the motor shaft is input from the resolver,
17. The semiconductor integrated circuit according to claim 16, wherein the central processing unit detects a rotation angle of the motor shaft based on the resolver signal and performs rotation drive control of the motor.

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