JP6943222B2 - Semiconductor devices, optical printheads, and image forming devices - Google Patents

Description

The present invention relates to a semiconductor device having a plurality of light emitting thyristors, an optical print head having the semiconductor device, and an image forming device having an optical print head.

Conventionally, an optical print head having a plurality of light emitting element array chips has been used as an exposure apparatus in an electrophotographic image forming apparatus. Each light emitting element array chip has, for example, a plurality of three-terminal light emitting elements, that is, a plurality of light emitting thyristors arranged in the longitudinal direction of the base material on the base material (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2010-239084 (see, for example, FIG. 9).

Generally, in the same light emitting element array chip, the amount of light (that is, light emission intensity) emitted from the light emitting thyristor closest to both ends in the longitudinal direction of the base material among the plurality of light emitting thyristors arranged on the base material is determined. It is larger than the amount of light emitted from a light emitting thyristor other than the light emitting thyristor closest to both ends. As a countermeasure, it is conceivable to suppress the amount of light by reducing the drive current supplied to the light emitting thyristor closest to both ends. However, when the light emitting element array chip is continuously driven, the amount of light emitted from the light emitting thyristor fluctuates with the driving time, and the amount of fluctuation depends on the current value of the driving current. Therefore, when the current value of the drive current is set to a different value for each light emitting thyristor, the amount of light emitted from the plurality of light emitting thyristors varies.

The present invention has been made to solve the above problems, and is a semiconductor device capable of reducing the variation in the amount of light emitted from a plurality of light emitting thyristors, an optical print head having this semiconductor device, and the present invention. It is an object of the present invention to provide an image forming apparatus having an optical print head.

The semiconductor device according to one aspect of the present invention has a base material portion and a plurality of light emitting thyristers provided on the base material portion and arranged at intervals in the longitudinal direction of the base material portion. Among the plurality of light emitting psyllistas, the first element, which is the light emitting thylister closest to the longitudinal end of the base material portion, includes a first conductive type first semiconductor layer and the first conductive type. The second semiconductor layer of the second conductive type, the third semiconductor layer of the first conductive type, and the fourth semiconductor layer of the second conductive type are formed from the base material portion side to the fourth semiconductor layer. The first element among the plurality of light emitting thyristers, which has a first semiconductor multilayer structure in which the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer are laminated in this order. The second element, which is a light emitting thylister other than the above, includes a first conductive type fifth semiconductor layer, a second conductive type sixth semiconductor layer, a first conductive type seventh semiconductor layer, and a second. The conductive type eighth semiconductor layer is laminated in this order from the base material side to the eighth semiconductor layer, the seventh semiconductor layer, the sixth semiconductor layer, and the fifth semiconductor layer. A second surface having two semiconductor multilayer structures, including a first surface including an end face of the first semiconductor layer on the side close to the end portion and an end face of the third semiconductor layer on the side close to the end portion. The first distance between the surfaces is the third surface including the end surface of the first semiconductor layer on the side far from the end and the end surface of the third semiconductor layer on the side far from the end. The seventh semiconductor layer on one side of the fifth surface and the seventh surface including the end face of the fifth semiconductor layer on one side in the longitudinal direction, which is smaller than the second distance between the fourth surface including the semiconductor layer. The third distance between the sixth surface including the end face of the fifth semiconductor layer is the seventh surface including the end face of the fifth semiconductor layer on the other side opposite to the one side and the said on the other side. The second distance is equal to the fourth distance to the eighth surface including the end face of the seventh semiconductor layer, and the second distance is equal to the third distance.

According to the present invention, it is possible to reduce the variation in the amount of light emitted from a plurality of light emitting thyristors in the same semiconductor device.

It is a schematic plan view which shows the light emitting element array chip as the semiconductor device which concerns on 1st Embodiment of this invention. It is a schematic cross-sectional view which shows the cross-sectional structure which cuts the light emitting element array chip of FIG. 1 by 2A-2A line and 2B-2B line. It is schematic cross-sectional view (the 1) which shows the manufacturing method of the multilayer semiconductor layer in which the light emitting thyristor which concerns on 1st Embodiment is formed. It is schematic cross-sectional view (the 2) which shows the manufacturing method of the multilayer semiconductor layer in which the light emitting thyristor which concerns on 1st Embodiment is formed. FIG. 3 is a schematic cross-sectional view (No. 3) showing a method of manufacturing a multilayer semiconductor layer on which a light emitting thyristor according to a first embodiment is formed. It is a schematic cross-sectional view which shows the cross-sectional structure which cuts the light emitting element array chip of FIG. 1 by line 2B-2B. It is a schematic plan view which shows the light emitting element array chip of the comparative example. It is a schematic cross-sectional view which shows the cross-sectional structure which cuts the light emitting element array chip of FIG. 7 by line 8A-8A and line 8B-8B. It is explanatory drawing which shows roughly the amount of light of the light emitted from the light emitting thyristor of the light emitting element array chip of the comparative example. It is explanatory drawing which shows roughly the light intensity and light intensity distribution of the light emitted from the light emitting thyristor of the light emitting element array chip of the comparative example. It is explanatory drawing which shows typically the amount of light of the light emitted from the light emitting thyristor of the light emitting element array chip which concerns on 1st Embodiment. It is explanatory drawing which shows the light intensity and light intensity distribution of the light emitted from the light emitting thyristor of the light emitting element array chip of the comparative example (FIG. 7) and 1st Embodiment (FIG. 6). It is a schematic cross-sectional view which shows the light emitting element array chip as the semiconductor device which concerns on 2nd Embodiment of this invention. It is a schematic cross-sectional view which shows the light emitting element array chip as the semiconductor device which concerns on 3rd Embodiment of this invention. It is a schematic cross-sectional view which shows the light emitting element array chip as the semiconductor device which concerns on 4th Embodiment of this invention. It is a schematic plan view which shows the light emitting element array chip as the semiconductor device which concerns on 5th Embodiment of this invention. It is a schematic cross-sectional view which shows the cross-sectional structure which cuts the light emitting element array chip of FIG. 16 by line 17A-17A and line 17B-17B. It is the schematic cross-sectional view which shows the cross-sectional structure which cuts the light emitting element array chip of FIG. 16 by line 17B-17B. It is explanatory drawing which shows typically the amount of light of the light emitted from the light emitting thyristor of the light emitting element array chip of 5th Embodiment. It is explanatory drawing which shows roughly the light intensity and light intensity distribution of the light emitted from the light emitting thyristor of the light emitting element array chip of the comparative example (FIG. 7) and the fifth embodiment (FIG. 18). It is explanatory drawing which shows the light intensity and light intensity distribution of the light emitted from the light emitting thyristor of the light emitting element array chip of 1st Embodiment (FIG. 6) and 5th Embodiment (FIG. 18). It is a schematic perspective view which shows the main part of the optical print head which concerns on 6th Embodiment of this invention. It is schematic cross-sectional view which shows the structure of the optical print head which concerns on 6th Embodiment. It is a schematic cross-sectional view which shows the structure of the image forming apparatus which concerns on 7th Embodiment of this invention.

Hereinafter, the light emitting element array chip, the optical print head, and the image forming apparatus, which are the semiconductor devices according to the embodiment of the present invention, will be described with reference to the accompanying drawings. The following embodiments are merely examples, and various modifications can be made within the scope of the present invention.

<< 1 >> First Embodiment << 1-1 >> Light emitting element array chip FIG. 1 is a schematic plan view showing a light emitting element array chip 10 as a semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view showing a cross-sectional structure in which the light emitting element array chip 10 shown in FIG. 1 is cut along the lines 2A-2A and 2B-2B.

As shown in FIG. 1 or 2, the light emitting element array chip 10 includes a base material 151, a flattening layer 152 formed on the base material 151, and a plurality of three-terminal light emitting elements, that is, a plurality of light emitting thyristors 100_1, ... , 100_n. n is an integer of 2 or more. Further, the base material 151 and the flattening layer 152 form a base material portion 150 on which a plurality of light emitting thyristors 100_1, ..., 100_n, that is, a semiconductor multilayer structure 110 is formed.

The luminescent thyristors 100_1, ..., 100_n are arranged on the flattening layer 152 of the base material portion 150. The luminescent thyristors 100_1, ..., 100_n are regularly (for example, evenly spaced) arranged at intervals in the longitudinal direction of the base material portion 150, that is, the longitudinal direction of the base material 151 (horizontal direction in FIG. 1 or 2). NS. A drive IC, which is an integrated circuit for driving the light emitting thyristors 100_1, ..., 100_n, may be provided inside the base material 151 and below the flattening layer 152. A plurality of electrode pads 153 and electrode wiring (not shown) are provided on the base material 151. The base material 151 is formed of, for example, Si (silicon) and has a thickness of, for example, 250 μm.

The surface of the flattening layer 152 is flattened. The flattening layer 152 is formed of, for example, an organic film, an inorganic film, a metal, or the like, and has a thickness of, for example, 2.00 μm. The surface roughness (that is, surface roughness) of the flattening layer 152 is preferably 10 nm or less. A semiconductor multilayer structure 110 is bonded on the surface of the flattening layer 152. The semiconductor multilayer structure 110 has light emitting thyristors 100_1, ..., 100_n. The semiconductor multilayer structure 110 is formed of, for example, a semiconductor thin film (for example, an epitaxial growth film) which is a multilayer semiconductor layer (110a shown in FIGS. 3 to 5 described later). When the unevenness (that is, surface roughness) of the surface of the base material 151 is 10 nm or less, the semiconductor multilayer structure 110 may be directly bonded to the surface of the base material 151 without the flattening layer 152. good. The base material 151 of the base material portion 150 may be formed of a material other than Si, such as glass, ceramic, plastic, or metal.

<< 1-2 >> Manufacturing Method of Semiconductor Multilayer Structure FIGS. 3 to 5 are schematic cross-sectional views showing a manufacturing method of the multilayer semiconductor layer 110a on which the light emitting thyristors 100_1, ..., 100_n of FIG. 1 are formed (Nos. 1 to 3). ). FIG. 3 shows the formation process of the multilayer semiconductor layer 110a, FIG. 4 shows the peeling process of the multilayer semiconductor layer 110a, and FIG. 5 shows the multilayer semiconductor layer 110a on the flattening layer 152 of the base material portion 150. The process of joining to is shown. The multilayer semiconductor layer 110a is a semiconductor thin film that is the basis of the semiconductor multilayer structure 110 shown in FIG.

As shown in FIG. 3, first, a buffer layer 702 for growing a multilayer semiconductor layer (for example, an epitaxial growth film) 110a is formed on the growth substrate 701. Next, a peeling layer 703 that serves as an etching layer for peeling the multilayer semiconductor layer 110a from the growth substrate 701 is formed. The growth substrate 701 is, for example, an N-type GaAs (gallium arsenide) layer using Si as a dopant, and has a thickness of, for example, 550 μm. The buffer layer 702 is, for example, an N-type GaAs layer using Si as a dopant, and has a thickness of, for example, 0.20 μm. The release layer 703 is, for example, an N-type AlAs (aluminum arsenide) layer using Si as a dopant, and has a thickness of, for example, 0.05 μm.

As shown in FIG. 3, the multilayer semiconductor layer 110a includes, for example, an N-type GaAs layer 101a, an N-type Al _0.4 Ga _0.6 As layer 102a, and N-type Al 0.4 Ga 0.6 As layer 102a, which are laminated in order from the growth substrate 701 side. Type Al _0.15 Ga _0.85 As layer 103a, P type Al _0.3 Ga _0.7 As layer 104a, N type Al _0.15 Ga _0.85 As layer 105a, and P type Al _0.4 It has a Ga _0.6 As layer 106a and a P-type GaAs layer 107a. The N-type GaAs layer 101a is formed, for example, using Si as a dopant, and has a thickness of, for example, 1.00 μm. The N-type Al _0.4 Ga _0.6 As layer 102a is formed using, for example, Si as a dopant, and has a thickness of, for example, 0.50 μm. The N-type Al _0.15 Ga _0.85 As layer 103a is formed using, for example, Si as a dopant, and has a thickness of, for example, 0.50 μm. The P-type Al _0.3 Ga _0.7 As layer 104a is formed using, for example, C (carbon) as a dopant, and has a thickness of, for example, 0.40 μm. The N-type Al _0.15 Ga _0.85 As layer 105a is formed using, for example, Si as a dopant, and has a thickness of, for example, 0.20 μm. The P-type Al _0.4 Ga _0.6 As layer 106a is formed using, for example, C (carbon) as a dopant, and has a thickness of, for example, 0.50 μm. The P-type GaAs layer 107a is formed using, for example, C (carbon) as a dopant, and has a thickness of, for example, 0.05 μm. The above configuration is merely an example and can be changed. For example, the multilayer semiconductor layer 110a may have a configuration in which the N-type and the P-type, which indicate the conductive type, are reversed. Further, the thickness of each semiconductor layer can be set to a value other than the above values.

Next, as shown in FIG. 4, the peeling layer 703 is selectively etched to make the multilayer semiconductor layer 110a separable (peeling) from the growth substrate 701, and the holding device (not shown) is used. The multilayer semiconductor layer 110a is separated from the growth substrate 701 while holding the multilayer semiconductor layer 110a.

Next, as shown in FIG. 5, the multilayer semiconductor layer 110a separated from the growth substrate 701 and the buffer layer 702 is placed on the flattening layer 152 of the base material portion 150 different from the growth substrate 701. The multilayer semiconductor layer 110a is bonded to the flattening layer 152 of the base material portion 150 by, for example, an intermolecular force.

By joining the multilayer semiconductor layer 110a onto the flattening layer 152 and then performing a known photolithography step and etching step, the multilayer semiconductor layer 110a shown in FIG. 5 is individually separated as shown in FIG. The element structure of the above, that is, the semiconductor multilayer structure 110 including the light emitting thyristors 100_1, ..., 100_n is formed. In other words, from the layers 101a to 107a constituting the multilayer semiconductor layer 110a shown in FIG. 5, the N-type cathode layers 101 and N-type forming the light emitting thyristors 100_1, ..., 100_n shown in FIGS. 2 and 6 Clad layers 102, 112, N-type active layers 103, 113, P-type clad layers 104, 114, N-type gate layers 105, 115, P-type anode layers 106, 116, P-type anode contact layers 107, 117 is formed. For the etching step, for example, a mixed solution of phosphoric acid, hydrogen peroxide solution, and water can be used.

Then, a metal such as Ti (titanium), Pt (platinum), Au (gold) capable of forming an ohmic contact with the P-type anode contact layers 107 and 117, or an alloy of those metals, or those metals and Au, Ge (germanium), Ni (nickel), which can form ohmic contacts with each of the anode electrode 141 having a laminated structure of an alloy and the N-type gate layers 105 and 115 and the N-type cathode layer 101, A gate electrode 143 (FIG. 1) and a cathode electrode 142 (FIGS. 1 and 2) made of a metal such as Pt, an alloy of those metals, or a laminated structure of those metals and an alloy are formed. At that time, the anode electrode 141, the gate electrode 143, and the cathode electrode 142 are the anode connection pad 131 (FIG. 1) and the gate connection pad 132, which are provided on the drive IC forming region in the base material 151 of the base material portion 150, respectively. (FIG. 1), connected to the cathode connection pad 133 (FIG. 1).

Further, in the first embodiment, the anode electrode 141, the gate electrode 143, and the cathode electrode 142 also serve as connection wirings with the drive IC, but the anode electrode 141, the gate electrode 143, the cathode electrode 142, and the semiconductor layer are connected. Another wiring for electrical connection may be provided in the light emitting element array chip 10.

In the figure, the insulating film made of an organic film such as polyimide or an inorganic film such as SiN (silicon nitride) formed on the surface of the semiconductor multilayer structure 110 and the base material portion 150 understands the shape of the semiconductor multilayer structure 110. Not shown for ease of use.

Further, in the first embodiment, in each light emitting thyristor of the light emitting element array chip 10, the cathode layers 101 are connected to each other, but the cathode layers 101 of the plurality of light emitting thyristors are separated from each other. May be good.

Further, in the first embodiment, the cathode electrode 142 is shared by two adjacent light emitting thyristors, but the cathode electrode may be formed for each light emitting thyristor, or three or more light emitting thyristors may be used. One cathode electrode 142 may be shared.

<< 1-3 >> Light-emitting thyristor FIG. 6 is a schematic cross-sectional view showing a cross-sectional structure of the light-emitting element array chip 10 of FIG. 1 cut along the line 2B-2B. FIG. 6 shows a part of FIG. 2 in an enlarged manner. As shown in FIGS. 1, 2 or 6, the light emitting element array chip 10 is provided on the base material portion 150, and a plurality of light emitting thyristors 100_1 arranged at intervals in the longitudinal direction of the base material portion 150. , ..., 100_n.

Of the plurality of light emitting psyllistas 100_1, ..., 100_n, the light emitting psyllista (first element) 100_n closest to the longitudinal end 150b of the base material portion 150 is a first conductive type first semiconductor layer 109 and A second conductive type second semiconductor layer (N-type gate layer) 105 different from the first conductive type, a first conductive type third semiconductor layer (P-type clad layer) 104, and a second conductive type. The fourth semiconductor layer 108 is the fourth semiconductor layer 108, the third semiconductor layer (P-type clad layer) 104, and the second semiconductor layer (N-type gate layer) 105 from the base material portion 150 side. , And a first semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 110) laminated in the order of the first semiconductor layer 109. In the first embodiment, the first conductive type is P type and the second conductive type is N type. The first semiconductor layer 109 includes a P-type anode layer 106 and a P-type anode contact layer 107 that are laminated in order from the base material portion 150 side. The fourth semiconductor layer 108 includes an N-type cathode layer 101, an N-type clad layer 102, and an N-type active layer 103 that are laminated in order from the base material portion 150 side. The semiconductor layers 101 to 107 of the semiconductor multilayer structure 110 constituting the light emitting thyristor (first element) 100_n are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively. The light emitting thyristor (first element) 100_1 closest to the end portion 150a in the longitudinal direction of the base material portion 150 has a structure in which the left and right sides of the light emitting thyristor 100_n are reversed.

Among the plurality of light emitting cylisters 100_1, ..., 100_n, the light emitting cylisters (second element) other than the light emitting cylisters (first element) 100_1, 100_n closest to the longitudinal ends 150a, 150b 100_2, ... Reference numeral 1 denotes a first conductive type fifth semiconductor layer 119, a second conductive type sixth semiconductor layer (N-type gate layer) 115, and a first conductive type seventh semiconductor layer (P-type). The clad layer (114) and the second conductive type eighth semiconductor layer (118) are the eighth semiconductor layer 118 from the base material portion 150 side, the seventh semiconductor layer (P-type clad layer) 114, and the seventh. It has a second semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 110) in which six semiconductor layers (N-type gate layer) 115 and a fifth semiconductor layer 119 are laminated in this order. The fifth semiconductor layer 119 includes a P-type anode layer 116 and a P-type anode contact layer 117 that are laminated in order from the base material portion 150 side. The eighth semiconductor layer 118 includes an N-type cathode layer 101, an N-type clad layer 112, and an N-type active layer 113 that are laminated in order from the base material portion 150 side. The semiconductor layers 101, 112 to 117 of the semiconductor multilayer structure 110 constituting the light emitting thyristor (second element) 100_2, ..., 100_n-1 are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively. Will be done.

In the light emitting thyristor (first element) 100_n, on the first surface 121 and the end 150b including the end surface of the first semiconductor layer 109 on the side close to the end (right end in FIG. 6) 150b of the base material portion 150. The first distance between the end face of the second semiconductor layer (N-type gate layer) 105 on the near side and the second surface 122 including the end face of the third semiconductor layer (P-type clad layer) 104. X1 is a third surface 123 including the end surface of the first semiconductor layer 109 on the side far from the end 150b, and the end surface and the second of the second semiconductor layer (N-type gate layer) 105 on the side far from the end 150b. It is smaller than the second distance X2 between the end face of the semiconductor layer (P-type clad layer) 104 and the fourth surface 124 including the third semiconductor layer (P-type clad layer) 104. That is, in FIG. 6, X1 <X2 is established. The light emitting thyristor (first element) 100_1 has a structure similar to that of the light emitting thyristor 100_n.

In the light emitting thyristor (second element) 100_2, ..., 100_n-1, the fifth semiconductor layer 119 including the end face of the fifth semiconductor layer 119 on one side (for example, the end portion 150b side) in the longitudinal direction of the base material portion 150. A sixth surface including the surface 131, the sixth semiconductor layer (N-type gate layer) 115 on one side (end 150b side), and the end surface of the seventh semiconductor layer (P-type clad layer) 114. The third distance X3 from 132 is the seventh surface 133 including the end face of the fifth semiconductor layer 119 on the other side opposite to one side (end 150b side) and the sixth on the other side. It is equal to the fourth distance X4 between the eighth surface 134 including the semiconductor layer (N-type gate layer) 115 and the end surface of the seventh semiconductor layer (P-type clad layer) 114. That is, in FIG. 6, X3 = X4 holds.

Further, in the light emitting element array chip 10, the second distance X2 is equal to the third distance X3. That is, in FIG. 6, X2 = X3 is established.

Further, the length W1 in the longitudinal direction of the base material portion 150 of the first semiconductor layer 109 of the light emitting thyristor (first element) 100_1, 100_n is the length W1 of the light emitting thyristor (second element) 100_1, ..., 100_n-1. It is equal to the longitudinal length W2 of the fifth semiconductor layer 119. That is, in FIG. 6, W1 = W2 is established. In other words, the planar shape of the first semiconductor layer 109 of the light emitting thyristor (first element) 100_1, 100_n is the plane of the fifth semiconductor layer 119 of the light emitting thyristor (second element) 100_2, ..., 100_n-1. It is the same as the shape.

<< 1-4 >> Comparative Example FIG. 7 is a schematic plan view showing a light emitting element array chip 70 of the comparative example. FIG. 8 is a schematic cross-sectional view showing a cross-sectional structure of the light emitting element array chip 70 of FIG. 7 cut along the lines 8A-8A and 8B-8B. In FIGS. 7 and 8, the same or corresponding components as those shown in FIGS. 1 and 2 are designated by the same reference numerals as those shown in FIGS. 1 and 2. In the comparative example, the structure of the two light emitting thyristors 700_1, 700_n closest to the end portion in the longitudinal direction (horizontal direction in FIG. 7) of the base material portion 150 is the light emitting thyristor of the light emitting element array chip 10 according to the first embodiment. It is different from the structure of 100_1,100_n. In the comparative example, the structure of the two light emitting thyristors 700_1, 700_n closest to the longitudinal end of the base material portion 150 is the same as the structure of the other light emitting thyristors 700_2, ..., 700_n-1.

In the comparative example, the light emitting thyristors 700_1, 700_n closest to the longitudinal end of the base material portion 150 are a P-type first semiconductor layer 109b and an N-type second semiconductor layer (N-type gate layer). The 105b, the P-type third semiconductor layer (P-type clad layer) 104b, and the N-type fourth semiconductor layer 108b are formed from the base material portion 150 side to the fourth semiconductor layer 108b and the third semiconductor. It has a structure in which a layer (P-type clad layer) 104b, a second semiconductor layer (N-type gate layer) 105b, and a first semiconductor layer 109b are laminated in this order (that is, a part of a semiconductor multilayer structure 710). .. In the comparative example, the first semiconductor layer 109b includes a P-type anode layer 106b and a P-type anode contact layer 107b laminated in order from the base material portion 150 side. The fourth semiconductor layer 108b includes an N-type cathode layer 101b, an N-type clad layer 102b, and an N-type active layer 103b that are laminated in order from the base material portion 150 side.

In the comparative example, the first surface including the end surface of the first semiconductor layer 109b on the side close to the end portion 150b of the base material portion 150 and the second semiconductor layer (N-type gate layer) on the side close to the end portion 150b. The first distance X1b between the end face of 105b and the second surface including the end face of the third semiconductor layer (P-type clad layer) 104b is the first semiconductor layer 109b on the side far from the end 150b. Includes a third surface including the end face of the second semiconductor layer (N-type gate layer) 105b and an end face of the third semiconductor layer (P-type clad layer) 104b on the side far from the end portion 150b. Equal to the second distance X2 to the fourth surface. That is, in FIG. 8, X1b = X2 is established. Further, in FIG. 8, since X3 = X4, X1b = X2 = X3 = X4 is established.

FIG. 9 is an explanatory diagram schematically showing the amount of light emitted from the light emitting thyristors 700_1, ..., 700_n of the light emitting element array chip 70 of the comparative example. In FIG. 9, the light emitted upward from the light emitting thyristors 700_1, ..., 700_n is represented by an arrow for each emission surface (upward surface). Light having a light intensity of L (L1s) is emitted from the light emitting thyristor 700_1 closest to the end portion 150a in addition to the light having a light intensity of L (C1), L (L1), and L (R1). Similarly, the light emitting thyristor 700_n closest to the end portion 150b emits light having a light intensity of L (Rns) in addition to light having a light intensity of L (Cn), L (Ln), and L (Rn). Therefore, when the amount of light emitted from the light emitting thyristor 700_1 is L0 (1) and the amount of light emitted from the light emitting thyristor 700_n is L0 (n), the following equation L0 (1) = L (C1) ) + L (L1) + L (R1) + L (L1s)
L0 (n) = L (Cn) + L (Ln) + L (Rn) + L (Rns)
Is established.

On the other hand, the light emitting thyristor 700_2 emits light having light amounts L (C2), L (L2), and L (R2). Similarly, the light emitting thyristor 700_3 emits light having light amounts L (C3), L (L3), and L (R3). Similarly, the light emitting thyristor 700_n-1 emits light having light amounts L (Cn-1), L (Ln-1), and L (Rn-1). Therefore, the amount of light emitted from the light emitting thyristor 700_2 is L0 (2), the amount of light emitted from the light emitting thyristor 700_3 is L0 (3), and the amount of light emitted from the light emitting thyristor 700_n-1. Is L0 (n-1), the following equation L0 (2) = L (C2) + L (L2) + L (R2)
L0 (3) = L (C3) + L (L3) + L (R3)
L0 (n-1) = L (Cn-1) + L (Ln-1) + L (Rn-1)
Is established.

As described above, in the comparative example, from the light emitting thyristors 700_1, 700_n closest to the ends 150a and 150b, the light of the light amount L (L1s) and the light amount L (Rns) caused by the end of the light emitting element array chip 70. Due to the light, the amount of light emitted is larger than that of other light emitting thyristors 700_2, ..., 700_n-1. That is, the state represented by the following equation occurs.
L0 (2) = L0 (3) = L0 (n-1) <L0 (1) = L0 (n)

FIG. 10 is an explanatory diagram schematically showing the light intensity and light intensity distribution of the light emitted from the light emitting thyristors 700_n-1,700_n of the light emitting element array chip 70 of the comparative example. On the left side of the middle row of FIG. 10, the light intensity distribution of the light emitted from the light emitting thyristor 700_n-1 is shown by a broken line. On the right side of the middle row of FIG. 10, the light intensity distribution of the light emitted from the light emitting thyristor 700_n is shown by a solid line. In the upper part of FIG. 10, two intensity distributions are superimposed so as to make it easy to compare the light intensity distribution of the light emitted from the light emitting thyristor 700_n-1 and the light intensity distribution of the light emitted from the light emitting thyristor 700_n. Has been done. In the middle and upper stages of FIG. 10, the positions on the horizontal axis of the coordinate system showing the light intensity distribution correspond to the positions in the longitudinal direction of the light emitting element array chip. As can be understood from FIG. 10, in the comparative example, the light amount L0 (n) of the light emitted from the light emitting thyristor 700_n and the light amount L0 (1) of the light emitted from the light emitting thyristor 700_1 are emitted from the light emitting thyristor 700_n-1. The amount of light to be produced is larger than L0 (n-1). That is, in the comparative example, a state that satisfies the following equation occurs.
L0 (n-1) <L0 (n) = L0 (1)

<< 1-5 >> Operation of the first embodiment FIG. 11 is an explanatory diagram schematically showing the amount of light emitted from the light emitting thyristors 100_1, ..., 100_n of the light emitting element array chip 10 according to the first embodiment. Is. In FIG. 11, the light emitted from the light emitting thyristors 100_1, ..., 100_n is represented by an arrow for each emission surface. Light of light quantities L (C1), L (L1a), L (R1), and L (L1s) is emitted from the light emitting thyristor 100_1 closest to the end portion 150a. Similarly, light of light quantities L (Cn), L (Ln), L (Rna), and L (Rns) is emitted from the light emitting thyristor 100_n closest to the end portion 150b. Therefore, when the amount of light emitted from the light emitting thyristor 100_1 is L1 (1) and the amount of light emitted from the light emitting thyristor 100_n is L1 (n).
L1 (1) = L (C1) + L (L1a) + L (R1) + L (L1s)
L1 (n) = L (Cn) + L (Ln) + L (Rna) + L (Rns)
Is established.

On the other hand, the light emitting thyristor 100_2 emits light having light amounts L (C2), L (L2), and L (R2). Similarly, the light emitting thyristor 100_3 emits light having light amounts L (C3), L (L3), and L (R3). Similarly, light having light amounts L (Cn-1), L (Ln-1), and L (Rn-1) is emitted from the light emitting thyristor 100_n-1. Therefore, the amount of light emitted from the light emitting thyristor 100_2 is L1 (2), the amount of light emitted from the light emitting thyristor 100_3 is L1 (3), and the amount of light emitted from the light emitting thyristor 100_n-1. Is L1 (n-1)
L1 (2) = L (C2) + L (L2) + L (R2)
L1 (3) = L (C3) + L (L3) + L (R3)
L1 (n-1) = L (Cn-1) + L (Ln-1) + L (Rn-1)
Is established.

In the first embodiment, the length of the light emitting surface (horizontal length in FIG. 6) of the amount of light L (Rna) emitted from the light emitting psyllista 100_n is the first distance X1 and the second. It is smaller than the distance X2, the third distance X3, and the fourth distance X4. That is, the area of the light emitting surface of the light amount L (Rna) emitted from the light emitting thyristor 100_n is small. Therefore, the amount of light L (Rna) emitted from the end 105b side of the second semiconductor layer (N-type gate layer) 105 of the light-emitting thyristor 100_n is the second semiconductor layer (N-type gate) of the light-emitting thyristor 100_n. The amount of light L (Ln) emitted from the opposite side of the end portion 105b of the layer 105, and the amount of light L (Rn) emitted from the second semiconductor layer (N-type gate layer) 115 of the light emitting thyristor 100_n-1. -1) and the amount of light L (Ln-1) of light emitted from the second semiconductor layer (N-type gate layer) 115 of the light emitting thyristor 100_n-1.

FIG. 12 is an explanatory diagram schematically showing the light intensity and light intensity distribution of the light emitted from the light emitting thyristors 100_n-1, 100_n of the light emitting element array chip 10 according to the first embodiment. On the left side of the middle row of FIG. 12, the light intensity distribution of the light emitted from the light emitting thyristor 700_n of the comparative example is shown by a broken line. On the right side of the middle row of FIG. 12, the light intensity distribution of the light emitted from the light emitting thyristor 100_n of the first embodiment is shown by a solid line. In the upper part of FIG. 12, two intensity distributions are superimposed so as to make it easy to compare the light intensity distribution of the light emitted from the light emitting thyristor 700_n and the light intensity distribution of the light emitted from the light emitting thyristor 100_n. There is. In the middle and upper stages of FIG. 12, the positions on the horizontal axis of the coordinate system showing the light intensity distribution correspond to the positions in the longitudinal direction of the light emitting element array chip. As can be understood from FIG. 12, in the first embodiment, the light intensity L1 (n) of the light emitted from the light emitting thyristor 100_n is smaller than the light intensity L0 (n-1) of the light emitted from the light emitting thyristor 700_n. This is because the amount of light L (Rna) is reduced by narrowing the width (first distance X1) of the light emitting surface of the light emitting thyristor 100_n.

As can be understood from FIGS. 11 and 12, in the first embodiment, the amounts of light emitted from the light emitting thyristors 100_1, 100_n are L1 (1), L1 (n), and the light emitting thyristors 100_2, ..., 100_n-1. The difference between the amount of light emitted from L1 (2), ..., L1 (n-1) is decreasing. That is, by setting the first distance X1 appropriately,
L1 (2) = L1 (3) = L1 (n-1) ≒ L1 (1) = L1 (n)
Can be achieved.

<< 1-6 >> Effect As described above, the light emitting element array chip 10 according to the first embodiment has a light amount L (L1a) of light emitted from the vicinity of the gate layer on the end side of the light emitting thyristor 100_1, 100_n. ), L (Rna) can be reduced, so that the amount of light L (L1a) and L (Rna) can be reduced, so that the amount of light L ( L1s) and L (Rns) are offset. In this way, the amount of light of the light emitting thyristors 100_1, 100_n can be brought close to the amount of light of the light emitting thyristors 100_1, ..., 100_n-1, so that the variation in the amount of light in the light emitting thyristors 100_1, ..., 100_n can be suppressed.

Further, in the light emitting element array chip 10 according to the first embodiment, the drive current of the light emitting thyristor can be made uniform, and the change in the amount of light emitted with time due to continuous operation is the same, so that the variation in the amount of light does not increase.

<< 2 >> Second Embodiment FIG. 13 is a schematic cross-sectional view showing a light emitting element array chip 20 as a semiconductor device according to the second embodiment. In FIG. 13, the same or corresponding components as in FIG. 6 (first embodiment) are designated by the same reference numerals as those shown in FIG. In the first embodiment, the case where the first conductive type is P type and the second conductive type is N type has been described, but in the second embodiment, the first conductive type is N type and the second conductive type. The case where the type is P type will be described. As shown in FIG. 13, the light emitting element array chip 20 is provided on the base material portion 150 and the base material portion 150, and a plurality of light emitting thyristors 200_1 arranged at intervals in the longitudinal direction of the base material portion 150. , ..., 200_n (only 200_n-1 and 200_n are shown in FIG. 13).

The light emitting thyristor (first element) 200_1, 200_n closest to the longitudinal end of the base material 150 (that is, the portion corresponding to the ends 150a, 150b in FIGS. 1 and 2) is the N-type first. Semiconductor layer 209, P-type second semiconductor layer (P-type gate layer) 205, N-type third semiconductor layer (N-type clad layer) 204, and P-type fourth semiconductor layer. The 208 is a fourth semiconductor layer 208, a third semiconductor layer (N-type clad layer) 204, a second semiconductor layer (P-type gate layer) 205, and a first semiconductor from the base material portion 150 side. It has a first semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 210) laminated in the order of layers 209. The first semiconductor layer 209 includes an N-type cathode layer 206 laminated in order from the base material portion 150 side and an N-type cathode contact layer 207 to which the cathode electrode 241 is bonded. The fourth semiconductor layer 208 includes a P-type anode layer 201, a P-type clad layer 202, and a P-type active layer 203 that are laminated in order from the base material portion 150 side. An anode electrode 242 is bonded onto the P-shaped anode layer 201. The semiconductor layers 201 to 207 of the semiconductor multilayer structure 210 constituting the light emitting thyristor (first element) 200_1, 200_n are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively.

The light emitting cylisters (second element) 200_2, ..., 200_n-1 other than the light emitting psyllista (first element) 200_1, 200_n closest to the end portion in the longitudinal direction of the base material portion 150 are N-type fifth semiconductors. Layer 219, P-type sixth semiconductor layer (P-type gate layer) 215, N-type seventh semiconductor layer (N-type clad layer) 214, and P-type eighth semiconductor layer 218. However, from the base material portion 150 side, the eighth semiconductor layer 218, the seventh semiconductor layer (N-type clad layer) 214, the sixth semiconductor layer (P-type gate layer) 215, and the fifth semiconductor layer 219 It has a second semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 210) laminated in the order of. The fifth semiconductor layer 219 includes an N-type cathode layer 216 laminated in order from the base material portion 150 side and an N-type cathode contact layer 217 to which the cathode electrode 241 is bonded. The eighth semiconductor layer 218 includes a P-type anode layer 201, a P-type clad layer 212, and a P-type active layer 213 laminated in order from the base material portion 150 side. The semiconductor layers 2011, 212 to 217 of the semiconductor multilayer structure 210 constituting the light emitting thyristor (second element) 200_2, ..., 200_n-1 are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively. Will be done.

In the light emitting thyristor (first element) 200_n, the first surface 221 including the end surface of the first semiconductor layer 209 on the side close to the end portion 150b of the base material portion 150 and the second surface on the side close to the end portion 150b. The first distance X1 between the end face of the semiconductor layer (P-type gate layer) 205 and the second surface 222 including the end face of the third semiconductor layer (N-type clad layer) 204 is the end 150b. The end face of the third surface 223 including the end face of the first semiconductor layer 209 on the side far from the side and the end face of the second semiconductor layer (P-type gate layer) 205 on the side far from the end 150b and the third semiconductor layer (N). The second distance X2 between the end face of the mold clad layer 204 and the fourth face 224 including. That is, in FIG. 13, X1 <X2 is established. The light emitting thyristor (first element) 200_1 has a structure in which the left and right sides are reversed from the light emitting thyristor 200_n.

In the light emitting thyristor (second element) 200_n-1, the fifth surface 231 including the end surface of the fifth semiconductor layer 219 on one side in the longitudinal direction of the base material portion 150 and the sixth semiconductor on one side. The third distance X3 between the sixth surface 232 including the layer (P-type gate layer) 215 and the end face of the seventh semiconductor layer (N-type clad layer) 214 is the fifth on the other side. Includes a seventh surface 233 including the end face of the semiconductor layer 219 of the above, a sixth semiconductor layer (P-type gate layer) 215 on the other side, and an end face of the seventh semiconductor layer (N-type clad layer) 214. Equal to the fourth distance X4 between the eighth surface 234. That is, in FIG. 13, X3 = X4 holds. The light emitting thyristor (second element) 200_2, ..., 200_n-2 has the same structure as the light emitting thyristor 200_n-1.

Further, in the light emitting element array chip 20, the second distance X2 is equal to the third distance X3. That is, in FIG. 13, X2 = X3 is established.

Further, the length W1 of the base material portion 150 of the first semiconductor layer 209 in the longitudinal direction is equal to the length W2 of the base material portion 150 of the fifth semiconductor layer 219 in the longitudinal direction. That is, in FIG. 13, W1 = W2 is established. In other words, the planar shape of the first semiconductor layer 209 is the same as the planar shape of the fifth semiconductor layer 219.

According to the light emitting element array chip 20 according to the second embodiment having the structure described above, the same effect as that of the light emitting element array chip 10 according to the first embodiment can be obtained. That is, by reducing the amount of light emitted from the vicinity of the gate layer on the end side of the light emitting thyristor 200_1, 200_n, the increase in the amount of light emitted from the vicinity of the corner portion of the anode layer 201 of the light emitting element array chip 20 is offset. doing. Therefore, the amount of light of the light emitting thyristors 200_1, 200_n can be brought close to the amount of light of the light emitting thyristors 200_1, ..., 200_n-1, so that the variation in the amount of light in the light emitting thyristors 200_1, ..., 200_n can be suppressed.

<< 3 >> Third Embodiment FIG. 14 is a schematic cross-sectional view showing a light emitting element array chip 30 as a semiconductor device according to the third embodiment. In FIG. 14, the same or corresponding components as in FIG. 6 (first embodiment) are designated by the same reference numerals as those shown in FIG. In the first embodiment, the case where the gate electrode (143 in FIG. 1) is provided on the second semiconductor layer (N-type gate layer) 105 has been described, but in the third embodiment, the third semiconductor A case where a gate electrode (that is, an electrode corresponding to 143 in FIG. 1) is provided on the layer (P-type gate layer) 304 will be described. As shown in FIG. 14, the light emitting element array chip 30 is provided on the base material portion 150 and the base material portion 150, and a plurality of light emitting thyristors 300_1 arranged at intervals in the longitudinal direction of the base material portion 150. , ..., 300_n (only 300_n-1 and 300_n are shown in FIG. 14).

The light emitting thyristor (first element) 300_1, 300_n closest to the longitudinal end of the base material 150 (that is, the portion corresponding to the ends 150a, 150b in FIGS. 1 and 2) is a P-shaped first element. 309, N-type second semiconductor layer (N-type gate layer) 305, P-type third semiconductor layer (P-type gate layer) 304, and N-type fourth semiconductor layer. The 308 is a fourth semiconductor layer 308, a third semiconductor layer (P-type gate layer) 304, a second semiconductor layer (N-type gate layer) 305, and a first semiconductor from the base material portion 150 side. It has a first semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 310) laminated in the order of layers 309. The first semiconductor layer 309 includes a P-type anode layer 306 laminated in order from the base material portion 150 side and a P-type anode contact layer 307 to which the anode electrode 341 is bonded. The fourth semiconductor layer 308 includes an N-type cathode layer 301, an N-type clad layer 302, and an N-type active layer 303, which are laminated in order from the base material portion 150 side. A cathode electrode 342 is bonded onto the N-shaped cathode layer 301. The semiconductor layers 301 to 307 of the semiconductor multilayer structure 310 constituting the light emitting thyristor (first element) 300_1, 300_n are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively.

The light emitting cylisters (second element) 300_1, ..., 300_n-1 other than the light emitting thyristor (first element) 300_1, 300_n closest to the end portion in the longitudinal direction of the base material portion 150 are P-type fifth semiconductors. Layer 319, N-type sixth semiconductor layer (N-type gate layer) 315, P-type seventh semiconductor layer (P-type gate layer) 314, and N-type eighth semiconductor layer 318. However, from the base material portion 150 side, the eighth semiconductor layer 318, the seventh semiconductor layer (P-type gate layer) 314, the sixth semiconductor layer (N-type gate layer) 315, and the fifth semiconductor layer 319. It has a second semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 310) laminated in the order of. The fifth semiconductor layer 319 includes a P-type anode layer 316 and a P-type anode contact layer 317 laminated in order from the base material portion 150 side. The eighth semiconductor layer 318 includes an N-type cathode layer 301, an N-type clad layer 312, and an N-type active layer 313 that are laminated in order from the base material portion 150 side. The semiconductor layers 301, 312 to 317 of the semiconductor multilayer structure 310 constituting the light emitting thyristor (second element) 300_2, ..., 300_n-1 are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively. Will be done.

In the light emitting thyristor (first element) 300_n, the end face of the first semiconductor layer 309 and the end face of the second semiconductor layer (N-type gate layer) 305 on the side close to the end portion 150b of the base material portion 150 are formed. The first distance X1 between the including first surface 321 and the second surface 322 including the end surface of the third semiconductor layer (N-type gate layer) 304 on the side close to the end 150b is the end 150b. A third surface 323 including an end face of the first semiconductor layer 309 on the side far from the end surface and an end surface of the second semiconductor layer (P-type gate layer) 305 and a third semiconductor layer on the side far from the end portion 150b ( It is smaller than the second distance X2 between the fourth surface 324 including the end surface of the N-type clad layer) 204. That is, in FIG. 14, X1 <X2 is established. The light emitting thyristor (first element) 300_1 has a structure in which the left and right sides are reversed from the light emitting thyristor 300_n.

In the light emitting thyristor (second element) 300_n-1, the end face of the fifth semiconductor layer 319 on one side in the longitudinal direction of the base material portion 150 and the sixth semiconductor layer (N-type gate layer) on one side. ) The third distance X3 between the fifth surface 331 including the end face of 315 and the sixth surface 332 including the end face of the seventh semiconductor layer (P-type gate layer) 314 on one side is. A seventh surface 333 including an end face of a fifth semiconductor layer 319 on the other side of the base material portion 150 in the longitudinal direction and an end face of a sixth semiconductor layer (N-type gate layer) 315 on the other side, and the other. Is equal to the fourth distance X4 between the seventh semiconductor layer (P-type gate layer) 314 on the side of the surface and the eighth surface 334 including the end face of the seventh semiconductor layer (P-type gate layer) 314. That is, in FIG. 14, X3 = X4 holds. The light emitting thyristor (second element) 300_2, ..., 300_n-2 has the same structure as the light emitting thyristor 300_n-1.

Further, in the light emitting element array chip 30, the second distance X2 is equal to the third distance X3. That is, in FIG. 14, X2 = X3 is established.

Further, the length W1 of the base material portion 150 of the first semiconductor layer 309 in the longitudinal direction is equal to the length W2 of the base material portion 150 of the fifth semiconductor layer 319 in the longitudinal direction. That is, in FIG. 14, W1 = W2 is established. In other words, the planar shapes of the first semiconductor layer 309 and the second semiconductor layer 305 are the same as the planar shapes of the fifth semiconductor layer 319 and the sixth semiconductor layer 315.

According to the light emitting element array chip 30 according to the third embodiment having the structure described above, the same effect as that of the light emitting element array chip 10 according to the first embodiment can be obtained. That is, by reducing the amount of light emitted from the vicinity of the gate layer on the end side of the light emitting thyristor 300_1, 300_n, the increase in the amount of light emitted from the vicinity of the corner portion of the cathode layer 301 of the light emitting element array chip 30 is offset. doing. Therefore, the amount of light of the light emitting thyristors 300_1, 300_n can be brought close to the amount of light of the light emitting thyristors 300_1, ..., 300_n-1, so that the variation in the amount of light in the light emitting thyristors 300_1, ..., 300_n can be suppressed.

<< 4 >> Fourth Embodiment FIG. 15 is a schematic cross-sectional view showing a light emitting element array chip 40 as a semiconductor device according to the fourth embodiment. In FIG. 15, the same or corresponding components as in FIG. 13 (second embodiment) are designated by the same reference numerals as those shown in FIG. In the second embodiment, the case where the gate electrode (the electrode corresponding to 143 in FIG. 1) is provided on the second semiconductor layer (P-type gate layer) 205 has been described, but in the fourth embodiment, the case has been described. A case where the gate electrode is provided on the third semiconductor layer (N-type gate layer) 404 will be described. As shown in FIG. 15, the light emitting element array chip 40 is provided on the base material portion 150 and the base material portion 150, and a plurality of light emitting thyristors 400_1 arranged at intervals in the longitudinal direction of the base material portion 150. , ..., 400_n (only 400_n-1 and 400_n are shown in the figure).

The light emitting thyristor (first element) 400_1, 400_n closest to the longitudinal end of the base material 150 (that is, the portion corresponding to the ends 150a, 150b in FIGS. 1 and 2) is the N-type first. 409, a P-type second semiconductor layer (P-type gate layer) 405, an N-type third semiconductor layer (N-type gate layer) 404, and a P-type fourth semiconductor layer. 408 is a fourth semiconductor layer 408, a third semiconductor layer (N-type gate layer) 404, a second semiconductor layer (P-type gate layer) 405, and a first semiconductor from the base material portion 150 side. It has a first semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 410) laminated in the order of layers 409. The first semiconductor layer 409 includes an N-type cathode layer 406 laminated in order from the base material portion 150 side and an N-type cathode contact layer 407 to which the cathode electrode 441 is bonded. The fourth semiconductor layer 408 includes a P-type anode layer 401, a P-type clad layer 402, and a P-type active layer 403 laminated in order from the base material portion 150 side. An anode electrode 442 is bonded onto the anode layer 401. The semiconductor layers 401 to 407 of the semiconductor multilayer structure 410 constituting the light emitting thyristor (first element) 400_1, 400_n are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively.

The light emitting cylisters (second element) 400_2, ..., 400_n-1 other than the light emitting psyllista (first element) 400_1, 400_n closest to the end portion in the longitudinal direction of the base material portion 150 are N-type fifth semiconductors. Layer 419, P-type sixth semiconductor layer (P-type gate layer) 415, N-type seventh semiconductor layer (N-type gate layer) 414, and P-type eighth semiconductor layer 418. However, from the base material portion 150 side, the eighth semiconductor layer 418, the seventh semiconductor layer (N-type gate layer) 414, the sixth semiconductor layer (P-type gate layer) 415, and the fifth semiconductor layer 419 It has a second semiconductor multilayer structure (that is, a part of the semiconductor multilayer structure 410) laminated in the order of. The fifth semiconductor layer 419 includes an N-type cathode layer 416 and an N-type cathode contact layer 417 that are laminated in order from the base material portion 150 side. The eighth semiconductor layer 418 includes a P-type anode layer 401, a P-type clad layer 412, and a P-type active layer 413 laminated in order from the base material portion 150 side. The semiconductor layers 401, 421 to 417 of the semiconductor multilayer structure 410 constituting the light emitting thyristor (second element) 400_2, ..., 400_n-1 are formed from the multilayer semiconductor layers 101a to 107a shown in FIGS. 3 to 5, respectively. Will be done.

In the light emitting thyristor (first element) 400_n, the end face of the first semiconductor layer 409 and the end face of the second semiconductor layer (P-type gate layer) 405 on the side close to the end portion 150b of the base material portion 150 are formed. The first distance X1 between the including first surface 421 and the second surface 422 including the end surface of the third semiconductor layer (P-type gate layer) 404 on the side closer to the end 150b is from the end. A third surface 423 including an end face of the first semiconductor layer 409 on the distant side and an end face of the second semiconductor layer (N-type gate layer) 405 and a third semiconductor layer (N) on the side far from the end 150b. The second distance X2 between the fourth surface 424 including the end face of the mold gate layer) 404 is smaller. That is, in FIG. 15, X1 <X2 is established. The light emitting thyristor (first element) 400_1 has a structure in which the left and right sides are reversed from the light emitting thyristor 400_n.

In the light emitting thyristor (second element) 400_n-1, the end face of the fifth semiconductor layer 419 and the end face of the sixth semiconductor layer (P-type gate layer) 415 on one side in the longitudinal direction of the base material portion 150. The third distance X3 between the fifth surface 431 including and the sixth surface 432 including the end surface of the seventh semiconductor layer (N-type gate layer) 414 on one side is the base material portion 150. A seventh surface 433 including an end face of a fifth semiconductor layer 419 and an end face of a sixth semiconductor layer (P-type gate layer) 415 on the other side in the longitudinal direction of the semiconductor layer and a seventh semiconductor layer on the other side. It is equal to the fourth distance X4 between the eighth surface 334 including the end surface of the (N-type gate layer) 414. That is, in FIG. 14, X3 = X4 holds. The light emitting thyristor (second element) 400_2, ..., 400_n-2 has the same structure as the light emitting thyristor 400_n-1.

Further, in the light emitting element array chip 40, the second distance X2 is equal to the third distance X3. That is, in FIG. 15, X2 = X3 is established.

Further, the length W1 of the base material portion 150 of the first semiconductor layer 409 in the longitudinal direction is equal to the length W2 of the base material portion 150 of the fifth semiconductor layer 319 in the longitudinal direction. That is, in FIG. 15, W1 = W2 is established. In other words, the planar shapes of the first semiconductor layer 409 and the second semiconductor layer 405 are the same as the planar shapes of the fifth semiconductor layer 419 and the sixth semiconductor layer 415.

According to the light emitting element array chip 40 according to the fourth embodiment having the structure described above, the same effect as that of the light emitting element array chip 10 according to the first embodiment can be obtained. That is, by reducing the amount of light emitted from the vicinity of the gate layer on the end side of the light emitting thyristor 400_1, 400_n, the increase in the amount of light emitted from the vicinity of the corner portion of the anode layer 401 of the light emitting element array chip 40 is offset. doing. Therefore, the amount of light of the luminescent thyristors 400_1, 400_n can be brought close to the amount of light of the luminescent thyristors 400_1, ..., 400_n-1, and the variation in the amount of light in the luminescent thyristors 400_1, ..., 400_n can be suppressed.

<< 5 >> Configuration of the Fifth Embodiment << 5-1 >> FIG. 16 is a schematic plan view showing a light emitting element array chip 50 as a semiconductor device according to the fifth embodiment. The same or corresponding components as those shown in FIG. 1 (first embodiment) in FIG. 16 are designated by the same reference numerals as those shown in FIG. FIG. 17 is a schematic cross-sectional view showing a cross-sectional structure in which the light emitting element array chip of FIG. 16 is cut along the lines 17A-17A and 17B-17B. The same or corresponding components as those shown in FIG. 2 (first embodiment) in FIG. 17 are designated by the same reference numerals as those shown in FIG. FIG. 18 is a schematic cross-sectional view showing a cross-sectional structure in which the light emitting element array chip of FIG. 16 is cut along the line 17B-17B. The same or corresponding components as those shown in FIG. 6 (first embodiment) in FIG. 18 are designated by the same reference numerals as those shown in FIG.

As shown in FIGS. 16 to 18, a plurality of light emitting element array chips 50 are provided on the base material portion 150 and the base material portion 150, and are arranged at intervals in the longitudinal direction of the base material portion 150. It has luminescent thyristors 500_1, ..., 500_n. As shown in FIGS. 16 to 18, the light emitting element array chip 50 according to the fifth embodiment is located between the ninth surface 521 and the second surface 122, which are the ends of the N-shaped cathode layer 501. The fifth distance WEB is smaller than the sixth distance WE between the tenth surface 522 including the end surface of the base material portion 150 and the second surface 122 on the side closer to the end. Except for this point, the light emitting element array chip 50 is the same as the light emitting element array chip 10 according to the first embodiment.

<< 5-2 >> Operation FIG. 19 is an explanatory diagram schematically showing the amount of light emitted from the light emitting thyristors 500_1, ..., 500_n of the light emitting element array chip 50 of the fifth embodiment. In FIG. 19, the light emitted from the light emitting thyristors 500_1, ..., 500_n is represented by an arrow for each emission surface. Light of light amounts L (C1), L (L1a), L (R1), and L (L1sa) is emitted from the light emitting thyristor 500_1 closest to the end portion 150a. Similarly, light having light amounts L (Cn), L (Ln), L (Rna), and L (Rnas) is emitted from the light emitting thyristor 500_n closest to the end portion 150b. Therefore, when the amount of light emitted from the light emitting thyristor 500_1 is L5 (1) and the amount of light emitted from the light emitting thyristor 500_n is L5 (n).
L5 (1) = L (C1) + L (L1a) + L (R1) + L (L1sa)
L5 (n) = L (Cn) + L (Ln) + L (Rna) + L (Rnas)
Is.

On the other hand, the light emitting thyristor 500_2 emits light having light amounts L (C2), L (L2), and L (R2). Similarly, the light emitting thyristor 500_3 emits light having light amounts L (C3), L (L3), and L (R3). Similarly, light having light amounts L (Cn-1), L (Ln-1), and L (Rn-1) is emitted from the light emitting thyristor 500_n-1. Therefore, the amount of light emitted from the light emitting thyristor 500_2 is L5 (2), the amount of light emitted from the light emitting thyristor 500_3 is L5 (3), and the amount of light emitted from the light emitting thyristor 500_n-1. Is L5 (n-1)
L5 (2) = L (C2) + L (L2) + L (R2)
L5 (3) = L (C3) + L (L3) + L (R3)
L5 (n-1) = L (Cn-1) + L (Ln-1) + L (Rn-1)
Is.

In the fifth embodiment, the length of the light emitting surface of the amount of light L (Rna) emitted from the light emitting psyllista 500_n is the first distance X1, the second distance X2, the third distance X3, and the third. It is smaller than the distance X4 of 4. That is, the area of the light emitting surface of the light amount L (Rna) emitted from the light emitting thyristor 500_n is small. Therefore, the amount of light L (Rna) is smaller than the amount of light L (Ln), L (Rn-1), and L (Ln-1).

Further, in the fifth embodiment, the length of the light emitting surface of the light amount L (Rnas) emitted from the light emitting thyristor 500_n is the fifth distance WEB, and the sixth distance WE (FIGS. 6 and 18). Is smaller than (shown in). That is, the area of the light emitting surface of the light amount L (Rnas) emitted from the light emitting thyristor 500_n is smaller than that of the first embodiment. Therefore, the light quantity L (Rnsa) is smaller than the light quantity L (Rns) (shown in FIG. 9) in the comparative example and the light quantity L (Rns) (shown in FIG. 11) in the first embodiment.

FIG. 20 is an explanatory diagram schematically showing the light intensity and light intensity distribution of the light emitted from the light emitting thyristor of the light emitting element array chip of the comparative example (FIG. 5) and the fifth embodiment (FIG. 18). On the left side of the middle row of FIG. 20, the light intensity distribution of the light emitted from the light emitting thyristor 700_n of the comparative example is shown by a broken line. On the right side of the middle row of FIG. 20, the light intensity distribution of the light emitted from the light emitting thyristor 500_n of the fifth embodiment is shown by a solid line. In the upper part of FIG. 20, two intensity distributions are superimposed so as to make it easy to compare the light intensity distribution of the light emitted from the light emitting thyristor 700_n and the light intensity distribution of the light emitted from the light emitting thyristor 500_n. There is. In the middle and upper stages of FIG. 20, the positions on the horizontal axis of the coordinate system showing the light intensity distribution correspond to the positions in the longitudinal direction of the light emitting element array chip. As can be understood from FIG. 20, in the fifth embodiment, the light intensity L5 (n) of the light emitted from the light emitting thyristor 500_n is smaller than the light intensity L0 (n) of the light emitted from the light emitting thyristor 700_n. This is because the light amounts L (Rna) and L (Rnas) are reduced by narrowing the width of the light emitting surface of the light emitting thyristor 500_n (first distance X1 and fifth distance WEB).

FIG. 21 is an explanatory diagram schematically showing the light intensity and light intensity distribution of the light emitted from the light emitting thyristor of the light emitting element array chip of the first embodiment (FIG. 3) and the fifth embodiment (FIG. 18). be. On the left side of the middle stage of FIG. 21, the light intensity distribution of the light emitted from the light emitting thyristor 100_n of the first embodiment (FIG. 3) is shown by a broken line. On the right side of the middle row of FIG. 21, the light intensity distribution of the light emitted from the light emitting thyristor 500_n of the fifth embodiment is shown by a solid line. In the upper part of FIG. 21, two intensity distributions are superimposed so as to make it easy to compare the light intensity distribution of the light emitted from the light emitting thyristor 100_n and the light intensity distribution of the light emitted from the light emitting thyristor 500_n. There is. In the middle and upper stages of FIG. 21, the positions on the horizontal axis of the coordinate system showing the light intensity distribution correspond to the positions in the longitudinal direction of the light emitting element array chip. As can be understood from FIG. 21, in the fifth embodiment, the light intensity L5 (n) of the light emitted from the light emitting thyristor 500_n is smaller than the light intensity L1 (n) of the light emitted from the light emitting thyristor 100_n. This is because the amount of light L (Rnas) is reduced by narrowing the width (fifth distance WEB) of the light emitting surface of the light emitting thyristor 500_n.

As can be understood from FIGS. 19, 20, and 21, in the fifth embodiment, the light amounts L5 (1), L5 (n) of the light emitted from the light emitting thyristor 500_1, 500_n, the light emitting thyristor 500_1, ... , The difference between the amount of light emitted from 500_n-1 and the amount of light L5 (2), ..., L5 (n-1) is decreasing. That is, by appropriately setting the first distance X1 and the fifth distance WEB,
L5 (2) = L5 (3) = L5 (n-1) ≒ L5 (1) = L5 (n)
Can be achieved.

<< 5-3 >> Effect As described above, the light emitting element array chip 50 according to the fifth embodiment has a light amount L (L1a) of light emitted from the vicinity of the gate layer on the end side of the light emitting thyristor 500_1,500_n. ), L (Rna) and the amount of light L (L1sa), L (Rnas) emitted from the vicinity of the cathode layer on the end side can be reduced. It can be suppressed.

Further, in the light emitting element array chip 50 according to the fifth embodiment, the drive current of the light emitting thyristor can be made uniform, and the change with time of the light emitting amount due to the continuous operation becomes the same, so that the variation in the light amount does not increase.

Even if the condition of the fifth distance WEB to the end face of the semiconductor layer on the substrate portion 150 side in the fifth embodiment is applied to any of the light emitting element array chips of the second to fourth embodiments. good.

<< 6 >> Sixth Embodiment FIG. 22 is a schematic perspective view showing a structure of a main part of an optical print head according to a sixth embodiment. As shown in FIG. 22, the substrate unit as a main part includes a printed wiring board 801 which is a mounting substrate, and a plurality of light emitting element array chips 10 arranged in an array. The light emitting element array chip 10 is fixed on the printed wiring board 801 with a thermosetting resin or the like. The electrode pad 153 for external connection of the light emitting element array chip 10 and the connection pad 802 of the printed wiring board 801 are electrically connected by the bonding wire 803. Further, various wiring patterns, electronic components, connectors and the like may be mounted on the printed wiring board 801. Further, instead of the light emitting element array chip 10, any of the light emitting element array chips 20, 30, 40, and 50 described in the second to fifth embodiments may be used.

FIG. 23 is a schematic cross-sectional view showing the structure of the optical print head 800 according to the sixth embodiment. The optical print head 800 is an exposure apparatus for an electrophotographic printer as an electrophotographic image forming apparatus. As shown in FIG. 23, the optical print head 800 includes a base member 811, a printed wiring board 801 and a light emitting element array chip 10 (or 20, 30, 40, 50), and a plurality of upright equal-magnification imaging. It includes a lens array 813 including a lens, a lens holder 814, and a clamper 815 which is a spring member. The base member 811 is a member for fixing the printed wiring board 801. On the side surface of the base member 811, a printed wiring board 801 and an opening 812 for fixing the lens holder 814 to the base member 811 are provided by using the clamper 815. The lens holder 814 is formed by, for example, injection molding an organic polymer material or the like. The lens array 813 is an optical lens group that forms an image of light emitted from the light emitting element array chip 10 (or 20, 30, 40, 50) on a photoconductor drum as an image carrier. The lens holder 814 holds the lens array 813 in a predetermined position on the base member 811. The clamper 815 sandwiches and holds each component via the opening 812 of the base member 811 and the opening of the lens holder 814.

In the optical print head 800, the light emitting thyristor of the light emitting element array chip 10 selectively emits light according to the print data, and the light emitted from the light emitting thyristor is uniformly charged by the lens array 813 on the photoconductor drum. It is imaged. As a result, an electrostatic latent image is formed on the photoconductor drum, and then an image made of a developer is formed (printed) on a printing medium (paper) through a developing step, a transfer step, and a fixing step.

As described above, the optical print head 800 according to the sixth embodiment includes a light emitting element array chip 10 (or 20, 30, 40, 50) having a small variation in light emission intensity. The print quality can be improved by mounting it on the forming apparatus.

<< 7 >> 7th Embodiment FIG. 24 is a schematic cross-sectional view showing the structure of the image forming apparatus 900 according to the 7th embodiment. The image forming apparatus 900 is, for example, a color printer using an electrophotographic process.

As shown in FIG. 24, the image forming apparatus 900 is mainly composed of an image forming unit (that is, a process) that forms a toner image (that is, a developer image) on a recording medium P such as paper by an electrophotographic process. Unit) 910K, 910Y, 910M, 910C, a medium supply unit 920 that supplies the recording medium P to the image forming units 910K, 910Y, 910M, 910C, a conveying unit 930 that conveys the recording medium P, and an image forming unit 910K, A transfer roller 940K, 940Y, 940M, 940C as a transfer unit arranged so as to correspond to each of the 910Y, 910M, and 910C, a fixing device 950 for fixing the toner image transferred on the recording medium P, and a fixing device. It has a guide 926 and a paper ejection roller pair 925 as a medium ejection unit that ejects the recording medium P that has passed through the 950 to the outside of the housing of the image forming apparatus 900. The number of image forming portions included in the image forming apparatus 900 may be 3 or less or 5 or more. Further, the image forming apparatus 900 may be a monochrome printer having one image forming unit as long as it is an apparatus for forming an image on the recording medium P by an electrophotographic process.

As shown in FIG. 24, the medium supply unit 920 includes a medium cassette 921, a hopping roller 922 that feeds out the recording media P loaded in the medium cassette 921 one by one, and a recording medium P that is fed out from the medium cassette 921. It has a roller pair 923 that conveys the material, a guide 970 that guides the recording medium P, and a resist roller / pinch roller 924 that corrects the skew of the recording medium P.

The image forming units 910K, 910Y, 910M, and 910C display a black (K) toner image, a yellow (Y) toner image, a magenta (M) toner image, and a cyan (C) toner image on the recording medium P. Form each. The image forming portions 910K, 910Y, 910M, and 910C are arranged side by side along the medium transport path from the upstream side to the downstream side (that is, from right to left in FIG. 1) in the medium transport direction. Each of the image forming portions 910K, 910Y, 910M, and 910C may be a detachable unit. The image forming portions 910K, 910Y, 910M, and 910C basically have the same structure as each other except that the colors of the toners to be accommodated are different.

The image forming units 910K, 910Y, 910M, and 910C have optical print heads 911K, 911Y, 911M, and 911C as exposure devices for each color, respectively. Each of the optical print heads 911K, 911Y, 911M, and 911C is the optical print head 800 according to the sixth embodiment.

The image forming portions 910K, 910Y, 910M, and 910C have uniform surfaces of the photoconductor drums 913K, 913Y, 913M, and 913C as image carriers supported rotatably and the photoconductor drums 913K, 913Y, 913M, and 913C. Electrostatic latent images are formed on the surface of the photoconductor drums 913K, 913Y, 913M, 913C by exposure with charging rollers 914K, 914Y, 914M, 914C as charging members and optical print heads 911K, 911Y, 911M, 911C. After that, it has developing units 915K, 915Y, 915M, 915C that supply toner to the surfaces of the photoconductor drums 913K, 913Y, 913M, 913C to form a toner image corresponding to the electrostatic latent image.

The developing units 915K, 915Y, 915M, 915C supply toner to the surface of the photoconductor drums 913K, 913Y, 913M, 913C and the toner accommodating unit as the developing agent accommodating unit forming the developing agent accommodating space for accommodating the toner. The developing rollers 916K, 916Y, 916M, 916C as the developing agent carrier and the supply rollers 917K, 917Y, 917M, 917C that supply the toner contained in the toner accommodating portion to the developing rollers 916K, 916Y, 916M, 916C are used for development. It has developing blades 918K, 918Y, 918M, 918C as toner regulating members that regulate the thickness of the toner layer on the surface of the rollers 916K, 916Y, 916M, 916C.

The exposure by the optical print heads 911K, 911Y, 911M, 911C is performed on the surface of the uniformly charged photoconductor drums 913K, 913Y, 913M, 913C based on the image data for printing. The optical print heads 911K, 911Y, 911M, and 911C include a light emitting element array in which light emitting thyristors are arranged as a plurality of light emitting elements in the axial direction of the photoconductor drums 913K, 913Y, 913M, and 913C.

As shown in FIG. 24, the transport unit 930 includes a transport belt (transfer belt) 933 that electrostatically attracts and conveys the recording medium P, and a drive roller 931 that is rotated by the drive unit to drive the transport belt 933. It has a tension roller (driven roller) 932 that is paired with the drive roller 931 and stretches the transport belt 933.

As shown in FIG. 24, the transfer rollers 940K, 940Y, 940M, 940C face the photoconductor drums 913K, 913Y, 913M, 913C of the image forming portions 910K, 910Y, 910M, 910C with the transport belt 933 sandwiched between them. Have been placed. The toner images formed on the surfaces of the photoconductor drums 913K, 913Y, 913M, and 913C of the image forming portions 910K, 910Y, 910M, and 910C are formed along the medium transport path by the transfer rollers 940K, 940Y, 940M, and 940C. The images are sequentially transferred to the upper surface of the recording medium P conveyed in the direction of the arrow. The image forming units 910K, 910Y, 910M, and 910C remained on the photoconductor drums 913K, 913Y, 913M, and 913C after transferring the toner image developed on the photoconductor drums 913K, 913Y, 913M, and 913C to the recording medium P. It has cleaning devices 919K, 919Y, 919M, 919C for removing toner.

The fuser 950 has a pair of rollers 951, 952 that are in pressure contact with each other. The roller 951 is a roller 951 (heat roller) having a built-in heater, and the roller 952 is a pressure roller pressed toward the roller 951. The recording medium P having the unfixed toner image passes between a pair of rollers 951, 952 of the fixer 950. At this time, the unfixed toner image is heated and pressurized and fixed on the recording medium P.

Further, the lower surface portion of the transport belt 933 is provided with a cleaning mechanism including a cleaning blade 934 and a waste toner accommodating portion (not shown).

At the time of printing, the recording medium P in the medium cassette 921 is unwound by the hopping roller 922 and sent to the roller pair 923. Subsequently, the recording medium P is sent from the roller pair 923 to the transport belt 933 via the resist roller and pinch roller 924, and is conveyed to the image forming units 910K, 910Y, 910M, and 910C as the transport belt 933 travels. Will be done. In the image forming portions 910K, 910Y, 910M, 910C, the surfaces of the photoconductor drums 913K, 913Y, 913M, 913C are charged by the charging rollers 914K, 914Y, 914M, 914C, and are charged by the optical print heads 911K, 911Y, 911M, 911C. It is exposed and an electrostatic latent image is formed. Toner thinned on the developing rollers 916K, 916Y, 916M, and 916C is electrostatically adhered to the electrostatic latent image to form a toner image of each color. The toner image of each color is transferred to the recording medium P by the transfer rollers 940K, 940Y, 940M, and 940C, and the color toner image is formed on the recording medium P. After the transfer, the toner remaining on the photoconductor drums 913K, 913Y, 913M, 913C is removed by the cleaning device 919K, 919Y, 919M, 919C. The recording medium P on which the color toner image is formed is sent to the fuser 950. In the fuser 950, the color toner image is fixed on the recording medium P, and the color image is formed. The recording medium P on which the color image is formed is conveyed along the guide 926 and discharged to the stacker by the paper ejection roller pair 925.

As described above, since the image forming apparatus 900 according to the seventh embodiment uses the optical printhead 800 according to the sixth embodiment as the optical printheads 911K, 911Y, 911M, and 911C, the image forming apparatus 900 is used. The print quality of the device 900 can be improved.

10, 20, 30, 40, 50 Light emitting element array chip (semiconductor device), 100_1,100_n, 200_1,200_n, 300_1,300_n, 400_1,400_n, 500_1,500_n The light emitting thylister closest to the end (first element) , 100_2, ..., 100_n-1, 200_2, ..., 200_n-1, 300_2, ..., 300_n-1, 400_2, ..., 400_n-1, 500_2, ..., 500_n-1 Luminous thyristor (second element), 101 , 301, 501 N-type cathode layer, 102, 302 N-type clad layer, 103, 303 N-type active layer, 104, 304 third semiconductor layer (P-type clad layer, P-type gate layer), 105,305 second semiconductor layer (N-type gate layer), 106,306 P-type anode layer, 107,307 P-type anode contact layer, 108,308,508 fourth semiconductor layer, 109,309th 1 semiconductor layer, 110, 310, 510 semiconductor multilayer structure, 110a multilayer semiconductor layer, 112, 312 N-type clad layer, 113, 313 N-type active layer, 114, 314 7th semiconductor layer (P-type) Clad layer), 115,315 6th semiconductor layer (N-type gate layer), 116,316 P-type anode layer, 117,317 P-type anode contact layer, 118,318 8th semiconductor layer, 119, 319 Fifth semiconductor layer, 201,401 P-type anode layer, 202,402 P-type clad layer, 203,403 P-type active layer, 204,404 Third semiconductor layer (N-type clad layer, N Type gate layer), 205,405 second semiconductor layer (P type gate layer), 206,406 N type cathode layer, 207,407 N type cathode contact layer, 208,408 fourth semiconductor layer, 209,409 1st semiconductor layer, 210,410 semiconductor multilayer structure, 212,412 P-type clad layer, 213,413 P-type active layer, 214,414 7th semiconductor layer (N-type clad layer), 215,415 6th semiconductor layer (P-type gate layer), 216,416 N-type cathode layer, 217,417 N Mold cathode contact layer, 218,418 8th semiconductor layer, 219,419 5th semiconductor layer, 121,221,321,421 first surface, 122,222,322,422 second surface, 123, 223,323,423 3rd surface, 124,224,324,424 4th surface, 131,231,331,431 5th surface, 132,232,332,432 6th surface, 133,233 333,433 7th surface, 134,234,334,434 8th surface, 150 base material, 150a, 150b end, 151 base material, 152 flattening layer, 153 electrode pad, 701 growth substrate, 702 buffer Layer, 703 peeling layer, 800 optical printhead, 900 image forming apparatus, X1 first distance, X2 second distance, X3 third distance, X4 fourth distance, WEB fifth distance, WE sixth distance.

Claims (15)

With the base material
A plurality of light emitting thyristors provided on the base material portion and arranged at intervals in the longitudinal direction of the base material portion.
Have,
Among the plurality of light emitting psyllistas, the first element, which is the light emitting thylister closest to the longitudinal end of the base material portion, includes a first conductive type first semiconductor layer and the first conductive type. The second semiconductor layer of the second conductive type, the third semiconductor layer of the first conductive type, and the fourth semiconductor layer of the second conductive type are formed from the base material portion side to the fourth semiconductor layer. It has a first semiconductor multilayer structure in which the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer are laminated in this order.
The second element, which is a light emitting thylister other than the first element among the plurality of light emitting psyllistas, includes a first conductive type fifth semiconductor layer, a second conductive type sixth semiconductor layer, and a second element. The first conductive type seventh semiconductor layer and the second conductive type eighth semiconductor layer are formed from the base material side to the eighth semiconductor layer, the seventh semiconductor layer, and the sixth semiconductor layer. , And a second semiconductor multilayer structure in which the fifth semiconductor layer is laminated in this order.
A first surface between a first surface including an end face of the first semiconductor layer on the side close to the end portion and a second surface including an end face of the third semiconductor layer on the side close to the end portion. The distance is the distance between the third surface including the end face of the first semiconductor layer on the side far from the end and the fourth surface including the end face of the third semiconductor layer on the side far from the end. Less than the second distance,
A third distance between a fifth surface including the end face of the fifth semiconductor layer on one side in the longitudinal direction and a sixth surface including the end face of the seventh semiconductor layer on the one side. Is between a seventh surface including the end face of the fifth semiconductor layer on the other side opposite to the one side and an eighth surface including the end face of the seventh semiconductor layer on the other side. Equal to the fourth distance of
A semiconductor device characterized in that the second distance is equal to the third distance. The second surface further includes an end surface of the second semiconductor layer on the side close to the end portion.
The fourth surface further includes an end surface of the second semiconductor layer on the side far from the end portion.
The sixth surface further includes an end surface of the sixth semiconductor layer on one side thereof.
The semiconductor device according to claim 1, wherein the eighth surface further includes an end surface of the sixth semiconductor layer on the other side. The first conductive type is a P type.
The second conductive type is an N type.
Each of the first semiconductor layer and the fifth semiconductor layer includes a P-type anode layer.
Each of the second semiconductor layer and the sixth semiconductor layer includes an N-type gate layer.
Each of the third semiconductor layer and the seventh semiconductor layer includes a P-type clad layer.
The semiconductor device according to claim 2, wherein each of the fourth semiconductor layer and the eighth semiconductor layer includes an N-type cathode layer. Each of the fourth semiconductor layer and the eighth semiconductor layer
An N-type clad layer arranged on the N-type cathode layer and
An N-type active layer arranged between the N-type clad layer and the P-type clad layer,
The semiconductor device according to claim 3, further comprising. The first conductive type is an N type.
The second conductive type is a P type.
Each of the first semiconductor layer and the fifth semiconductor layer includes an N-type cathode layer.
Each of the second semiconductor layer and the sixth semiconductor layer includes a P-type gate layer.
Each of the third semiconductor layer and the seventh semiconductor layer includes an N-type clad layer.
The semiconductor device according to claim 2, wherein each of the fourth semiconductor layer and the eighth semiconductor layer includes a P-type anode layer. Each of the fourth semiconductor layer and the eighth semiconductor layer
The P-type clad layer arranged on the P-type anode layer and
A P-type active layer arranged between the P-type clad layer and the N-type clad layer,
The semiconductor device according to claim 5, further comprising. The first surface further includes an end surface of the second semiconductor layer on the side close to the end portion.
The third surface further includes an end surface of the second semiconductor layer on the side far from the end portion.
The fifth surface further includes an end surface of the sixth semiconductor layer on one side thereof.
The semiconductor device according to claim 1, wherein the seventh surface further includes an end surface of the sixth semiconductor layer on the other side. The first conductive type is a P type.
The second conductive type is an N type.
Each of the first semiconductor layer and the fifth semiconductor layer includes a P-type anode layer.
Each of the second semiconductor layer and the sixth semiconductor layer includes an N-type gate layer.
Each of the third semiconductor layer and the seventh semiconductor layer includes a P-type gate layer.
The semiconductor device according to claim 7, wherein each of the fourth semiconductor layer and the eighth semiconductor layer includes an N-type cathode layer. The first conductive type is an N type.
The second conductive type is a P type.
Each of the first semiconductor layer and the fifth semiconductor layer includes an N-type cathode layer.
Each of the second semiconductor layer and the sixth semiconductor layer includes a P-type gate layer.
Each of the third semiconductor layer and the seventh semiconductor layer includes an N-type gate layer.
The semiconductor device according to claim 7, wherein each of the fourth semiconductor layer and the eighth semiconductor layer includes a P-type anode layer. The fifth distance between the ninth surface including the end surface of the fourth semiconductor layer on the side close to the end portion and the second surface on the side close to the end portion is
1. The first aspect of the present invention is that the distance is smaller than the sixth distance between the tenth surface including the end surface of the base material portion on the side close to the end portion and the second surface on the side close to the end portion. 9. The semiconductor device according to any one of 9. The semiconductor device according to any one of claims 1 to 10, wherein the length of the first semiconductor layer in the longitudinal direction is equal to the length of the fifth semiconductor layer in the longitudinal direction. .. The semiconductor device according to any one of claims 1 to 11, wherein the planar shape of the first semiconductor layer is the same as the planar shape of the fifth semiconductor layer. The semiconductor device according to any one of claims 1 to 12, wherein the base material portion has a circuit for driving the plurality of light emitting thyristors. An optical print head comprising the semiconductor device according to any one of claims 1 to 13. An image forming apparatus according to claim 14, further comprising the optical print head.

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